nmigen/vendor/lattice_ecp5.py

   1 from abc import abstractproperty
   2
   3 from ..hdl import *
   4 from ..build import *
   5
   6
   7 __all__ = ["LatticeECP5Platform"]
   8
   9
  10 class LatticeECP5Platform(TemplatedPlatform):
  11     """
  12     Required tools:
  13         * ``yosys``
  14         * ``nextpnr-ecp5``
  15         * ``ecppack``
  16
  17     Available overrides:
  18         * ``verbose``: enables logging of informational messages to standard error.
  19         * ``read_verilog_opts``: adds options for ``read_verilog`` Yosys command.
  20         * ``synth_opts``: adds options for ``synth_ecp5`` Yosys command.
  21         * ``script_after_read``: inserts commands after ``read_ilang`` in Yosys script.
  22         * ``script_after_synth``: inserts commands after ``synth_ecp5`` in Yosys script.
  23         * ``yosys_opts``: adds extra options for Yosys.
  24         * ``nextpnr_opts``: adds extra options for nextpnr.
  25         * ``ecppack_opts``: adds extra options for ecppack.
  26
  27     Build products:
  28         * ``{{name}}.rpt``: Yosys log.
  29         * ``{{name}}.json``: synthesized RTL.
  30         * ``{{name}}.tim``: nextpnr log.
  31         * ``{{name}}.config``: ASCII bitstream.
  32         * ``{{name}}.bit``: binary bitstream.
  33         * ``{{name}}.svf``: JTAG programming vector.
  34     """
  35
  36     device  = abstractproperty()
  37     package = abstractproperty()
  38     speed   = abstractproperty()
  39
  40     _nextpnr_device_options = {
  41         "LFE5U-12F":    "--25k",
  42         "LFE5U-25F":    "--25k",
  43         "LFE5U-45F":    "--45k",
  44         "LFE5U-85F":    "--85k",
  45         "LFE5UM-12F":   "--um-25k",
  46         "LFE5UM-25F":   "--um-25k",
  47         "LFE5UM-45F":   "--um-45k",
  48         "LFE5UM-85F":   "--um-85k",
  49         "LFE5UM5G-12F": "--um5g-25k",
  50         "LFE5UM5G-25F": "--um5g-25k",
  51         "LFE5UM5G-45F": "--um5g-45k",
  52         "LFE5UM5G-85F": "--um5g-85k",
  53     }
  54     _nextpnr_package_options = {
  55         "BG256": "caBGA256",
  56         "MG285": "csfBGA285",
  57         "BG381": "caBGA381",
  58         "BG554": "caBGA554",
  59         "BG756": "caBGA756",
  60     }
  61
  62     file_templates = {
  63         **TemplatedPlatform.build_script_templates,
  64         "{{name}}.il": r"""
  65             # {{autogenerated}}
  66             {{emit_design("rtlil")}}
  67         """,
  68         "{{name}}.ys": r"""
  69             # {{autogenerated}}
  70             {% for file in platform.extra_files %}
  71                 {% if file.endswith(".v") -%}
  72                     read_verilog {{get_override("read_opts")|join(" ")}} {{file}}
  73                 {% elif file.endswith(".sv") -%}
  74                     read_verilog -sv {{get_override("read_opts")|join(" ")}} {{file}}
  75                 {% endif %}
  76             {% endfor %}
  77             read_ilang {{name}}.il
  78             {{get_override("script_after_read")|default("# (script_after_read placeholder)")}}
  79             synth_ecp5 {{get_override("synth_opts")|join(" ")}} -top {{name}}
  80             {{get_override("script_after_synth")|default("# (script_after_synth placeholder)")}}
  81             write_json {{name}}.json
  82         """,
  83         "{{name}}.lpf": r"""
  84             # {{autogenerated}}
  85             BLOCK ASYNCPATHS;
  86             BLOCK RESETPATHS;
  87             {% for port_name, pin_name, extras in platform.iter_port_constraints_bits() -%}
  88                 LOCATE COMP "{{port_name}}" SITE "{{pin_name}}";
  89                 IOBUF PORT "{{port_name}}"
  90                     {%- for key, value in extras.items() %} {{key}}={{value}}{% endfor %};
  91             {% endfor %}
  92             {% for signal, frequency in platform.iter_clock_constraints() -%}
  93                 FREQUENCY PORT "{{signal.name}}" {{frequency}} HZ;
  94             {% endfor %}
  95         """
  96     }
  97     command_templates = [
  98         r"""
  99         {{get_tool("yosys")}}
 100             {{quiet("-q")}}
 101             {{get_override("yosys_opts")|join(" ")}}
 102             -l {{name}}.rpt
 103             {{name}}.ys
 104         """,
 105         r"""
 106         {{get_tool("nextpnr-ecp5")}}
 107             {{quiet("--quiet")}}
 108             {{get_override("nextpnr_opts")|join(" ")}}
 109             --log {{name}}.tim
 110             {{platform._nextpnr_device_options[platform.device]}}
 111             --package {{platform._nextpnr_package_options[platform.package]|upper}}
 112             --speed {{platform.speed}}
 113             --json {{name}}.json
 114             --lpf {{name}}.lpf
 115             --textcfg {{name}}.config
 116         """,
 117         r"""
 118         {{get_tool("ecppack")}}
 119             {{verbose("--verbose")}}
 120             --input {{name}}.config
 121             --bit {{name}}.bit
 122             --svf {{name}}.svf
 123         """
 124     ]
 125
 126     _single_ended_io_types = [
 127         "HSUL12", "LVCMOS12", "LVCMOS15", "LVCMOS18", "LVCMOS25", "LVCMOS33", "LVTTL33",
 128         "SSTL135_I", "SSTL135_II", "SSTL15_I", "SSTL15_II", "SSTL18_I", "SSTL18_II",
 129     ]
 130     _differential_io_types = [
 131         "BLVDS25", "BLVDS25E", "HSUL12D", "LVCMOS18D", "LVCMOS25D", "LVCMOS33D",
 132         "LVDS", "LVDS25E", "LVPECL33", "LVPECL33E", "LVTTL33D", "MLVDS", "MLVDS25E",
 133         "SLVS", "SSTL135D_II", "SSTL15D_II", "SSTL18D_II", "SUBLVDS",
 134     ]
 135
 136     def should_skip_port_component(self, port, attrs, component):
 137         # On ECP5, a differential IO is placed by only instantiating an IO buffer primitive at
 138         # the PIOA or PIOC location, which is always the non-inverting pin.
 139         if attrs.get("IO_TYPE", "LVCMOS25") in self._differential_io_types and component == "n":
 140             return True
 141         return False
 142
 143     def _get_xdr_buffer(self, m, pin, i_invert=None, o_invert=None):
 144         def get_ireg(clk, d, q):
 145             for bit in range(len(q)):
 146                 m.submodules += Instance("IFS1P3DX",
 147                     i_SCLK=clk,
 148                     i_SP=Const(1),
 149                     i_CD=Const(0),
 150                     i_D=d[bit],
 151                     o_Q=q[bit]
 152                 )
 153
 154         def get_oreg(clk, d, q):
 155             for bit in range(len(q)):
 156                 m.submodules += Instance("OFS1P3DX",
 157                     i_SCLK=clk,
 158                     i_SP=Const(1),
 159                     i_CD=Const(0),
 160                     i_D=d[bit],
 161                     o_Q=q[bit]
 162                 )
 163
 164         def get_iddr(sclk, d, q0, q1):
 165             for bit in range(len(d)):
 166                 m.submodules += Instance("IDDRX1F",
 167                     i_SCLK=sclk,
 168                     i_RST=Const(0),
 169                     i_D=d[bit],
 170                     o_Q0=q0[bit], o_Q1=q1[bit]
 171                 )
 172
 173         def get_oddr(sclk, d0, d1, q):
 174             for bit in range(len(q)):
 175                 m.submodules += Instance("ODDRX1F",
 176                     i_SCLK=sclk,
 177                     i_RST=Const(0),
 178                     i_D0=d0[bit], i_D1=d1[bit],
 179                     o_Q=q[bit]
 180                 )
 181
 182         def get_ixor(z, invert):
 183             if invert is None:
 184                 return z
 185             else:
 186                 a = Signal.like(z, name_suffix="_x{}".format(1 if invert else 0))
 187                 for bit in range(len(z)):
 188                     m.submodules += Instance("LUT4",
 189                         p_INIT=0x5555 if invert else 0xaaaa,
 190                         i_A=a[bit],
 191                         o_Z=z[bit]
 192                     )
 193                 return a
 194
 195         def get_oxor(a, invert):
 196             if invert is None:
 197                 return a
 198             else:
 199                 z = Signal.like(a, name_suffix="_x{}".format(1 if invert else 0))
 200                 for bit in range(len(a)):
 201                     m.submodules += Instance("LUT4",
 202                         p_INIT=0x5555 if invert else 0xaaaa,
 203                         i_A=a[bit],
 204                         o_Z=z[bit]
 205                     )
 206                 return z
 207
 208         if "i" in pin.dir:
 209             if pin.xdr < 2:
 210                 pin_i  = get_ixor(pin.i,  i_invert)
 211             elif pin.xdr == 2:
 212                 pin_i0 = get_ixor(pin.i0, i_invert)
 213                 pin_i1 = get_ixor(pin.i1, i_invert)
 214         if "o" in pin.dir:
 215             if pin.xdr < 2:
 216                 pin_o  = get_oxor(pin.o,  o_invert)
 217             elif pin.xdr == 2:
 218                 pin_o0 = get_oxor(pin.o0, o_invert)
 219                 pin_o1 = get_oxor(pin.o1, o_invert)
 220
 221         i = o = t = None
 222         if "i" in pin.dir:
 223             i = Signal(pin.width, name="{}_xdr_i".format(pin.name))
 224         if "o" in pin.dir:
 225             o = Signal(pin.width, name="{}_xdr_o".format(pin.name))
 226         if pin.dir in ("oe", "io"):
 227             t = Signal(1,         name="{}_xdr_t".format(pin.name))
 228
 229         if pin.xdr == 0:
 230             if "i" in pin.dir:
 231                 i = pin_i
 232             if "o" in pin.dir:
 233                 o = pin_o
 234             if pin.dir in ("oe", "io"):
 235                 t = ~pin_oe
 236         elif pin.xdr == 1:
 237             # Note that currently nextpnr will not pack an FF (*FS1P3DX) into the PIO.
 238             if "i" in pin.dir:
 239                 get_ireg(pin.i_clk, i, pin_i)
 240             if "o" in pin.dir:
 241                 get_oreg(pin.o_clk, pin_o, o)
 242             if pin.dir in ("oe", "io"):
 243                 get_oreg(pin.o_clk, ~pin.oe, t)
 244         elif pin.xdr == 2:
 245             if "i" in pin.dir:
 246                 get_iddr(pin.i_clk, i, pin_i0, pin_i1)
 247             if "o" in pin.dir:
 248                 get_oddr(pin.o_clk, pin_o0, pin_o1, o)
 249             if pin.dir in ("oe", "io"):
 250                 # It looks like Diamond will not pack an OREG as a tristate register in a DDR PIO.
 251                 # It is not clear what is the recommended set of primitives for this task.
 252                 # Similarly, nextpnr will not pack anything as a tristate register in a DDR PIO.
 253                 get_oreg(pin.o_clk, ~pin.oe, t)
 254         else:
 255             assert False
 256
 257         return (i, o, t)
 258
 259     def get_input(self, pin, port, attrs, invert):
 260         self._check_feature("single-ended input", pin, attrs,
 261                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 262         m = Module()
 263         t, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None)
 264         for bit in range(len(port)):
 265             m.submodules += Instance("IB",
 266                 i_I=port[bit],
 267                 o_O=i[bit]
 268             )
 269         return m
 270
 271     def get_output(self, pin, port, attrs, invert):
 272         self._check_feature("single-ended output", pin, attrs,
 273                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 274         m = Module()
 275         i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None)
 276         for bit in range(len(port)):
 277             m.submodules += Instance("OB",
 278                 i_I=o[bit],
 279                 o_O=port[bit]
 280             )
 281         return m
 282
 283     def get_tristate(self, pin, port, attrs, invert):
 284         self._check_feature("single-ended tristate", pin, attrs,
 285                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 286         m = Module()
 287         i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None)
 288         for bit in range(len(port)):
 289             m.submodules += Instance("OBZ",
 290                 i_T=t,
 291                 i_I=o[bit],
 292                 o_O=port[bit]
 293             )
 294         return m
 295
 296     def get_input_output(self, pin, port, attrs, invert):
 297         self._check_feature("single-ended input/output", pin, attrs,
 298                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 299         m = Module()
 300         i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None,
 301                                                o_invert=True if invert else None)
 302         for bit in range(len(port)):
 303             m.submodules += Instance("BB",
 304                 i_T=t,
 305                 i_I=o[bit],
 306                 o_O=i[bit],
 307                 io_B=port[bit]
 308             )
 309         return m
 310
 311     def get_diff_input(self, pin, p_port, n_port, attrs, invert):
 312         self._check_feature("differential input", pin, attrs,
 313                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 314         m = Module()
 315         i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None)
 316         for bit in range(len(p_port)):
 317             m.submodules += Instance("IB",
 318                 i_I=p_port[bit],
 319                 o_O=i[bit]
 320             )
 321         return m
 322
 323     def get_diff_output(self, pin, p_port, n_port, attrs, invert):
 324         self._check_feature("differential output", pin, attrs,
 325                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 326         m = Module()
 327         i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None)
 328         for bit in range(len(p_port)):
 329             m.submodules += Instance("OB",
 330                 i_I=o[bit],
 331                 o_O=p_port[bit],
 332             )
 333         return m
 334
 335     def get_diff_tristate(self, pin, p_port, n_port, attrs, invert):
 336         self._check_feature("differential tristate", pin, attrs,
 337                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 338         m = Module()
 339         i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None)
 340         for bit in range(len(p_port)):
 341             m.submodules += Instance("OBZ",
 342                 i_T=t,
 343                 i_I=o[bit],
 344                 o_O=p_port[bit],
 345             )
 346         return m
 347
 348     def get_diff_input_output(self, pin, p_port, n_port, attrs, invert):
 349         self._check_feature("differential input/output", pin, attrs,
 350                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 351         m = Module()
 352         i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None,
 353                                                o_invert=True if invert else None)
 354         for bit in range(len(p_port)):
 355             m.submodules += Instance("BB",
 356                 i_T=t,
 357                 i_I=o[bit],
 358                 o_O=i[bit],
 359                 io_B=p_port[bit],
 360             )
 361         return m