1 from abc
import abstractproperty
7 __all__
= ["LatticeECP5Platform"]
10 class LatticeECP5Platform(TemplatedPlatform
):
18 * ``verbose``: enables logging of informational messages to standard error.
19 * ``read_verilog_opts``: adds options for ``read_verilog`` Yosys command.
20 * ``synth_opts``: adds options for ``synth_ecp5`` Yosys command.
21 * ``script_after_read``: inserts commands after ``read_ilang`` in Yosys script.
22 * ``script_after_synth``: inserts commands after ``synth_ecp5`` in Yosys script.
23 * ``yosys_opts``: adds extra options for Yosys.
24 * ``nextpnr_opts``: adds extra options for nextpnr.
25 * ``ecppack_opts``: adds extra options for ecppack.
28 * ``{{name}}.rpt``: Yosys log.
29 * ``{{name}}.json``: synthesized RTL.
30 * ``{{name}}.tim``: nextpnr log.
31 * ``{{name}}.config``: ASCII bitstream.
32 * ``{{name}}.bit``: binary bitstream.
33 * ``{{name}}.svf``: JTAG programming vector.
36 device
= abstractproperty()
37 package
= abstractproperty()
38 speed
= abstractproperty()
40 _nextpnr_device_options
= {
45 "LFE5UM-12F": "--um-25k",
46 "LFE5UM-25F": "--um-25k",
47 "LFE5UM-45F": "--um-45k",
48 "LFE5UM-85F": "--um-85k",
49 "LFE5UM5G-12F": "--um5g-25k",
50 "LFE5UM5G-25F": "--um5g-25k",
51 "LFE5UM5G-45F": "--um5g-45k",
52 "LFE5UM5G-85F": "--um5g-85k",
54 _nextpnr_package_options
= {
63 **TemplatedPlatform
.build_script_templates
,
66 {{emit_design("rtlil")}}
70 {% for file in platform.iter_extra_files(".v") -%}
71 read_verilog {{get_override("read_opts")|join(" ")}} {{file}}
73 {% for file in platform.iter_extra_files(".sv") -%}
74 read_verilog -sv {{get_override("read_opts")|join(" ")}} {{file}}
76 read_ilang {{name}}.il
77 {{get_override("script_after_read")|default("# (script_after_read placeholder)")}}
78 synth_ecp5 {{get_override("synth_opts")|join(" ")}} -top {{name}}
79 {{get_override("script_after_synth")|default("# (script_after_synth placeholder)")}}
80 write_json {{name}}.json
86 {% for port_name, pin_name, extras in platform.iter_port_constraints_bits() -%}
87 LOCATE COMP "{{port_name}}" SITE "{{pin_name}}";
88 IOBUF PORT "{{port_name}}"
89 {%- for key, value in extras.items() %} {{key}}={{value}}{% endfor %};
91 {% for signal, frequency in platform.iter_clock_constraints() -%}
92 FREQUENCY PORT "{{signal.name}}" {{frequency}} HZ;
100 {{get_override("yosys_opts")|join(" ")}}
105 {{get_tool("nextpnr-ecp5")}}
107 {{get_override("nextpnr_opts")|join(" ")}}
109 {{platform._nextpnr_device_options[platform.device]}}
110 --package {{platform._nextpnr_package_options[platform.package]|upper}}
111 --speed {{platform.speed}}
114 --textcfg {{name}}.config
117 {{get_tool("ecppack")}}
118 {{verbose("--verbose")}}
119 --input {{name}}.config
125 _single_ended_io_types
= [
126 "HSUL12", "LVCMOS12", "LVCMOS15", "LVCMOS18", "LVCMOS25", "LVCMOS33", "LVTTL33",
127 "SSTL135_I", "SSTL135_II", "SSTL15_I", "SSTL15_II", "SSTL18_I", "SSTL18_II",
129 _differential_io_types
= [
130 "BLVDS25", "BLVDS25E", "HSUL12D", "LVCMOS18D", "LVCMOS25D", "LVCMOS33D",
131 "LVDS", "LVDS25E", "LVPECL33", "LVPECL33E", "LVTTL33D", "MLVDS", "MLVDS25E",
132 "SLVS", "SSTL135D_II", "SSTL15D_II", "SSTL18D_II", "SUBLVDS",
135 def should_skip_port_component(self
, port
, attrs
, component
):
136 # On ECP5, a differential IO is placed by only instantiating an IO buffer primitive at
137 # the PIOA or PIOC location, which is always the non-inverting pin.
138 if attrs
.get("IO_TYPE", "LVCMOS25") in self
._differential
_io
_types
and component
== "n":
142 def _get_xdr_buffer(self
, m
, pin
, i_invert
=None, o_invert
=None):
143 def get_ireg(clk
, d
, q
):
144 for bit
in range(len(q
)):
145 m
.submodules
+= Instance("IFS1P3DX",
153 def get_oreg(clk
, d
, q
):
154 for bit
in range(len(q
)):
155 m
.submodules
+= Instance("OFS1P3DX",
163 def get_iddr(sclk
, d
, q0
, q1
):
164 for bit
in range(len(d
)):
165 m
.submodules
+= Instance("IDDRX1F",
169 o_Q0
=q0
[bit
], o_Q1
=q1
[bit
]
172 def get_oddr(sclk
, d0
, d1
, q
):
173 for bit
in range(len(q
)):
174 m
.submodules
+= Instance("ODDRX1F",
177 i_D0
=d0
[bit
], i_D1
=d1
[bit
],
181 def get_ixor(z
, invert
):
185 a
= Signal
.like(z
, name_suffix
="_x{}".format(1 if invert
else 0))
186 for bit
in range(len(z
)):
187 m
.submodules
+= Instance("LUT4",
188 p_INIT
=0x5555 if invert
else 0xaaaa,
194 def get_oxor(a
, invert
):
198 z
= Signal
.like(a
, name_suffix
="_x{}".format(1 if invert
else 0))
199 for bit
in range(len(a
)):
200 m
.submodules
+= Instance("LUT4",
201 p_INIT
=0x5555 if invert
else 0xaaaa,
209 pin_i
= get_ixor(pin
.i
, i_invert
)
211 pin_i0
= get_ixor(pin
.i0
, i_invert
)
212 pin_i1
= get_ixor(pin
.i1
, i_invert
)
215 pin_o
= get_oxor(pin
.o
, o_invert
)
217 pin_o0
= get_oxor(pin
.o0
, o_invert
)
218 pin_o1
= get_oxor(pin
.o1
, o_invert
)
222 i
= Signal(pin
.width
, name
="{}_xdr_i".format(pin
.name
))
224 o
= Signal(pin
.width
, name
="{}_xdr_o".format(pin
.name
))
225 if pin
.dir in ("oe", "io"):
226 t
= Signal(1, name
="{}_xdr_t".format(pin
.name
))
233 if pin
.dir in ("oe", "io"):
236 # Note that currently nextpnr will not pack an FF (*FS1P3DX) into the PIO.
238 get_ireg(pin
.i_clk
, i
, pin_i
)
240 get_oreg(pin
.o_clk
, pin_o
, o
)
241 if pin
.dir in ("oe", "io"):
242 get_oreg(pin
.o_clk
, ~pin
.oe
, t
)
245 get_iddr(pin
.i_clk
, i
, pin_i0
, pin_i1
)
247 get_oddr(pin
.o_clk
, pin_o0
, pin_o1
, o
)
248 if pin
.dir in ("oe", "io"):
249 # It looks like Diamond will not pack an OREG as a tristate register in a DDR PIO.
250 # It is not clear what is the recommended set of primitives for this task.
251 # Similarly, nextpnr will not pack anything as a tristate register in a DDR PIO.
252 get_oreg(pin
.o_clk
, ~pin
.oe
, t
)
258 def get_input(self
, pin
, port
, attrs
, invert
):
259 self
._check
_feature
("single-ended input", pin
, attrs
,
260 valid_xdrs
=(0, 1, 2), valid_attrs
=True)
262 t
, o
, t
= self
._get
_xdr
_buffer
(m
, pin
, i_invert
=True if invert
else None)
263 for bit
in range(len(port
)):
264 m
.submodules
+= Instance("IB",
270 def get_output(self
, pin
, port
, attrs
, invert
):
271 self
._check
_feature
("single-ended output", pin
, attrs
,
272 valid_xdrs
=(0, 1, 2), valid_attrs
=True)
274 i
, o
, t
= self
._get
_xdr
_buffer
(m
, pin
, o_invert
=True if invert
else None)
275 for bit
in range(len(port
)):
276 m
.submodules
+= Instance("OB",
282 def get_tristate(self
, pin
, port
, attrs
, invert
):
283 self
._check
_feature
("single-ended tristate", pin
, attrs
,
284 valid_xdrs
=(0, 1, 2), valid_attrs
=True)
286 i
, o
, t
= self
._get
_xdr
_buffer
(m
, pin
, o_invert
=True if invert
else None)
287 for bit
in range(len(port
)):
288 m
.submodules
+= Instance("OBZ",
295 def get_input_output(self
, pin
, port
, attrs
, invert
):
296 self
._check
_feature
("single-ended input/output", pin
, attrs
,
297 valid_xdrs
=(0, 1, 2), valid_attrs
=True)
299 i
, o
, t
= self
._get
_xdr
_buffer
(m
, pin
, i_invert
=True if invert
else None,
300 o_invert
=True if invert
else None)
301 for bit
in range(len(port
)):
302 m
.submodules
+= Instance("BB",
310 def get_diff_input(self
, pin
, p_port
, n_port
, attrs
, invert
):
311 self
._check
_feature
("differential input", pin
, attrs
,
312 valid_xdrs
=(0, 1, 2), valid_attrs
=True)
314 i
, o
, t
= self
._get
_xdr
_buffer
(m
, pin
, i_invert
=True if invert
else None)
315 for bit
in range(len(p_port
)):
316 m
.submodules
+= Instance("IB",
322 def get_diff_output(self
, pin
, p_port
, n_port
, attrs
, invert
):
323 self
._check
_feature
("differential output", pin
, attrs
,
324 valid_xdrs
=(0, 1, 2), valid_attrs
=True)
326 i
, o
, t
= self
._get
_xdr
_buffer
(m
, pin
, o_invert
=True if invert
else None)
327 for bit
in range(len(p_port
)):
328 m
.submodules
+= Instance("OB",
334 def get_diff_tristate(self
, pin
, p_port
, n_port
, attrs
, invert
):
335 self
._check
_feature
("differential tristate", pin
, attrs
,
336 valid_xdrs
=(0, 1, 2), valid_attrs
=True)
338 i
, o
, t
= self
._get
_xdr
_buffer
(m
, pin
, o_invert
=True if invert
else None)
339 for bit
in range(len(p_port
)):
340 m
.submodules
+= Instance("OBZ",
347 def get_diff_input_output(self
, pin
, p_port
, n_port
, attrs
, invert
):
348 self
._check
_feature
("differential input/output", pin
, attrs
,
349 valid_xdrs
=(0, 1, 2), valid_attrs
=True)
351 i
, o
, t
= self
._get
_xdr
_buffer
(m
, pin
, i_invert
=True if invert
else None,
352 o_invert
=True if invert
else None)
353 for bit
in range(len(p_port
)):
354 m
.submodules
+= Instance("BB",