nmigen/vendor/lattice_ecp5.py

   1 from abc import abstractproperty
   2
   3 from ..hdl import *
   4 from ..build import *
   5
   6
   7 __all__ = ["LatticeECP5Platform"]
   8
   9
  10 class LatticeECP5Platform(TemplatedPlatform):
  11     """
  12     Trellis toolchain
  13     -----------------
  14
  15     Required tools:
  16         * ``yosys``
  17         * ``nextpnr-ecp5``
  18         * ``ecppack``
  19
  20     The environment is populated by running the script specified in the environment variable
  21     ``NMIGEN_ENV_Trellis``, if present.
  22
  23     Available overrides:
  24         * ``verbose``: enables logging of informational messages to standard error.
  25         * ``read_verilog_opts``: adds options for ``read_verilog`` Yosys command.
  26         * ``synth_opts``: adds options for ``synth_ecp5`` Yosys command.
  27         * ``script_after_read``: inserts commands after ``read_ilang`` in Yosys script.
  28         * ``script_after_synth``: inserts commands after ``synth_ecp5`` in Yosys script.
  29         * ``yosys_opts``: adds extra options for ``yosys``.
  30         * ``nextpnr_opts``: adds extra options for ``nextpnr-ecp5``.
  31         * ``ecppack_opts``: adds extra options for ``ecppack``.
  32         * ``add_preferences``: inserts commands at the end of the LPF file.
  33
  34     Build products:
  35         * ``{{name}}.rpt``: Yosys log.
  36         * ``{{name}}.json``: synthesized RTL.
  37         * ``{{name}}.tim``: nextpnr log.
  38         * ``{{name}}.config``: ASCII bitstream.
  39         * ``{{name}}.bit``: binary bitstream.
  40         * ``{{name}}.svf``: JTAG programming vector.
  41
  42     Diamond toolchain
  43     -----------------
  44
  45     Required tools:
  46         * ``pnmainc``
  47         * ``ddtcmd``
  48
  49     The environment is populated by running the script specified in the environment variable
  50     ``NMIGEN_ENV_Diamond``, if present.
  51
  52     Available overrides:
  53         * ``script_project``: inserts commands before ``prj_project save`` in Tcl script.
  54         * ``script_after_export``: inserts commands after ``prj_run Export`` in Tcl script.
  55         * ``add_preferences``: inserts commands at the end of the LPF file.
  56         * ``add_constraints``: inserts commands at the end of the XDC file.
  57
  58     Build products:
  59         * ``{{name}}_impl/{{name}}_impl.htm``: consolidated log.
  60         * ``{{name}}.bit``: binary bitstream.
  61         * ``{{name}}.svf``: JTAG programming vector.
  62     """
  63
  64     toolchain = None # selected when creating platform
  65
  66     device  = abstractproperty()
  67     package = abstractproperty()
  68     speed   = abstractproperty()
  69     grade   = "C" # [C]ommercial, [I]ndustrial
  70
  71     # Trellis templates
  72
  73     _nextpnr_device_options = {
  74         "LFE5U-12F":    "--25k",
  75         "LFE5U-25F":    "--25k",
  76         "LFE5U-45F":    "--45k",
  77         "LFE5U-85F":    "--85k",
  78         "LFE5UM-12F":   "--um-25k",
  79         "LFE5UM-25F":   "--um-25k",
  80         "LFE5UM-45F":   "--um-45k",
  81         "LFE5UM-85F":   "--um-85k",
  82         "LFE5UM5G-12F": "--um5g-25k",
  83         "LFE5UM5G-25F": "--um5g-25k",
  84         "LFE5UM5G-45F": "--um5g-45k",
  85         "LFE5UM5G-85F": "--um5g-85k",
  86     }
  87     _nextpnr_package_options = {
  88         "BG256": "caBGA256",
  89         "MG285": "csfBGA285",
  90         "BG381": "caBGA381",
  91         "BG554": "caBGA554",
  92         "BG756": "caBGA756",
  93     }
  94
  95     _trellis_required_tools = [
  96         "yosys",
  97         "nextpnr-ecp5",
  98         "ecppack"
  99     ]
 100     _trellis_file_templates = {
 101         **TemplatedPlatform.build_script_templates,
 102         "{{name}}.il": r"""
 103             # {{autogenerated}}
 104             {{emit_rtlil()}}
 105         """,
 106         "{{name}}.debug.v": r"""
 107             /* {{autogenerated}} */
 108             {{emit_debug_verilog()}}
 109         """,
 110         "{{name}}.ys": r"""
 111             # {{autogenerated}}
 112             {% for file in platform.iter_extra_files(".v") -%}
 113                 read_verilog {{get_override("read_verilog_opts")|options}} {{file}}
 114             {% endfor %}
 115             {% for file in platform.iter_extra_files(".sv") -%}
 116                 read_verilog -sv {{get_override("read_verilog_opts")|options}} {{file}}
 117             {% endfor %}
 118             {% for file in platform.iter_extra_files(".il") -%}
 119                 read_ilang {{file}}
 120             {% endfor %}
 121             read_ilang {{name}}.il
 122             {{get_override("script_after_read")|default("# (script_after_read placeholder)")}}
 123             synth_ecp5 {{get_override("synth_opts")|options}} -top {{name}}
 124             {{get_override("script_after_synth")|default("# (script_after_synth placeholder)")}}
 125             write_json {{name}}.json
 126         """,
 127         "{{name}}.lpf": r"""
 128             # {{autogenerated}}
 129             BLOCK ASYNCPATHS;
 130             BLOCK RESETPATHS;
 131             {% for port_name, pin_name, extras in platform.iter_port_constraints_bits() -%}
 132                 LOCATE COMP "{{port_name}}" SITE "{{pin_name}}";
 133                 {% if extras -%}
 134                 IOBUF PORT "{{port_name}}"
 135                     {%- for key, value in extras.items() %} {{key}}={{value}}{% endfor %};
 136                 {% endif %}
 137             {% endfor %}
 138             {% for net_signal, port_signal, frequency in platform.iter_clock_constraints() -%}
 139                 {% if port_signal is not none -%}
 140                     FREQUENCY PORT "{{port_signal.name}}" {{frequency}} HZ;
 141                 {% else -%}
 142                     FREQUENCY NET "{{net_signal|hierarchy(".")}}" {{frequency}} HZ;
 143                 {% endif %}
 144             {% endfor %}
 145             {{get_override("add_preferences")|default("# (add_preferences placeholder)")}}
 146         """
 147     }
 148     _trellis_command_templates = [
 149         r"""
 150         {{invoke_tool("yosys")}}
 151             {{quiet("-q")}}
 152             {{get_override("yosys_opts")|options}}
 153             -l {{name}}.rpt
 154             {{name}}.ys
 155         """,
 156         r"""
 157         {{invoke_tool("nextpnr-ecp5")}}
 158             {{quiet("--quiet")}}
 159             {{get_override("nextpnr_opts")|options}}
 160             --log {{name}}.tim
 161             {{platform._nextpnr_device_options[platform.device]}}
 162             --package {{platform._nextpnr_package_options[platform.package]|upper}}
 163             --speed {{platform.speed}}
 164             --json {{name}}.json
 165             --lpf {{name}}.lpf
 166             --textcfg {{name}}.config
 167         """,
 168         r"""
 169         {{invoke_tool("ecppack")}}
 170             {{verbose("--verbose")}}
 171             {{get_override("ecppack_opts")|options}}
 172             --input {{name}}.config
 173             --bit {{name}}.bit
 174             --svf {{name}}.svf
 175         """
 176     ]
 177
 178     # Diamond templates
 179
 180     _diamond_required_tools = [
 181         "yosys",
 182         "pnmainc",
 183         "ddtcmd"
 184     ]
 185     _diamond_file_templates = {
 186         **TemplatedPlatform.build_script_templates,
 187         "build_{{name}}.sh": r"""
 188             # {{autogenerated}}
 189             set -e{{verbose("x")}}
 190             if [ -z "$BASH" ] ; then exec /bin/bash "$0" "$@"; fi
 191             if [ -n "${{platform._toolchain_env_var}}" ]; then
 192                 bindir=$(dirname "${{platform._toolchain_env_var}}")
 193                 . "${{platform._toolchain_env_var}}"
 194             fi
 195             {{emit_commands("sh")}}
 196         """,
 197         "{{name}}.v": r"""
 198             /* {{autogenerated}} */
 199             {{emit_verilog()}}
 200         """,
 201         "{{name}}.debug.v": r"""
 202             /* {{autogenerated}} */
 203             {{emit_debug_verilog()}}
 204         """,
 205         "{{name}}.tcl": r"""
 206             prj_project new -name {{name}} -impl impl -impl_dir top_impl \
 207                 -dev {{platform.device}}-{{platform.speed}}{{platform.package}}{{platform.grade}} \
 208                 -lpf {{name}}.lpf \
 209                 -synthesis synplify
 210             {% for file in platform.iter_extra_files(".v", ".sv", ".vhd", ".vhdl") -%}
 211                 prj_src add "{{file}}"
 212             {% endfor %}
 213             prj_src add {{name}}.v
 214             prj_impl option top {{name}}
 215             prj_src add {{name}}.sdc
 216             {{get_override("script_project")|default("# (script_project placeholder)")}}
 217             prj_project save
 218             prj_run Synthesis -impl impl -forceAll
 219             prj_run Translate -impl impl -forceAll
 220             prj_run Map -impl impl -forceAll
 221             prj_run PAR -impl impl -forceAll
 222             prj_run Export -impl "impl" -forceAll -task Bitgen
 223             {{get_override("script_after_export")|default("# (script_after_export placeholder)")}}
 224         """,
 225         "{{name}}.lpf": r"""
 226             # {{autogenerated}}
 227             BLOCK ASYNCPATHS;
 228             BLOCK RESETPATHS;
 229             {% for port_name, pin_name, extras in platform.iter_port_constraints_bits() -%}
 230                 LOCATE COMP "{{port_name}}" SITE "{{pin_name}}";
 231                 IOBUF PORT "{{port_name}}"
 232                     {%- for key, value in extras.items() %} {{key}}={{value}}{% endfor %};
 233             {% endfor %}
 234             {{get_override("add_preferences")|default("# (add_preferences placeholder)")}}
 235         """,
 236         "{{name}}.sdc": r"""
 237             {% for net_signal, port_signal, frequency in platform.iter_clock_constraints() -%}
 238                 {% if port_signal is not none -%}
 239                     create_clock -name {{port_signal.name}} -period {{1000000000/frequency}} [get_ports {{port_signal.name}}]
 240                 {% else -%}
 241                     create_clock -name {{net_signal.name}} -period {{1000000000/frequency}} [get_nets {{net_signal|hierarchy("/")}}]
 242                 {% endif %}
 243             {% endfor %}
 244             {{get_override("add_constraints")|default("# (add_constraints placeholder)")}}
 245         """,
 246     }
 247     _diamond_command_templates = [
 248         # These don't have any usable command-line option overrides.
 249         r"""
 250         {{invoke_tool("pnmainc")}}
 251             {{name}}.tcl
 252         """,
 253         r"""
 254         {{invoke_tool("ddtcmd")}}
 255             -oft -bit
 256             -if {{name}}_impl/{{name}}_impl.bit -of {{name}}.bit
 257         """,
 258         r"""
 259         {{invoke_tool("ddtcmd")}}
 260             -oft -svfsingle -revd -op "Fast Program"
 261             -if {{name}}_impl/{{name}}_impl.bit -of {{name}}.svf
 262         """,
 263     ]
 264
 265     # Common logic
 266
 267     def __init__(self, *, toolchain="Trellis"):
 268         super().__init__()
 269
 270         assert toolchain in ("Trellis", "Diamond")
 271         self.toolchain = toolchain
 272
 273     @property
 274     def required_tools(self):
 275         if self.toolchain == "Trellis":
 276             return self._trellis_required_tools
 277         if self.toolchain == "Diamond":
 278             return self._diamond_required_tools
 279         assert False
 280
 281     @property
 282     def file_templates(self):
 283         if self.toolchain == "Trellis":
 284             return self._trellis_file_templates
 285         if self.toolchain == "Diamond":
 286             return self._diamond_file_templates
 287         assert False
 288
 289     @property
 290     def command_templates(self):
 291         if self.toolchain == "Trellis":
 292             return self._trellis_command_templates
 293         if self.toolchain == "Diamond":
 294             return self._diamond_command_templates
 295         assert False
 296
 297     @property
 298     def default_clk_constraint(self):
 299         if self.default_clk == "OSCG":
 300             return Clock(310e6 / self.oscg_div)
 301         return super().default_clk_constraint
 302
 303     def create_missing_domain(self, name):
 304         # Lattice ECP5 devices have two global set/reset signals: PUR, which is driven at startup
 305         # by the configuration logic and unconditionally resets every storage element, and GSR,
 306         # which is driven by user logic and each storage element may be configured as affected or
 307         # unaffected by GSR. PUR is purely asynchronous, so even though it is a low-skew global
 308         # network, its deassertion may violate a setup/hold constraint with relation to a user
 309         # clock. To avoid this, a GSR/SGSR instance should be driven synchronized to user clock.
 310         if name == "sync" and self.default_clk is not None:
 311             m = Module()
 312             if self.default_clk == "OSCG":
 313                 if not hasattr(self, "oscg_div"):
 314                     raise ValueError("OSCG divider (oscg_div) must be an integer between 2 "
 315                                      "and 128")
 316                 if not isinstance(self.oscg_div, int) or self.oscg_div < 2 or self.oscg_div > 128:
 317                     raise ValueError("OSCG divider (oscg_div) must be an integer between 2 "
 318                                      "and 128, not {!r}"
 319                                      .format(self.oscg_div))
 320                 clk_i = Signal()
 321                 m.submodules += Instance("OSCG", p_DIV=self.oscg_div, o_OSC=clk_i)
 322             else:
 323                 clk_i = self.request(self.default_clk).i
 324             if self.default_rst is not None:
 325                 rst_i = self.request(self.default_rst).i
 326             else:
 327                 rst_i = Const(0)
 328
 329             gsr0 = Signal()
 330             gsr1 = Signal()
 331             # There is no end-of-startup signal on ECP5, but PUR is released after IOB enable, so
 332             # a simple reset synchronizer (with PUR as the asynchronous reset) does the job.
 333             m.submodules += [
 334                 Instance("FD1S3AX", p_GSR="DISABLED", i_CK=clk_i, i_D=~rst_i, o_Q=gsr0),
 335                 Instance("FD1S3AX", p_GSR="DISABLED", i_CK=clk_i, i_D=gsr0,   o_Q=gsr1),
 336                 # Although we already synchronize the reset input to user clock, SGSR has dedicated
 337                 # clock routing to the center of the FPGA; use that just in case it turns out to be
 338                 # more reliable. (None of this is documented.)
 339                 Instance("SGSR", i_CLK=clk_i, i_GSR=gsr1),
 340             ]
 341             # GSR implicitly connects to every appropriate storage element. As such, the sync
 342             # domain is reset-less; domains driven by other clocks would need to have dedicated
 343             # reset circuitry or otherwise meet setup/hold constraints on their own.
 344             m.domains += ClockDomain("sync", reset_less=True)
 345             m.d.comb += ClockSignal("sync").eq(clk_i)
 346             return m
 347
 348     _single_ended_io_types = [
 349         "HSUL12", "LVCMOS12", "LVCMOS15", "LVCMOS18", "LVCMOS25", "LVCMOS33", "LVTTL33",
 350         "SSTL135_I", "SSTL135_II", "SSTL15_I", "SSTL15_II", "SSTL18_I", "SSTL18_II",
 351     ]
 352     _differential_io_types = [
 353         "BLVDS25", "BLVDS25E", "HSUL12D", "LVCMOS18D", "LVCMOS25D", "LVCMOS33D",
 354         "LVDS", "LVDS25E", "LVPECL33", "LVPECL33E", "LVTTL33D", "MLVDS", "MLVDS25E",
 355         "SLVS", "SSTL135D_II", "SSTL15D_II", "SSTL18D_II", "SUBLVDS",
 356     ]
 357
 358     def should_skip_port_component(self, port, attrs, component):
 359         # On ECP5, a differential IO is placed by only instantiating an IO buffer primitive at
 360         # the PIOA or PIOC location, which is always the non-inverting pin.
 361         if attrs.get("IO_TYPE", "LVCMOS25") in self._differential_io_types and component == "n":
 362             return True
 363         return False
 364
 365     def _get_xdr_buffer(self, m, pin, *, i_invert=False, o_invert=False):
 366         def get_ireg(clk, d, q):
 367             for bit in range(len(q)):
 368                 m.submodules += Instance("IFS1P3DX",
 369                     i_SCLK=clk,
 370                     i_SP=Const(1),
 371                     i_CD=Const(0),
 372                     i_D=d[bit],
 373                     o_Q=q[bit]
 374                 )
 375
 376         def get_oreg(clk, d, q):
 377             for bit in range(len(q)):
 378                 m.submodules += Instance("OFS1P3DX",
 379                     i_SCLK=clk,
 380                     i_SP=Const(1),
 381                     i_CD=Const(0),
 382                     i_D=d[bit],
 383                     o_Q=q[bit]
 384                 )
 385
 386         def get_iddr(sclk, d, q0, q1):
 387             for bit in range(len(d)):
 388                 m.submodules += Instance("IDDRX1F",
 389                     i_SCLK=sclk,
 390                     i_RST=Const(0),
 391                     i_D=d[bit],
 392                     o_Q0=q0[bit], o_Q1=q1[bit]
 393                 )
 394
 395         def get_oddr(sclk, d0, d1, q):
 396             for bit in range(len(q)):
 397                 m.submodules += Instance("ODDRX1F",
 398                     i_SCLK=sclk,
 399                     i_RST=Const(0),
 400                     i_D0=d0[bit], i_D1=d1[bit],
 401                     o_Q=q[bit]
 402                 )
 403
 404         def get_ineg(z, invert):
 405             if invert:
 406                 a = Signal.like(z, name_suffix="_n")
 407                 m.d.comb += z.eq(~a)
 408                 return a
 409             else:
 410                 return z
 411
 412         def get_oneg(a, invert):
 413             if invert:
 414                 z = Signal.like(a, name_suffix="_n")
 415                 m.d.comb += z.eq(~a)
 416                 return z
 417             else:
 418                 return a
 419
 420         if "i" in pin.dir:
 421             if pin.xdr < 2:
 422                 pin_i  = get_ineg(pin.i,  i_invert)
 423             elif pin.xdr == 2:
 424                 pin_i0 = get_ineg(pin.i0, i_invert)
 425                 pin_i1 = get_ineg(pin.i1, i_invert)
 426         if "o" in pin.dir:
 427             if pin.xdr < 2:
 428                 pin_o  = get_oneg(pin.o,  o_invert)
 429             elif pin.xdr == 2:
 430                 pin_o0 = get_oneg(pin.o0, o_invert)
 431                 pin_o1 = get_oneg(pin.o1, o_invert)
 432
 433         i = o = t = None
 434         if "i" in pin.dir:
 435             i = Signal(pin.width, name="{}_xdr_i".format(pin.name))
 436         if "o" in pin.dir:
 437             o = Signal(pin.width, name="{}_xdr_o".format(pin.name))
 438         if pin.dir in ("oe", "io"):
 439             t = Signal(1,         name="{}_xdr_t".format(pin.name))
 440
 441         if pin.xdr == 0:
 442             if "i" in pin.dir:
 443                 i = pin_i
 444             if "o" in pin.dir:
 445                 o = pin_o
 446             if pin.dir in ("oe", "io"):
 447                 t = ~pin.oe
 448         elif pin.xdr == 1:
 449             # Note that currently nextpnr will not pack an FF (*FS1P3DX) into the PIO.
 450             if "i" in pin.dir:
 451                 get_ireg(pin.i_clk, i, pin_i)
 452             if "o" in pin.dir:
 453                 get_oreg(pin.o_clk, pin_o, o)
 454             if pin.dir in ("oe", "io"):
 455                 get_oreg(pin.o_clk, ~pin.oe, t)
 456         elif pin.xdr == 2:
 457             if "i" in pin.dir:
 458                 get_iddr(pin.i_clk, i, pin_i0, pin_i1)
 459             if "o" in pin.dir:
 460                 get_oddr(pin.o_clk, pin_o0, pin_o1, o)
 461             if pin.dir in ("oe", "io"):
 462                 # It looks like Diamond will not pack an OREG as a tristate register in a DDR PIO.
 463                 # It is not clear what is the recommended set of primitives for this task.
 464                 # Similarly, nextpnr will not pack anything as a tristate register in a DDR PIO.
 465                 get_oreg(pin.o_clk, ~pin.oe, t)
 466         else:
 467             assert False
 468
 469         return (i, o, t)
 470
 471     def get_input(self, pin, port, attrs, invert):
 472         self._check_feature("single-ended input", pin, attrs,
 473                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 474         m = Module()
 475         i, o, t = self._get_xdr_buffer(m, pin, i_invert=invert)
 476         for bit in range(len(port)):
 477             m.submodules["{}_{}".format(pin.name, bit)] = Instance("IB",
 478                 i_I=port[bit],
 479                 o_O=i[bit]
 480             )
 481         return m
 482
 483     def get_output(self, pin, port, attrs, invert):
 484         self._check_feature("single-ended output", pin, attrs,
 485                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 486         m = Module()
 487         i, o, t = self._get_xdr_buffer(m, pin, o_invert=invert)
 488         for bit in range(len(port)):
 489             m.submodules["{}_{}".format(pin.name, bit)] = Instance("OB",
 490                 i_I=o[bit],
 491                 o_O=port[bit]
 492             )
 493         return m
 494
 495     def get_tristate(self, pin, port, attrs, invert):
 496         self._check_feature("single-ended tristate", pin, attrs,
 497                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 498         m = Module()
 499         i, o, t = self._get_xdr_buffer(m, pin, o_invert=invert)
 500         for bit in range(len(port)):
 501             m.submodules["{}_{}".format(pin.name, bit)] = Instance("OBZ",
 502                 i_T=t,
 503                 i_I=o[bit],
 504                 o_O=port[bit]
 505             )
 506         return m
 507
 508     def get_input_output(self, pin, port, attrs, invert):
 509         self._check_feature("single-ended input/output", pin, attrs,
 510                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 511         m = Module()
 512         i, o, t = self._get_xdr_buffer(m, pin, i_invert=invert, o_invert=invert)
 513         for bit in range(len(port)):
 514             m.submodules["{}_{}".format(pin.name, bit)] = Instance("BB",
 515                 i_T=t,
 516                 i_I=o[bit],
 517                 o_O=i[bit],
 518                 io_B=port[bit]
 519             )
 520         return m
 521
 522     def get_diff_input(self, pin, p_port, n_port, attrs, invert):
 523         self._check_feature("differential input", pin, attrs,
 524                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 525         m = Module()
 526         i, o, t = self._get_xdr_buffer(m, pin, i_invert=invert)
 527         for bit in range(len(p_port)):
 528             m.submodules["{}_{}".format(pin.name, bit)] = Instance("IB",
 529                 i_I=p_port[bit],
 530                 o_O=i[bit]
 531             )
 532         return m
 533
 534     def get_diff_output(self, pin, p_port, n_port, attrs, invert):
 535         self._check_feature("differential output", pin, attrs,
 536                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 537         m = Module()
 538         i, o, t = self._get_xdr_buffer(m, pin, o_invert=invert)
 539         for bit in range(len(p_port)):
 540             m.submodules["{}_{}".format(pin.name, bit)] = Instance("OB",
 541                 i_I=o[bit],
 542                 o_O=p_port[bit],
 543             )
 544         return m
 545
 546     def get_diff_tristate(self, pin, p_port, n_port, attrs, invert):
 547         self._check_feature("differential tristate", pin, attrs,
 548                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 549         m = Module()
 550         i, o, t = self._get_xdr_buffer(m, pin, o_invert=invert)
 551         for bit in range(len(p_port)):
 552             m.submodules["{}_{}".format(pin.name, bit)] = Instance("OBZ",
 553                 i_T=t,
 554                 i_I=o[bit],
 555                 o_O=p_port[bit],
 556             )
 557         return m
 558
 559     def get_diff_input_output(self, pin, p_port, n_port, attrs, invert):
 560         self._check_feature("differential input/output", pin, attrs,
 561                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 562         m = Module()
 563         i, o, t = self._get_xdr_buffer(m, pin, i_invert=invert, o_invert=invert)
 564         for bit in range(len(p_port)):
 565             m.submodules["{}_{}".format(pin.name, bit)] = Instance("BB",
 566                 i_T=t,
 567                 i_I=o[bit],
 568                 o_O=i[bit],
 569                 io_B=p_port[bit],
 570             )
 571         return m
 572
 573     # CDC primitives are not currently specialized for ECP5.
 574     # While Diamond supports false path constraints; nextpnr-ecp5 does not.