nmigen/vendor/lattice_ecp5.py

   1 from abc import abstractproperty
   2
   3 from ..hdl import *
   4 from ..build import *
   5
   6
   7 __all__ = ["LatticeECP5Platform"]
   8
   9
  10 class LatticeECP5Platform(TemplatedPlatform):
  11     """
  12     Required tools:
  13         * ``yosys``
  14         * ``nextpnr-ecp5``
  15         * ``ecppack``
  16
  17     The environment is populated by running the script specified in the environment variable
  18     ``NMIGEN_Trellis_env``, if present.
  19
  20     Available overrides:
  21         * ``verbose``: enables logging of informational messages to standard error.
  22         * ``read_verilog_opts``: adds options for ``read_verilog`` Yosys command.
  23         * ``synth_opts``: adds options for ``synth_ecp5`` Yosys command.
  24         * ``script_after_read``: inserts commands after ``read_ilang`` in Yosys script.
  25         * ``script_after_synth``: inserts commands after ``synth_ecp5`` in Yosys script.
  26         * ``yosys_opts``: adds extra options for Yosys.
  27         * ``nextpnr_opts``: adds extra options for nextpnr.
  28         * ``ecppack_opts``: adds extra options for ecppack.
  29
  30     Build products:
  31         * ``{{name}}.rpt``: Yosys log.
  32         * ``{{name}}.json``: synthesized RTL.
  33         * ``{{name}}.tim``: nextpnr log.
  34         * ``{{name}}.config``: ASCII bitstream.
  35         * ``{{name}}.bit``: binary bitstream.
  36         * ``{{name}}.svf``: JTAG programming vector.
  37     """
  38
  39     toolchain = "Trellis"
  40
  41     device  = abstractproperty()
  42     package = abstractproperty()
  43     speed   = abstractproperty()
  44
  45     _nextpnr_device_options = {
  46         "LFE5U-12F":    "--25k",
  47         "LFE5U-25F":    "--25k",
  48         "LFE5U-45F":    "--45k",
  49         "LFE5U-85F":    "--85k",
  50         "LFE5UM-12F":   "--um-25k",
  51         "LFE5UM-25F":   "--um-25k",
  52         "LFE5UM-45F":   "--um-45k",
  53         "LFE5UM-85F":   "--um-85k",
  54         "LFE5UM5G-12F": "--um5g-25k",
  55         "LFE5UM5G-25F": "--um5g-25k",
  56         "LFE5UM5G-45F": "--um5g-45k",
  57         "LFE5UM5G-85F": "--um5g-85k",
  58     }
  59     _nextpnr_package_options = {
  60         "BG256": "caBGA256",
  61         "MG285": "csfBGA285",
  62         "BG381": "caBGA381",
  63         "BG554": "caBGA554",
  64         "BG756": "caBGA756",
  65     }
  66
  67     file_templates = {
  68         **TemplatedPlatform.build_script_templates,
  69         "{{name}}.il": r"""
  70             # {{autogenerated}}
  71             {{emit_design("rtlil")}}
  72         """,
  73         "{{name}}.ys": r"""
  74             # {{autogenerated}}
  75             {% for file in platform.iter_extra_files(".v") -%}
  76                 read_verilog {{get_override("read_opts")|options}} {{file}}
  77             {% endfor %}
  78             {% for file in platform.iter_extra_files(".sv") -%}
  79                 read_verilog -sv {{get_override("read_opts")|options}} {{file}}
  80             {% endfor %}
  81             read_ilang {{name}}.il
  82             {{get_override("script_after_read")|default("# (script_after_read placeholder)")}}
  83             synth_ecp5 {{get_override("synth_opts")|options}} -top {{name}}
  84             {{get_override("script_after_synth")|default("# (script_after_synth placeholder)")}}
  85             write_json {{name}}.json
  86         """,
  87         "{{name}}.lpf": r"""
  88             # {{autogenerated}}
  89             BLOCK ASYNCPATHS;
  90             BLOCK RESETPATHS;
  91             {% for port_name, pin_name, extras in platform.iter_port_constraints_bits() -%}
  92                 LOCATE COMP "{{port_name}}" SITE "{{pin_name}}";
  93                 IOBUF PORT "{{port_name}}"
  94                     {%- for key, value in extras.items() %} {{key}}={{value}}{% endfor %};
  95             {% endfor %}
  96             {% for signal, frequency in platform.iter_clock_constraints() -%}
  97                 FREQUENCY PORT "{{signal.name}}" {{frequency}} HZ;
  98             {% endfor %}
  99         """
 100     }
 101     command_templates = [
 102         r"""
 103         {{get_tool("yosys")}}
 104             {{quiet("-q")}}
 105             {{get_override("yosys_opts")|options}}
 106             -l {{name}}.rpt
 107             {{name}}.ys
 108         """,
 109         r"""
 110         {{get_tool("nextpnr-ecp5")}}
 111             {{quiet("--quiet")}}
 112             {{get_override("nextpnr_opts")|options}}
 113             --log {{name}}.tim
 114             {{platform._nextpnr_device_options[platform.device]}}
 115             --package {{platform._nextpnr_package_options[platform.package]|upper}}
 116             --speed {{platform.speed}}
 117             --json {{name}}.json
 118             --lpf {{name}}.lpf
 119             --textcfg {{name}}.config
 120         """,
 121         r"""
 122         {{get_tool("ecppack")}}
 123             {{verbose("--verbose")}}
 124             --input {{name}}.config
 125             --bit {{name}}.bit
 126             --svf {{name}}.svf
 127         """
 128     ]
 129
 130     def create_missing_domain(self, name):
 131         # No additional reset logic needed.
 132         return super().create_missing_domain(name)
 133
 134     _single_ended_io_types = [
 135         "HSUL12", "LVCMOS12", "LVCMOS15", "LVCMOS18", "LVCMOS25", "LVCMOS33", "LVTTL33",
 136         "SSTL135_I", "SSTL135_II", "SSTL15_I", "SSTL15_II", "SSTL18_I", "SSTL18_II",
 137     ]
 138     _differential_io_types = [
 139         "BLVDS25", "BLVDS25E", "HSUL12D", "LVCMOS18D", "LVCMOS25D", "LVCMOS33D",
 140         "LVDS", "LVDS25E", "LVPECL33", "LVPECL33E", "LVTTL33D", "MLVDS", "MLVDS25E",
 141         "SLVS", "SSTL135D_II", "SSTL15D_II", "SSTL18D_II", "SUBLVDS",
 142     ]
 143
 144     def should_skip_port_component(self, port, attrs, component):
 145         # On ECP5, a differential IO is placed by only instantiating an IO buffer primitive at
 146         # the PIOA or PIOC location, which is always the non-inverting pin.
 147         if attrs.get("IO_TYPE", "LVCMOS25") in self._differential_io_types and component == "n":
 148             return True
 149         return False
 150
 151     def _get_xdr_buffer(self, m, pin, i_invert=None, o_invert=None):
 152         def get_ireg(clk, d, q):
 153             for bit in range(len(q)):
 154                 m.submodules += Instance("IFS1P3DX",
 155                     i_SCLK=clk,
 156                     i_SP=Const(1),
 157                     i_CD=Const(0),
 158                     i_D=d[bit],
 159                     o_Q=q[bit]
 160                 )
 161
 162         def get_oreg(clk, d, q):
 163             for bit in range(len(q)):
 164                 m.submodules += Instance("OFS1P3DX",
 165                     i_SCLK=clk,
 166                     i_SP=Const(1),
 167                     i_CD=Const(0),
 168                     i_D=d[bit],
 169                     o_Q=q[bit]
 170                 )
 171
 172         def get_iddr(sclk, d, q0, q1):
 173             for bit in range(len(d)):
 174                 m.submodules += Instance("IDDRX1F",
 175                     i_SCLK=sclk,
 176                     i_RST=Const(0),
 177                     i_D=d[bit],
 178                     o_Q0=q0[bit], o_Q1=q1[bit]
 179                 )
 180
 181         def get_oddr(sclk, d0, d1, q):
 182             for bit in range(len(q)):
 183                 m.submodules += Instance("ODDRX1F",
 184                     i_SCLK=sclk,
 185                     i_RST=Const(0),
 186                     i_D0=d0[bit], i_D1=d1[bit],
 187                     o_Q=q[bit]
 188                 )
 189
 190         def get_ixor(z, invert):
 191             if invert is None:
 192                 return z
 193             else:
 194                 a = Signal.like(z, name_suffix="_x{}".format(1 if invert else 0))
 195                 for bit in range(len(z)):
 196                     m.submodules += Instance("LUT4",
 197                         p_INIT=0x5555 if invert else 0xaaaa,
 198                         i_A=a[bit],
 199                         i_B=Const(0),
 200                         i_C=Const(0),
 201                         i_D=Const(0),
 202                         o_Z=z[bit]
 203                     )
 204                 return a
 205
 206         def get_oxor(a, invert):
 207             if invert is None:
 208                 return a
 209             else:
 210                 z = Signal.like(a, name_suffix="_x{}".format(1 if invert else 0))
 211                 for bit in range(len(a)):
 212                     m.submodules += Instance("LUT4",
 213                         p_INIT=0x5555 if invert else 0xaaaa,
 214                         i_A=a[bit],
 215                         i_B=Const(0),
 216                         i_C=Const(0),
 217                         i_D=Const(0),
 218                         o_Z=z[bit]
 219                     )
 220                 return z
 221
 222         if "i" in pin.dir:
 223             if pin.xdr < 2:
 224                 pin_i  = get_ixor(pin.i,  i_invert)
 225             elif pin.xdr == 2:
 226                 pin_i0 = get_ixor(pin.i0, i_invert)
 227                 pin_i1 = get_ixor(pin.i1, i_invert)
 228         if "o" in pin.dir:
 229             if pin.xdr < 2:
 230                 pin_o  = get_oxor(pin.o,  o_invert)
 231             elif pin.xdr == 2:
 232                 pin_o0 = get_oxor(pin.o0, o_invert)
 233                 pin_o1 = get_oxor(pin.o1, o_invert)
 234
 235         i = o = t = None
 236         if "i" in pin.dir:
 237             i = Signal(pin.width, name="{}_xdr_i".format(pin.name))
 238         if "o" in pin.dir:
 239             o = Signal(pin.width, name="{}_xdr_o".format(pin.name))
 240         if pin.dir in ("oe", "io"):
 241             t = Signal(1,         name="{}_xdr_t".format(pin.name))
 242
 243         if pin.xdr == 0:
 244             if "i" in pin.dir:
 245                 i = pin_i
 246             if "o" in pin.dir:
 247                 o = pin_o
 248             if pin.dir in ("oe", "io"):
 249                 t = ~pin_oe
 250         elif pin.xdr == 1:
 251             # Note that currently nextpnr will not pack an FF (*FS1P3DX) into the PIO.
 252             if "i" in pin.dir:
 253                 get_ireg(pin.i_clk, i, pin_i)
 254             if "o" in pin.dir:
 255                 get_oreg(pin.o_clk, pin_o, o)
 256             if pin.dir in ("oe", "io"):
 257                 get_oreg(pin.o_clk, ~pin.oe, t)
 258         elif pin.xdr == 2:
 259             if "i" in pin.dir:
 260                 get_iddr(pin.i_clk, i, pin_i0, pin_i1)
 261             if "o" in pin.dir:
 262                 get_oddr(pin.o_clk, pin_o0, pin_o1, o)
 263             if pin.dir in ("oe", "io"):
 264                 # It looks like Diamond will not pack an OREG as a tristate register in a DDR PIO.
 265                 # It is not clear what is the recommended set of primitives for this task.
 266                 # Similarly, nextpnr will not pack anything as a tristate register in a DDR PIO.
 267                 get_oreg(pin.o_clk, ~pin.oe, t)
 268         else:
 269             assert False
 270
 271         return (i, o, t)
 272
 273     def get_input(self, pin, port, attrs, invert):
 274         self._check_feature("single-ended input", pin, attrs,
 275                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 276         m = Module()
 277         i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None)
 278         for bit in range(len(port)):
 279             m.submodules["{}_{}".format(pin.name, bit)] = Instance("IB",
 280                 i_I=port[bit],
 281                 o_O=i[bit]
 282             )
 283         return m
 284
 285     def get_output(self, pin, port, attrs, invert):
 286         self._check_feature("single-ended output", pin, attrs,
 287                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 288         m = Module()
 289         i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None)
 290         for bit in range(len(port)):
 291             m.submodules["{}_{}".format(pin.name, bit)] = Instance("OB",
 292                 i_I=o[bit],
 293                 o_O=port[bit]
 294             )
 295         return m
 296
 297     def get_tristate(self, pin, port, attrs, invert):
 298         self._check_feature("single-ended tristate", pin, attrs,
 299                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 300         m = Module()
 301         i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None)
 302         for bit in range(len(port)):
 303             m.submodules["{}_{}".format(pin.name, bit)] = Instance("OBZ",
 304                 i_T=t,
 305                 i_I=o[bit],
 306                 o_O=port[bit]
 307             )
 308         return m
 309
 310     def get_input_output(self, pin, port, attrs, invert):
 311         self._check_feature("single-ended input/output", pin, attrs,
 312                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 313         m = Module()
 314         i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None,
 315                                                o_invert=True if invert else None)
 316         for bit in range(len(port)):
 317             m.submodules["{}_{}".format(pin.name, bit)] = Instance("BB",
 318                 i_T=t,
 319                 i_I=o[bit],
 320                 o_O=i[bit],
 321                 io_B=port[bit]
 322             )
 323         return m
 324
 325     def get_diff_input(self, pin, p_port, n_port, attrs, invert):
 326         self._check_feature("differential input", pin, attrs,
 327                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 328         m = Module()
 329         i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None)
 330         for bit in range(len(p_port)):
 331             m.submodules["{}_{}".format(pin.name, bit)] = Instance("IB",
 332                 i_I=p_port[bit],
 333                 o_O=i[bit]
 334             )
 335         return m
 336
 337     def get_diff_output(self, pin, p_port, n_port, attrs, invert):
 338         self._check_feature("differential output", pin, attrs,
 339                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 340         m = Module()
 341         i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None)
 342         for bit in range(len(p_port)):
 343             m.submodules["{}_{}".format(pin.name, bit)] = Instance("OB",
 344                 i_I=o[bit],
 345                 o_O=p_port[bit],
 346             )
 347         return m
 348
 349     def get_diff_tristate(self, pin, p_port, n_port, attrs, invert):
 350         self._check_feature("differential tristate", pin, attrs,
 351                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 352         m = Module()
 353         i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None)
 354         for bit in range(len(p_port)):
 355             m.submodules["{}_{}".format(pin.name, bit)] = Instance("OBZ",
 356                 i_T=t,
 357                 i_I=o[bit],
 358                 o_O=p_port[bit],
 359             )
 360         return m
 361
 362     def get_diff_input_output(self, pin, p_port, n_port, attrs, invert):
 363         self._check_feature("differential input/output", pin, attrs,
 364                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 365         m = Module()
 366         i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None,
 367                                                o_invert=True if invert else None)
 368         for bit in range(len(p_port)):
 369             m.submodules["{}_{}".format(pin.name, bit)] = Instance("BB",
 370                 i_T=t,
 371                 i_I=o[bit],
 372                 o_O=i[bit],
 373                 io_B=p_port[bit],
 374             )
 375         return m