nmigen/vendor/lattice_ecp5.py

   1 from abc import abstractproperty
   2
   3 from ..hdl import *
   4 from ..build import *
   5
   6
   7 __all__ = ["LatticeECP5Platform"]
   8
   9
  10 class LatticeECP5Platform(TemplatedPlatform):
  11     """
  12     Trellis toolchain
  13     -----------------
  14
  15     Required tools:
  16         * ``yosys``
  17         * ``nextpnr-ecp5``
  18         * ``ecppack``
  19
  20     The environment is populated by running the script specified in the environment variable
  21     ``NMIGEN_ENV_Trellis``, if present.
  22
  23     Available overrides:
  24         * ``verbose``: enables logging of informational messages to standard error.
  25         * ``read_verilog_opts``: adds options for ``read_verilog`` Yosys command.
  26         * ``synth_opts``: adds options for ``synth_ecp5`` Yosys command.
  27         * ``script_after_read``: inserts commands after ``read_ilang`` in Yosys script.
  28         * ``script_after_synth``: inserts commands after ``synth_ecp5`` in Yosys script.
  29         * ``yosys_opts``: adds extra options for ``yosys``.
  30         * ``nextpnr_opts``: adds extra options for ``nextpnr-ecp5``.
  31         * ``ecppack_opts``: adds extra options for ``ecppack``.
  32         * ``add_preferences``: inserts commands at the end of the LPF file.
  33
  34     Build products:
  35         * ``{{name}}.rpt``: Yosys log.
  36         * ``{{name}}.json``: synthesized RTL.
  37         * ``{{name}}.tim``: nextpnr log.
  38         * ``{{name}}.config``: ASCII bitstream.
  39         * ``{{name}}.bit``: binary bitstream.
  40         * ``{{name}}.svf``: JTAG programming vector.
  41
  42     Diamond toolchain
  43     -----------------
  44
  45     Required tools:
  46         * ``pnmainc``
  47         * ``ddtcmd``
  48
  49     The environment is populated by running the script specified in the environment variable
  50     ``NMIGEN_ENV_Diamond``, if present.
  51
  52     Available overrides:
  53         * ``script_project``: inserts commands before ``prj_project save`` in Tcl script.
  54         * ``script_after_export``: inserts commands after ``prj_run Export`` in Tcl script.
  55         * ``add_preferences``: inserts commands at the end of the LPF file.
  56         * ``add_constraints``: inserts commands at the end of the XDC file.
  57
  58     Build products:
  59         * ``{{name}}_impl/{{name}}_impl.htm``: consolidated log.
  60         * ``{{name}}.bit``: binary bitstream.
  61         * ``{{name}}.svf``: JTAG programming vector.
  62     """
  63
  64     toolchain = None # selected when creating platform
  65
  66     device  = abstractproperty()
  67     package = abstractproperty()
  68     speed   = abstractproperty()
  69     grade   = "C" # [C]ommercial, [I]ndustrial
  70
  71     # Trellis templates
  72
  73     _nextpnr_device_options = {
  74         "LFE5U-12F":    "--12k",
  75         "LFE5U-25F":    "--25k",
  76         "LFE5U-45F":    "--45k",
  77         "LFE5U-85F":    "--85k",
  78         "LFE5UM-25F":   "--um-25k",
  79         "LFE5UM-45F":   "--um-45k",
  80         "LFE5UM-85F":   "--um-85k",
  81         "LFE5UM5G-25F": "--um5g-25k",
  82         "LFE5UM5G-45F": "--um5g-45k",
  83         "LFE5UM5G-85F": "--um5g-85k",
  84     }
  85     _nextpnr_package_options = {
  86         "BG256": "caBGA256",
  87         "MG285": "csfBGA285",
  88         "BG381": "caBGA381",
  89         "BG554": "caBGA554",
  90         "BG756": "caBGA756",
  91     }
  92
  93     _trellis_required_tools = [
  94         "yosys",
  95         "nextpnr-ecp5",
  96         "ecppack"
  97     ]
  98     _trellis_file_templates = {
  99         **TemplatedPlatform.build_script_templates,
 100         "{{name}}.il": r"""
 101             # {{autogenerated}}
 102             {{emit_rtlil()}}
 103         """,
 104         "{{name}}.debug.v": r"""
 105             /* {{autogenerated}} */
 106             {{emit_debug_verilog()}}
 107         """,
 108         "{{name}}.ys": r"""
 109             # {{autogenerated}}
 110             {% for file in platform.iter_extra_files(".v") -%}
 111                 read_verilog {{get_override("read_verilog_opts")|options}} {{file}}
 112             {% endfor %}
 113             {% for file in platform.iter_extra_files(".sv") -%}
 114                 read_verilog -sv {{get_override("read_verilog_opts")|options}} {{file}}
 115             {% endfor %}
 116             {% for file in platform.iter_extra_files(".il") -%}
 117                 read_ilang {{file}}
 118             {% endfor %}
 119             read_ilang {{name}}.il
 120             {{get_override("script_after_read")|default("# (script_after_read placeholder)")}}
 121             synth_ecp5 {{get_override("synth_opts")|options}} -top {{name}}
 122             {{get_override("script_after_synth")|default("# (script_after_synth placeholder)")}}
 123             write_json {{name}}.json
 124         """,
 125         "{{name}}.lpf": r"""
 126             # {{autogenerated}}
 127             BLOCK ASYNCPATHS;
 128             BLOCK RESETPATHS;
 129             {% for port_name, pin_name, attrs in platform.iter_port_constraints_bits() -%}
 130                 LOCATE COMP "{{port_name}}" SITE "{{pin_name}}";
 131                 {% if attrs -%}
 132                 IOBUF PORT "{{port_name}}"
 133                     {%- for key, value in attrs.items() %} {{key}}={{value}}{% endfor %};
 134                 {% endif %}
 135             {% endfor %}
 136             {% for net_signal, port_signal, frequency in platform.iter_clock_constraints() -%}
 137                 {% if port_signal is not none -%}
 138                     FREQUENCY PORT "{{port_signal.name}}" {{frequency}} HZ;
 139                 {% else -%}
 140                     FREQUENCY NET "{{net_signal|hierarchy(".")}}" {{frequency}} HZ;
 141                 {% endif %}
 142             {% endfor %}
 143             {{get_override("add_preferences")|default("# (add_preferences placeholder)")}}
 144         """
 145     }
 146     _trellis_command_templates = [
 147         r"""
 148         {{invoke_tool("yosys")}}
 149             {{quiet("-q")}}
 150             {{get_override("yosys_opts")|options}}
 151             -l {{name}}.rpt
 152             {{name}}.ys
 153         """,
 154         r"""
 155         {{invoke_tool("nextpnr-ecp5")}}
 156             {{quiet("--quiet")}}
 157             {{get_override("nextpnr_opts")|options}}
 158             --log {{name}}.tim
 159             {{platform._nextpnr_device_options[platform.device]}}
 160             --package {{platform._nextpnr_package_options[platform.package]|upper}}
 161             --speed {{platform.speed}}
 162             --json {{name}}.json
 163             --lpf {{name}}.lpf
 164             --textcfg {{name}}.config
 165         """,
 166         r"""
 167         {{invoke_tool("ecppack")}}
 168             {{verbose("--verbose")}}
 169             {{get_override("ecppack_opts")|options}}
 170             --input {{name}}.config
 171             --bit {{name}}.bit
 172             --svf {{name}}.svf
 173         """
 174     ]
 175
 176     # Diamond templates
 177
 178     _diamond_required_tools = [
 179         "pnmainc",
 180         "ddtcmd"
 181     ]
 182     _diamond_file_templates = {
 183         **TemplatedPlatform.build_script_templates,
 184         "build_{{name}}.sh": r"""
 185             # {{autogenerated}}
 186             set -e{{verbose("x")}}
 187             if [ -z "$BASH" ] ; then exec /bin/bash "$0" "$@"; fi
 188             if [ -n "${{platform._toolchain_env_var}}" ]; then
 189                 bindir=$(dirname "${{platform._toolchain_env_var}}")
 190                 . "${{platform._toolchain_env_var}}"
 191             fi
 192             {{emit_commands("sh")}}
 193         """,
 194         "{{name}}.v": r"""
 195             /* {{autogenerated}} */
 196             {{emit_verilog()}}
 197         """,
 198         "{{name}}.debug.v": r"""
 199             /* {{autogenerated}} */
 200             {{emit_debug_verilog()}}
 201         """,
 202         "{{name}}.tcl": r"""
 203             prj_project new -name {{name}} -impl impl -impl_dir top_impl \
 204                 -dev {{platform.device}}-{{platform.speed}}{{platform.package}}{{platform.grade}} \
 205                 -lpf {{name}}.lpf \
 206                 -synthesis synplify
 207             {% for file in platform.iter_extra_files(".v", ".sv", ".vhd", ".vhdl") -%}
 208                 prj_src add {{file|tcl_escape}}
 209             {% endfor %}
 210             prj_src add {{name}}.v
 211             prj_impl option top {{name}}
 212             prj_src add {{name}}.sdc
 213             {{get_override("script_project")|default("# (script_project placeholder)")}}
 214             prj_project save
 215             prj_run Synthesis -impl impl -forceAll
 216             prj_run Translate -impl impl -forceAll
 217             prj_run Map -impl impl -forceAll
 218             prj_run PAR -impl impl -forceAll
 219             prj_run Export -impl impl -forceAll -task Bitgen
 220             {{get_override("script_after_export")|default("# (script_after_export placeholder)")}}
 221         """,
 222         "{{name}}.lpf": r"""
 223             # {{autogenerated}}
 224             BLOCK ASYNCPATHS;
 225             BLOCK RESETPATHS;
 226             {% for port_name, pin_name, extras in platform.iter_port_constraints_bits() -%}
 227                 LOCATE COMP "{{port_name}}" SITE "{{pin_name}}";
 228                 IOBUF PORT "{{port_name}}"
 229                     {%- for key, value in extras.items() %} {{key}}={{value}}{% endfor %};
 230             {% endfor %}
 231             {{get_override("add_preferences")|default("# (add_preferences placeholder)")}}
 232         """,
 233         "{{name}}.sdc": r"""
 234             {% for net_signal, port_signal, frequency in platform.iter_clock_constraints() -%}
 235                 {% if port_signal is not none -%}
 236                     create_clock -name {{port_signal.name|tcl_escape}} -period {{1000000000/frequency}} [get_ports {{port_signal.name|tcl_escape}}]
 237                 {% else -%}
 238                     create_clock -name {{net_signal.name|tcl_escape}} -period {{1000000000/frequency}} [get_nets {{net_signal|hierarchy("/")|tcl_escape}}]
 239                 {% endif %}
 240             {% endfor %}
 241             {{get_override("add_constraints")|default("# (add_constraints placeholder)")}}
 242         """,
 243     }
 244     _diamond_command_templates = [
 245         # These don't have any usable command-line option overrides.
 246         r"""
 247         {{invoke_tool("pnmainc")}}
 248             {{name}}.tcl
 249         """,
 250         r"""
 251         {{invoke_tool("ddtcmd")}}
 252             -oft -bit
 253             -if {{name}}_impl/{{name}}_impl.bit -of {{name}}.bit
 254         """,
 255         r"""
 256         {{invoke_tool("ddtcmd")}}
 257             -oft -svfsingle -revd -op "Fast Program"
 258             -if {{name}}_impl/{{name}}_impl.bit -of {{name}}.svf
 259         """,
 260     ]
 261
 262     # Common logic
 263
 264     def __init__(self, *, toolchain="Trellis"):
 265         super().__init__()
 266
 267         assert toolchain in ("Trellis", "Diamond")
 268         self.toolchain = toolchain
 269
 270     @property
 271     def required_tools(self):
 272         if self.toolchain == "Trellis":
 273             return self._trellis_required_tools
 274         if self.toolchain == "Diamond":
 275             return self._diamond_required_tools
 276         assert False
 277
 278     @property
 279     def file_templates(self):
 280         if self.toolchain == "Trellis":
 281             return self._trellis_file_templates
 282         if self.toolchain == "Diamond":
 283             return self._diamond_file_templates
 284         assert False
 285
 286     @property
 287     def command_templates(self):
 288         if self.toolchain == "Trellis":
 289             return self._trellis_command_templates
 290         if self.toolchain == "Diamond":
 291             return self._diamond_command_templates
 292         assert False
 293
 294     @property
 295     def default_clk_constraint(self):
 296         if self.default_clk == "OSCG":
 297             return Clock(310e6 / self.oscg_div)
 298         return super().default_clk_constraint
 299
 300     def create_missing_domain(self, name):
 301         # Lattice ECP5 devices have two global set/reset signals: PUR, which is driven at startup
 302         # by the configuration logic and unconditionally resets every storage element, and GSR,
 303         # which is driven by user logic and each storage element may be configured as affected or
 304         # unaffected by GSR. PUR is purely asynchronous, so even though it is a low-skew global
 305         # network, its deassertion may violate a setup/hold constraint with relation to a user
 306         # clock. To avoid this, a GSR/SGSR instance should be driven synchronized to user clock.
 307         if name == "sync" and self.default_clk is not None:
 308             m = Module()
 309             if self.default_clk == "OSCG":
 310                 if not hasattr(self, "oscg_div"):
 311                     raise ValueError("OSCG divider (oscg_div) must be an integer between 2 "
 312                                      "and 128")
 313                 if not isinstance(self.oscg_div, int) or self.oscg_div < 2 or self.oscg_div > 128:
 314                     raise ValueError("OSCG divider (oscg_div) must be an integer between 2 "
 315                                      "and 128, not {!r}"
 316                                      .format(self.oscg_div))
 317                 clk_i = Signal()
 318                 m.submodules += Instance("OSCG", p_DIV=self.oscg_div, o_OSC=clk_i)
 319             else:
 320                 clk_i = self.request(self.default_clk).i
 321             if self.default_rst is not None:
 322                 rst_i = self.request(self.default_rst).i
 323             else:
 324                 rst_i = Const(0)
 325
 326             gsr0 = Signal()
 327             gsr1 = Signal()
 328             # There is no end-of-startup signal on ECP5, but PUR is released after IOB enable, so
 329             # a simple reset synchronizer (with PUR as the asynchronous reset) does the job.
 330             m.submodules += [
 331                 Instance("FD1S3AX", p_GSR="DISABLED", i_CK=clk_i, i_D=~rst_i, o_Q=gsr0),
 332                 Instance("FD1S3AX", p_GSR="DISABLED", i_CK=clk_i, i_D=gsr0,   o_Q=gsr1),
 333                 # Although we already synchronize the reset input to user clock, SGSR has dedicated
 334                 # clock routing to the center of the FPGA; use that just in case it turns out to be
 335                 # more reliable. (None of this is documented.)
 336                 Instance("SGSR", i_CLK=clk_i, i_GSR=gsr1),
 337             ]
 338             # GSR implicitly connects to every appropriate storage element. As such, the sync
 339             # domain is reset-less; domains driven by other clocks would need to have dedicated
 340             # reset circuitry or otherwise meet setup/hold constraints on their own.
 341             m.domains += ClockDomain("sync", reset_less=True)
 342             m.d.comb += ClockSignal("sync").eq(clk_i)
 343             return m
 344
 345     _single_ended_io_types = [
 346         "HSUL12", "LVCMOS12", "LVCMOS15", "LVCMOS18", "LVCMOS25", "LVCMOS33", "LVTTL33",
 347         "SSTL135_I", "SSTL135_II", "SSTL15_I", "SSTL15_II", "SSTL18_I", "SSTL18_II",
 348     ]
 349     _differential_io_types = [
 350         "BLVDS25", "BLVDS25E", "HSUL12D", "LVCMOS18D", "LVCMOS25D", "LVCMOS33D",
 351         "LVDS", "LVDS25E", "LVPECL33", "LVPECL33E", "LVTTL33D", "MLVDS", "MLVDS25E",
 352         "SLVS", "SSTL135D_II", "SSTL15D_II", "SSTL18D_II", "SUBLVDS",
 353     ]
 354
 355     def should_skip_port_component(self, port, attrs, component):
 356         # On ECP5, a differential IO is placed by only instantiating an IO buffer primitive at
 357         # the PIOA or PIOC location, which is always the non-inverting pin.
 358         if attrs.get("IO_TYPE", "LVCMOS25") in self._differential_io_types and component == "n":
 359             return True
 360         return False
 361
 362     def _get_xdr_buffer(self, m, pin, *, i_invert=False, o_invert=False):
 363         def get_ireg(clk, d, q):
 364             for bit in range(len(q)):
 365                 m.submodules += Instance("IFS1P3DX",
 366                     i_SCLK=clk,
 367                     i_SP=Const(1),
 368                     i_CD=Const(0),
 369                     i_D=d[bit],
 370                     o_Q=q[bit]
 371                 )
 372
 373         def get_oreg(clk, d, q):
 374             for bit in range(len(q)):
 375                 m.submodules += Instance("OFS1P3DX",
 376                     i_SCLK=clk,
 377                     i_SP=Const(1),
 378                     i_CD=Const(0),
 379                     i_D=d[bit],
 380                     o_Q=q[bit]
 381                 )
 382
 383         def get_iddr(sclk, d, q0, q1):
 384             for bit in range(len(d)):
 385                 m.submodules += Instance("IDDRX1F",
 386                     i_SCLK=sclk,
 387                     i_RST=Const(0),
 388                     i_D=d[bit],
 389                     o_Q0=q0[bit], o_Q1=q1[bit]
 390                 )
 391
 392         def get_iddrx2(sclk, eclk, d, q0, q1, q2, q3):
 393             for bit in range(len(d)):
 394                 m.submodules += Instance("IDDRX2F",
 395                     i_SCLK=sclk,
 396                     i_ECLK=eclk,
 397                     i_RST=Const(0),
 398                     i_D=d[bit],
 399                     o_Q0=q0[bit], o_Q1=q1[bit], o_Q2=q2[bit], o_Q3=q3[bit]
 400                 )
 401
 402         def get_oddr(sclk, d0, d1, q):
 403             for bit in range(len(q)):
 404                 m.submodules += Instance("ODDRX1F",
 405                     i_SCLK=sclk,
 406                     i_RST=Const(0),
 407                     i_D0=d0[bit], i_D1=d1[bit],
 408                     o_Q=q[bit]
 409                 )
 410
 411         def get_oddrx2(sclk, eclk, d0, d1, d2, d3, q):
 412             for bit in range(len(q)):
 413                 m.submodules += Instance("ODDRX2F",
 414                     i_SCLK=sclk,
 415                     i_ECLK=eclk,
 416                     i_RST=Const(0),
 417                     i_D0=d0[bit], i_D1=d1[bit], i_D2=d2[bit], i_D3=d3[bit],
 418                     o_Q=q[bit]
 419                 )
 420
 421         def get_ineg(z, invert):
 422             if invert:
 423                 a = Signal.like(z, name_suffix="_n")
 424                 m.d.comb += z.eq(~a)
 425                 return a
 426             else:
 427                 return z
 428
 429         def get_oneg(a, invert):
 430             if invert:
 431                 z = Signal.like(a, name_suffix="_n")
 432                 m.d.comb += z.eq(~a)
 433                 return z
 434             else:
 435                 return a
 436
 437         if "i" in pin.dir:
 438             if pin.xdr < 2:
 439                 pin_i  = get_ineg(pin.i,  i_invert)
 440             elif pin.xdr == 2:
 441                 pin_i0 = get_ineg(pin.i0, i_invert)
 442                 pin_i1 = get_ineg(pin.i1, i_invert)
 443             elif pin.xdr == 4:
 444                 pin_i0 = get_ineg(pin.i0, i_invert)
 445                 pin_i1 = get_ineg(pin.i1, i_invert)
 446                 pin_i2 = get_ineg(pin.i2, i_invert)
 447                 pin_i3 = get_ineg(pin.i3, i_invert)
 448         if "o" in pin.dir:
 449             if pin.xdr < 2:
 450                 pin_o  = get_oneg(pin.o,  o_invert)
 451             elif pin.xdr == 2:
 452                 pin_o0 = get_oneg(pin.o0, o_invert)
 453                 pin_o1 = get_oneg(pin.o1, o_invert)
 454             elif pin.xdr == 4:
 455                 pin_o0 = get_oneg(pin.o0, o_invert)
 456                 pin_o1 = get_oneg(pin.o1, o_invert)
 457                 pin_o2 = get_oneg(pin.o2, o_invert)
 458                 pin_o3 = get_oneg(pin.o3, o_invert)
 459
 460         i = o = t = None
 461         if "i" in pin.dir:
 462             i = Signal(pin.width, name="{}_xdr_i".format(pin.name))
 463         if "o" in pin.dir:
 464             o = Signal(pin.width, name="{}_xdr_o".format(pin.name))
 465         if pin.dir in ("oe", "io"):
 466             t = Signal(1,         name="{}_xdr_t".format(pin.name))
 467
 468         if pin.xdr == 0:
 469             if "i" in pin.dir:
 470                 i = pin_i
 471             if "o" in pin.dir:
 472                 o = pin_o
 473             if pin.dir in ("oe", "io"):
 474                 t = ~pin.oe
 475         elif pin.xdr == 1:
 476             # Note that currently nextpnr will not pack an FF (*FS1P3DX) into the PIO.
 477             if "i" in pin.dir:
 478                 get_ireg(pin.i_clk, i, pin_i)
 479             if "o" in pin.dir:
 480                 get_oreg(pin.o_clk, pin_o, o)
 481             if pin.dir in ("oe", "io"):
 482                 get_oreg(pin.o_clk, ~pin.oe, t)
 483         elif pin.xdr == 2:
 484             if "i" in pin.dir:
 485                 get_iddr(pin.i_clk, i, pin_i0, pin_i1)
 486             if "o" in pin.dir:
 487                 get_oddr(pin.o_clk, pin_o0, pin_o1, o)
 488             if pin.dir in ("oe", "io"):
 489                 # It looks like Diamond will not pack an OREG as a tristate register in a DDR PIO.
 490                 # It is not clear what is the recommended set of primitives for this task.
 491                 # Similarly, nextpnr will not pack anything as a tristate register in a DDR PIO.
 492                 get_oreg(pin.o_clk, ~pin.oe, t)
 493         elif pin.xdr == 4:
 494             if "i" in pin.dir:
 495                 get_iddrx2(pin.i_clk, pin.i_fclk, i, pin_i0, pin_i1, pin_i2, pin_i3)
 496             if "o" in pin.dir:
 497                 get_oddrx2(pin.o_clk, pin.o_fclk, pin_o0, pin_o1, pin_o2, pin_o3, o)
 498             if pin.dir in ("oe", "io"):
 499                 get_oreg(pin.o_clk, ~pin.oe, t)
 500         else:
 501             assert False
 502
 503         return (i, o, t)
 504
 505     def get_input(self, pin, port, attrs, invert):
 506         self._check_feature("single-ended input", pin, attrs,
 507                             valid_xdrs=(0, 1, 2, 4), valid_attrs=True)
 508         m = Module()
 509         i, o, t = self._get_xdr_buffer(m, pin, i_invert=invert)
 510         for bit in range(len(port)):
 511             m.submodules["{}_{}".format(pin.name, bit)] = Instance("IB",
 512                 i_I=port[bit],
 513                 o_O=i[bit]
 514             )
 515         return m
 516
 517     def get_output(self, pin, port, attrs, invert):
 518         self._check_feature("single-ended output", pin, attrs,
 519                             valid_xdrs=(0, 1, 2, 4), valid_attrs=True)
 520         m = Module()
 521         i, o, t = self._get_xdr_buffer(m, pin, o_invert=invert)
 522         for bit in range(len(port)):
 523             m.submodules["{}_{}".format(pin.name, bit)] = Instance("OB",
 524                 i_I=o[bit],
 525                 o_O=port[bit]
 526             )
 527         return m
 528
 529     def get_tristate(self, pin, port, attrs, invert):
 530         self._check_feature("single-ended tristate", pin, attrs,
 531                             valid_xdrs=(0, 1, 2, 4), valid_attrs=True)
 532         m = Module()
 533         i, o, t = self._get_xdr_buffer(m, pin, o_invert=invert)
 534         for bit in range(len(port)):
 535             m.submodules["{}_{}".format(pin.name, bit)] = Instance("OBZ",
 536                 i_T=t,
 537                 i_I=o[bit],
 538                 o_O=port[bit]
 539             )
 540         return m
 541
 542     def get_input_output(self, pin, port, attrs, invert):
 543         self._check_feature("single-ended input/output", pin, attrs,
 544                             valid_xdrs=(0, 1, 2, 4), valid_attrs=True)
 545         m = Module()
 546         i, o, t = self._get_xdr_buffer(m, pin, i_invert=invert, o_invert=invert)
 547         for bit in range(len(port)):
 548             m.submodules["{}_{}".format(pin.name, bit)] = Instance("BB",
 549                 i_T=t,
 550                 i_I=o[bit],
 551                 o_O=i[bit],
 552                 io_B=port[bit]
 553             )
 554         return m
 555
 556     def get_diff_input(self, pin, p_port, n_port, attrs, invert):
 557         self._check_feature("differential input", pin, attrs,
 558                             valid_xdrs=(0, 1, 2, 4), valid_attrs=True)
 559         m = Module()
 560         i, o, t = self._get_xdr_buffer(m, pin, i_invert=invert)
 561         for bit in range(len(p_port)):
 562             m.submodules["{}_{}".format(pin.name, bit)] = Instance("IB",
 563                 i_I=p_port[bit],
 564                 o_O=i[bit]
 565             )
 566         return m
 567
 568     def get_diff_output(self, pin, p_port, n_port, attrs, invert):
 569         self._check_feature("differential output", pin, attrs,
 570                             valid_xdrs=(0, 1, 2, 4), valid_attrs=True)
 571         m = Module()
 572         i, o, t = self._get_xdr_buffer(m, pin, o_invert=invert)
 573         for bit in range(len(p_port)):
 574             m.submodules["{}_{}".format(pin.name, bit)] = Instance("OB",
 575                 i_I=o[bit],
 576                 o_O=p_port[bit],
 577             )
 578         return m
 579
 580     def get_diff_tristate(self, pin, p_port, n_port, attrs, invert):
 581         self._check_feature("differential tristate", pin, attrs,
 582                             valid_xdrs=(0, 1, 2, 4), valid_attrs=True)
 583         m = Module()
 584         i, o, t = self._get_xdr_buffer(m, pin, o_invert=invert)
 585         for bit in range(len(p_port)):
 586             m.submodules["{}_{}".format(pin.name, bit)] = Instance("OBZ",
 587                 i_T=t,
 588                 i_I=o[bit],
 589                 o_O=p_port[bit],
 590             )
 591         return m
 592
 593     def get_diff_input_output(self, pin, p_port, n_port, attrs, invert):
 594         self._check_feature("differential input/output", pin, attrs,
 595                             valid_xdrs=(0, 1, 2, 4), valid_attrs=True)
 596         m = Module()
 597         i, o, t = self._get_xdr_buffer(m, pin, i_invert=invert, o_invert=invert)
 598         for bit in range(len(p_port)):
 599             m.submodules["{}_{}".format(pin.name, bit)] = Instance("BB",
 600                 i_T=t,
 601                 i_I=o[bit],
 602                 o_O=i[bit],
 603                 io_B=p_port[bit],
 604             )
 605         return m
 606
 607     # CDC primitives are not currently specialized for ECP5.
 608     # While Diamond supports false path constraints; nextpnr-ecp5 does not.