nmigen/vendor/lattice_ecp5.py

   1 from abc import abstractproperty
   2
   3 from ..hdl import *
   4 from ..build import *
   5
   6
   7 __all__ = ["LatticeECP5Platform"]
   8
   9
  10 class LatticeECP5Platform(TemplatedPlatform):
  11     """
  12     Required tools:
  13         * ``yosys``
  14         * ``nextpnr-ecp5``
  15         * ``ecppack``
  16
  17     The environment is populated by running the script specified in the environment variable
  18     ``NMIGEN_Trellis_env``, if present.
  19
  20     Available overrides:
  21         * ``verbose``: enables logging of informational messages to standard error.
  22         * ``read_verilog_opts``: adds options for ``read_verilog`` Yosys command.
  23         * ``synth_opts``: adds options for ``synth_ecp5`` Yosys command.
  24         * ``script_after_read``: inserts commands after ``read_ilang`` in Yosys script.
  25         * ``script_after_synth``: inserts commands after ``synth_ecp5`` in Yosys script.
  26         * ``yosys_opts``: adds extra options for Yosys.
  27         * ``nextpnr_opts``: adds extra options for nextpnr.
  28         * ``ecppack_opts``: adds extra options for ecppack.
  29
  30     Build products:
  31         * ``{{name}}.rpt``: Yosys log.
  32         * ``{{name}}.json``: synthesized RTL.
  33         * ``{{name}}.tim``: nextpnr log.
  34         * ``{{name}}.config``: ASCII bitstream.
  35         * ``{{name}}.bit``: binary bitstream.
  36         * ``{{name}}.svf``: JTAG programming vector.
  37     """
  38
  39     toolchain = "Trellis"
  40
  41     device  = abstractproperty()
  42     package = abstractproperty()
  43     speed   = abstractproperty()
  44
  45     _nextpnr_device_options = {
  46         "LFE5U-12F":    "--25k",
  47         "LFE5U-25F":    "--25k",
  48         "LFE5U-45F":    "--45k",
  49         "LFE5U-85F":    "--85k",
  50         "LFE5UM-12F":   "--um-25k",
  51         "LFE5UM-25F":   "--um-25k",
  52         "LFE5UM-45F":   "--um-45k",
  53         "LFE5UM-85F":   "--um-85k",
  54         "LFE5UM5G-12F": "--um5g-25k",
  55         "LFE5UM5G-25F": "--um5g-25k",
  56         "LFE5UM5G-45F": "--um5g-45k",
  57         "LFE5UM5G-85F": "--um5g-85k",
  58     }
  59     _nextpnr_package_options = {
  60         "BG256": "caBGA256",
  61         "MG285": "csfBGA285",
  62         "BG381": "caBGA381",
  63         "BG554": "caBGA554",
  64         "BG756": "caBGA756",
  65     }
  66
  67     file_templates = {
  68         **TemplatedPlatform.build_script_templates,
  69         "{{name}}.il": r"""
  70             # {{autogenerated}}
  71             {{emit_design("rtlil")}}
  72         """,
  73         "{{name}}.ys": r"""
  74             # {{autogenerated}}
  75             {% for file in platform.iter_extra_files(".v") -%}
  76                 read_verilog {{get_override("read_opts")|options}} {{file}}
  77             {% endfor %}
  78             {% for file in platform.iter_extra_files(".sv") -%}
  79                 read_verilog -sv {{get_override("read_opts")|options}} {{file}}
  80             {% endfor %}
  81             read_ilang {{name}}.il
  82             {{get_override("script_after_read")|default("# (script_after_read placeholder)")}}
  83             synth_ecp5 {{get_override("synth_opts")|options}} -top {{name}}
  84             {{get_override("script_after_synth")|default("# (script_after_synth placeholder)")}}
  85             write_json {{name}}.json
  86         """,
  87         "{{name}}.lpf": r"""
  88             # {{autogenerated}}
  89             BLOCK ASYNCPATHS;
  90             BLOCK RESETPATHS;
  91             {% for port_name, pin_name, extras in platform.iter_port_constraints_bits() -%}
  92                 LOCATE COMP "{{port_name}}" SITE "{{pin_name}}";
  93                 IOBUF PORT "{{port_name}}"
  94                     {%- for key, value in extras.items() %} {{key}}={{value}}{% endfor %};
  95             {% endfor %}
  96             {% for signal, frequency in platform.iter_clock_constraints() -%}
  97                 FREQUENCY PORT "{{signal.name}}" {{frequency}} HZ;
  98             {% endfor %}
  99         """
 100     }
 101     command_templates = [
 102         r"""
 103         {{get_tool("yosys")}}
 104             {{quiet("-q")}}
 105             {{get_override("yosys_opts")|options}}
 106             -l {{name}}.rpt
 107             {{name}}.ys
 108         """,
 109         r"""
 110         {{get_tool("nextpnr-ecp5")}}
 111             {{quiet("--quiet")}}
 112             {{get_override("nextpnr_opts")|options}}
 113             --log {{name}}.tim
 114             {{platform._nextpnr_device_options[platform.device]}}
 115             --package {{platform._nextpnr_package_options[platform.package]|upper}}
 116             --speed {{platform.speed}}
 117             --json {{name}}.json
 118             --lpf {{name}}.lpf
 119             --textcfg {{name}}.config
 120         """,
 121         r"""
 122         {{get_tool("ecppack")}}
 123             {{verbose("--verbose")}}
 124             --input {{name}}.config
 125             --bit {{name}}.bit
 126             --svf {{name}}.svf
 127         """
 128     ]
 129
 130     _single_ended_io_types = [
 131         "HSUL12", "LVCMOS12", "LVCMOS15", "LVCMOS18", "LVCMOS25", "LVCMOS33", "LVTTL33",
 132         "SSTL135_I", "SSTL135_II", "SSTL15_I", "SSTL15_II", "SSTL18_I", "SSTL18_II",
 133     ]
 134     _differential_io_types = [
 135         "BLVDS25", "BLVDS25E", "HSUL12D", "LVCMOS18D", "LVCMOS25D", "LVCMOS33D",
 136         "LVDS", "LVDS25E", "LVPECL33", "LVPECL33E", "LVTTL33D", "MLVDS", "MLVDS25E",
 137         "SLVS", "SSTL135D_II", "SSTL15D_II", "SSTL18D_II", "SUBLVDS",
 138     ]
 139
 140     def should_skip_port_component(self, port, attrs, component):
 141         # On ECP5, a differential IO is placed by only instantiating an IO buffer primitive at
 142         # the PIOA or PIOC location, which is always the non-inverting pin.
 143         if attrs.get("IO_TYPE", "LVCMOS25") in self._differential_io_types and component == "n":
 144             return True
 145         return False
 146
 147     def _get_xdr_buffer(self, m, pin, i_invert=None, o_invert=None):
 148         def get_ireg(clk, d, q):
 149             for bit in range(len(q)):
 150                 m.submodules += Instance("IFS1P3DX",
 151                     i_SCLK=clk,
 152                     i_SP=Const(1),
 153                     i_CD=Const(0),
 154                     i_D=d[bit],
 155                     o_Q=q[bit]
 156                 )
 157
 158         def get_oreg(clk, d, q):
 159             for bit in range(len(q)):
 160                 m.submodules += Instance("OFS1P3DX",
 161                     i_SCLK=clk,
 162                     i_SP=Const(1),
 163                     i_CD=Const(0),
 164                     i_D=d[bit],
 165                     o_Q=q[bit]
 166                 )
 167
 168         def get_iddr(sclk, d, q0, q1):
 169             for bit in range(len(d)):
 170                 m.submodules += Instance("IDDRX1F",
 171                     i_SCLK=sclk,
 172                     i_RST=Const(0),
 173                     i_D=d[bit],
 174                     o_Q0=q0[bit], o_Q1=q1[bit]
 175                 )
 176
 177         def get_oddr(sclk, d0, d1, q):
 178             for bit in range(len(q)):
 179                 m.submodules += Instance("ODDRX1F",
 180                     i_SCLK=sclk,
 181                     i_RST=Const(0),
 182                     i_D0=d0[bit], i_D1=d1[bit],
 183                     o_Q=q[bit]
 184                 )
 185
 186         def get_ixor(z, invert):
 187             if invert is None:
 188                 return z
 189             else:
 190                 a = Signal.like(z, name_suffix="_x{}".format(1 if invert else 0))
 191                 for bit in range(len(z)):
 192                     m.submodules += Instance("LUT4",
 193                         p_INIT=0x5555 if invert else 0xaaaa,
 194                         i_A=a[bit],
 195                         i_B=Const(0),
 196                         i_C=Const(0),
 197                         i_D=Const(0),
 198                         o_Z=z[bit]
 199                     )
 200                 return a
 201
 202         def get_oxor(a, invert):
 203             if invert is None:
 204                 return a
 205             else:
 206                 z = Signal.like(a, name_suffix="_x{}".format(1 if invert else 0))
 207                 for bit in range(len(a)):
 208                     m.submodules += Instance("LUT4",
 209                         p_INIT=0x5555 if invert else 0xaaaa,
 210                         i_A=a[bit],
 211                         i_B=Const(0),
 212                         i_C=Const(0),
 213                         i_D=Const(0),
 214                         o_Z=z[bit]
 215                     )
 216                 return z
 217
 218         if "i" in pin.dir:
 219             if pin.xdr < 2:
 220                 pin_i  = get_ixor(pin.i,  i_invert)
 221             elif pin.xdr == 2:
 222                 pin_i0 = get_ixor(pin.i0, i_invert)
 223                 pin_i1 = get_ixor(pin.i1, i_invert)
 224         if "o" in pin.dir:
 225             if pin.xdr < 2:
 226                 pin_o  = get_oxor(pin.o,  o_invert)
 227             elif pin.xdr == 2:
 228                 pin_o0 = get_oxor(pin.o0, o_invert)
 229                 pin_o1 = get_oxor(pin.o1, o_invert)
 230
 231         i = o = t = None
 232         if "i" in pin.dir:
 233             i = Signal(pin.width, name="{}_xdr_i".format(pin.name))
 234         if "o" in pin.dir:
 235             o = Signal(pin.width, name="{}_xdr_o".format(pin.name))
 236         if pin.dir in ("oe", "io"):
 237             t = Signal(1,         name="{}_xdr_t".format(pin.name))
 238
 239         if pin.xdr == 0:
 240             if "i" in pin.dir:
 241                 i = pin_i
 242             if "o" in pin.dir:
 243                 o = pin_o
 244             if pin.dir in ("oe", "io"):
 245                 t = ~pin_oe
 246         elif pin.xdr == 1:
 247             # Note that currently nextpnr will not pack an FF (*FS1P3DX) into the PIO.
 248             if "i" in pin.dir:
 249                 get_ireg(pin.i_clk, i, pin_i)
 250             if "o" in pin.dir:
 251                 get_oreg(pin.o_clk, pin_o, o)
 252             if pin.dir in ("oe", "io"):
 253                 get_oreg(pin.o_clk, ~pin.oe, t)
 254         elif pin.xdr == 2:
 255             if "i" in pin.dir:
 256                 get_iddr(pin.i_clk, i, pin_i0, pin_i1)
 257             if "o" in pin.dir:
 258                 get_oddr(pin.o_clk, pin_o0, pin_o1, o)
 259             if pin.dir in ("oe", "io"):
 260                 # It looks like Diamond will not pack an OREG as a tristate register in a DDR PIO.
 261                 # It is not clear what is the recommended set of primitives for this task.
 262                 # Similarly, nextpnr will not pack anything as a tristate register in a DDR PIO.
 263                 get_oreg(pin.o_clk, ~pin.oe, t)
 264         else:
 265             assert False
 266
 267         return (i, o, t)
 268
 269     def get_input(self, pin, port, attrs, invert):
 270         self._check_feature("single-ended input", pin, attrs,
 271                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 272         m = Module()
 273         i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None)
 274         for bit in range(len(port)):
 275             m.submodules[pin.name] = Instance("IB",
 276                 i_I=port[bit],
 277                 o_O=i[bit]
 278             )
 279         return m
 280
 281     def get_output(self, pin, port, attrs, invert):
 282         self._check_feature("single-ended output", pin, attrs,
 283                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 284         m = Module()
 285         i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None)
 286         for bit in range(len(port)):
 287             m.submodules[pin.name] = Instance("OB",
 288                 i_I=o[bit],
 289                 o_O=port[bit]
 290             )
 291         return m
 292
 293     def get_tristate(self, pin, port, attrs, invert):
 294         self._check_feature("single-ended tristate", pin, attrs,
 295                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 296         m = Module()
 297         i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None)
 298         for bit in range(len(port)):
 299             m.submodules[pin.name] = Instance("OBZ",
 300                 i_T=t,
 301                 i_I=o[bit],
 302                 o_O=port[bit]
 303             )
 304         return m
 305
 306     def get_input_output(self, pin, port, attrs, invert):
 307         self._check_feature("single-ended input/output", pin, attrs,
 308                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 309         m = Module()
 310         i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None,
 311                                                o_invert=True if invert else None)
 312         for bit in range(len(port)):
 313             m.submodules[pin.name] = Instance("BB",
 314                 i_T=t,
 315                 i_I=o[bit],
 316                 o_O=i[bit],
 317                 io_B=port[bit]
 318             )
 319         return m
 320
 321     def get_diff_input(self, pin, p_port, n_port, attrs, invert):
 322         self._check_feature("differential input", pin, attrs,
 323                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 324         m = Module()
 325         i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None)
 326         for bit in range(len(p_port)):
 327             m.submodules[pin.name] = Instance("IB",
 328                 i_I=p_port[bit],
 329                 o_O=i[bit]
 330             )
 331         return m
 332
 333     def get_diff_output(self, pin, p_port, n_port, attrs, invert):
 334         self._check_feature("differential output", pin, attrs,
 335                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 336         m = Module()
 337         i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None)
 338         for bit in range(len(p_port)):
 339             m.submodules[pin.name] = Instance("OB",
 340                 i_I=o[bit],
 341                 o_O=p_port[bit],
 342             )
 343         return m
 344
 345     def get_diff_tristate(self, pin, p_port, n_port, attrs, invert):
 346         self._check_feature("differential tristate", pin, attrs,
 347                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 348         m = Module()
 349         i, o, t = self._get_xdr_buffer(m, pin, o_invert=True if invert else None)
 350         for bit in range(len(p_port)):
 351             m.submodules[pin.name] = Instance("OBZ",
 352                 i_T=t,
 353                 i_I=o[bit],
 354                 o_O=p_port[bit],
 355             )
 356         return m
 357
 358     def get_diff_input_output(self, pin, p_port, n_port, attrs, invert):
 359         self._check_feature("differential input/output", pin, attrs,
 360                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 361         m = Module()
 362         i, o, t = self._get_xdr_buffer(m, pin, i_invert=True if invert else None,
 363                                                o_invert=True if invert else None)
 364         for bit in range(len(p_port)):
 365             m.submodules[pin.name] = Instance("BB",
 366                 i_T=t,
 367                 i_I=o[bit],
 368                 o_O=i[bit],
 369                 io_B=p_port[bit],
 370             )
 371         return m