nmigen/vendor/lattice_ecp5.py

   1 from abc import abstractproperty
   2
   3 from ..hdl import *
   4 from ..build import *
   5
   6
   7 __all__ = ["LatticeECP5Platform"]
   8
   9
  10 class LatticeECP5Platform(TemplatedPlatform):
  11     """
  12     Trellis toolchain
  13     -----------------
  14
  15     Required tools:
  16         * ``yosys``
  17         * ``nextpnr-ecp5``
  18         * ``ecppack``
  19
  20     The environment is populated by running the script specified in the environment variable
  21     ``NMIGEN_ENV_Trellis``, if present.
  22
  23     Available overrides:
  24         * ``verbose``: enables logging of informational messages to standard error.
  25         * ``read_verilog_opts``: adds options for ``read_verilog`` Yosys command.
  26         * ``synth_opts``: adds options for ``synth_ecp5`` Yosys command.
  27         * ``script_after_read``: inserts commands after ``read_ilang`` in Yosys script.
  28         * ``script_after_synth``: inserts commands after ``synth_ecp5`` in Yosys script.
  29         * ``yosys_opts``: adds extra options for ``yosys``.
  30         * ``nextpnr_opts``: adds extra options for ``nextpnr-ecp5``.
  31         * ``ecppack_opts``: adds extra options for ``ecppack``.
  32         * ``add_preferences``: inserts commands at the end of the LPF file.
  33
  34     Build products:
  35         * ``{{name}}.rpt``: Yosys log.
  36         * ``{{name}}.json``: synthesized RTL.
  37         * ``{{name}}.tim``: nextpnr log.
  38         * ``{{name}}.config``: ASCII bitstream.
  39         * ``{{name}}.bit``: binary bitstream.
  40         * ``{{name}}.svf``: JTAG programming vector.
  41
  42     Diamond toolchain
  43     -----------------
  44
  45     Required tools:
  46         * ``pnmainc``
  47         * ``ddtcmd``
  48
  49     The environment is populated by running the script specified in the environment variable
  50     ``NMIGEN_ENV_Diamond``, if present.
  51
  52     Available overrides:
  53         * ``script_project``: inserts commands before ``prj_project save`` in Tcl script.
  54         * ``script_after_export``: inserts commands after ``prj_run Export`` in Tcl script.
  55         * ``add_preferences``: inserts commands at the end of the LPF file.
  56         * ``add_constraints``: inserts commands at the end of the XDC file.
  57
  58     Build products:
  59         * ``{{name}}_impl/{{name}}_impl.htm``: consolidated log.
  60         * ``{{name}}.bit``: binary bitstream.
  61         * ``{{name}}.svf``: JTAG programming vector.
  62     """
  63
  64     toolchain = None # selected when creating platform
  65
  66     device  = abstractproperty()
  67     package = abstractproperty()
  68     speed   = abstractproperty()
  69     grade   = "C" # [C]ommercial, [I]ndustrial
  70
  71     # Trellis templates
  72
  73     _nextpnr_device_options = {
  74         "LFE5U-12F":    "--25k",
  75         "LFE5U-25F":    "--25k",
  76         "LFE5U-45F":    "--45k",
  77         "LFE5U-85F":    "--85k",
  78         "LFE5UM-12F":   "--um-25k",
  79         "LFE5UM-25F":   "--um-25k",
  80         "LFE5UM-45F":   "--um-45k",
  81         "LFE5UM-85F":   "--um-85k",
  82         "LFE5UM5G-12F": "--um5g-25k",
  83         "LFE5UM5G-25F": "--um5g-25k",
  84         "LFE5UM5G-45F": "--um5g-45k",
  85         "LFE5UM5G-85F": "--um5g-85k",
  86     }
  87     _nextpnr_package_options = {
  88         "BG256": "caBGA256",
  89         "MG285": "csfBGA285",
  90         "BG381": "caBGA381",
  91         "BG554": "caBGA554",
  92         "BG756": "caBGA756",
  93     }
  94
  95     _trellis_required_tools = [
  96         "yosys",
  97         "nextpnr-ecp5",
  98         "ecppack"
  99     ]
 100     _trellis_file_templates = {
 101         **TemplatedPlatform.build_script_templates,
 102         "{{name}}.il": r"""
 103             # {{autogenerated}}
 104             {{emit_design("rtlil")}}
 105         """,
 106         "{{name}}.ys": r"""
 107             # {{autogenerated}}
 108             {% for file in platform.iter_extra_files(".v") -%}
 109                 read_verilog {{get_override("read_opts")|options}} {{file}}
 110             {% endfor %}
 111             {% for file in platform.iter_extra_files(".sv") -%}
 112                 read_verilog -sv {{get_override("read_opts")|options}} {{file}}
 113             {% endfor %}
 114             read_ilang {{name}}.il
 115             {{get_override("script_after_read")|default("# (script_after_read placeholder)")}}
 116             synth_ecp5 {{get_override("synth_opts")|options}} -top {{name}}
 117             {{get_override("script_after_synth")|default("# (script_after_synth placeholder)")}}
 118             write_json {{name}}.json
 119         """,
 120         "{{name}}.lpf": r"""
 121             # {{autogenerated}}
 122             BLOCK ASYNCPATHS;
 123             BLOCK RESETPATHS;
 124             {% for port_name, pin_name, extras in platform.iter_port_constraints_bits() -%}
 125                 LOCATE COMP "{{port_name}}" SITE "{{pin_name}}";
 126                 IOBUF PORT "{{port_name}}"
 127                     {%- for key, value in extras.items() %} {{key}}={{value}}{% endfor %};
 128             {% endfor %}
 129             {% for signal, frequency in platform.iter_clock_constraints() -%}
 130                 FREQUENCY NET "{{signal|hierarchy(".")}}" {{frequency}} HZ;
 131             {% endfor %}
 132             {{get_override("add_preferences")|default("# (add_preferences placeholder)")}}
 133         """
 134     }
 135     _trellis_command_templates = [
 136         r"""
 137         {{get_tool("yosys")}}
 138             {{quiet("-q")}}
 139             {{get_override("yosys_opts")|options}}
 140             -l {{name}}.rpt
 141             {{name}}.ys
 142         """,
 143         r"""
 144         {{get_tool("nextpnr-ecp5")}}
 145             {{quiet("--quiet")}}
 146             {{get_override("nextpnr_opts")|options}}
 147             --log {{name}}.tim
 148             {{platform._nextpnr_device_options[platform.device]}}
 149             --package {{platform._nextpnr_package_options[platform.package]|upper}}
 150             --speed {{platform.speed}}
 151             --json {{name}}.json
 152             --lpf {{name}}.lpf
 153             --textcfg {{name}}.config
 154         """,
 155         r"""
 156         {{get_tool("ecppack")}}
 157             {{verbose("--verbose")}}
 158             {{get_override("ecppack_opts")|options}}
 159             --input {{name}}.config
 160             --bit {{name}}.bit
 161             --svf {{name}}.svf
 162         """
 163     ]
 164
 165     # Diamond templates
 166
 167     _diamond_required_tools = [
 168         "pnmainc",
 169         "ddtcmd"
 170     ]
 171     _diamond_file_templates = {
 172         **TemplatedPlatform.build_script_templates,
 173         "build_{{name}}.sh": r"""
 174             # {{autogenerated}}
 175             set -e{{verbose("x")}}
 176             if [ -z "$BASH" ] ; then exec /bin/bash "$0" "$@"; fi
 177             if [ -n "${{platform._toolchain_env_var}}" ]; then
 178                 bindir=$(dirname "${{platform._toolchain_env_var}}")
 179                 . "${{platform._toolchain_env_var}}"
 180             fi
 181             {{emit_commands("sh")}}
 182         """,
 183         "{{name}}.v": r"""
 184             /* {{autogenerated}} */
 185             {{emit_design("verilog")}}
 186         """,
 187         "{{name}}.tcl": r"""
 188             prj_project new -name {{name}} -impl impl -impl_dir top_impl \
 189                 -dev {{platform.device}}-{{platform.speed}}{{platform.package}}{{platform.grade}} \
 190                 -lpf {{name}}.lpf \
 191                 -synthesis synplify
 192             {% for file in platform.iter_extra_files(".v", ".sv", ".vhd", ".vhdl") -%}
 193                 prj_src add "{{file}}"
 194             {% endfor %}
 195             prj_src add {{name}}.v
 196             prj_impl option top {{name}}
 197             prj_src add {{name}}.sdc
 198             {{get_override("script_project")|default("# (script_project placeholder)")}}
 199             prj_project save
 200             prj_run Synthesis -impl impl -forceAll
 201             prj_run Translate -impl impl -forceAll
 202             prj_run Map -impl impl -forceAll
 203             prj_run PAR -impl impl -forceAll
 204             prj_run Export -impl "impl" -forceAll -task Bitgen
 205             {{get_override("script_after_export")|default("# (script_after_export placeholder)")}}
 206         """,
 207         "{{name}}.lpf": r"""
 208             # {{autogenerated}}
 209             BLOCK ASYNCPATHS;
 210             BLOCK RESETPATHS;
 211             {% for port_name, pin_name, extras in platform.iter_port_constraints_bits() -%}
 212                 LOCATE COMP "{{port_name}}" SITE "{{pin_name}}";
 213                 IOBUF PORT "{{port_name}}"
 214                     {%- for key, value in extras.items() %} {{key}}={{value}}{% endfor %};
 215             {% endfor %}
 216             {% for signal, frequency in platform.iter_clock_constraints() -%}
 217                 FREQUENCY NET "{{signal|hierarchy("/")}}" {{frequency/1000000}} MHZ;
 218             {% endfor %}
 219             {{get_override("add_preferences")|default("# (add_preferences placeholder)")}}
 220         """,
 221         "{{name}}.sdc": r"""
 222             {% for signal, frequency in platform.iter_clock_constraints() -%}
 223                 create_clock -period {{1000000000/frequency}} [get_nets {{signal|hierarchy("/")}}]
 224             {% endfor %}
 225             {{get_override("add_constraints")|default("# (add_constraints placeholder)")}}
 226         """,
 227     }
 228     _diamond_command_templates = [
 229         # These don't have any usable command-line option overrides.
 230         r"""
 231         {{get_tool("pnmainc")}}
 232             {{name}}.tcl
 233         """,
 234         r"""
 235         {{get_tool("ddtcmd")}}
 236             -oft -bit
 237             -if {{name}}_impl/{{name}}_impl.bit -of {{name}}.bit
 238         """,
 239         r"""
 240         {{get_tool("ddtcmd")}}
 241             -oft -svfsingle -revd -op "Fast Program"
 242             -if {{name}}_impl/{{name}}_impl.bit -of {{name}}.svf
 243         """,
 244     ]
 245
 246     # Common logic
 247
 248     def __init__(self, *, toolchain="Trellis"):
 249         super().__init__()
 250
 251         assert toolchain in ("Trellis", "Diamond")
 252         self.toolchain = toolchain
 253
 254     @property
 255     def required_tools(self):
 256         if self.toolchain == "Trellis":
 257             return self._trellis_required_tools
 258         if self.toolchain == "Diamond":
 259             return self._diamond_required_tools
 260         assert False
 261
 262     @property
 263     def file_templates(self):
 264         if self.toolchain == "Trellis":
 265             return self._trellis_file_templates
 266         if self.toolchain == "Diamond":
 267             return self._diamond_file_templates
 268         assert False
 269
 270     @property
 271     def command_templates(self):
 272         if self.toolchain == "Trellis":
 273             return self._trellis_command_templates
 274         if self.toolchain == "Diamond":
 275             return self._diamond_command_templates
 276         assert False
 277
 278     def create_missing_domain(self, name):
 279         # Lattice ECP devices have two global set/reset signals: PUR, which is driven at startup
 280         # by the configuration logic and unconditionally resets every storage element, and GSR,
 281         # which is driven by user logic and each storage element may be configured as affected or
 282         # unaffected by GSR. PUR is purely asynchronous, so even though it is a low-skew global
 283         # network, its deassertion may violate a setup/hold constraint with relation to a user
 284         # clock. To avoid this, a GSR/SGSR instance should be driven synchronized to user clock.
 285         if name == "sync" and self.default_clk is not None:
 286             clk_i = self.request(self.default_clk).i
 287             if self.default_rst is not None:
 288                 rst_i = self.request(self.default_rst).i
 289             else:
 290                 rst_i = Const(0)
 291
 292             gsr0 = Signal()
 293             gsr1 = Signal()
 294             m = Module()
 295             # There is no end-of-startup signal on ECP5, but PUR is released after IOB enable, so
 296             # a simple reset synchronizer (with PUR as the asynchronous reset) does the job.
 297             m.submodules += [
 298                 Instance("FD1S3AX", p_GSR="DISABLED", i_CK=clk_i, i_D=~rst_i, o_Q=gsr0),
 299                 Instance("FD1S3AX", p_GSR="DISABLED", i_CK=clk_i, i_D=gsr0,   o_Q=gsr1),
 300                 # Although we already synchronize the reset input to user clock, SGSR has dedicated
 301                 # clock routing to the center of the FPGA; use that just in case it turns out to be
 302                 # more reliable. (None of this is documented.)
 303                 Instance("SGSR", i_CLK=clk_i, i_GSR=gsr1),
 304             ]
 305             # GSR implicitly connects to every appropriate storage element. As such, the sync
 306             # domain is reset-less; domains driven by other clocks would need to have dedicated
 307             # reset circuitry or otherwise meet setup/hold constraints on their own.
 308             m.domains += ClockDomain("sync", reset_less=True)
 309             m.d.comb += ClockSignal("sync").eq(clk_i)
 310             return m
 311
 312     _single_ended_io_types = [
 313         "HSUL12", "LVCMOS12", "LVCMOS15", "LVCMOS18", "LVCMOS25", "LVCMOS33", "LVTTL33",
 314         "SSTL135_I", "SSTL135_II", "SSTL15_I", "SSTL15_II", "SSTL18_I", "SSTL18_II",
 315     ]
 316     _differential_io_types = [
 317         "BLVDS25", "BLVDS25E", "HSUL12D", "LVCMOS18D", "LVCMOS25D", "LVCMOS33D",
 318         "LVDS", "LVDS25E", "LVPECL33", "LVPECL33E", "LVTTL33D", "MLVDS", "MLVDS25E",
 319         "SLVS", "SSTL135D_II", "SSTL15D_II", "SSTL18D_II", "SUBLVDS",
 320     ]
 321
 322     def should_skip_port_component(self, port, attrs, component):
 323         # On ECP5, a differential IO is placed by only instantiating an IO buffer primitive at
 324         # the PIOA or PIOC location, which is always the non-inverting pin.
 325         if attrs.get("IO_TYPE", "LVCMOS25") in self._differential_io_types and component == "n":
 326             return True
 327         return False
 328
 329     def _get_xdr_buffer(self, m, pin, *, i_invert=False, o_invert=False):
 330         def get_ireg(clk, d, q):
 331             for bit in range(len(q)):
 332                 m.submodules += Instance("IFS1P3DX",
 333                     i_SCLK=clk,
 334                     i_SP=Const(1),
 335                     i_CD=Const(0),
 336                     i_D=d[bit],
 337                     o_Q=q[bit]
 338                 )
 339
 340         def get_oreg(clk, d, q):
 341             for bit in range(len(q)):
 342                 m.submodules += Instance("OFS1P3DX",
 343                     i_SCLK=clk,
 344                     i_SP=Const(1),
 345                     i_CD=Const(0),
 346                     i_D=d[bit],
 347                     o_Q=q[bit]
 348                 )
 349
 350         def get_iddr(sclk, d, q0, q1):
 351             for bit in range(len(d)):
 352                 m.submodules += Instance("IDDRX1F",
 353                     i_SCLK=sclk,
 354                     i_RST=Const(0),
 355                     i_D=d[bit],
 356                     o_Q0=q0[bit], o_Q1=q1[bit]
 357                 )
 358
 359         def get_oddr(sclk, d0, d1, q):
 360             for bit in range(len(q)):
 361                 m.submodules += Instance("ODDRX1F",
 362                     i_SCLK=sclk,
 363                     i_RST=Const(0),
 364                     i_D0=d0[bit], i_D1=d1[bit],
 365                     o_Q=q[bit]
 366                 )
 367
 368         def get_ineg(z, invert):
 369             if invert:
 370                 a = Signal.like(z, name_suffix="_n")
 371                 m.d.comb += z.eq(~a)
 372                 return a
 373             else:
 374                 return z
 375
 376         def get_oneg(a, invert):
 377             if invert:
 378                 z = Signal.like(a, name_suffix="_n")
 379                 m.d.comb += z.eq(~a)
 380                 return z
 381             else:
 382                 return a
 383
 384         if "i" in pin.dir:
 385             if pin.xdr < 2:
 386                 pin_i  = get_ineg(pin.i,  i_invert)
 387             elif pin.xdr == 2:
 388                 pin_i0 = get_ineg(pin.i0, i_invert)
 389                 pin_i1 = get_ineg(pin.i1, i_invert)
 390         if "o" in pin.dir:
 391             if pin.xdr < 2:
 392                 pin_o  = get_oneg(pin.o,  o_invert)
 393             elif pin.xdr == 2:
 394                 pin_o0 = get_oneg(pin.o0, o_invert)
 395                 pin_o1 = get_oneg(pin.o1, o_invert)
 396
 397         i = o = t = None
 398         if "i" in pin.dir:
 399             i = Signal(pin.width, name="{}_xdr_i".format(pin.name))
 400         if "o" in pin.dir:
 401             o = Signal(pin.width, name="{}_xdr_o".format(pin.name))
 402         if pin.dir in ("oe", "io"):
 403             t = Signal(1,         name="{}_xdr_t".format(pin.name))
 404
 405         if pin.xdr == 0:
 406             if "i" in pin.dir:
 407                 i = pin_i
 408             if "o" in pin.dir:
 409                 o = pin_o
 410             if pin.dir in ("oe", "io"):
 411                 t = ~pin_oe
 412         elif pin.xdr == 1:
 413             # Note that currently nextpnr will not pack an FF (*FS1P3DX) into the PIO.
 414             if "i" in pin.dir:
 415                 get_ireg(pin.i_clk, i, pin_i)
 416             if "o" in pin.dir:
 417                 get_oreg(pin.o_clk, pin_o, o)
 418             if pin.dir in ("oe", "io"):
 419                 get_oreg(pin.o_clk, ~pin.oe, t)
 420         elif pin.xdr == 2:
 421             if "i" in pin.dir:
 422                 get_iddr(pin.i_clk, i, pin_i0, pin_i1)
 423             if "o" in pin.dir:
 424                 get_oddr(pin.o_clk, pin_o0, pin_o1, o)
 425             if pin.dir in ("oe", "io"):
 426                 # It looks like Diamond will not pack an OREG as a tristate register in a DDR PIO.
 427                 # It is not clear what is the recommended set of primitives for this task.
 428                 # Similarly, nextpnr will not pack anything as a tristate register in a DDR PIO.
 429                 get_oreg(pin.o_clk, ~pin.oe, t)
 430         else:
 431             assert False
 432
 433         return (i, o, t)
 434
 435     def get_input(self, pin, port, attrs, invert):
 436         self._check_feature("single-ended input", pin, attrs,
 437                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 438         m = Module()
 439         i, o, t = self._get_xdr_buffer(m, pin, i_invert=invert)
 440         for bit in range(len(port)):
 441             m.submodules["{}_{}".format(pin.name, bit)] = Instance("IB",
 442                 i_I=port[bit],
 443                 o_O=i[bit]
 444             )
 445         return m
 446
 447     def get_output(self, pin, port, attrs, invert):
 448         self._check_feature("single-ended output", pin, attrs,
 449                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 450         m = Module()
 451         i, o, t = self._get_xdr_buffer(m, pin, o_invert=invert)
 452         for bit in range(len(port)):
 453             m.submodules["{}_{}".format(pin.name, bit)] = Instance("OB",
 454                 i_I=o[bit],
 455                 o_O=port[bit]
 456             )
 457         return m
 458
 459     def get_tristate(self, pin, port, attrs, invert):
 460         self._check_feature("single-ended tristate", pin, attrs,
 461                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 462         m = Module()
 463         i, o, t = self._get_xdr_buffer(m, pin, o_invert=invert)
 464         for bit in range(len(port)):
 465             m.submodules["{}_{}".format(pin.name, bit)] = Instance("OBZ",
 466                 i_T=t,
 467                 i_I=o[bit],
 468                 o_O=port[bit]
 469             )
 470         return m
 471
 472     def get_input_output(self, pin, port, attrs, invert):
 473         self._check_feature("single-ended input/output", pin, attrs,
 474                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 475         m = Module()
 476         i, o, t = self._get_xdr_buffer(m, pin, i_invert=invert, o_invert=invert)
 477         for bit in range(len(port)):
 478             m.submodules["{}_{}".format(pin.name, bit)] = Instance("BB",
 479                 i_T=t,
 480                 i_I=o[bit],
 481                 o_O=i[bit],
 482                 io_B=port[bit]
 483             )
 484         return m
 485
 486     def get_diff_input(self, pin, p_port, n_port, attrs, invert):
 487         self._check_feature("differential input", pin, attrs,
 488                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 489         m = Module()
 490         i, o, t = self._get_xdr_buffer(m, pin, i_invert=invert)
 491         for bit in range(len(p_port)):
 492             m.submodules["{}_{}".format(pin.name, bit)] = Instance("IB",
 493                 i_I=p_port[bit],
 494                 o_O=i[bit]
 495             )
 496         return m
 497
 498     def get_diff_output(self, pin, p_port, n_port, attrs, invert):
 499         self._check_feature("differential output", pin, attrs,
 500                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 501         m = Module()
 502         i, o, t = self._get_xdr_buffer(m, pin, o_invert=invert)
 503         for bit in range(len(p_port)):
 504             m.submodules["{}_{}".format(pin.name, bit)] = Instance("OB",
 505                 i_I=o[bit],
 506                 o_O=p_port[bit],
 507             )
 508         return m
 509
 510     def get_diff_tristate(self, pin, p_port, n_port, attrs, invert):
 511         self._check_feature("differential tristate", pin, attrs,
 512                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 513         m = Module()
 514         i, o, t = self._get_xdr_buffer(m, pin, o_invert=invert)
 515         for bit in range(len(p_port)):
 516             m.submodules["{}_{}".format(pin.name, bit)] = Instance("OBZ",
 517                 i_T=t,
 518                 i_I=o[bit],
 519                 o_O=p_port[bit],
 520             )
 521         return m
 522
 523     def get_diff_input_output(self, pin, p_port, n_port, attrs, invert):
 524         self._check_feature("differential input/output", pin, attrs,
 525                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 526         m = Module()
 527         i, o, t = self._get_xdr_buffer(m, pin, i_invert=invert, o_invert=invert)
 528         for bit in range(len(p_port)):
 529             m.submodules["{}_{}".format(pin.name, bit)] = Instance("BB",
 530                 i_T=t,
 531                 i_I=o[bit],
 532                 o_O=i[bit],
 533                 io_B=p_port[bit],
 534             )
 535         return m
 536
 537     # CDC primitives are not currently specialized for ECP5. While Diamond supports the necessary
 538     # attributes (TBD); nextpnr-ecp5 does not.