nmigen/vendor/lattice_ice40.py

   1 from abc import abstractproperty
   2
   3 from ..hdl import *
   4 from ..build import *
   5
   6
   7 __all__ = ["LatticeICE40Platform"]
   8
   9
  10 class LatticeICE40Platform(TemplatedPlatform):
  11     """
  12     IceStorm toolchain
  13     ------------------
  14
  15     Required tools:
  16         * ``yosys``
  17         * ``nextpnr-ice40``
  18         * ``icepack``
  19
  20     The environment is populated by running the script specified in the environment variable
  21     ``NMIGEN_ENV_IceStorm``, if present.
  22
  23     Available overrides:
  24         * ``verbose``: enables logging of informational messages to standard error.
  25         * ``read_verilog_opts``: adds options for ``read_verilog`` Yosys command.
  26         * ``synth_opts``: adds options for ``synth_ice40`` Yosys command.
  27         * ``script_after_read``: inserts commands after ``read_ilang`` in Yosys script.
  28         * ``script_after_synth``: inserts commands after ``synth_ice40`` in Yosys script.
  29         * ``yosys_opts``: adds extra options for ``yosys``.
  30         * ``nextpnr_opts``: adds extra options for ``nextpnr-ice40``.
  31         * ``add_pre_pack``: inserts commands at the end in pre-pack Python script.
  32         * ``add_constraints``: inserts commands at the end in the PCF file.
  33
  34     Build products:
  35         * ``{{name}}.rpt``: Yosys log.
  36         * ``{{name}}.json``: synthesized RTL.
  37         * ``{{name}}.tim``: nextpnr log.
  38         * ``{{name}}.asc``: ASCII bitstream.
  39         * ``{{name}}.bin``: binary bitstream.
  40
  41     iCECube2 toolchain
  42     ------------------
  43
  44     This toolchain comes in two variants: ``LSE-iCECube2`` and ``Synplify-iCECube2``.
  45
  46     Required tools:
  47         * iCECube2 toolchain
  48         * ``tclsh``
  49
  50     The environment is populated by setting the necessary environment variables based on
  51     ``NMIGEN_ENV_iCECube2``, which must point to the root of the iCECube2 installation, and
  52     is required.
  53
  54     Available overrides:
  55         * ``verbose``: enables logging of informational messages to standard error.
  56         * ``lse_opts``: adds options for LSE.
  57         * ``script_after_add``: inserts commands after ``add_file`` in Synplify Tcl script.
  58         * ``script_after_options``: inserts commands after ``set_option`` in Synplify Tcl script.
  59         * ``add_constraints``: inserts commands in SDC file.
  60         * ``script_after_flow``: inserts commands after ``run_sbt_backend_auto`` in SBT
  61           Tcl script.
  62
  63     Build products:
  64         * ``{{name}}_lse.log`` (LSE) or ``{{name}}_design/{{name}}.htm`` (Synplify): synthesis log.
  65         * ``sbt/outputs/router/{{name}}_timing.rpt``: timing report.
  66         * ``{{name}}.edf``: EDIF netlist.
  67         * ``{{name}}.bin``: binary bitstream.
  68     """
  69
  70     toolchain = None # selected when creating platform
  71
  72     device  = abstractproperty()
  73     package = abstractproperty()
  74
  75     # IceStorm templates
  76
  77     _nextpnr_device_options = {
  78         "iCE40LP384": "--lp384",
  79         "iCE40LP1K":  "--lp1k",
  80         "iCE40LP4K":  "--lp8k",
  81         "iCE40LP8K":  "--lp8k",
  82         "iCE40HX1K":  "--hx1k",
  83         "iCE40HX4K":  "--hx8k",
  84         "iCE40HX8K":  "--hx8k",
  85         "iCE40UP5K":  "--up5k",
  86         "iCE40UP3K":  "--up5k",
  87         "iCE5LP4K":   "--u4k",
  88         "iCE5LP2K":   "--u4k",
  89         "iCE5LP1K":   "--u4k",
  90     }
  91     _nextpnr_package_options = {
  92         "iCE40LP4K":  ":4k",
  93         "iCE40HX4K":  ":4k",
  94         "iCE40UP3K":  "",
  95         "iCE5LP2K":   "",
  96         "iCE5LP1K":   "",
  97     }
  98
  99     _icestorm_required_tools = [
 100         "yosys",
 101         "nextpnr-ice40",
 102         "icepack",
 103     ]
 104     _icestorm_file_templates = {
 105         **TemplatedPlatform.build_script_templates,
 106         "{{name}}.il": r"""
 107             # {{autogenerated}}
 108             {{emit_design("rtlil")}}
 109         """,
 110         "{{name}}.ys": r"""
 111             # {{autogenerated}}
 112             {% for file in platform.iter_extra_files(".v") -%}
 113                 read_verilog {{get_override("read_opts")|options}} {{file}}
 114             {% endfor %}
 115             {% for file in platform.iter_extra_files(".sv") -%}
 116                 read_verilog -sv {{get_override("read_opts")|options}} {{file}}
 117             {% endfor %}
 118             read_ilang {{name}}.il
 119             {{get_override("script_after_read")|default("# (script_after_read placeholder)")}}
 120             synth_ice40 {{get_override("synth_opts")|options}} -top {{name}}
 121             {{get_override("script_after_synth")|default("# (script_after_synth placeholder)")}}
 122             write_json {{name}}.json
 123         """,
 124         "{{name}}_pre_pack.py": r"""
 125             # {{autogenerated}}
 126             {% for signal, frequency in platform.iter_clock_constraints() -%}
 127             {# Clock in MHz #}
 128             ctx.addClock("{{signal|hierarchy(".")}}", {{frequency/1000000}})
 129             {% endfor%}
 130             {{get_override("add_pre_pack")|default("# (add_pre_pack placeholder)")}}
 131         """,
 132         "{{name}}.pcf": r"""
 133             # {{autogenerated}}
 134             {% for port_name, pin_name, attrs in platform.iter_port_constraints_bits() -%}
 135                 set_io {{port_name}} {{pin_name}}
 136             {% endfor %}
 137             {{get_override("add_constraints")|default("# (add_constraints placeholder)")}}
 138         """,
 139     }
 140     _icestorm_command_templates = [
 141         r"""
 142         {{get_tool("yosys")}}
 143             {{quiet("-q")}}
 144             {{get_override("yosys_opts")|options}}
 145             -l {{name}}.rpt
 146             {{name}}.ys
 147         """,
 148         r"""
 149         {{get_tool("nextpnr-ice40")}}
 150             {{quiet("--quiet")}}
 151             {{get_override("nextpnr_opts")|options}}
 152             --log {{name}}.tim
 153             {{platform._nextpnr_device_options[platform.device]}}
 154             --package
 155                 {{platform.package|lower}}{{platform._nextpnr_package_options[platform.device]}}
 156             --json {{name}}.json
 157             --pcf {{name}}.pcf
 158             --pre-pack {{name}}_pre_pack.py
 159             --asc {{name}}.asc
 160         """,
 161         r"""
 162         {{get_tool("icepack")}}
 163             {{verbose("-v")}}
 164             {{name}}.asc
 165             {{name}}.bin
 166         """
 167     ]
 168
 169     # iCECube2 templates
 170
 171     _icecube2_required_tools = [
 172         "synthesis",
 173         "synpwrap",
 174         "tclsh",
 175     ]
 176     _icecube2_file_templates = {
 177         **TemplatedPlatform.build_script_templates,
 178         "build_{{name}}.sh": r"""
 179             # {{autogenerated}}
 180             set -e{{verbose("x")}}
 181             if [ -n "${{platform._toolchain_env_var}}" ]; then
 182                 # LSE environment
 183                 export LD_LIBRARY_PATH=${{platform._toolchain_env_var}}/LSE/bin/lin64:$LD_LIBRARY_PATH
 184                 export PATH=${{platform._toolchain_env_var}}/LSE/bin/lin64:$PATH
 185                 export FOUNDRY=${{platform._toolchain_env_var}}/LSE
 186                 # Synplify environment
 187                 export LD_LIBRARY_PATH=${{platform._toolchain_env_var}}/sbt_backend/bin/linux/opt/synpwrap:$LD_LIBRARY_PATH
 188                 export PATH=${{platform._toolchain_env_var}}/sbt_backend/bin/linux/opt/synpwrap:$PATH
 189                 export SYNPLIFY_PATH=${{platform._toolchain_env_var}}/synpbase
 190                 # Common environment
 191                 export SBT_DIR=${{platform._toolchain_env_var}}/sbt_backend
 192             else
 193                 echo "Variable ${{platform._toolchain_env_var}} must be set" >&2; exit 1
 194             fi
 195             {{emit_commands("sh")}}
 196         """,
 197         "{{name}}.v": r"""
 198             /* {{autogenerated}} */
 199             {{emit_design("verilog")}}
 200         """,
 201         "{{name}}_lse.prj": r"""
 202             # {{autogenerated}}
 203             -a SBT{{platform.family}}
 204             -d {{platform.device}}
 205             -t {{platform.package}}
 206             {{get_override("lse_opts")|options|default("# (lse_opts placeholder)")}}
 207             {% for file in platform.iter_extra_files(".v") -%}
 208                 -ver {{file}}
 209             {% endfor %}
 210             -ver {{name}}.v
 211             -sdc {{name}}.sdc
 212             -top {{name}}
 213             -output_edif {{name}}.edf
 214             -logfile {{name}}_lse.log
 215         """,
 216         "{{name}}_syn.prj": r"""
 217             # {{autogenerated}}
 218             {% for file in platform.iter_extra_files(".v", ".sv", ".vhd", ".vhdl") -%}
 219                 add_file -verilog {{file}}
 220             {% endfor %}
 221             add_file -verilog {{name}}.v
 222             add_file -constraint {{name}}.sdc
 223             {{get_override("script_after_add")|default("# (script_after_add placeholder)")}}
 224             impl -add {{name}}_design -type fpga
 225             set_option -technology SBT{{platform.family}}
 226             set_option -part {{platform.device}}
 227             set_option -package {{platform.package}}
 228             {{get_override("script_after_options")|default("# (script_after_options placeholder)")}}
 229             project -result_format edif
 230             project -result_file {{name}}.edf
 231             impl -active {{name}}_design
 232             project -run compile
 233             project -run map
 234             project -run fpga_mapper
 235             file copy -force -- {{name}}_design/{{name}}.edf {{name}}.edf
 236         """,
 237         "{{name}}.sdc": r"""
 238             # {{autogenerated}}
 239             {% for signal, frequency in platform.iter_clock_constraints() -%}
 240                 create_clock -name {{signal.name}} -period {{1000000000/frequency}} [get_nets {{signal|hierarchy("/")}}]
 241             {% endfor %}
 242             {{get_override("add_constraints")|default("# (add_constraints placeholder)")}}
 243         """,
 244         "{{name}}.tcl": r"""
 245             # {{autogenerated}}
 246             set device {{platform.device}}-{{platform.package}}
 247             set top_module {{name}}
 248             set proj_dir .
 249             set output_dir .
 250             set edif_file {{name}}
 251             set tool_options ":edifparser -y {{name}}.pcf"
 252             set sbt_root $::env(SBT_DIR)
 253             append sbt_tcl $sbt_root "/tcl/sbt_backend_synpl.tcl"
 254             source $sbt_tcl
 255             run_sbt_backend_auto $device $top_module $proj_dir $output_dir $tool_options $edif_file
 256             {{get_override("script_after_file")|default("# (script_after_file placeholder)")}}
 257             file copy -force -- sbt/outputs/bitmap/{{name}}_bitmap.bin {{name}}.bin
 258             exit
 259         """,
 260         "{{name}}.pcf": r"""
 261             # {{autogenerated}}
 262             {% for port_name, pin_name, attrs in platform.iter_port_constraints_bits() -%}
 263                 set_io {{port_name}} {{pin_name}}
 264             {% endfor %}
 265         """,
 266     }
 267     _lse_icecube2_command_templates = [
 268         r"""synthesis -f {{name}}_lse.prj""",
 269         r"""tclsh {{name}}.tcl""",
 270     ]
 271     _synplify_icecube2_command_templates = [
 272         r"""synpwrap -prj {{name}}_syn.prj -log {{name}}_syn.log""",
 273         r"""tclsh {{name}}.tcl""",
 274     ]
 275
 276     # Common logic
 277
 278     def __init__(self, *, toolchain="IceStorm"):
 279         super().__init__()
 280
 281         assert toolchain in ("IceStorm", "LSE-iCECube2", "Synplify-iCECube2")
 282         self.toolchain = toolchain
 283
 284     @property
 285     def family(self):
 286         if self.device.startswith("iCE40"):
 287             return "iCE40"
 288         if self.device.startswith("iCE5"):
 289             return "iCE5"
 290         assert False
 291
 292     @property
 293     def _toolchain_env_var(self):
 294         if self.toolchain == "IceStorm":
 295             return f"NMIGEN_ENV_{self.toolchain}"
 296         if self.toolchain in ("LSE-iCECube2", "Synplify-iCECube2"):
 297             return f"NMIGEN_ENV_iCECube2"
 298         assert False
 299
 300     @property
 301     def required_tools(self):
 302         if self.toolchain == "IceStorm":
 303             return self._icestorm_required_tools
 304         if self.toolchain in ("LSE-iCECube2", "Synplify-iCECube2"):
 305             return self._icecube2_required_tools
 306         assert False
 307
 308     @property
 309     def file_templates(self):
 310         if self.toolchain == "IceStorm":
 311             return self._icestorm_file_templates
 312         if self.toolchain in ("LSE-iCECube2", "Synplify-iCECube2"):
 313             return self._icecube2_file_templates
 314         assert False
 315
 316     @property
 317     def command_templates(self):
 318         if self.toolchain == "IceStorm":
 319             return self._icestorm_command_templates
 320         if self.toolchain == "LSE-iCECube2":
 321             return self._lse_icecube2_command_templates
 322         if self.toolchain == "Synplify-iCECube2":
 323             return self._synplify_icecube2_command_templates
 324         assert False
 325
 326     def create_missing_domain(self, name):
 327         # For unknown reasons (no errata was ever published, and no documentation mentions this
 328         # issue), iCE40 BRAMs read as zeroes for ~3 us after configuration and release of internal
 329         # global reset. Note that this is a *time-based* delay, generated purely by the internal
 330         # oscillator, which may not be observed nor influenced directly. For details, see links:
 331         #  * https://github.com/cliffordwolf/icestorm/issues/76#issuecomment-289270411
 332         #  * https://github.com/cliffordwolf/icotools/issues/2#issuecomment-299734673
 333         #
 334         # To handle this, it is necessary to have a global reset in any iCE40 design that may
 335         # potentially instantiate BRAMs, and assert this reset for >3 us after configuration.
 336         # (We add a margin of 5x to allow for PVT variation.) If the board includes a dedicated
 337         # reset line, this line is ORed with the power on reset.
 338         #
 339         # The power-on reset timer counts up because the vendor tools do not support initialization
 340         # of flip-flops.
 341         if name == "sync" and self.default_clk is not None:
 342             clk_i = self.request(self.default_clk).i
 343             if self.default_rst is not None:
 344                 rst_i = self.request(self.default_rst).i
 345
 346             m = Module()
 347             # Power-on-reset domain
 348             m.domains += ClockDomain("por", reset_less=True, local=True)
 349             delay = int(15e-6 * self.default_clk_frequency)
 350             timer = Signal(max=delay)
 351             ready = Signal()
 352             m.d.comb += ClockSignal("por").eq(clk_i)
 353             with m.If(timer == delay):
 354                 m.d.por += ready.eq(1)
 355             with m.Else():
 356                 m.d.por += timer.eq(timer + 1)
 357             # Primary domain
 358             m.domains += ClockDomain("sync")
 359             m.d.comb += ClockSignal("sync").eq(clk_i)
 360             if self.default_rst is not None:
 361                 m.d.comb += ResetSignal("sync").eq(~ready | rst_i)
 362             else:
 363                 m.d.comb += ResetSignal("sync").eq(~ready)
 364             return m
 365
 366     def should_skip_port_component(self, port, attrs, component):
 367         # On iCE40, a differential input is placed by only instantiating an SB_IO primitive for
 368         # the pin with z=0, which is the non-inverting pin. The pinout unfortunately differs
 369         # between LP/HX and UP series:
 370         #  * for LP/HX, z=0 is DPxxB   (B is non-inverting, A is inverting)
 371         #  * for UP,    z=0 is IOB_xxA (A is non-inverting, B is inverting)
 372         if attrs.get("IO_STANDARD", "SB_LVCMOS") == "SB_LVDS_INPUT" and component == "n":
 373             return True
 374         return False
 375
 376     def _get_io_buffer(self, m, pin, port, attrs, *, i_invert=False, o_invert=False,
 377                        invert_lut=False):
 378         def get_dff(clk, d, q):
 379             m.submodules += Instance("$dff",
 380                 p_CLK_POLARITY=1,
 381                 p_WIDTH=len(d),
 382                 i_CLK=clk,
 383                 i_D=d,
 384                 o_Q=q)
 385
 386         def get_ineg(y, invert):
 387             if invert_lut:
 388                 a = Signal.like(y, name_suffix="_x{}".format(1 if invert else 0))
 389                 for bit in range(len(y)):
 390                     m.submodules += Instance("SB_LUT4",
 391                         p_LUT_INIT=Const(0b01 if invert else 0b10, 16),
 392                         i_I0=a[bit],
 393                         i_I1=Const(0),
 394                         i_I2=Const(0),
 395                         i_I3=Const(0),
 396                         o_O=y[bit])
 397                 return a
 398             elif invert:
 399                 a = Signal.like(y, name_suffix="_n")
 400                 m.d.comb += y.eq(~a)
 401                 return a
 402             else:
 403                 return y
 404
 405         def get_oneg(a, invert):
 406             if invert_lut:
 407                 y = Signal.like(a, name_suffix="_x{}".format(1 if invert else 0))
 408                 for bit in range(len(a)):
 409                     m.submodules += Instance("SB_LUT4",
 410                         p_LUT_INIT=Const(0b01 if invert else 0b10, 16),
 411                         i_I0=a[bit],
 412                         i_I1=Const(0),
 413                         i_I2=Const(0),
 414                         i_I3=Const(0),
 415                         o_O=y[bit])
 416                 return y
 417             elif invert:
 418                 y = Signal.like(a, name_suffix="_n")
 419                 m.d.comb += y.eq(~a)
 420                 return y
 421             else:
 422                 return a
 423
 424         if "GLOBAL" in attrs:
 425             is_global_input = bool(attrs["GLOBAL"])
 426             del attrs["GLOBAL"]
 427         else:
 428             is_global_input = False
 429         assert not (is_global_input and i_invert)
 430
 431         if "i" in pin.dir:
 432             if pin.xdr < 2:
 433                 pin_i  = get_ineg(pin.i,  i_invert)
 434             elif pin.xdr == 2:
 435                 pin_i0 = get_ineg(pin.i0, i_invert)
 436                 pin_i1 = get_ineg(pin.i1, i_invert)
 437         if "o" in pin.dir:
 438             if pin.xdr < 2:
 439                 pin_o  = get_oneg(pin.o,  o_invert)
 440             elif pin.xdr == 2:
 441                 pin_o0 = get_oneg(pin.o0, o_invert)
 442                 pin_o1 = get_oneg(pin.o1, o_invert)
 443
 444         if "i" in pin.dir and pin.xdr == 2:
 445             i0_ff = Signal.like(pin_i0, name_suffix="_ff")
 446             i1_ff = Signal.like(pin_i1, name_suffix="_ff")
 447             get_dff(pin.i_clk, i0_ff, pin_i0)
 448             get_dff(pin.i_clk, i1_ff, pin_i1)
 449         if "o" in pin.dir and pin.xdr == 2:
 450             o1_ff = Signal.like(pin_o1, name_suffix="_ff")
 451             get_dff(pin.o_clk, pin_o1, o1_ff)
 452
 453         for bit in range(len(port)):
 454             io_args = [
 455                 ("io", "PACKAGE_PIN", port[bit]),
 456                 *(("p", key, value) for key, value in attrs.items()),
 457             ]
 458
 459             if "i" not in pin.dir:
 460                 # If no input pin is requested, it is important to use a non-registered input pin
 461                 # type, because an output-only pin would not have an input clock, and if its input
 462                 # is configured as registered, this would prevent a co-located input-capable pin
 463                 # from using an input clock.
 464                 i_type =     0b01 # PIN_INPUT
 465             elif pin.xdr == 0:
 466                 i_type =     0b01 # PIN_INPUT
 467             elif pin.xdr > 0:
 468                 i_type =     0b00 # PIN_INPUT_REGISTERED aka PIN_INPUT_DDR
 469             if "o" not in pin.dir:
 470                 o_type = 0b0000   # PIN_NO_OUTPUT
 471             elif pin.xdr == 0 and pin.dir == "o":
 472                 o_type = 0b0110   # PIN_OUTPUT
 473             elif pin.xdr == 0:
 474                 o_type = 0b1010   # PIN_OUTPUT_TRISTATE
 475             elif pin.xdr == 1 and pin.dir == "o":
 476                 o_type = 0b0101   # PIN_OUTPUT_REGISTERED
 477             elif pin.xdr == 1:
 478                 o_type = 0b1101   # PIN_OUTPUT_REGISTERED_ENABLE_REGISTERED
 479             elif pin.xdr == 2 and pin.dir == "o":
 480                 o_type = 0b0100   # PIN_OUTPUT_DDR
 481             elif pin.xdr == 2:
 482                 o_type = 0b1100   # PIN_OUTPUT_DDR_ENABLE_REGISTERED
 483             io_args.append(("p", "PIN_TYPE", C((o_type << 2) | i_type, 6)))
 484
 485             if hasattr(pin, "i_clk"):
 486                 io_args.append(("i", "INPUT_CLK",  pin.i_clk))
 487             if hasattr(pin, "o_clk"):
 488                 io_args.append(("i", "OUTPUT_CLK", pin.o_clk))
 489
 490             if "i" in pin.dir:
 491                 if pin.xdr == 0 and is_global_input:
 492                     io_args.append(("o", "GLOBAL_BUFFER_OUTPUT", pin.i[bit]))
 493                 elif pin.xdr < 2:
 494                     io_args.append(("o", "D_IN_0",  pin_i[bit]))
 495                 elif pin.xdr == 2:
 496                     # Re-register both inputs before they enter fabric. This increases hold time
 497                     # to an entire cycle, and adds one cycle of latency.
 498                     io_args.append(("o", "D_IN_0",  i0_ff[bit]))
 499                     io_args.append(("o", "D_IN_1",  i1_ff[bit]))
 500             if "o" in pin.dir:
 501                 if pin.xdr < 2:
 502                     io_args.append(("i", "D_OUT_0", pin_o[bit]))
 503                 elif pin.xdr == 2:
 504                     # Re-register negedge output after it leaves fabric. This increases setup time
 505                     # to an entire cycle, and doesn't add latency.
 506                     io_args.append(("i", "D_OUT_0", pin_o0[bit]))
 507                     io_args.append(("i", "D_OUT_1", o1_ff[bit]))
 508
 509             if pin.dir in ("oe", "io"):
 510                 io_args.append(("i", "OUTPUT_ENABLE", pin.oe))
 511
 512             if is_global_input:
 513                 m.submodules["{}_{}".format(pin.name, bit)] = Instance("SB_GB_IO", *io_args)
 514             else:
 515                 m.submodules["{}_{}".format(pin.name, bit)] = Instance("SB_IO", *io_args)
 516
 517     def get_input(self, pin, port, attrs, invert):
 518         self._check_feature("single-ended input", pin, attrs,
 519                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 520         m = Module()
 521         self._get_io_buffer(m, pin, port, attrs, i_invert=invert)
 522         return m
 523
 524     def get_output(self, pin, port, attrs, invert):
 525         self._check_feature("single-ended output", pin, attrs,
 526                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 527         m = Module()
 528         self._get_io_buffer(m, pin, port, attrs, o_invert=invert)
 529         return m
 530
 531     def get_tristate(self, pin, port, attrs, invert):
 532         self._check_feature("single-ended tristate", pin, attrs,
 533                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 534         m = Module()
 535         self._get_io_buffer(m, pin, port, attrs, o_invert=invert)
 536         return m
 537
 538     def get_input_output(self, pin, port, attrs, invert):
 539         self._check_feature("single-ended input/output", pin, attrs,
 540                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 541         m = Module()
 542         self._get_io_buffer(m, pin, port, attrs, i_invert=invert, o_invert=invert)
 543         return m
 544
 545     def get_diff_input(self, pin, p_port, n_port, attrs, invert):
 546         self._check_feature("differential input", pin, attrs,
 547                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 548         m = Module()
 549         # See comment in should_skip_port_component above.
 550         self._get_io_buffer(m, pin, p_port, attrs, i_invert=invert)
 551         return m
 552
 553     def get_diff_output(self, pin, p_port, n_port, attrs, invert):
 554         self._check_feature("differential output", pin, attrs,
 555                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 556         m = Module()
 557         # Note that the non-inverting output pin is not driven the same way as a regular
 558         # output pin. The inverter introduces a delay, so for a non-inverting output pin,
 559         # an identical delay is introduced by instantiating a LUT. This makes the waveform
 560         # perfectly symmetric in the xdr=0 case.
 561         self._get_io_buffer(m, pin, p_port, attrs, o_invert=    invert, invert_lut=True)
 562         self._get_io_buffer(m, pin, n_port, attrs, o_invert=not invert, invert_lut=True)
 563         return m
 564
 565     # Tristate and bidirectional buffers are not supported on iCE40 because it requires external
 566     # termination, which is incompatible for input and output differential I/Os.
 567
 568     # CDC primitives are not currently specialized for iCE40. It is not known if iCECube2 supports
 569     # the necessary attributes; nextpnr-ice40 does not.