nmigen/vendor/lattice_machxo_2_3l.py

   1 from abc import abstractproperty
   2
   3 from ..hdl import *
   4 from ..build import *
   5
   6
   7 __all__ = ["LatticeMachXO2Platform", "LatticeMachXO3LPlatform"]
   8
   9
  10 # MachXO2 and MachXO3L primitives are the same. Handle both using
  11 # one class and expose user-aliases for convenience.
  12 class LatticeMachXO2Or3LPlatform(TemplatedPlatform):
  13     """
  14     Required tools:
  15         * ``pnmainc``
  16         * ``ddtcmd``
  17
  18     The environment is populated by running the script specified in the environment variable
  19     ``NMIGEN_ENV_Diamond``, if present.
  20
  21     Available overrides:
  22         * ``script_project``: inserts commands before ``prj_project save`` in Tcl script.
  23         * ``script_after_export``: inserts commands after ``prj_run Export`` in Tcl script.
  24         * ``add_preferences``: inserts commands at the end of the LPF file.
  25         * ``add_constraints``: inserts commands at the end of the XDC file.
  26
  27     Build products:
  28         * ``{{name}}_impl/{{name}}_impl.htm``: consolidated log.
  29         * ``{{name}}.jed``: JEDEC fuse file.
  30         * ``{{name}}.bit``: binary bitstream.
  31         * ``{{name}}.svf``: JTAG programming vector.
  32     """
  33
  34     toolchain = "Diamond"
  35
  36     device  = abstractproperty()
  37     package = abstractproperty()
  38     speed   = abstractproperty()
  39     grade   = "C" # [C]ommercial, [I]ndustrial
  40
  41     required_tools = [
  42         "yosys",
  43         "pnmainc",
  44         "ddtcmd"
  45     ]
  46     file_templates = {
  47         **TemplatedPlatform.build_script_templates,
  48         "build_{{name}}.sh": r"""
  49             # {{autogenerated}}
  50             set -e{{verbose("x")}}
  51             if [ -z "$BASH" ] ; then exec /bin/bash "$0" "$@"; fi
  52             if [ -n "${{platform._toolchain_env_var}}" ]; then
  53                 bindir=$(dirname "${{platform._toolchain_env_var}}")
  54                 . "${{platform._toolchain_env_var}}"
  55             fi
  56             {{emit_commands("sh")}}
  57         """,
  58         "{{name}}.v": r"""
  59             /* {{autogenerated}} */
  60             {{emit_verilog()}}
  61         """,
  62         "{{name}}.debug.v": r"""
  63             /* {{autogenerated}} */
  64             {{emit_debug_verilog()}}
  65         """,
  66         "{{name}}.tcl": r"""
  67             prj_project new -name {{name}} -impl impl -impl_dir top_impl \
  68                 -dev {{platform.device}}-{{platform.speed}}{{platform.package}}{{platform.grade}} \
  69                 -lpf {{name}}.lpf \
  70                 -synthesis synplify
  71             {% for file in platform.iter_extra_files(".v", ".sv", ".vhd", ".vhdl") -%}
  72                 prj_src add {{file|tcl_escape}}
  73             {% endfor %}
  74             prj_src add {{name}}.v
  75             prj_impl option top {{name}}
  76             prj_src add {{name}}.sdc
  77             {{get_override("script_project")|default("# (script_project placeholder)")}}
  78             prj_project save
  79             prj_run Synthesis -impl impl -forceAll
  80             prj_run Translate -impl impl -forceAll
  81             prj_run Map -impl impl -forceAll
  82             prj_run PAR -impl impl -forceAll
  83             prj_run Export -impl impl -forceAll -task Bitgen
  84             prj_run Export -impl impl -forceAll -task Jedecgen
  85             {{get_override("script_after_export")|default("# (script_after_export placeholder)")}}
  86         """,
  87         "{{name}}.lpf": r"""
  88             # {{autogenerated}}
  89             BLOCK ASYNCPATHS;
  90             BLOCK RESETPATHS;
  91             {% for port_name, pin_name, attrs in platform.iter_port_constraints_bits() -%}
  92                 LOCATE COMP "{{port_name}}" SITE "{{pin_name}}";
  93                 {% if attrs -%}
  94                 IOBUF PORT "{{port_name}}"
  95                     {%- for key, value in attrs.items() %} {{key}}={{value}}{% endfor %};
  96                 {% endif %}
  97             {% endfor %}
  98             {{get_override("add_preferences")|default("# (add_preferences placeholder)")}}
  99         """,
 100         "{{name}}.sdc": r"""
 101             {% for net_signal, port_signal, frequency in platform.iter_clock_constraints() -%}
 102                 {% if port_signal is not none -%}
 103                     create_clock -name {{port_signal.name|tcl_escape}} -period {{1000000000/frequency}} [get_ports {{port_signal.name|tcl_escape}}]
 104                 {% else -%}
 105                     create_clock -name {{net_signal.name|tcl_escape}} -period {{1000000000/frequency}} [get_nets {{net_signal|hierarchy("/")|tcl_escape}}]
 106                 {% endif %}
 107             {% endfor %}
 108             {{get_override("add_constraints")|default("# (add_constraints placeholder)")}}
 109         """,
 110     }
 111     command_templates = [
 112         # These don't have any usable command-line option overrides.
 113         r"""
 114         {{invoke_tool("pnmainc")}}
 115             {{name}}.tcl
 116         """,
 117         r"""
 118         {{invoke_tool("ddtcmd")}}
 119             -oft -bit
 120             -if {{name}}_impl/{{name}}_impl.bit -of {{name}}.bit
 121         """,
 122         r"""
 123         {{invoke_tool("ddtcmd")}}
 124             -oft -jed
 125             -dev {{platform.device}}-{{platform.speed}}{{platform.package}}{{platform.grade}}
 126             -if {{name}}_impl/{{name}}_impl.jed -of {{name}}.jed
 127         """,
 128         r"""
 129         {{invoke_tool("ddtcmd")}}
 130             -oft -svfsingle -revd -op "FLASH Erase,Program,Verify"
 131             -if {{name}}_impl/{{name}}_impl.jed -of {{name}}.svf
 132         """,
 133     ]
 134
 135     def create_missing_domain(self, name):
 136         # Lattice MachXO2/MachXO3L devices have two global set/reset signals: PUR, which is driven at
 137         # startup by the configuration logic and unconditionally resets every storage element,
 138         # and GSR, which is driven by user logic and each storage element may be configured as
 139         # affected or unaffected by GSR. PUR is purely asynchronous, so even though it is
 140         # a low-skew global network, its deassertion may violate a setup/hold constraint with
 141         # relation to a user clock. To avoid this, a GSR/SGSR instance should be driven
 142         # synchronized to user clock.
 143         if name == "sync" and self.default_clk is not None:
 144             clk_i = self.request(self.default_clk).i
 145             if self.default_rst is not None:
 146                 rst_i = self.request(self.default_rst).i
 147             else:
 148                 rst_i = Const(0)
 149
 150             gsr0 = Signal()
 151             gsr1 = Signal()
 152             m = Module()
 153             # There is no end-of-startup signal on MachXO2/MachXO3L, but PUR is released after IOB
 154             # enable, so a simple reset synchronizer (with PUR as the asynchronous reset) does the job.
 155             m.submodules += [
 156                 Instance("FD1S3AX", p_GSR="DISABLED", i_CK=clk_i, i_D=~rst_i, o_Q=gsr0),
 157                 Instance("FD1S3AX", p_GSR="DISABLED", i_CK=clk_i, i_D=gsr0,   o_Q=gsr1),
 158                 # Although we already synchronize the reset input to user clock, SGSR has dedicated
 159                 # clock routing to the center of the FPGA; use that just in case it turns out to be
 160                 # more reliable. (None of this is documented.)
 161                 Instance("SGSR", i_CLK=clk_i, i_GSR=gsr1),
 162             ]
 163             # GSR implicitly connects to every appropriate storage element. As such, the sync
 164             # domain is reset-less; domains driven by other clocks would need to have dedicated
 165             # reset circuitry or otherwise meet setup/hold constraints on their own.
 166             m.domains += ClockDomain("sync", reset_less=True)
 167             m.d.comb += ClockSignal("sync").eq(clk_i)
 168             return m
 169
 170     _single_ended_io_types = [
 171         "PCI33", "LVTTL33", "LVCMOS33", "LVCMOS25", "LVCMOS18", "LVCMOS15", "LVCMOS12",
 172         "LVCMOS25R33", "LVCMOS18R33", "LVCMOS18R25", "LVCMOS15R33", "LVCMOS15R25", "LVCMOS12R33",
 173         "LVCMOS12R25", "LVCMOS10R33", "LVCMOS10R25", "SSTL25_I", "SSTL25_II", "SSTL18_I",
 174         "SSTL18_II", "HSTL18_I", "HSTL18_II",
 175     ]
 176     _differential_io_types = [
 177         "LVDS25", "LVDS25E", "RSDS25", "RSDS25E", "BLVDS25", "BLVDS25E", "MLVDS25", "MLVDS25E",
 178         "LVPECL33", "LVPECL33E", "SSTL25D_I", "SSTL25D_II", "SSTL18D_I", "SSTL18D_II",
 179         "HSTL18D_I", "HSTL18D_II", "LVTTL33D", "LVCMOS33D", "LVCMOS25D", "LVCMOS18D", "LVCMOS15D",
 180         "LVCMOS12D", "MIPI",
 181     ]
 182
 183     def should_skip_port_component(self, port, attrs, component):
 184         # On ECP5, a differential IO is placed by only instantiating an IO buffer primitive at
 185         # the PIOA or PIOC location, which is always the non-inverting pin.
 186         if attrs.get("IO_TYPE", "LVCMOS25") in self._differential_io_types and component == "n":
 187             return True
 188         return False
 189
 190     def _get_xdr_buffer(self, m, pin, *, i_invert=False, o_invert=False):
 191         def get_ireg(clk, d, q):
 192             for bit in range(len(q)):
 193                 m.submodules += Instance("IFS1P3DX",
 194                     i_SCLK=clk,
 195                     i_SP=Const(1),
 196                     i_CD=Const(0),
 197                     i_D=d[bit],
 198                     o_Q=q[bit]
 199                 )
 200
 201         def get_oreg(clk, d, q):
 202             for bit in range(len(q)):
 203                 m.submodules += Instance("OFS1P3DX",
 204                     i_SCLK=clk,
 205                     i_SP=Const(1),
 206                     i_CD=Const(0),
 207                     i_D=d[bit],
 208                     o_Q=q[bit]
 209                 )
 210
 211         def get_iddr(sclk, d, q0, q1):
 212             for bit in range(len(d)):
 213                 m.submodules += Instance("IDDRXE",
 214                     i_SCLK=sclk,
 215                     i_RST=Const(0),
 216                     i_D=d[bit],
 217                     o_Q0=q0[bit], o_Q1=q1[bit]
 218                 )
 219
 220         def get_oddr(sclk, d0, d1, q):
 221             for bit in range(len(q)):
 222                 m.submodules += Instance("ODDRXE",
 223                     i_SCLK=sclk,
 224                     i_RST=Const(0),
 225                     i_D0=d0[bit], i_D1=d1[bit],
 226                     o_Q=q[bit]
 227                 )
 228
 229         def get_ineg(z, invert):
 230             if invert:
 231                 a = Signal.like(z, name_suffix="_n")
 232                 m.d.comb += z.eq(~a)
 233                 return a
 234             else:
 235                 return z
 236
 237         def get_oneg(a, invert):
 238             if invert:
 239                 z = Signal.like(a, name_suffix="_n")
 240                 m.d.comb += z.eq(~a)
 241                 return z
 242             else:
 243                 return a
 244
 245         if "i" in pin.dir:
 246             if pin.xdr < 2:
 247                 pin_i  = get_ineg(pin.i,  i_invert)
 248             elif pin.xdr == 2:
 249                 pin_i0 = get_ineg(pin.i0, i_invert)
 250                 pin_i1 = get_ineg(pin.i1, i_invert)
 251         if "o" in pin.dir:
 252             if pin.xdr < 2:
 253                 pin_o  = get_oneg(pin.o,  o_invert)
 254             elif pin.xdr == 2:
 255                 pin_o0 = get_oneg(pin.o0, o_invert)
 256                 pin_o1 = get_oneg(pin.o1, o_invert)
 257
 258         i = o = t = None
 259         if "i" in pin.dir:
 260             i = Signal(pin.width, name="{}_xdr_i".format(pin.name))
 261         if "o" in pin.dir:
 262             o = Signal(pin.width, name="{}_xdr_o".format(pin.name))
 263         if pin.dir in ("oe", "io"):
 264             t = Signal(1,         name="{}_xdr_t".format(pin.name))
 265
 266         if pin.xdr == 0:
 267             if "i" in pin.dir:
 268                 i = pin_i
 269             if "o" in pin.dir:
 270                 o = pin_o
 271             if pin.dir in ("oe", "io"):
 272                 t = ~pin.oe
 273         elif pin.xdr == 1:
 274             # Note that currently nextpnr will not pack an FF (*FS1P3DX) into the PIO.
 275             if "i" in pin.dir:
 276                 get_ireg(pin.i_clk, i, pin_i)
 277             if "o" in pin.dir:
 278                 get_oreg(pin.o_clk, pin_o, o)
 279             if pin.dir in ("oe", "io"):
 280                 get_oreg(pin.o_clk, ~pin.oe, t)
 281         elif pin.xdr == 2:
 282             if "i" in pin.dir:
 283                 get_iddr(pin.i_clk, i, pin_i0, pin_i1)
 284             if "o" in pin.dir:
 285                 get_oddr(pin.o_clk, pin_o0, pin_o1, o)
 286             if pin.dir in ("oe", "io"):
 287                 # It looks like Diamond will not pack an OREG as a tristate register in a DDR PIO.
 288                 # It is not clear what is the recommended set of primitives for this task.
 289                 # Similarly, nextpnr will not pack anything as a tristate register in a DDR PIO.
 290                 get_oreg(pin.o_clk, ~pin.oe, t)
 291         else:
 292             assert False
 293
 294         return (i, o, t)
 295
 296     def get_input(self, pin, port, attrs, invert):
 297         self._check_feature("single-ended input", pin, attrs,
 298                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 299         m = Module()
 300         i, o, t = self._get_xdr_buffer(m, pin, i_invert=invert)
 301         for bit in range(len(port)):
 302             m.submodules["{}_{}".format(pin.name, bit)] = Instance("IB",
 303                 i_I=port[bit],
 304                 o_O=i[bit]
 305             )
 306         return m
 307
 308     def get_output(self, pin, port, attrs, invert):
 309         self._check_feature("single-ended output", pin, attrs,
 310                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 311         m = Module()
 312         i, o, t = self._get_xdr_buffer(m, pin, o_invert=invert)
 313         for bit in range(len(port)):
 314             m.submodules["{}_{}".format(pin.name, bit)] = Instance("OB",
 315                 i_I=o[bit],
 316                 o_O=port[bit]
 317             )
 318         return m
 319
 320     def get_tristate(self, pin, port, attrs, invert):
 321         self._check_feature("single-ended tristate", pin, attrs,
 322                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 323         m = Module()
 324         i, o, t = self._get_xdr_buffer(m, pin, o_invert=invert)
 325         for bit in range(len(port)):
 326             m.submodules["{}_{}".format(pin.name, bit)] = Instance("OBZ",
 327                 i_T=t,
 328                 i_I=o[bit],
 329                 o_O=port[bit]
 330             )
 331         return m
 332
 333     def get_input_output(self, pin, port, attrs, invert):
 334         self._check_feature("single-ended input/output", pin, attrs,
 335                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 336         m = Module()
 337         i, o, t = self._get_xdr_buffer(m, pin, i_invert=invert, o_invert=invert)
 338         for bit in range(len(port)):
 339             m.submodules["{}_{}".format(pin.name, bit)] = Instance("BB",
 340                 i_T=t,
 341                 i_I=o[bit],
 342                 o_O=i[bit],
 343                 io_B=port[bit]
 344             )
 345         return m
 346
 347     def get_diff_input(self, pin, p_port, n_port, attrs, invert):
 348         self._check_feature("differential input", pin, attrs,
 349                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 350         m = Module()
 351         i, o, t = self._get_xdr_buffer(m, pin, i_invert=invert)
 352         for bit in range(len(p_port)):
 353             m.submodules["{}_{}".format(pin.name, bit)] = Instance("IB",
 354                 i_I=p_port[bit],
 355                 o_O=i[bit]
 356             )
 357         return m
 358
 359     def get_diff_output(self, pin, p_port, n_port, attrs, invert):
 360         self._check_feature("differential output", pin, attrs,
 361                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 362         m = Module()
 363         i, o, t = self._get_xdr_buffer(m, pin, o_invert=invert)
 364         for bit in range(len(p_port)):
 365             m.submodules["{}_{}".format(pin.name, bit)] = Instance("OB",
 366                 i_I=o[bit],
 367                 o_O=p_port[bit],
 368             )
 369         return m
 370
 371     def get_diff_tristate(self, pin, p_port, n_port, attrs, invert):
 372         self._check_feature("differential tristate", pin, attrs,
 373                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 374         m = Module()
 375         i, o, t = self._get_xdr_buffer(m, pin, o_invert=invert)
 376         for bit in range(len(p_port)):
 377             m.submodules["{}_{}".format(pin.name, bit)] = Instance("OBZ",
 378                 i_T=t,
 379                 i_I=o[bit],
 380                 o_O=p_port[bit],
 381             )
 382         return m
 383
 384     def get_diff_input_output(self, pin, p_port, n_port, attrs, invert):
 385         self._check_feature("differential input/output", pin, attrs,
 386                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 387         m = Module()
 388         i, o, t = self._get_xdr_buffer(m, pin, i_invert=invert, o_invert=invert)
 389         for bit in range(len(p_port)):
 390             m.submodules["{}_{}".format(pin.name, bit)] = Instance("BB",
 391                 i_T=t,
 392                 i_I=o[bit],
 393                 o_O=i[bit],
 394                 io_B=p_port[bit],
 395             )
 396         return m
 397
 398     # CDC primitives are not currently specialized for MachXO2/MachXO3L.
 399
 400
 401 LatticeMachXO2Platform = LatticeMachXO2Or3LPlatform
 402 LatticeMachXO3LPlatform = LatticeMachXO2Or3LPlatform