nmigen/vendor/lattice_machxo_2_3l.py

   1 from abc import abstractproperty
   2
   3 from ..hdl import *
   4 from ..build import *
   5
   6
   7 __all__ = ["LatticeMachXO2Platform", "LatticeMachXO3LPlatform"]
   8
   9
  10 # MachXO2 and MachXO3L primitives are the same. Handle both using
  11 # one class and expose user-aliases for convenience.
  12 class LatticeMachXO2Or3LPlatform(TemplatedPlatform):
  13     """
  14     Required tools:
  15         * ``pnmainc``
  16         * ``ddtcmd``
  17
  18     The environment is populated by running the script specified in the environment variable
  19     ``NMIGEN_ENV_Diamond``, if present.
  20
  21     Available overrides:
  22         * ``script_project``: inserts commands before ``prj_project save`` in Tcl script.
  23         * ``script_after_export``: inserts commands after ``prj_run Export`` in Tcl script.
  24         * ``add_preferences``: inserts commands at the end of the LPF file.
  25         * ``add_constraints``: inserts commands at the end of the XDC file.
  26
  27     Build products:
  28         * ``{{name}}_impl/{{name}}_impl.htm``: consolidated log.
  29         * ``{{name}}.jed``: JEDEC fuse file.
  30         * ``{{name}}.bit``: binary bitstream.
  31         * ``{{name}}.svf``: JTAG programming vector.
  32     """
  33
  34     toolchain = "Diamond"
  35
  36     device  = abstractproperty()
  37     package = abstractproperty()
  38     speed   = abstractproperty()
  39     grade   = "C" # [C]ommercial, [I]ndustrial
  40
  41     required_tools = [
  42         "pnmainc",
  43         "ddtcmd"
  44     ]
  45     file_templates = {
  46         **TemplatedPlatform.build_script_templates,
  47         "build_{{name}}.sh": r"""
  48             # {{autogenerated}}
  49             set -e{{verbose("x")}}
  50             if [ -z "$BASH" ] ; then exec /bin/bash "$0" "$@"; fi
  51             if [ -n "${{platform._toolchain_env_var}}" ]; then
  52                 bindir=$(dirname "${{platform._toolchain_env_var}}")
  53                 . "${{platform._toolchain_env_var}}"
  54             fi
  55             {{emit_commands("sh")}}
  56         """,
  57         "{{name}}.v": r"""
  58             /* {{autogenerated}} */
  59             {{emit_verilog()}}
  60         """,
  61         "{{name}}.debug.v": r"""
  62             /* {{autogenerated}} */
  63             {{emit_debug_verilog()}}
  64         """,
  65         "{{name}}.tcl": r"""
  66             prj_project new -name {{name}} -impl impl -impl_dir top_impl \
  67                 -dev {{platform.device}}-{{platform.speed}}{{platform.package}}{{platform.grade}} \
  68                 -lpf {{name}}.lpf \
  69                 -synthesis synplify
  70             {% for file in platform.iter_extra_files(".v", ".sv", ".vhd", ".vhdl") -%}
  71                 prj_src add {{file|tcl_escape}}
  72             {% endfor %}
  73             prj_src add {{name}}.v
  74             prj_impl option top {{name}}
  75             prj_src add {{name}}.sdc
  76             {{get_override("script_project")|default("# (script_project placeholder)")}}
  77             prj_project save
  78             prj_run Synthesis -impl impl -forceAll
  79             prj_run Translate -impl impl -forceAll
  80             prj_run Map -impl impl -forceAll
  81             prj_run PAR -impl impl -forceAll
  82             prj_run Export -impl impl -forceAll -task Bitgen
  83             prj_run Export -impl impl -forceAll -task Jedecgen
  84             {{get_override("script_after_export")|default("# (script_after_export placeholder)")}}
  85         """,
  86         "{{name}}.lpf": r"""
  87             # {{autogenerated}}
  88             BLOCK ASYNCPATHS;
  89             BLOCK RESETPATHS;
  90             {% for port_name, pin_name, attrs in platform.iter_port_constraints_bits() -%}
  91                 LOCATE COMP "{{port_name}}" SITE "{{pin_name}}";
  92                 {% if attrs -%}
  93                 IOBUF PORT "{{port_name}}"
  94                     {%- for key, value in attrs.items() %} {{key}}={{value}}{% endfor %};
  95                 {% endif %}
  96             {% endfor %}
  97             {{get_override("add_preferences")|default("# (add_preferences placeholder)")}}
  98         """,
  99         "{{name}}.sdc": r"""
 100             {% for net_signal, port_signal, frequency in platform.iter_clock_constraints() -%}
 101                 {% if port_signal is not none -%}
 102                     create_clock -name {{port_signal.name|tcl_escape}} -period {{1000000000/frequency}} [get_ports {{port_signal.name|tcl_escape}}]
 103                 {% else -%}
 104                     create_clock -name {{net_signal.name|tcl_escape}} -period {{1000000000/frequency}} [get_nets {{net_signal|hierarchy("/")|tcl_escape}}]
 105                 {% endif %}
 106             {% endfor %}
 107             {{get_override("add_constraints")|default("# (add_constraints placeholder)")}}
 108         """,
 109     }
 110     command_templates = [
 111         # These don't have any usable command-line option overrides.
 112         r"""
 113         {{invoke_tool("pnmainc")}}
 114             {{name}}.tcl
 115         """,
 116         r"""
 117         {{invoke_tool("ddtcmd")}}
 118             -oft -bit
 119             -if {{name}}_impl/{{name}}_impl.bit -of {{name}}.bit
 120         """,
 121         r"""
 122         {{invoke_tool("ddtcmd")}}
 123             -oft -jed
 124             -dev {{platform.device}}-{{platform.speed}}{{platform.package}}{{platform.grade}}
 125             -if {{name}}_impl/{{name}}_impl.jed -of {{name}}.jed
 126         """,
 127         r"""
 128         {{invoke_tool("ddtcmd")}}
 129             -oft -svfsingle -revd -op "FLASH Erase,Program,Verify"
 130             -if {{name}}_impl/{{name}}_impl.jed -of {{name}}.svf
 131         """,
 132     ]
 133
 134     def create_missing_domain(self, name):
 135         # Lattice MachXO2/MachXO3L devices have two global set/reset signals: PUR, which is driven at
 136         # startup by the configuration logic and unconditionally resets every storage element,
 137         # and GSR, which is driven by user logic and each storage element may be configured as
 138         # affected or unaffected by GSR. PUR is purely asynchronous, so even though it is
 139         # a low-skew global network, its deassertion may violate a setup/hold constraint with
 140         # relation to a user clock. To avoid this, a GSR/SGSR instance should be driven
 141         # synchronized to user clock.
 142         if name == "sync" and self.default_clk is not None:
 143             clk_i = self.request(self.default_clk).i
 144             if self.default_rst is not None:
 145                 rst_i = self.request(self.default_rst).i
 146             else:
 147                 rst_i = Const(0)
 148
 149             gsr0 = Signal()
 150             gsr1 = Signal()
 151             m = Module()
 152             # There is no end-of-startup signal on MachXO2/MachXO3L, but PUR is released after IOB
 153             # enable, so a simple reset synchronizer (with PUR as the asynchronous reset) does the job.
 154             m.submodules += [
 155                 Instance("FD1S3AX", p_GSR="DISABLED", i_CK=clk_i, i_D=~rst_i, o_Q=gsr0),
 156                 Instance("FD1S3AX", p_GSR="DISABLED", i_CK=clk_i, i_D=gsr0,   o_Q=gsr1),
 157                 # Although we already synchronize the reset input to user clock, SGSR has dedicated
 158                 # clock routing to the center of the FPGA; use that just in case it turns out to be
 159                 # more reliable. (None of this is documented.)
 160                 Instance("SGSR", i_CLK=clk_i, i_GSR=gsr1),
 161             ]
 162             # GSR implicitly connects to every appropriate storage element. As such, the sync
 163             # domain is reset-less; domains driven by other clocks would need to have dedicated
 164             # reset circuitry or otherwise meet setup/hold constraints on their own.
 165             m.domains += ClockDomain("sync", reset_less=True)
 166             m.d.comb += ClockSignal("sync").eq(clk_i)
 167             return m
 168
 169     _single_ended_io_types = [
 170         "PCI33", "LVTTL33", "LVCMOS33", "LVCMOS25", "LVCMOS18", "LVCMOS15", "LVCMOS12",
 171         "LVCMOS25R33", "LVCMOS18R33", "LVCMOS18R25", "LVCMOS15R33", "LVCMOS15R25", "LVCMOS12R33",
 172         "LVCMOS12R25", "LVCMOS10R33", "LVCMOS10R25", "SSTL25_I", "SSTL25_II", "SSTL18_I",
 173         "SSTL18_II", "HSTL18_I", "HSTL18_II",
 174     ]
 175     _differential_io_types = [
 176         "LVDS25", "LVDS25E", "RSDS25", "RSDS25E", "BLVDS25", "BLVDS25E", "MLVDS25", "MLVDS25E",
 177         "LVPECL33", "LVPECL33E", "SSTL25D_I", "SSTL25D_II", "SSTL18D_I", "SSTL18D_II",
 178         "HSTL18D_I", "HSTL18D_II", "LVTTL33D", "LVCMOS33D", "LVCMOS25D", "LVCMOS18D", "LVCMOS15D",
 179         "LVCMOS12D", "MIPI",
 180     ]
 181
 182     def should_skip_port_component(self, port, attrs, component):
 183         # On ECP5, a differential IO is placed by only instantiating an IO buffer primitive at
 184         # the PIOA or PIOC location, which is always the non-inverting pin.
 185         if attrs.get("IO_TYPE", "LVCMOS25") in self._differential_io_types and component == "n":
 186             return True
 187         return False
 188
 189     def _get_xdr_buffer(self, m, pin, *, i_invert=False, o_invert=False):
 190         def get_ireg(clk, d, q):
 191             for bit in range(len(q)):
 192                 m.submodules += Instance("IFS1P3DX",
 193                     i_SCLK=clk,
 194                     i_SP=Const(1),
 195                     i_CD=Const(0),
 196                     i_D=d[bit],
 197                     o_Q=q[bit]
 198                 )
 199
 200         def get_oreg(clk, d, q):
 201             for bit in range(len(q)):
 202                 m.submodules += Instance("OFS1P3DX",
 203                     i_SCLK=clk,
 204                     i_SP=Const(1),
 205                     i_CD=Const(0),
 206                     i_D=d[bit],
 207                     o_Q=q[bit]
 208                 )
 209
 210         def get_iddr(sclk, d, q0, q1):
 211             for bit in range(len(d)):
 212                 m.submodules += Instance("IDDRXE",
 213                     i_SCLK=sclk,
 214                     i_RST=Const(0),
 215                     i_D=d[bit],
 216                     o_Q0=q0[bit], o_Q1=q1[bit]
 217                 )
 218
 219         def get_oddr(sclk, d0, d1, q):
 220             for bit in range(len(q)):
 221                 m.submodules += Instance("ODDRXE",
 222                     i_SCLK=sclk,
 223                     i_RST=Const(0),
 224                     i_D0=d0[bit], i_D1=d1[bit],
 225                     o_Q=q[bit]
 226                 )
 227
 228         def get_ineg(z, invert):
 229             if invert:
 230                 a = Signal.like(z, name_suffix="_n")
 231                 m.d.comb += z.eq(~a)
 232                 return a
 233             else:
 234                 return z
 235
 236         def get_oneg(a, invert):
 237             if invert:
 238                 z = Signal.like(a, name_suffix="_n")
 239                 m.d.comb += z.eq(~a)
 240                 return z
 241             else:
 242                 return a
 243
 244         if "i" in pin.dir:
 245             if pin.xdr < 2:
 246                 pin_i  = get_ineg(pin.i,  i_invert)
 247             elif pin.xdr == 2:
 248                 pin_i0 = get_ineg(pin.i0, i_invert)
 249                 pin_i1 = get_ineg(pin.i1, i_invert)
 250         if "o" in pin.dir:
 251             if pin.xdr < 2:
 252                 pin_o  = get_oneg(pin.o,  o_invert)
 253             elif pin.xdr == 2:
 254                 pin_o0 = get_oneg(pin.o0, o_invert)
 255                 pin_o1 = get_oneg(pin.o1, o_invert)
 256
 257         i = o = t = None
 258         if "i" in pin.dir:
 259             i = Signal(pin.width, name="{}_xdr_i".format(pin.name))
 260         if "o" in pin.dir:
 261             o = Signal(pin.width, name="{}_xdr_o".format(pin.name))
 262         if pin.dir in ("oe", "io"):
 263             t = Signal(1,         name="{}_xdr_t".format(pin.name))
 264
 265         if pin.xdr == 0:
 266             if "i" in pin.dir:
 267                 i = pin_i
 268             if "o" in pin.dir:
 269                 o = pin_o
 270             if pin.dir in ("oe", "io"):
 271                 t = ~pin.oe
 272         elif pin.xdr == 1:
 273             # Note that currently nextpnr will not pack an FF (*FS1P3DX) into the PIO.
 274             if "i" in pin.dir:
 275                 get_ireg(pin.i_clk, i, pin_i)
 276             if "o" in pin.dir:
 277                 get_oreg(pin.o_clk, pin_o, o)
 278             if pin.dir in ("oe", "io"):
 279                 get_oreg(pin.o_clk, ~pin.oe, t)
 280         elif pin.xdr == 2:
 281             if "i" in pin.dir:
 282                 get_iddr(pin.i_clk, i, pin_i0, pin_i1)
 283             if "o" in pin.dir:
 284                 get_oddr(pin.o_clk, pin_o0, pin_o1, o)
 285             if pin.dir in ("oe", "io"):
 286                 # It looks like Diamond will not pack an OREG as a tristate register in a DDR PIO.
 287                 # It is not clear what is the recommended set of primitives for this task.
 288                 # Similarly, nextpnr will not pack anything as a tristate register in a DDR PIO.
 289                 get_oreg(pin.o_clk, ~pin.oe, t)
 290         else:
 291             assert False
 292
 293         return (i, o, t)
 294
 295     def get_input(self, pin, port, attrs, invert):
 296         self._check_feature("single-ended input", pin, attrs,
 297                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 298         m = Module()
 299         i, o, t = self._get_xdr_buffer(m, pin, i_invert=invert)
 300         for bit in range(len(port)):
 301             m.submodules["{}_{}".format(pin.name, bit)] = Instance("IB",
 302                 i_I=port[bit],
 303                 o_O=i[bit]
 304             )
 305         return m
 306
 307     def get_output(self, pin, port, attrs, invert):
 308         self._check_feature("single-ended output", pin, attrs,
 309                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 310         m = Module()
 311         i, o, t = self._get_xdr_buffer(m, pin, o_invert=invert)
 312         for bit in range(len(port)):
 313             m.submodules["{}_{}".format(pin.name, bit)] = Instance("OB",
 314                 i_I=o[bit],
 315                 o_O=port[bit]
 316             )
 317         return m
 318
 319     def get_tristate(self, pin, port, attrs, invert):
 320         self._check_feature("single-ended tristate", pin, attrs,
 321                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 322         m = Module()
 323         i, o, t = self._get_xdr_buffer(m, pin, o_invert=invert)
 324         for bit in range(len(port)):
 325             m.submodules["{}_{}".format(pin.name, bit)] = Instance("OBZ",
 326                 i_T=t,
 327                 i_I=o[bit],
 328                 o_O=port[bit]
 329             )
 330         return m
 331
 332     def get_input_output(self, pin, port, attrs, invert):
 333         self._check_feature("single-ended input/output", pin, attrs,
 334                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 335         m = Module()
 336         i, o, t = self._get_xdr_buffer(m, pin, i_invert=invert, o_invert=invert)
 337         for bit in range(len(port)):
 338             m.submodules["{}_{}".format(pin.name, bit)] = Instance("BB",
 339                 i_T=t,
 340                 i_I=o[bit],
 341                 o_O=i[bit],
 342                 io_B=port[bit]
 343             )
 344         return m
 345
 346     def get_diff_input(self, pin, p_port, n_port, attrs, invert):
 347         self._check_feature("differential input", pin, attrs,
 348                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 349         m = Module()
 350         i, o, t = self._get_xdr_buffer(m, pin, i_invert=invert)
 351         for bit in range(len(p_port)):
 352             m.submodules["{}_{}".format(pin.name, bit)] = Instance("IB",
 353                 i_I=p_port[bit],
 354                 o_O=i[bit]
 355             )
 356         return m
 357
 358     def get_diff_output(self, pin, p_port, n_port, attrs, invert):
 359         self._check_feature("differential output", pin, attrs,
 360                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 361         m = Module()
 362         i, o, t = self._get_xdr_buffer(m, pin, o_invert=invert)
 363         for bit in range(len(p_port)):
 364             m.submodules["{}_{}".format(pin.name, bit)] = Instance("OB",
 365                 i_I=o[bit],
 366                 o_O=p_port[bit],
 367             )
 368         return m
 369
 370     def get_diff_tristate(self, pin, p_port, n_port, attrs, invert):
 371         self._check_feature("differential tristate", pin, attrs,
 372                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 373         m = Module()
 374         i, o, t = self._get_xdr_buffer(m, pin, o_invert=invert)
 375         for bit in range(len(p_port)):
 376             m.submodules["{}_{}".format(pin.name, bit)] = Instance("OBZ",
 377                 i_T=t,
 378                 i_I=o[bit],
 379                 o_O=p_port[bit],
 380             )
 381         return m
 382
 383     def get_diff_input_output(self, pin, p_port, n_port, attrs, invert):
 384         self._check_feature("differential input/output", pin, attrs,
 385                             valid_xdrs=(0, 1, 2), valid_attrs=True)
 386         m = Module()
 387         i, o, t = self._get_xdr_buffer(m, pin, i_invert=invert, o_invert=invert)
 388         for bit in range(len(p_port)):
 389             m.submodules["{}_{}".format(pin.name, bit)] = Instance("BB",
 390                 i_T=t,
 391                 i_I=o[bit],
 392                 o_O=i[bit],
 393                 io_B=p_port[bit],
 394             )
 395         return m
 396
 397     # CDC primitives are not currently specialized for MachXO2/MachXO3L.
 398
 399
 400 LatticeMachXO2Platform = LatticeMachXO2Or3LPlatform
 401 LatticeMachXO3LPlatform = LatticeMachXO2Or3LPlatform