4 from nmigen
.build
import *
5 from nmigen
.vendor
.lattice_ice40
import *
8 __all__
= ["TinyFPGABXPlatform"]
11 class TinyFPGABXPlatform(LatticeICE40Platform
):
18 Resource("clk16", 0, Pins("B2", dir="i"),
19 extras
={"IO_STANDARD": "SB_LVCMOS33"}),
21 Resource("user_led", 0, Pins("B3", dir="o"), extras
={"IO_STANDARD": "SB_LVCMOS33"}),
24 Subsignal("d_p", Pins("B4", dir="io")),
25 Subsignal("d_n", Pins("A4", dir="io")),
26 Subsignal("pullup", Pins("A3", dir="o")),
27 extras
={"IO_STANDARD": "SB_LVCMOS33"}
30 Resource("spiflash", 0,
31 Subsignal("cs_n", Pins("F7", dir="o")),
32 Subsignal("clk", Pins("G7", dir="o")),
33 Subsignal("mosi", Pins("G6", dir="o")),
34 Subsignal("miso", Pins("H7", dir="i")),
35 Subsignal("wp", Pins("H4", dir="o")),
36 Subsignal("hold", Pins("J8", dir="o")),
37 extras
={"IO_STANDARD": "SB_LVCMOS33"}
40 Resource("spiflash4x", 0,
41 Subsignal("cs_n", Pins("F7", dir="o")),
42 Subsignal("clk", Pins("G7", dir="o")),
43 Subsignal("dq", Pins("G6 H7 H4 J8", dir="io")),
44 extras
={"IO_STANDARD": "SB_LVCMOS33"}
49 # Left side of the board
50 # 1 2 3 4 5 6 7 8 9 10 11 12 13
51 " A2 A1 B1 C2 C1 D2 D1 E2 E1 G2 H1 J1 H2"
52 # Right side of the board
53 # 14 15 16 17 18 19 20 21 22 23 24
54 " H9 D9 D8 B8 A9 B8 A8 B7 A7 B6 A6"
56 # 25 26 27 28 29 30 31
57 "G1 J3 J4 G9 J9 E8 J2"),
60 def toolchain_program(self
, products
, name
):
61 tinyprog
= os
.environ
.get("TINYPROG", "tinyprog")
62 with products
.extract("{}.bin".format(name
)) as bitstream_filename
:
63 subprocess
.run([tinyprog
, "-p", bitstream_filename
], check
=True)