4 from nmigen
.build
import *
5 from nmigen
.vendor
.lattice_ecp5
import *
9 __all__
= ["VersaECP5Platform"]
12 class VersaECP5Platform(LatticeECP5Platform
):
17 Resource("rst", 0, PinsN("T1", dir="i"), Attrs(IO_TYPE
="LVCMOS33")),
18 Resource("clk100", 0, DiffPairs("P3", "P4", dir="i"),
19 Clock(100e6
), Attrs(IO_TYPE
="LVDS")),
20 Resource("pclk", 0, DiffPairs("A4", "A5", dir="i"),
21 Attrs(IO_TYPE
="LVDS")),
23 Resource("user_led", 0, PinsN("E16", dir="o"), Attrs(IO_TYPE
="LVCMOS25")),
24 Resource("user_led", 1, PinsN("D17", dir="o"), Attrs(IO_TYPE
="LVCMOS25")),
25 Resource("user_led", 2, PinsN("D18", dir="o"), Attrs(IO_TYPE
="LVCMOS25")),
26 Resource("user_led", 3, PinsN("E18", dir="o"), Attrs(IO_TYPE
="LVCMOS25")),
27 Resource("user_led", 4, PinsN("F17", dir="o"), Attrs(IO_TYPE
="LVCMOS25")),
28 Resource("user_led", 5, PinsN("F18", dir="o"), Attrs(IO_TYPE
="LVCMOS25")),
29 Resource("user_led", 6, PinsN("E17", dir="o"), Attrs(IO_TYPE
="LVCMOS25")),
30 Resource("user_led", 7, PinsN("F16", dir="o"), Attrs(IO_TYPE
="LVCMOS25")),
32 Resource("alnum_led", 0,
33 Subsignal("a", PinsN("M20", dir="o")),
34 Subsignal("b", PinsN("L18", dir="o")),
35 Subsignal("c", PinsN("M19", dir="o")),
36 Subsignal("d", PinsN("L16", dir="o")),
37 Subsignal("e", PinsN("L17", dir="o")),
38 Subsignal("f", PinsN("M18", dir="o")),
39 Subsignal("g", PinsN("N16", dir="o")),
40 Subsignal("h", PinsN("M17", dir="o")),
41 Subsignal("j", PinsN("N18", dir="o")),
42 Subsignal("k", PinsN("P17", dir="o")),
43 Subsignal("l", PinsN("N17", dir="o")),
44 Subsignal("m", PinsN("P16", dir="o")),
45 Subsignal("n", PinsN("R16", dir="o")),
46 Subsignal("p", PinsN("R17", dir="o")),
47 Subsignal("dp", PinsN("U1", dir="o")),
48 Attrs(IO_TYPE
="LVCMOS25")
51 Resource("user_sw", 0, PinsN("H2", dir="i"), Attrs(IO_TYPE
="LVCMOS15")),
52 Resource("user_sw", 1, PinsN("K3", dir="i"), Attrs(IO_TYPE
="LVCMOS15")),
53 Resource("user_sw", 2, PinsN("G3", dir="i"), Attrs(IO_TYPE
="LVCMOS15")),
54 Resource("user_sw", 3, PinsN("F2", dir="i"), Attrs(IO_TYPE
="LVCMOS15")),
55 Resource("user_sw", 4, PinsN("J18", dir="i"), Attrs(IO_TYPE
="LVCMOS25")),
56 Resource("user_sw", 5, PinsN("K18", dir="i"), Attrs(IO_TYPE
="LVCMOS25")),
57 Resource("user_sw", 6, PinsN("K19", dir="i"), Attrs(IO_TYPE
="LVCMOS25")),
58 Resource("user_sw", 7, PinsN("K20", dir="i"), Attrs(IO_TYPE
="LVCMOS25")),
62 attrs
=Attrs(IO_TYPE
="LVCMOS33", PULLMODE
="UP")
66 cs
="R2", clk
="U3", miso
="W2", mosi
="V2", wp
="Y2", hold
="W1",
67 attrs
=Attrs(IO_STANDARD
="LVCMOS33")
70 Resource("eth_clk125", 0, Pins("L19", dir="i"),
71 Clock(125e6
), Attrs(IO_TYPE
="LVCMOS25")),
72 Resource("eth_clk125_pll", 0, Pins("U16", dir="i"),
73 Clock(125e6
), Attrs(IO_TYPE
="LVCMOS25")), # NC by default
74 Resource("eth_rgmii", 0,
75 Subsignal("rst", PinsN("U17", dir="o")),
76 Subsignal("mdc", Pins("T18", dir="o")),
77 Subsignal("mdio", Pins("U18", dir="io")),
78 Subsignal("tx_clk", Pins("P19", dir="o")),
79 Subsignal("tx_ctl", Pins("R20", dir="o")),
80 Subsignal("tx_data", Pins("N19 N20 P18 P20", dir="o")),
81 Subsignal("rx_clk", Pins("L20", dir="i")),
82 Subsignal("rx_ctl", Pins("U19", dir="i")),
83 Subsignal("rx_data", Pins("T20 U20 T19 R18", dir="i")),
84 Attrs(IO_TYPE
="LVCMOS25")
86 Resource("eth_sgmii", 0,
87 Subsignal("rst", PinsN("U17", dir="o"), Attrs(IO_TYPE
="LVCMOS25")),
88 Subsignal("mdc", Pins("T18", dir="o"), Attrs(IO_TYPE
="LVCMOS25")),
89 Subsignal("mdio", Pins("U18", dir="io"), Attrs(IO_TYPE
="LVCMOS25")),
90 Subsignal("tx", DiffPairs("W13", "W14", dir="o")),
91 Subsignal("rx", DiffPairs("Y14", "Y15", dir="i")),
94 Resource("eth_clk125", 1, Pins("J20", dir="i"),
95 Clock(125e6
), Attrs(IO_TYPE
="LVCMOS25")),
96 Resource("eth_clk125_pll", 1, Pins("C18", dir="i"),
97 Clock(125e6
), Attrs(IO_TYPE
="LVCMOS25")), # NC by default
98 Resource("eth_rgmii", 1,
99 Subsignal("rst", PinsN("F20", dir="o")),
100 Subsignal("mdc", Pins("G19", dir="o")),
101 Subsignal("mdio", Pins("H20", dir="io")),
102 Subsignal("tx_clk", Pins("C20", dir="o")),
103 Subsignal("tx_ctrl", Pins("E19", dir="o")),
104 Subsignal("tx_data", Pins("J17 J16 D19 D20", dir="o")),
105 Subsignal("rx_clk", Pins("J19", dir="i")),
106 Subsignal("rx_ctrl", Pins("F19", dir="i")),
107 Subsignal("rx_data", Pins("G18 G16 H18 H17", dir="i")),
108 Attrs(IO_TYPE
="LVCMOS25")
110 Resource("eth_sgmii", 1,
111 Subsignal("rst", PinsN("F20", dir="o"), Attrs(IO_TYPE
="LVCMOS25")),
112 Subsignal("mdc", Pins("G19", dir="o"), Attrs(IO_TYPE
="LVCMOS25")),
113 Subsignal("mdio", Pins("H20", dir="io"), Attrs(IO_TYPE
="LVCMOS25")),
114 Subsignal("tx", DiffPairs("W17", "W18", dir="o")),
115 Subsignal("rx", DiffPairs("Y16", "Y17", dir="i")),
119 Subsignal("rst", PinsN("N4", dir="o")),
120 Subsignal("clk", DiffPairs("M4", "N5", dir="o"), Attrs(IO_TYPE
="LVDS")),
121 Subsignal("clk_en", Pins("N2", dir="o")),
122 Subsignal("cs", PinsN("K1", dir="o")),
123 Subsignal("we", PinsN("M1", dir="o")),
124 Subsignal("ras", PinsN("P1", dir="o")),
125 Subsignal("cas", PinsN("L1", dir="o")),
126 Subsignal("a", Pins("P2 C4 E5 F5 B3 F4 B5 E4 C5 E3 D5 B4 C3", dir="o")),
127 Subsignal("ba", Pins("P5 N3 M3", dir="o")),
128 Subsignal("dqs", DiffPairs("K2 H4", "J1 G5", dir="io"), Attrs(IO_TYPE
="LVDS")),
129 Subsignal("dq", Pins("L5 F1 K4 G1 L4 H1 G2 J3 D1 C1 E2 C2 F3 A2 E1 B1",
131 Subsignal("dm", Pins("J4 H5", dir="o")),
132 Subsignal("odt", Pins("L2", dir="o")),
133 Attrs(IO_TYPE
="LVCMOS15")
137 Connector("expcon", 1, """
138 - - - B19 B12 B9 E6 D6 E7 D7 B11 B6 E9 D9 B8 C8 D8 E8 C7 C6
139 - - - - - - - - - - - - - - - - - - - -
141 Connector("expcon", 2, """
142 A8 - A12 A13 B13 C13 D13 E13 A14 C14 D14 E14 D11 C10 A9 B10 D12 E12 - -
143 B15 - C15 - D15 - E15 A16 B16 - C16 D16 B17 - C17 A17 B18 A7 A18 -
148 **LatticeECP5Platform
.file_templates
,
149 "{{name}}-openocd.cfg": r
"""
151 {# FTDI descriptors is identical between non-5G and 5G recent Versa boards #}
152 ftdi_device_desc "Lattice ECP5_5G VERSA Board"
153 ftdi_vid_pid 0x0403 0x6010
155 ftdi_layout_init 0xfff8 0xfffb
159 # ispCLOCK device (unusable with openocd and must be bypassed)
160 #jtag newtap ispclock tap -irlen 8 -expected-id 0x00191043
162 {% if "5G" in platform.device -%}
163 jtag newtap ecp5 tap -irlen 8 -expected-id 0x81112043 ; # LFE5UM5G-45F
165 jtag newtap ecp5 tap -irlen 8 -expected-id 0x01112043 ; # LFE5UM-45F
170 def toolchain_program(self
, products
, name
):
171 openocd
= os
.environ
.get("OPENOCD", "openocd")
172 with products
.extract("{}-openocd.cfg".format(name
), "{}.svf".format(name
)) \
173 as (config_filename
, vector_filename
):
174 subprocess
.run([openocd
,
175 "-f", config_filename
,
176 "-c", "transport select jtag; init; svf -quiet {}; exit".format(vector_filename
)
180 if __name__
== "__main__":
181 from ._blinky
import build_and_program
182 build_and_program(VersaECP5Platform
, "clk100")