opcodes/ChangeLog

   1 2017-12-03  Alan Modra  <amodra@gmail.com>
   2
   3         * ppc-opc.c (extract_li20): Rewrite.
   4
   5 2017-12-01  Peter Bergner  <bergner@vnet.ibm.com>
   6
   7         * opcodes/ppc-dis.c (disassemble_init_powerpc): Fix white space.
   8         (operand_value_powerpc): Update return and argument type.
   9         <value, top>: Update type.
  10         (skip_optional_operands): Update argument type.
  11         (lookup_powerpc): Likewise.
  12         (lookup_vle): Likewise.
  13         <table_opcd, table_mask, insn2>: Update type.
  14         (lookup_spe2): Update argument type.
  15         <table_opcd, table_mask, insn2>: Update type.
  16         (print_insn_powerpc) <insn, value>: Update type.
  17         Use PPC_INT_FMT for printing instructions and operands.
  18         * opcodes/ppc-opc.c (insert_arx, extract_arx, insert_ary, extract_ary,
  19         insert_rx, extract_rx, insert_ry, extract_ry, insert_bat, extract_bat,
  20         insert_bba, extract_bba, insert_bdm, extract_bdm, insert_bdp,
  21         extract_bdp, valid_bo_pre_v2, valid_bo_post_v2, valid_bo, insert_bo,
  22         extract_bo, insert_boe, extract_boe, insert_dcmxs, extract_dcmxs,
  23         insert_dxd, extract_dxd, insert_dxdn, extract_dxdn, insert_fxm,
  24         extract_fxm, insert_li20, extract_li20, insert_ls, extract_ls,
  25         insert_esync, extract_esync, insert_mbe, extract_mbe, insert_mb6,
  26         extract_mb6, extract_nb, insert_nbi, insert_nsi, extract_nsi,
  27         insert_ral, extract_ral, insert_ram, extract_ram, insert_raq,
  28         extract_raq, insert_ras, extract_ras, insert_rbs, extract_rbs,
  29         insert_rbx, extract_rbx, insert_sci8, extract_sci8, insert_sci8n,
  30         extract_sci8n, insert_sd4h, extract_sd4h, insert_sd4w, extract_sd4w,
  31         insert_oimm, extract_oimm, insert_sh6, extract_sh6, insert_spr,
  32         extract_spr, insert_sprg, extract_sprg, insert_tbr, extract_tbr,
  33         insert_xt6, extract_xt6, insert_xtq6, extract_xtq6, insert_xa6,
  34         extract_xa6, insert_xb6, extract_xb6, insert_xb6s, extract_xb6s,
  35         insert_xc6, extract_xc6, insert_dm, extract_dm, insert_vlesi,
  36         extract_vlesi, insert_vlensi, extract_vlensi, insert_vleui,
  37         extract_vleui, insert_vleil, extract_vleil, insert_evuimm1_ex0,
  38         extract_evuimm1_ex0, insert_evuimm2_ex0, extract_evuimm2_ex0,
  39         insert_evuimm4_ex0, extract_evuimm4_ex0, insert_evuimm8_ex0,
  40         extract_evuimm8_ex0, insert_evuimm_lt8, extract_evuimm_lt8,
  41         insert_evuimm_lt16, extract_evuimm_lt16, insert_rD_rS_even,
  42         extract_rD_rS_even, insert_off_lsp, extract_off_lsp, insert_off_spe2,
  43         extract_off_spe2, insert_Ddd, extract_Ddd): Update types.
  44         (OP, OPTO, OPL, OPVUP, OPVUPRT, A, AFRALFRC_MASK, B, BD8, BD8IO, BD15,
  45         BD24, BBO, Y_MASK  , AT1_MASK, AT2_MASK, BBOCB, C_LK, C, CTX, UCTX,
  46         DX, EVSEL, IA16, I16A, I16L, IM7, LI20, MME, MD, MDS, SC, SC_MASK,
  47         SCI8, SCI8BF, SD4, SE_IM5, SE_R, SE_RR, VX, VX_LSP, VX_RA_CONST,
  48         VX_RB_CONST, VX_SPE_CRFD, VX_SPE2_CLR, VX_SPE2_SPLATB, VX_SPE2_OCTET,
  49         VX_SPE2_DDHH, VX_SPE2_HH, VX_SPE2_EVMAR, VX_SPE2_EVMAR_MASK, VXA,
  50         VXR, VXASH, X, EX, XX2, XX3, XX3RC, XX4, Z, XWRA_MASK, XLRT_MASK,
  51         XRLARB_MASK, XLRAND_MASK, XRTLRA_MASK, XRTLRARB_MASK, XRTARARB_MASK,
  52         XRTBFRARB_MASK, XOPL, XOPL2, XRCL, XRT, XRTRA, XCMP_MASK, XCMPL_MASK,
  53         XTO, XTLB, XSYNC, XEH_MASK, XDSS, XFL, XISEL, XL, XLO, XLYLK, XLOCB,
  54         XMBAR, XO, XOPS, XS, XFXM, XSPR, XUC, XW, APU): Update types in casts.
  55
  56 2017-11-29  Jan Beulich  <jbeulich@suse.com>
  57
  58         * i386-gen.c (active_cpu_flags, active_isstring, enum stage):
  59         New.
  60         (output_cpu_flags): Update active_cpu_flags.
  61         (process_i386_opcode_modifier): Update active_isstring.
  62         (output_operand_type): Rename "macro"   parameter to "stage",
  63         changing its type.
  64         (process_i386_operand_type): Likewise. Track presence of
  65         BaseIndex and emit DispN accordingly.
  66         (output_i386_opcode, process_i386_registers,
  67         process_i386_initializers): Adjust calls to
  68         process_i386_operand_type() for its changed parameter type.
  69         * i386-opc.tbl: Drop Disp8, Disp16, Disp32, and Disp32S from
  70         all insns operands having BaseIndex set.
  71         * i386-tbl.h: Re-generate.
  72
  73 2017-11-29  Jan Beulich  <jbeulich@suse.com>
  74
  75         * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_VEC_DISP8
  76         entry.
  77         (operand_types): Remove Vec_Disp8 entry.
  78         * i386-opc.h (Vec_Disp8): Delete.
  79         (union i386_operand_type): Remove vec_disp8.
  80         (i386-opc.tbl): Remove Vec_Disp8.
  81         * i386-init.h, i386-tbl.h: Re-generate.
  82
  83 2017-11-29  Stefan Stroe  <stroestefan@gmail.com>
  84
  85         * po/Make-in (datadir): Define as @datadir@.
  86         (localedir): Define as @localedir@.
  87         (gnulocaledir, gettextsrcdir): Use @datarootdir@.
  88
  89 2017-11-27  Nick Clifton  <nickc@redhat.com>
  90
  91         * po/zh_CN.po: Updated simplified Chinese translation.
  92
  93 2017-11-24  Jan Beulich  <jbeulich@suse.com>
  94
  95         * i386-dis.c (float_mem): Add suffixes to fi* in the "de" and
  96         "df" groups.
  97
  98 2017-11-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
  99
 100         * i386-opc.tbl: Add Disp8MemShift for AVX512 VAES instructions.
 101         * i386-tbl.h: Regenerate.
 102
 103 2017-11-23  Jan Beulich  <jbeulich@suse.com>
 104
 105         * i386-dis.c (OP_E_memory): Also shift the 8-bit immediate in
 106         the 16-bit addressing case.
 107
 108 2017-11-23  Jan Beulich  <jbeulich@suse.com>
 109
 110         * i386-dis.c (dis386_twobyte): Correct ud1. Add ud0.
 111         (twobyte_has_modrm): Set flag for index 0xb9 and 0xff.
 112         * i386-opc.tbl (ud1, ud2b): Add operands.
 113         (ud0): New.
 114         * i386-tbl.h: Re-generate.
 115
 116 2017-11-22  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 117
 118         * i386-opc.tbl: Remove Vec_Disp8 from vgf2p8mulb.
 119         * i386-tbl.h: Regenerate.
 120
 121 2017-11-22  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 122
 123         * i386-opc.tbl: Remove Vec_Disp8 from vpcompressb and vpexpandb.
 124         * i386-tbl.h: Regenerate.
 125
 126 2017-11-22  Claudiu Zissulescu  <claziss@synopsys.com>
 127
 128         *arc-opc (insert_rhv2): Check h-regs range.
 129
 130 2017-11-21  Claudiu Zissulescu <claziss@synopsys.com>
 131
 132         * arc-dis.c (print_insn_arc): Pretty print pc-relative offsets.
 133         * arc-opc.c (SIMM21_A16_5): Make it pc-relative.
 134
 135 2017-11-16  Tamar Christina  <tamar.christina@arm.com>
 136
 137         * aarch64-tbl.h (aarch64_feature_fp_16_v8_2): Require AARCH64_FEATURE_F16_FML
 138         and AARCH64_FEATURE_F16.
 139
 140 2017-11-16  Tamar Christina  <tamar.christina@arm.com>
 141
 142         * aarch64-tbl.h (sha512h, sha512h2, sha512su0, sha512su1, eor3): New.
 143         (rax1, xar, bcax, sm3ss1, sm3tt1a, sm3tt1b, sm3tt2a, sm3tt2b): New.
 144         (sm3partw1, sm3partw2, sm4e, sm4ekey, fmlal, fmlsl): New.
 145         (fmlal2, fmlsl2, cfinv, rmif, setf8, setf16, stlurb): New.
 146         (ldapurb, ldapursb, stlurh, ldapurh, ldapursh, stlur): New.
 147         (ldapur, ldapursw, stlur): New.
 148         * aarch64-dis-2.c: Regenerate.
 149
 150 2017-11-16  Jan Beulich  <jbeulich@suse.com>
 151
 152         (get_valid_dis386): Never flag bad opcode when
 153         vex.register_specifier is beyond 7. Always store all four
 154         bits of it. Move 16-/32-bit override in EVEX handling after
 155         all to be overridden bits have been set.
 156         (OP_VEX): Mask vex.register_specifier outside of 64-bit mode.
 157         Use rex to determine GPR register set.
 158         (OP_EX_VexReg, OP_Vex_2src_1, OP_Vex_2src_2, OP_REG_VexI4,
 159         OP_LWP_E): Mask vex.register_specifier outside of 64-bit mode.
 160
 161 2017-11-15  Jan Beulich  <jbeulich@suse.com>
 162
 163         * i386-dis.c (OP_VEX, OP_LWPCB_E, OP_LWP_E): Use rex to
 164         determine GPR register set.
 165
 166 2017-11-15  Jan Beulich  <jbeulich@suse.com>
 167
 168         * i386-dis.c (VEXI4_Fixup, VexI4): Delete.
 169         (prefix_table, xop_table, vex_len_table): Remove VexI4 uses.
 170         (OP_EX_VexW): Move setting of vex_w_done. Update codep on 2nd
 171         pass.
 172         (OP_REG_VexI4): Drop low 4 bits check.
 173
 174 2017-11-15  Jan Beulich  <jbeulich@suse.com>
 175
 176         * i386-reg.tbl (axl): Remove Acc and Byte.
 177         * i386-tbl.h: Re-generate.
 178
 179 2017-11-14  Jan Beulich  <jbeulich@suse.com>
 180
 181         * i386-dis.c (VPCOM_Fixup, VPCOM, xop_cmp_op): New.
 182         (vex_len_table): Use VPCOM.
 183
 184 2017-11-14  Jan Beulich  <jbeulich@suse.com>
 185
 186         * i386-dis-evex.h (evex_table[EVEX_W_0F3A3E_P_2]): Use VPCMP.
 187         (evex_table[EVEX_W_0F3A3F_P_2]): Likewise.
 188         * i386-opc.tbl (vpcmpeqb, vpcmpgtb, vpcmpeqw, vpcmpgtw, vpcmpuw,
 189         vpcmpw): Move up.
 190         (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb, vpcmpnleb, vpcmpnltb,
 191         vpcmpequb, vpcmpleub, vpcmpltub, vpcmpnequb, vpcmpnleub,
 192         vpcmpnltub, vpcmpeqw, vpcmplew, vpcmpltw, vpcmpneqw, vpcmpnlew,
 193         vpcmpnltw, vpcmpequw, vpcmpleuw, vpcmpltuw, vpcmpnequw, vpcmpnleuw,
 194         vpcmpnltuw): New.
 195         * i386-tbl.h: Re-generate.
 196
 197 2017-11-14  Jan Beulich  <jbeulich@suse.com>
 198
 199         * i386-opc.tbl (cmps, ins, lods, movs, outs, scas, scmp, slod,
 200         smov, ssca, stos, ssto, xlat): Drop Disp*.
 201         * i386-tbl.h: Re-generate.
 202
 203 2017-11-13  Jan Beulich  <jbeulich@suse.com>
 204
 205         * i386-opc.tbl (fxsave64, fxrstor64, xsave64, xrstor64,
 206         xsaveopt64): Add No_qSuf.
 207         * i386-tbl.h: Re-generate.
 208
 209 2017-11-09  Tamar Christina  <tamar.christina@arm.com>
 210
 211         * aarch64-opc.c (aarch64_sys_regs): Add ARMv8.4-a registers;
 212         dit, vstcr_el2, vsttbr_el2, cnthvs_tval_el2, cnthvs_cval_el2,
 213         cnthvs_ctl_el2, cnthps_tval_el2, cnthps_cval_el2, cnthps_ctl_el2,
 214         sder32_el2, vncr_el2.
 215         (aarch64_sys_reg_supported_p): Likewise.
 216         (aarch64_pstatefields): Add dit register.
 217         (aarch64_pstatefield_supported_p): Likewise.
 218         (aarch64_sys_regs_tlbi): Add vmalle1os, vae1os, aside1os, vaae1os,
 219         vale1os, vaale1os, ipas2e1os, ipas2le1os, vae2os, vale2os, vmalls12e1os,
 220         vae3os, vale3os, alle2os, alle1os, alle3os, rvae1, rvaae1, rvale1,
 221         rvaale1, rvae1is, rvaae1is, rvale1is, rvaale1is, rvae1os, rvaae1os,
 222         rvale1os, rvaale1os, ripas2e1is, ripas2le1is, ripas2e1, ripas2le1,
 223         ripas2e1os, ripas2le1os, rvae2, rvale2, rvae2is, rvale2is, rvae2os,
 224         rvale2os, rvae3, rvale3, rvae3is, rvale3is, rvae3os, rvale3os.
 225
 226 2017-11-09  Tamar Christina  <tamar.christina@arm.com>
 227
 228         * aarch64-tbl.h (QL_SHA512UPT, QL_V2SAME2D, QL_V3SAME2D): New.
 229         (QL_V4SAME16B, QL_V4SAME4S, QL_XAR, QL_SM3TT, QL_V3FML2S): New.
 230         (QL_V3FML4S, QL_V2FML2S, QL_V2FML4S, QL_RMIF, QL_SETF): New.
 231         (QL_STLW, QL_STLX): New.
 232
 233 2017-11-09  Tamar Christina  <tamar.christina@arm.com>
 234
 235         * aarch64-asm.h (ins_addr_offset): New.
 236         * aarch64-asm.c (aarch64_ins_reglane): Add cryptosm3.
 237         (aarch64_ins_addr_offset): New.
 238         * aarch64-asm-2.c: Regenerate.
 239         * aarch64-dis.h (ext_addr_offset): New.
 240         * aarch64-dis.c (aarch64_ext_reglane): Add cryptosm3.
 241         (aarch64_ext_addr_offset): New.
 242         * aarch64-dis-2.c: Regenerate.
 243         * aarch64-opc.h (aarch64_field_kind): Add FLD_imm6_2,
 244         FLD_imm4_2 and FLD_SM3_imm2.
 245         * aarch64-opc.c (fields): Add FLD_imm6_2,
 246         FLD_imm4_2 and FLD_SM3_imm2.
 247         (operand_general_constraint_met_p): Add AARCH64_OPND_ADDR_OFFSET.
 248         (aarch64_print_operand): Add AARCH64_OPND_Va, AARCH64_OPND_SM3_IMM2,
 249         AARCH64_OPND_MASK, AARCH64_OPND_IMM_2 and AARCH64_OPND_ADDR_OFFSET.
 250         * aarch64-opc-2.c (Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2): New.
 251         * aarch64-tbl.h
 252         (aarch64_opcode_table): Add Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2.
 253
 254 2017-11-09 Tamar Christina  <tamar.christina@arm.com>
 255
 256         * aarch64-tbl.h
 257         (aarch64_feature_v8_4, aarch64_feature_crypto_v8_2): New.
 258         (aarch64_feature_sm4, aarch64_feature_sha3): New.
 259         (aarch64_feature_fp_16_v8_2): New.
 260         (ARMV8_4, SHA3, SM4, CRYPTO_V8_2, FP_F16_V8_2): New.
 261         (V8_4_INSN, CRYPTO_V8_2_INSN): New.
 262         (SHA3_INSN, SM4_INSN, FP16_V8_2_INSN): New.
 263
 264 2017-11-08  Tamar Christina  <tamar.christina@arm.com>
 265
 266         * aarch64-tbl.h (aarch64_feature_crypto): Add AES and SHA2.
 267         (aarch64_feature_sha2, aarch64_feature_aes): New.
 268         (SHA2, AES): New.
 269         (AES_INSN, SHA2_INSN): New.
 270         (pmull, pmull2, aese, aesd, aesmc, aesimc): Change to AES_INS.
 271         (sha1h, sha1su1, sha256su0, sha1c, sha1p,
 272          sha1m, sha1su0, sha256h, sha256h2, sha256su1):
 273         Change to SHA2_INS.
 274
 275 2017-11-08  Jiong Wang  <jiong.wang@arm.com>
 276             Tamar Christina <tamar.christina@arm.com>
 277
 278         * arm-dis.c (coprocessor_opcodes): New entries for ARMv8.2-A new
 279         FP16 instructions, including vfmal.f16 and vfmsl.f16.
 280
 281 2017-11-07  Andrew Burgess  <andrew.burgess@embecosm.com>
 282
 283         * arc-nps400-tbl.h: Change incorrect use of NONE to MISC.
 284
 285 2017-11-07  Alan Modra  <amodra@gmail.com>
 286
 287         * opintl.h: Formatting, comment fixes.
 288         (gettext, ngettext): Redefine when ENABLE_NLS.
 289         (ngettext, dngettext, dcngettext): Define when !ENABLE_NLS.
 290         (_): Define using gettext.
 291         (textdomain, bindtextdomain): Use safer "do nothing".
 292
 293 2017-11-03  Claudiu Zissulescu  <claziss@synopsys.com>
 294
 295         * arc-dis.c (print_hex): New variable.
 296         (parse_option): Check for hex option.
 297         (print_insn_arc): Use hexadecimal representation for short
 298         immediate values when requested.
 299         (print_arc_disassembler_options): Add hex option to the list.
 300
 301 2017-11-03  Claudiu Zissulescu  <claziss@synopsys.com>
 302
 303         * arc-tbl.h (abss, abssh, adc, adcs, adds, aslacc, asls, aslsacc)
 304         (asrs, asrsr, cbflyhf0r, cbflyhf1r, cmacchfr, cmacchnfr, cmachfr)
 305         (cmachnfr, cmpychfr, cmpychnfr, cmpyhfmr, cmpyhfr, cmpyhnfr, divf)
 306         (dmachbl, dmachbm, dmachf, dmachfr, dmacwhf, dmpyhbl, dmpyhbm)
 307         (dmpyhf, dmpyhfr, dmpyhwf, dmpywhf, dsync, flagacc, getacc, macdf)
 308         (macf, macfr, macwhfl, macwhflr, macwhfm, macwhfmr, macwhkl)
 309         (macwhkul, macwhl, macwhul, mpydf, mpyf, mpyfr, mpywhfl, mpywhflr)
 310         (mpywhfm, mpywhfmr, mpywhkl, mpywhkul, mpywhl, mpywhul, msubdf)
 311         (msubf, msubfr, msubwhfl, msubwhflr, msubwhfm, msubwhfmr, mul64)
 312         (negs, negsh, normacc, qmachf, qmpyh, qmpyhf, rndh, satf, sath)
 313         (sbcs, setacc, sflag, sqrt, sqrtf, subs, swi_s, vabs2h, vabss2h)
 314         (vadd4b, vadds2, vadds2h, vadds4h, vaddsubs, vaddsubs2h)
 315         (vaddsubs4h, valgn2h, vasl2h, vasls2h, vasr2h, vasrs2h, vasrsr2h)
 316         (vext2bhl, vext2bhlf, vext2bhm, vext2bhmf, vlsr2h, vmac2hf)
 317         (vmac2hfr, vmac2hnfr, vmax2h, vmin2h, vmpy2h, vmpy2hf, vmpy2hfr)
 318         (vmpy2hwf, vmsub2hf, vmsub2hfr, vmsub2hnfr, vneg2h, vnegs2h)
 319         (vnorm2h, vpack2hbl, vpack2hblf, vpack2hbm, vpack2hbmf, vpack2hl)
 320         (vpack2hm, vperm, vrep2hl, vrep2hm, vsext2bhl, vsext2bhm, vsub4b)
 321         (vsubadds, vsubadds2h, vsubadds4h, vsubs2, vsubs2h, vsubs4h):
 322         Changed opcodes.
 323         (prealloc, prefetch*): Place them before ld instruction.
 324         * arc-opc.c (skip_this_opcode): Add ARITH class.
 325
 326 2017-10-25  Alan Modra  <amodra@gmail.com>
 327
 328         PR 22348
 329         * cr16-dis.c (cr16_cinvs, instruction, cr16_currInsn): Make static.
 330         (cr16_words, cr16_allWords, processing_argument_number): Likewise.
 331         (imm4flag, size_changed): Likewise.
 332         * crx-dis.c (crx_cinvs, NUMCINVS, instruction, currInsn): Likewise.
 333         (words, allWords, processing_argument_number): Likewise.
 334         (cst4flag, size_changed): Likewise.
 335         * crx-opc.c (crx_cst4_map): Rename from cst4_map.
 336         (crx_cst4_maps): Rename from cst4_maps.
 337         (crx_no_op_insn): Rename from no_op_insn.
 338
 339 2017-10-24  Andrew Waterman  <andrew@sifive.com>
 340
 341         * riscv-opc.c (match_c_addi16sp) : New function.
 342         (match_c_addi4spn): New function.
 343         (match_c_lui): Don't allow 0-immediate encodings.
 344         (riscv_opcodes) <addi>: Use the above functions.
 345         <add>: Likewise.
 346         <c.addi4spn>: Likewise.
 347         <c.addi16sp>: Likewise.
 348
 349 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 350
 351         * i386-init.h: Regenerate
 352         * i386-tbl.h: Likewise
 353
 354 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 355
 356         * i386-dis.c (enum): Add PREFIX_EVEX_0F3854, PREFIX_EVEX_0F388F.
 357         (enum): Add EVEX_W_0F3854_P_2.
 358         * i386-dis-evex.h (evex_table): Updated.
 359         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BITALG,
 360         CPU_ANY_AVX512_BITALG_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 361         (cpu_flags): Add CpuAVX512_BITALG.
 362         * i386-opc.h (enum): Add CpuAVX512_BITALG.
 363         (i386_cpu_flags): Add cpuavx512_bitalg..
 364         * i386-opc.tbl: Add Intel AVX512_BITALG instructions.
 365         * i386-init.h: Regenerate.
 366         * i386-tbl.h: Likewise.
 367
 368 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 369
 370         * i386-dis.c (enum): Add PREFIX_EVEX_0F3850, PREFIX_EVEX_0F3851.
 371         * i386-dis-evex.h (evex_table): Updated.
 372         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VNNI,
 373         CPU_ANY_AVX512_VNNI_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 374         (cpu_flags): Add CpuAVX512_VNNI.
 375         * i386-opc.h (enum): Add CpuAVX512_VNNI.
 376         (i386_cpu_flags): Add cpuavx512_vnni.
 377         * i386-opc.tbl Add Intel AVX512_VNNI instructions.
 378         * i386-init.h: Regenerate.
 379         * i386-tbl.h: Likewise.
 380
 381 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 382
 383         * i386-dis.c (enum): Add PREFIX_EVEX_0F3A44.
 384         (enum): Remove VEX_LEN_0F3A44_P_2.
 385         (vex_len_table): Ditto.
 386         (enum): Remove VEX_W_0F3A44_P_2.
 387         (vew_w_table): Ditto.
 388         (prefix_table): Adjust instructions (see prefixes above).
 389         * i386-dis-evex.h (evex_table):
 390         Add new instructions (see prefixes above).
 391         * i386-gen.c (cpu_flag_init): Add VPCLMULQDQ.
 392         (bitfield_cpu_flags): Ditto.
 393         * i386-opc.h (enum): Ditto.
 394         (i386_cpu_flags): Ditto.
 395         (CpuUnused): Comment out to avoid zero-width field problem.
 396         * i386-opc.tbl (vpclmulqdq): New instruction.
 397         * i386-init.h: Regenerate.
 398         * i386-tbl.h: Ditto.
 399
 400 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 401
 402         * i386-dis.c (enum): Add PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD,
 403         PREFIX_EVEX_0F38DE, PREFIX_EVEX_0F38DF.
 404         (enum): Remove VEX_LEN_0F38DC_P_2, VEX_LEN_0F38DD_P_2,
 405         VEX_LEN_0F38DE_P_2, VEX_LEN_0F38DF_P_2.
 406         (vex_len_table): Ditto.
 407         (enum): Remove VEX_W_0F38DC_P_2, VEX_W_0F38DD_P_2,
 408         VEX_W_0F38DE_P_2, VEX_W_0F38DF_P_2.
 409         (vew_w_table): Ditto.
 410         (prefix_table): Adjust instructions (see prefixes above).
 411         * i386-dis-evex.h (evex_table):
 412         Add new instructions (see prefixes above).
 413         * i386-gen.c (cpu_flag_init): Add VAES.
 414         (bitfield_cpu_flags): Ditto.
 415         * i386-opc.h (enum): Ditto.
 416         (i386_cpu_flags): Ditto.
 417         * i386-opc.tbl (vaes{enc,dec}{last,}): New instructions.
 418         * i386-init.h: Regenerate.
 419         * i386-tbl.h: Ditto.
 420
 421 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 422
 423         * i386-dis.c (enum): Add PREFIX_0F38CF, PREFIX_0F3ACE, PREFIX_0F3ACF,
 424         PREFIX_VEX_0F38CF, PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF,
 425         PREFIX_EVEX_0F38CF, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF.
 426         (enum): Add VEX_W_0F38CF_P_2, VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2,
 427         EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2.
 428         (prefix_table): Updated (see prefixes above).
 429         (three_byte_table): Likewise.
 430         (vex_w_table): Likewise.
 431         * i386-dis-evex.h: Likewise.
 432         * i386-gen.c (cpu_flag_init): Add CPU_GFNI_FLAGS, CpuGFNI.
 433         (cpu_flags): Add CpuGFNI.
 434         * i386-opc.h (enum): Add CpuGFNI.
 435         (i386_cpu_flags): Add cpugfni.
 436         * i386-opc.tbl: Add Intel GFNI instructions.
 437         * i386-init.h: Regenerate.
 438         * i386-tbl.h: Likewise.
 439
 440 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 441
 442         * i386-dis.c (enum): Add b_scalar_mode, w_scalar_mode.
 443         Define EXbScalar and EXwScalar for OP_EX.
 444         (enum): Add PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863,
 445         PREFIX_EVEX_0F3870, PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3872,
 446         PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
 447         PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73.
 448         (enum): Add EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2,
 449         EVEX_W_0F3870_P_2, EVEX_W_0F3871_P_2, EVEX_W_0F3872_P_2,
 450         EVEX_W_0F3873_P_2, EVEX_W_0F3A70_P_2, EVEX_W_0F3A71_P_2,
 451         EVEX_W_0F3A72_P_2, EVEX_W_0F3A73_P_2.
 452         (intel_operand_size): Handle b_scalar_mode and w_scalar_mode.
 453         (OP_E_memory): Likewise.
 454         * i386-dis-evex.h: Updated.
 455         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VBMI2,
 456         CPU_ANY_AVX512_VBMI2_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 457         (cpu_flags): Add CpuAVX512_VBMI2.
 458         * i386-opc.h (enum): Add CpuAVX512_VBMI2.
 459         (i386_cpu_flags): Add cpuavx512_vbmi2.
 460         * i386-opc.tbl: Add Intel AVX512_VBMI2 instructions.
 461         * i386-init.h: Regenerate.
 462         * i386-tbl.h: Likewise.
 463
 464 2017-10-18  Eric Botcazou  <ebotcazou@adacore.com>
 465
 466         * visium-dis.c (disassem_class1) <case 0>: Print the operands.
 467
 468 2017-10-12  James Bowman  <james.bowman@ftdichip.com>
 469
 470         * ft32-dis.c (print_insn_ft32): Replace FT32_FLD_K8 with K15.
 471         * ft32-opc.c (ft32_opc_info): Replace FT32_FLD_K8 with
 472         K15. Add jmpix pattern.
 473
 474 2017-10-09  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 475
 476         * s390-opc.txt (prno, tpei, irbm): New instructions added.
 477
 478 2017-10-09  Heiko Carstens  <heiko.carstens@de.ibm.com>
 479
 480         * s390-opc.c (INSTR_SI_RD): New macro.
 481         (INSTR_S_RD): Adjust example instruction.
 482         * s390-opc.txt (lpsw, ssm, ts): Change S_RD instruction format to
 483         SI_RD.
 484
 485 2017-10-01  Alexander Fedotov  <alfedotov@gmail.com>
 486
 487         * ppc-opc.c (vle_opcodes): Add e_lmvsprw, e_lmvgprw,
 488         e_lmvsrrw, e_lmvcsrrw and e_lmvcsrrw as official mnemonics for
 489         VLE multimple load/store instructions. Old e_ldm* variants are
 490         kept as aliases.
 491         Add missing e_lmvmcsrrw and e_stmvmcsrrw.
 492
 493 2017-09-27  Nick Clifton  <nickc@redhat.com>
 494
 495         PR 22179
 496         * riscv-opc.c (riscv_opcodes): Add fmv.x.w and fmv.w.x as the new
 497         names for the fmv.x.s and fmv.s.x instructions respectively.
 498
 499 2017-09-26  do  <do@nerilex.org>
 500
 501         PR 22123
 502         * m68k-opc.c (m68k_opcodes): Allow macw and macl instructions to
 503         be used on CPUs that have emacs support.
 504
 505 2017-09-21  Sergio Durigan Junior  <sergiodj@redhat.com>
 506
 507         * aarch64-opc.c (expand_fp_imm): Initialize 'imm'.
 508
 509 2017-09-09  Kamil Rytarowski  <n54@gmx.com>
 510
 511         * nds32-asm.c: Rename __BIT() to N32_BIT().
 512         * nds32-asm.h: Likewise.
 513         * nds32-dis.c: Likewise.
 514
 515 2017-09-09  H.J. Lu  <hongjiu.lu@intel.com>
 516
 517         * i386-dis.c (last_active_prefix): Removed.
 518         (ckprefix): Don't set last_active_prefix.
 519         (NOTRACK_Fixup): Don't check last_active_prefix.
 520
 521 2017-08-31  Nick Clifton  <nickc@redhat.com>
 522
 523         * po/fr.po: Updated French translation.
 524
 525 2017-08-31  James Bowman  <james.bowman@ftdichip.com>
 526
 527         * ft32-dis.c (print_insn_ft32): Correct display of non-address
 528         fields.
 529
 530 2017-08-23  Alexander Fedotov <alexander.fedotov@nxp.com>
 531             Edmar Wienskoski <edmar.wienskoski@nxp.com>
 532
 533         * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_SPE2 and
 534         PPC_OPCODE_EFS2 flag to "e200z4" entry.
 535         New entries efs2 and spe2.
 536         Add PPC_OPCODE_SPE2 and PPC_OPCODE_EFS2 flag to "vle" entry.
 537         (SPE2_OPCD_SEGS): New macro.
 538         (spe2_opcd_indices): New.
 539         (disassemble_init_powerpc): Handle SPE2 opcodes.
 540         (lookup_spe2): New function.
 541         (print_insn_powerpc): call lookup_spe2.
 542         * ppc-opc.c (insert_evuimm1_ex0): New function.
 543         (extract_evuimm1_ex0): Likewise.
 544         (insert_evuimm_lt8): Likewise.
 545         (extract_evuimm_lt8): Likewise.
 546         (insert_off_spe2): Likewise.
 547         (extract_off_spe2): Likewise.
 548         (insert_Ddd): Likewise.
 549         (extract_Ddd): Likewise.
 550         (DD): New operand.
 551         (EVUIMM_LT8): Likewise.
 552         (EVUIMM_LT16): Adjust.
 553         (MMMM): New operand.
 554         (EVUIMM_1): Likewise.
 555         (EVUIMM_1_EX0): Likewise.
 556         (EVUIMM_2): Adjust.
 557         (NNN): New operand.
 558         (VX_OFF_SPE2): Likewise.
 559         (BBB): Likewise.
 560         (DDD): Likewise.
 561         (VX_MASK_DDD): New mask.
 562         (HH): New operand.
 563         (VX_RA_CONST): New macro.
 564         (VX_RA_CONST_MASK): Likewise.
 565         (VX_RB_CONST): Likewise.
 566         (VX_RB_CONST_MASK): Likewise.
 567         (VX_OFF_SPE2_MASK): Likewise.
 568         (VX_SPE_CRFD): Likewise.
 569         (VX_SPE_CRFD_MASK VX): Likewise.
 570         (VX_SPE2_CLR): Likewise.
 571         (VX_SPE2_CLR_MASK): Likewise.
 572         (VX_SPE2_SPLATB): Likewise.
 573         (VX_SPE2_SPLATB_MASK): Likewise.
 574         (VX_SPE2_OCTET): Likewise.
 575         (VX_SPE2_OCTET_MASK): Likewise.
 576         (VX_SPE2_DDHH): Likewise.
 577         (VX_SPE2_DDHH_MASK): Likewise.
 578         (VX_SPE2_HH): Likewise.
 579         (VX_SPE2_HH_MASK): Likewise.
 580         (VX_SPE2_EVMAR): Likewise.
 581         (VX_SPE2_EVMAR_MASK): Likewise.
 582         (PPCSPE2): Likewise.
 583         (PPCEFS2): Likewise.
 584         (vle_opcodes): Add EFS2 and some missing SPE opcodes.
 585         (powerpc_macros): Map old SPE instructions have new names
 586         with the same opcodes. Add SPE2 instructions which just are
 587         mapped to SPE2.
 588         (spe2_opcodes): Add SPE2 opcodes.
 589
 590 2017-08-23  Alan Modra  <amodra@gmail.com>
 591
 592         * ppc-opc.c: Formatting and comment fixes.  Move insert and
 593         extract functions earlier, deleting forward declarations.
 594         (insert_nbi, insert_raq, insert_rbx): Expand use of RT_MASK and
 595         RA_MASK.
 596
 597 2017-08-22  Palmer Dabbelt  <palmer@dabbelt.com>
 598
 599         * riscv-opc.c (riscv_opcodes): Mark "c.nop" as an alias.
 600
 601 2017-08-21  Alexander Fedotov <alexander.fedotov@nxp.com>
 602             Edmar Wienskoski <edmar.wienskoski@nxp.com>
 603
 604         * ppc-opc.c (insert_evuimm2_ex0): New function.
 605         (extract_evuimm2_ex0): Likewise.
 606         (insert_evuimm4_ex0): Likewise.
 607         (extract_evuimm4_ex0): Likewise.
 608         (insert_evuimm8_ex0): Likewise.
 609         (extract_evuimm8_ex0): Likewise.
 610         (insert_evuimm_lt16): Likewise.
 611         (extract_evuimm_lt16): Likewise.
 612         (insert_rD_rS_even): Likewise.
 613         (extract_rD_rS_even): Likewise.
 614         (insert_off_lsp): Likewise.
 615         (extract_off_lsp): Likewise.
 616         (RD_EVEN): New operand.
 617         (RS_EVEN): Likewise.
 618         (RSQ): Adjust.
 619         (EVUIMM_LT16): New operand.
 620         (HTM_SI): Adjust.
 621         (EVUIMM_2_EX0): New operand.
 622         (EVUIMM_4): Adjust.
 623         (EVUIMM_4_EX0): New operand.
 624         (EVUIMM_8): Adjust.
 625         (EVUIMM_8_EX0): New operand.
 626         (WS): Adjust.
 627         (VX_OFF): New operand.
 628         (VX_LSP): New macro.
 629         (VX_LSP_MASK): Likewise.
 630         (VX_LSP_OFF_MASK): Likewise.
 631         (PPC_OPCODE_LSP): Likewise.
 632         (vle_opcodes): Add LSP opcodes.
 633         * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_LSP flag to "vle" entry.
 634
 635 2017-08-09  Jiong Wang  <jiong.wang@arm.com>
 636
 637         * arm-dis.c (thumb32_opcodes): Use format 'R' instead of 'S' for
 638         register operands in CRC instructions.
 639         (print_insn_thumb32): Remove "<bitfield>S" support.  Updated the
 640         comments.
 641
 642 2017-08-07  H.J. Lu  <hongjiu.lu@intel.com>
 643
 644         * disassemble.c (disassembler): Mark big and mach with
 645         ATTRIBUTE_UNUSED.
 646
 647 2017-08-07  Maciej W. Rozycki  <macro@imgtec.com>
 648
 649         * disassemble.c (disassembler): Remove arch/mach/endian
 650         assertions.
 651
 652 2017-07-25  Nick Clifton  <nickc@redhat.com>
 653
 654         PR 21739
 655         * arc-opc.c (insert_rhv2): Use lower case first letter in error
 656         message.
 657         (insert_r0): Likewise.
 658         (insert_r1): Likewise.
 659         (insert_r2): Likewise.
 660         (insert_r3): Likewise.
 661         (insert_sp): Likewise.
 662         (insert_gp): Likewise.
 663         (insert_pcl): Likewise.
 664         (insert_blink): Likewise.
 665         (insert_ilink1): Likewise.
 666         (insert_ilink2): Likewise.
 667         (insert_ras): Likewise.
 668         (insert_rbs): Likewise.
 669         (insert_rcs): Likewise.
 670         (insert_simm3s): Likewise.
 671         (insert_rrange): Likewise.
 672         (insert_r13el): Likewise.
 673         (insert_fpel): Likewise.
 674         (insert_blinkel): Likewise.
 675         (insert_pclel): Likewise.
 676         (insert_nps_bitop_size_2b): Likewise.
 677         (insert_nps_imm_offset): Likewise.
 678         (insert_nps_imm_entry): Likewise.
 679         (insert_nps_size_16bit): Likewise.
 680         (insert_nps_##NAME##_pos): Likewise.
 681         (insert_nps_##NAME): Likewise.
 682         (insert_nps_bitop_ins_ext): Likewise.
 683         (insert_nps_##NAME): Likewise.
 684         (insert_nps_min_hofs): Likewise.
 685         (insert_nps_##NAME): Likewise.
 686         (insert_nps_rbdouble_64): Likewise.
 687         (insert_nps_misc_imm_offset): Likewise.
 688         * riscv-dis.c (print_riscv_disassembler_options): Fix typo in
 689         option description.
 690
 691 2017-07-24  Laurent Desnogues  <laurent.desnogues@arm.com>
 692             Jiong Wang  <jiong.wang@arm.com>
 693
 694         * aarch64-gen.c (print_decision_tree_1): Reverse the index of PATTERN to
 695         correct the print.
 696         * aarch64-dis-2.c: Regenerated.
 697
 698 2017-07-21  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 699
 700         * s390-mkopc.c (main): Enable z14 as CPU string in the opcode
 701         table.
 702
 703 2017-07-20  Nick Clifton  <nickc@redhat.com>
 704
 705         * po/de.po: Updated German translation.
 706
 707 2017-07-19  Claudiu Zissulescu  <claziss@synopsys.com>
 708
 709         * arc-regs.h (sec_stat): New aux register.
 710         (aux_kernel_sp): Likewise.
 711         (aux_sec_u_sp): Likewise.
 712         (aux_sec_k_sp): Likewise.
 713         (sec_vecbase_build): Likewise.
 714         (nsc_table_top): Likewise.
 715         (nsc_table_base): Likewise.
 716         (ersec_stat): Likewise.
 717         (aux_sec_except): Likewise.
 718
 719 2017-07-19  Claudiu Zissulescu  <claziss@synopsys.com>
 720
 721         * arc-opc.c (extract_uimm12_20): New function.
 722         (UIMM12_20): New operand.
 723         (SIMM3_5_S): Adjust.
 724         * arc-tbl.h (sjli): Add new instruction.
 725
 726 2017-07-19  Claudiu Zissulescu  <claziss@synopsys.com>
 727             John Eric Martin  <John.Martin@emmicro-us.com>
 728
 729         * arc-opc.c (UIMM10_6_S_JLIOFF): Define.
 730         (UIMM3_23): Adjust accordingly.
 731         * arc-regs.h: Add/correct jli_base register.
 732         * arc-tbl.h (jli_s): Likewise.
 733
 734 2017-07-18  Nick Clifton  <nickc@redhat.com>
 735
 736         PR 21775
 737         * aarch64-opc.c: Fix spelling typos.
 738         * i386-dis.c: Likewise.
 739
 740 2017-07-14  Ravi Bangoria  <ravi.bangoria@linux.vnet.ibm.com>
 741
 742         * dis-buf.c (buffer_read_memory): Change type of end_addr_offset,
 743         max_addr_offset and octets variables to size_t.
 744
 745 2017-07-12  Alan Modra  <amodra@gmail.com>
 746
 747         * po/da.po: Update from translationproject.org/latest/opcodes/.
 748         * po/de.po: Likewise.
 749         * po/es.po: Likewise.
 750         * po/fi.po: Likewise.
 751         * po/fr.po: Likewise.
 752         * po/id.po: Likewise.
 753         * po/it.po: Likewise.
 754         * po/nl.po: Likewise.
 755         * po/pt_BR.po: Likewise.
 756         * po/ro.po: Likewise.
 757         * po/sv.po: Likewise.
 758         * po/tr.po: Likewise.
 759         * po/uk.po: Likewise.
 760         * po/vi.po: Likewise.
 761         * po/zh_CN.po: Likewise.
 762
 763 2017-07-11  Yao Qi  <yao.qi@linaro.org>
 764             Alan Modra  <amodra@gmail.com>
 765
 766         * cgen.sh: Mark generated files read-only.
 767         * epiphany-asm.c: Regenerate.
 768         * epiphany-desc.c: Regenerate.
 769         * epiphany-desc.h: Regenerate.
 770         * epiphany-dis.c: Regenerate.
 771         * epiphany-ibld.c: Regenerate.
 772         * epiphany-opc.c: Regenerate.
 773         * epiphany-opc.h: Regenerate.
 774         * fr30-asm.c: Regenerate.
 775         * fr30-desc.c: Regenerate.
 776         * fr30-desc.h: Regenerate.
 777         * fr30-dis.c: Regenerate.
 778         * fr30-ibld.c: Regenerate.
 779         * fr30-opc.c: Regenerate.
 780         * fr30-opc.h: Regenerate.
 781         * frv-asm.c: Regenerate.
 782         * frv-desc.c: Regenerate.
 783         * frv-desc.h: Regenerate.
 784         * frv-dis.c: Regenerate.
 785         * frv-ibld.c: Regenerate.
 786         * frv-opc.c: Regenerate.
 787         * frv-opc.h: Regenerate.
 788         * ip2k-asm.c: Regenerate.
 789         * ip2k-desc.c: Regenerate.
 790         * ip2k-desc.h: Regenerate.
 791         * ip2k-dis.c: Regenerate.
 792         * ip2k-ibld.c: Regenerate.
 793         * ip2k-opc.c: Regenerate.
 794         * ip2k-opc.h: Regenerate.
 795         * iq2000-asm.c: Regenerate.
 796         * iq2000-desc.c: Regenerate.
 797         * iq2000-desc.h: Regenerate.
 798         * iq2000-dis.c: Regenerate.
 799         * iq2000-ibld.c: Regenerate.
 800         * iq2000-opc.c: Regenerate.
 801         * iq2000-opc.h: Regenerate.
 802         * lm32-asm.c: Regenerate.
 803         * lm32-desc.c: Regenerate.
 804         * lm32-desc.h: Regenerate.
 805         * lm32-dis.c: Regenerate.
 806         * lm32-ibld.c: Regenerate.
 807         * lm32-opc.c: Regenerate.
 808         * lm32-opc.h: Regenerate.
 809         * lm32-opinst.c: Regenerate.
 810         * m32c-asm.c: Regenerate.
 811         * m32c-desc.c: Regenerate.
 812         * m32c-desc.h: Regenerate.
 813         * m32c-dis.c: Regenerate.
 814         * m32c-ibld.c: Regenerate.
 815         * m32c-opc.c: Regenerate.
 816         * m32c-opc.h: Regenerate.
 817         * m32r-asm.c: Regenerate.
 818         * m32r-desc.c: Regenerate.
 819         * m32r-desc.h: Regenerate.
 820         * m32r-dis.c: Regenerate.
 821         * m32r-ibld.c: Regenerate.
 822         * m32r-opc.c: Regenerate.
 823         * m32r-opc.h: Regenerate.
 824         * m32r-opinst.c: Regenerate.
 825         * mep-asm.c: Regenerate.
 826         * mep-desc.c: Regenerate.
 827         * mep-desc.h: Regenerate.
 828         * mep-dis.c: Regenerate.
 829         * mep-ibld.c: Regenerate.
 830         * mep-opc.c: Regenerate.
 831         * mep-opc.h: Regenerate.
 832         * mt-asm.c: Regenerate.
 833         * mt-desc.c: Regenerate.
 834         * mt-desc.h: Regenerate.
 835         * mt-dis.c: Regenerate.
 836         * mt-ibld.c: Regenerate.
 837         * mt-opc.c: Regenerate.
 838         * mt-opc.h: Regenerate.
 839         * or1k-asm.c: Regenerate.
 840         * or1k-desc.c: Regenerate.
 841         * or1k-desc.h: Regenerate.
 842         * or1k-dis.c: Regenerate.
 843         * or1k-ibld.c: Regenerate.
 844         * or1k-opc.c: Regenerate.
 845         * or1k-opc.h: Regenerate.
 846         * or1k-opinst.c: Regenerate.
 847         * xc16x-asm.c: Regenerate.
 848         * xc16x-desc.c: Regenerate.
 849         * xc16x-desc.h: Regenerate.
 850         * xc16x-dis.c: Regenerate.
 851         * xc16x-ibld.c: Regenerate.
 852         * xc16x-opc.c: Regenerate.
 853         * xc16x-opc.h: Regenerate.
 854         * xstormy16-asm.c: Regenerate.
 855         * xstormy16-desc.c: Regenerate.
 856         * xstormy16-desc.h: Regenerate.
 857         * xstormy16-dis.c: Regenerate.
 858         * xstormy16-ibld.c: Regenerate.
 859         * xstormy16-opc.c: Regenerate.
 860         * xstormy16-opc.h: Regenerate.
 861
 862 2017-07-07  Alan Modra  <amodra@gmail.com>
 863
 864         * cgen-dis.in: Include disassemble.h, not dis-asm.h.
 865         * m32c-dis.c: Regenerate.
 866         * mep-dis.c: Regenerate.
 867
 868 2017-07-05  Borislav Petkov  <bp@suse.de>
 869
 870         * i386-dis.c: Enable ModRM.reg /6 aliases.
 871
 872 2017-07-04  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
 873
 874         * opcodes/arm-dis.c: Support MVFR2 in disassembly
 875         with vmrs and vmsr.
 876
 877 2017-07-04  Tristan Gingold  <gingold@adacore.com>
 878
 879         * configure: Regenerate.
 880
 881 2017-07-03  Tristan Gingold  <gingold@adacore.com>
 882
 883         * po/opcodes.pot: Regenerate.
 884
 885 2017-06-30  Maciej W. Rozycki  <macro@imgtec.com>
 886
 887         * mips-opc.c (mips_builtin_opcodes): Move "lsa" and "dlsa"
 888         entries to the MSA ASE instruction block.
 889
 890 2017-06-30  Andrew Bennett  <andrew.bennett@imgtec.com>
 891             Maciej W. Rozycki  <macro@imgtec.com>
 892
 893         * micromips-opc.c (XPA, XPAVZ): New macros.
 894         (micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and
 895         "mthgc0".
 896
 897 2017-06-30  Andrew Bennett  <andrew.bennett@imgtec.com>
 898             Maciej W. Rozycki  <macro@imgtec.com>
 899
 900         * micromips-opc.c (I36): New macro.
 901         (micromips_opcodes): Add "eretnc".
 902
 903 2017-06-30  Maciej W. Rozycki  <macro@imgtec.com>
 904             Andrew Bennett  <andrew.bennett@imgtec.com>
 905
 906         * mips-dis.c (mips_calculate_combination_ases): Handle the
 907         ASE_XPA_VIRT flag.
 908         (parse_mips_ase_option): New function.
 909         (parse_mips_dis_option): Factor out ASE option handling to the
 910         new function.  Call `mips_calculate_combination_ases'.
 911         * mips-opc.c (XPAVZ): New macro.
 912         (mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0",
 913         "mfhgc0", "mthc0" and "mthgc0".
 914
 915 2017-06-29  Maciej W. Rozycki  <macro@imgtec.com>
 916
 917         * mips-dis.c (mips_calculate_combination_ases): New function.
 918         (mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT
 919         calculation to the new function.
 920         (set_default_mips_dis_options): Call the new function.
 921
 922 2017-06-29  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 923
 924         * arc-dis.c (parse_disassembler_options): Use
 925         FOR_EACH_DISASSEMBLER_OPTION.
 926
 927 2017-06-29  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 928
 929         * arc-dis.c (parse_option): Use disassembler_options_cmp to compare
 930         disassembler option strings.
 931         (parse_cpu_option): Likewise.
 932
 933 2017-06-28  Tamar Christina  <tamar.christina@arm.com>
 934
 935         * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod.
 936         * aarch64-dis.c (aarch64_ext_reglane): Likewise.
 937         * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New.
 938         (aarch64_feature_dotprod, DOT_INSN): New.
 939         (udot, sdot): New.
 940         * aarch64-dis-2.c: Regenerated.
 941
 942 2017-06-28  Jiong Wang  <jiong.wang@arm.com>
 943
 944         * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
 945
 946 2017-06-28  Maciej W. Rozycki  <macro@imgtec.com>
 947             Matthew Fortune  <matthew.fortune@imgtec.com>
 948             Andrew Bennett  <andrew.bennett@imgtec.com>
 949
 950         * mips-formats.h (INT_BIAS): New macro.
 951         (INT_ADJ): Redefine in INT_BIAS terms.
 952         * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
 953         (mips_print_save_restore): New function.
 954         (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
 955         (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
 956         call.
 957         (print_insn_args): Handle OP_SAVE_RESTORE_LIST.
 958         (print_mips16_insn_arg): Call `mips_print_save_restore' for
 959         OP_SAVE_RESTORE_LIST handling, factored out from here.
 960         * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
 961         (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
 962         (mips_builtin_opcodes): Add "restore" and "save" entries.
 963         * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
 964         (IAMR2): New macro.
 965         (mips16_opcodes): Add "copyw" and "ucopyw" entries.
 966
 967 2017-06-23  Andrew Waterman  <andrew@sifive.com>
 968
 969         * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
 970         alias; do not mark SLTI instruction as an alias.
 971
 972 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 973
 974         * i386-dis.c (RM_0FAE_REG_5): Removed.
 975         (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
 976         (PREFIX_MOD_3_0F01_REG_5_RM_0): New.
 977         (PREFIX_MOD_3_0FAE_REG_5): Likewise.
 978         (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1.  Add
 979         PREFIX_MOD_3_0F01_REG_5_RM_0.
 980         (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5.  Add
 981         PREFIX_MOD_3_0FAE_REG_5.
 982         (mod_table): Update MOD_0FAE_REG_5.
 983         (rm_table): Update RM_0F01_REG_5.  Remove RM_0FAE_REG_5.
 984         * i386-opc.tbl: Update incsspd, incsspq and setssbsy.
 985         * i386-tbl.h: Regenerated.
 986
 987 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 988
 989         * i386-dis.c (prefix_table): Replace savessp with saveprevssp.
 990         * i386-opc.tbl: Likewise.
 991         * i386-tbl.h: Regenerated.
 992
 993 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 994
 995         * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"
 996         and "jmp{&|}".
 997         (NOTRACK_Fixup): Support memory indirect branch with NOTRACK
 998         prefix.
 999
1000 2017-06-19  Nick Clifton  <nickc@redhat.com>
1001
1002         PR binutils/21614
1003         * score-dis.c (score_opcodes): Add sentinel.
1004
1005 2017-06-16  Alan Modra  <amodra@gmail.com>
1006
1007         * rx-decode.c: Regenerate.
1008
1009 2017-06-15  H.J. Lu  <hongjiu.lu@intel.com>
1010
1011         PR binutils/21594
1012         * i386-dis.c (OP_E_register): Check valid bnd register.
1013         (OP_G): Likewise.
1014
1015 2017-06-15  Nick Clifton  <nickc@redhat.com>
1016
1017         PR binutils/21595
1018         * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
1019         range value.
1020
1021 2017-06-15  Nick Clifton  <nickc@redhat.com>
1022
1023         PR binutils/21588
1024         * rl78-decode.opc (OP_BUF_LEN): Define.
1025         (GETBYTE): Check for the index exceeding OP_BUF_LEN.
1026         (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
1027         array.
1028         * rl78-decode.c: Regenerate.
1029
1030 2017-06-15  Nick Clifton  <nickc@redhat.com>
1031
1032         PR binutils/21586
1033         * bfin-dis.c (gregs): Clip index to prevent overflow.
1034         (regs): Likewise.
1035         (regs_lo): Likewise.
1036         (regs_hi): Likewise.
1037
1038 2017-06-14  Nick Clifton  <nickc@redhat.com>
1039
1040         PR binutils/21576
1041         * score7-dis.c (score_opcodes): Add sentinel.
1042
1043 2017-06-14  Yao Qi  <yao.qi@linaro.org>
1044
1045         * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
1046         * arm-dis.c: Likewise.
1047         * ia64-dis.c: Likewise.
1048         * mips-dis.c: Likewise.
1049         * spu-dis.c: Likewise.
1050         * disassemble.h (print_insn_aarch64): New declaration, moved from
1051         include/dis-asm.h.
1052         (print_insn_big_arm, print_insn_big_mips): Likewise.
1053         (print_insn_i386, print_insn_ia64): Likewise.
1054         (print_insn_little_arm, print_insn_little_mips): Likewise.
1055
1056 2017-06-14  Nick Clifton  <nickc@redhat.com>
1057
1058         PR binutils/21587
1059         * rx-decode.opc: Include libiberty.h
1060         (GET_SCALE): New macro - validates access to SCALE array.
1061         (GET_PSCALE): New macro - validates access to PSCALE array.
1062         (DIs, SIs, S2Is, rx_disp): Use new macros.
1063         * rx-decode.c: Regenerate.
1064
1065 2017-07-14  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1066
1067         * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
1068
1069 2017-05-30  Anton Kolesov  <anton.kolesov@synopsys.com>
1070
1071         * arc-dis.c (enforced_isa_mask): Declare.
1072         (cpu_types): Likewise.
1073         (parse_cpu_option): New function.
1074         (parse_disassembler_options): Use it.
1075         (print_insn_arc): Use enforced_isa_mask.
1076         (print_arc_disassembler_options): Document new options.
1077
1078 2017-05-24  Yao Qi  <yao.qi@linaro.org>
1079
1080         * alpha-dis.c: Include disassemble.h, don't include
1081         dis-asm.h.
1082         * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
1083         * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
1084         * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
1085         * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
1086         * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
1087         * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
1088         * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
1089         * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
1090         * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
1091         * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
1092         * moxie-dis.c, msp430-dis.c, mt-dis.c:
1093         * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
1094         * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
1095         * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
1096         * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
1097         * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
1098         * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
1099         * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
1100         * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
1101         * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
1102         * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
1103         * z80-dis.c, z8k-dis.c: Likewise.
1104         * disassemble.h: New file.
1105
1106 2017-05-24  Yao Qi  <yao.qi@linaro.org>
1107
1108         * rl78-dis.c (rl78_get_disassembler): If parameter abfd
1109         is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
1110
1111 2017-05-24  Yao Qi  <yao.qi@linaro.org>
1112
1113         * disassemble.c (disassembler): Add arguments a, big and mach.
1114         Use them.
1115
1116 2017-05-22  H.J. Lu  <hongjiu.lu@intel.com>
1117
1118         * i386-dis.c (NOTRACK_Fixup): New.
1119         (NOTRACK): Likewise.
1120         (NOTRACK_PREFIX): Likewise.
1121         (last_active_prefix): Likewise.
1122         (reg_table): Use NOTRACK on indirect call and jmp.
1123         (ckprefix): Set last_active_prefix.
1124         (prefix_name): Return "notrack" for NOTRACK_PREFIX.
1125         * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
1126         * i386-opc.h (NoTrackPrefixOk): New.
1127         (i386_opcode_modifier): Add notrackprefixok.
1128         * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
1129         Add notrack.
1130         * i386-tbl.h: Regenerated.
1131
1132 2017-05-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
1133
1134         * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
1135         (X_IMM2): Define.
1136         (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
1137         bfd_mach_sparc_v9m8.
1138         (print_insn_sparc): Handle new operand types.
1139         * sparc-opc.c (MASK_M8): Define.
1140         (v6): Add MASK_M8.
1141         (v6notlet): Likewise.
1142         (v7): Likewise.
1143         (v8): Likewise.
1144         (v9): Likewise.
1145         (v9a): Likewise.
1146         (v9b): Likewise.
1147         (v9c): Likewise.
1148         (v9d): Likewise.
1149         (v9e): Likewise.
1150         (v9v): Likewise.
1151         (v9m): Likewise.
1152         (v9andleon): Likewise.
1153         (m8): Define.
1154         (HWS_VM8): Define.
1155         (HWS2_VM8): Likewise.
1156         (sparc_opcode_archs): Add entry for "m8".
1157         (sparc_opcodes): Add OSA2017 and M8 instructions
1158         dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
1159         fpx{ll,ra,rl}64x,
1160         ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
1161         ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
1162         revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
1163         stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
1164         (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
1165         ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
1166         ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
1167         ASI_CORE_SELECT_COMMIT_NHT.
1168
1169 2017-05-18  Alan Modra  <amodra@gmail.com>
1170
1171         * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
1172         * aarch64-dis.c: Likewise.
1173         * aarch64-gen.c: Likewise.
1174         * aarch64-opc.c: Likewise.
1175
1176 2017-05-15  Maciej W. Rozycki  <macro@imgtec.com>
1177             Matthew Fortune  <matthew.fortune@imgtec.com>
1178
1179         * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
1180         ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
1181         (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
1182         (print_insn_arg) <OP_REG28>: Add handler.
1183         (validate_insn_args) <OP_REG28>: Handle.
1184         (print_mips16_insn_arg): Handle MIPS16 instructions that require
1185         32-bit encoding and 9-bit immediates.
1186         (print_insn_mips16): Handle MIPS16 instructions that require
1187         32-bit encoding and MFC0/MTC0 operand decoding.
1188         * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
1189         <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
1190         (RD_C0, WR_C0, E2, E2MT): New macros.
1191         (mips16_opcodes): Add entries for MIPS16e2 instructions:
1192         GP-relative "addiu" and its "addu" spelling, "andi", "cache",
1193         "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
1194         "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
1195         "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
1196         "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
1197         instructions, "swl", "swr", "sync" and its "sync_acquire",
1198         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
1199         "xori", "dmt", "dvpe", "emt" and "evpe".  Add split
1200         regular/extended entries for original MIPS16 ISA revision
1201         instructions whose extended forms are subdecoded in the MIPS16e2
1202         ISA revision: "li", "sll" and "srl".
1203
1204 2017-05-15  Maciej W. Rozycki  <macro@imgtec.com>
1205
1206         * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
1207         reference in CP0 move operand decoding.
1208
1209 2017-05-12  Maciej W. Rozycki  <macro@imgtec.com>
1210
1211         * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
1212         type to hexadecimal.
1213         (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
1214
1215 2017-05-11  Maciej W. Rozycki  <macro@imgtec.com>
1216
1217         * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
1218         "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
1219         "sync_rmb" and "sync_wmb" as aliases.
1220         * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
1221         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
1222
1223 2017-05-10  Claudiu Zissulescu  <claziss@synopsys.com>
1224
1225         * arc-dis.c (parse_option): Update quarkse_em option..
1226         * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
1227         QUARKSE1.
1228         (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
1229
1230 2017-05-03  Kito Cheng  <kito.cheng@gmail.com>
1231
1232         * riscv-dis.c (print_insn_args): Handle 'Co' operands.
1233
1234 2017-05-01  Michael Clark  <michaeljclark@mac.com>
1235
1236         * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
1237         register.
1238
1239 2017-05-02  Maciej W. Rozycki  <macro@imgtec.com>
1240
1241         * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
1242         and branches and not synthetic data instructions.
1243
1244 2017-05-02  Bernd Edlinger   <bernd.edlinger@hotmail.de>
1245
1246         * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
1247
1248 2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>
1249
1250         * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
1251         * arc-opc.c (insert_r13el): New function.
1252         (R13_EL): Define.
1253         * arc-tbl.h: Add new enter/leave variants.
1254
1255 2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>
1256
1257         * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
1258
1259 2017-04-25  Maciej W. Rozycki  <macro@imgtec.com>
1260
1261         * mips-dis.c (print_mips_disassembler_options): Add
1262         `no-aliases'.
1263
1264 2017-04-25  Maciej W. Rozycki  <macro@imgtec.com>
1265
1266         * mips16-opc.c (AL): New macro.
1267         (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
1268         of "ld" and "lw" as aliases.
1269
1270 2017-04-24  Tamar Christina  <tamar.christina@arm.com>
1271
1272         * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
1273         arguments.
1274
1275 2017-04-22  Alexander Fedotov  <alfedotov@gmail.com>
1276             Alan Modra  <amodra@gmail.com>
1277
1278         * ppc-opc.c (ELEV): Define.
1279         (vle_opcodes): Add se_rfgi and e_sc.
1280         (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
1281         for E200Z4.
1282
1283 2017-04-21  Jose E. Marchesi  <jose.marchesi@oracle.com>
1284
1285         * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
1286
1287 2017-04-21  Nick Clifton  <nickc@redhat.com>
1288
1289         PR binutils/21380
1290         * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
1291         LD3R and LD4R.
1292
1293 2017-04-13  Alan Modra  <amodra@gmail.com>
1294
1295         * epiphany-desc.c: Regenerate.
1296         * fr30-desc.c: Regenerate.
1297         * frv-desc.c: Regenerate.
1298         * ip2k-desc.c: Regenerate.
1299         * iq2000-desc.c: Regenerate.
1300         * lm32-desc.c: Regenerate.
1301         * m32c-desc.c: Regenerate.
1302         * m32r-desc.c: Regenerate.
1303         * mep-desc.c: Regenerate.
1304         * mt-desc.c: Regenerate.
1305         * or1k-desc.c: Regenerate.
1306         * xc16x-desc.c: Regenerate.
1307         * xstormy16-desc.c: Regenerate.
1308
1309 2017-04-11  Alan Modra  <amodra@gmail.com>
1310
1311         * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
1312         PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm".  Formatting.  Set
1313         PPC_OPCODE_TMR for e6500.
1314         * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
1315         (PPCVEC3): Define as PPC_OPCODE_POWER9.
1316         (PPCVSX2): Define as PPC_OPCODE_POWER8.
1317         (PPCVSX3): Define as PPC_OPCODE_POWER9.
1318         (PPCHTM): Define as PPC_OPCODE_POWER8.
1319         (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
1320
1321 2017-04-10  Alan Modra  <amodra@gmail.com>
1322
1323         * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
1324         * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
1325         (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
1326         removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
1327
1328 2017-04-09  Pip Cet  <pipcet@gmail.com>
1329
1330         * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
1331         appropriate floating-point precision directly.
1332
1333 2017-04-07  Alan Modra  <amodra@gmail.com>
1334
1335         * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
1336         lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
1337         lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
1338         lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
1339         vector instructions with E6500 not PPCVEC2.
1340
1341 2017-04-06  Pip Cet  <pipcet@gmail.com>
1342
1343         * Makefile.am: Add wasm32-dis.c.
1344         * configure.ac: Add wasm32-dis.c to wasm32 target.
1345         * disassemble.c: Add wasm32 disassembler code.
1346         * wasm32-dis.c: New file.
1347         * Makefile.in: Regenerate.
1348         * configure: Regenerate.
1349         * po/POTFILES.in: Regenerate.
1350         * po/opcodes.pot: Regenerate.
1351
1352 2017-04-05  Pedro Alves  <palves@redhat.com>
1353
1354         * arc-dis.c (parse_option, parse_disassembler_options): Constify.
1355         * arm-dis.c (parse_arm_disassembler_options): Constify.
1356         * ppc-dis.c (powerpc_init_dialect): Constify local.
1357         * vax-dis.c (parse_disassembler_options): Constify.
1358
1359 2017-04-03  Palmer Dabbelt  <palmer@dabbelt.com>
1360
1361         * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
1362         RISCV_GP_SYMBOL.
1363
1364 2017-03-30  Pip Cet  <pipcet@gmail.com>
1365
1366         * configure.ac: Add (empty) bfd_wasm32_arch target.
1367         * configure: Regenerate
1368         * po/opcodes.pot: Regenerate.
1369
1370 2017-03-29  Sheldon Lobo  <sheldon.lobo@oracle.com>
1371
1372         Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
1373         OSA2015.
1374         * opcodes/sparc-opc.c (asi_table): New ASIs.
1375
1376 2017-03-29  Alan Modra  <amodra@gmail.com>
1377
1378         * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags.  Add
1379         "raw" option.
1380         (lookup_powerpc): Don't special case -1 dialect.  Handle
1381         PPC_OPCODE_RAW.
1382         (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
1383         lookup_powerpc call, pass it on second.
1384
1385 2017-03-27  Alan Modra  <amodra@gmail.com>
1386
1387         PR 21303
1388         * ppc-dis.c (struct ppc_mopt): Comment.
1389         (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
1390
1391 2017-03-27  Rinat Zelig  <rinat@mellanox.com>
1392
1393         * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
1394         * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
1395         F_NPS_M, F_NPS_CORE, F_NPS_ALL.
1396         (insert_nps_misc_imm_offset): New function.
1397         (extract_nps_misc imm_offset): New function.
1398         (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
1399         (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
1400
1401 2017-03-21  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
1402
1403         * s390-mkopc.c (main): Remove vx2 check.
1404         * s390-opc.txt: Remove vx2 instruction flags.
1405
1406 2017-03-21  Rinat Zelig  <rinat@mellanox.com>
1407
1408         * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
1409         * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
1410         (insert_nps_imm_offset): New function.
1411         (extract_nps_imm_offset): New function.
1412         (insert_nps_imm_entry): New function.
1413         (extract_nps_imm_entry): New function.
1414
1415 2017-03-17  Alan Modra  <amodra@gmail.com>
1416
1417         PR 21248
1418         * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
1419         mtivor32, and mtivor33 for e6500.  Move mfibatl and mfibatu after
1420         those spr mnemonics they alias.  Similarly for mtibatl, mtibatu.
1421
1422 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
1423
1424         * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
1425         <c.andi>: Likewise.
1426         <c.addiw> Likewise.
1427
1428 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
1429
1430         * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
1431
1432 2017-03-13  Andrew Waterman  <andrew@sifive.com>
1433
1434         * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
1435         <srl> Likewise.
1436         <srai> Likewise.
1437         <sra> Likewise.
1438
1439 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
1440
1441         * i386-gen.c (opcode_modifiers): Replace S with Load.
1442         * i386-opc.h (S): Removed.
1443         (Load): New.
1444         (i386_opcode_modifier): Replace s with load.
1445         * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
1446         and {evex}.  Replace S with Load.
1447         * i386-tbl.h: Regenerated.
1448
1449 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
1450
1451         * i386-opc.tbl: Use CpuCET on rdsspq.
1452         * i386-tbl.h: Regenerated.
1453
1454 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
1455
1456         * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
1457         <vsx>: Do not use PPC_OPCODE_VSX3;
1458
1459 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
1460
1461         * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
1462
1463 2017-03-06  H.J. Lu  <hongjiu.lu@intel.com>
1464
1465         * i386-dis.c (REG_0F1E_MOD_3): New enum.
1466         (MOD_0F1E_PREFIX_1): Likewise.
1467         (MOD_0F38F5_PREFIX_2): Likewise.
1468         (MOD_0F38F6_PREFIX_0): Likewise.
1469         (RM_0F1E_MOD_3_REG_7): Likewise.
1470         (PREFIX_MOD_0_0F01_REG_5): Likewise.
1471         (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
1472         (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
1473         (PREFIX_0F1E): Likewise.
1474         (PREFIX_MOD_0_0FAE_REG_5): Likewise.
1475         (PREFIX_0F38F5): Likewise.
1476         (dis386_twobyte): Use PREFIX_0F1E.
1477         (reg_table): Add REG_0F1E_MOD_3.
1478         (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
1479         PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
1480         PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5.  Update
1481         PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
1482         (three_byte_table): Use PREFIX_0F38F5.
1483         (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
1484         Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
1485         (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
1486         RM_0F1E_MOD_3_REG_7.  Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
1487         PREFIX_MOD_3_0F01_REG_5_RM_2.
1488         * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
1489         (cpu_flags): Add CpuCET.
1490         * i386-opc.h (CpuCET): New enum.
1491         (CpuUnused): Commented out.
1492         (i386_cpu_flags): Add cpucet.
1493         * i386-opc.tbl: Add Intel CET instructions.
1494         * i386-init.h: Regenerated.
1495         * i386-tbl.h: Likewise.
1496
1497 2017-03-06  Alan Modra  <amodra@gmail.com>
1498
1499         PR 21124
1500         * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
1501         (extract_raq, extract_ras, extract_rbx): New functions.
1502         (powerpc_operands): Use opposite corresponding insert function.
1503         (Q_MASK): Define.
1504         (powerpc_opcodes): Apply Q_MASK to all quad insns with even
1505         register restriction.
1506
1507 2017-02-28  Peter Bergner  <bergner@vnet.ibm.com>
1508
1509         * disassemble.c Include "safe-ctype.h".
1510         (disassemble_init_for_target): Handle s390 init.
1511         (remove_whitespace_and_extra_commas): New function.
1512         (disassembler_options_cmp): Likewise.
1513         * arm-dis.c: Include "libiberty.h".
1514         (NUM_ELEM): Delete.
1515         (regnames): Use long disassembler style names.
1516         Add force-thumb and no-force-thumb options.
1517         (NUM_ARM_REGNAMES): Rename from this...
1518         (NUM_ARM_OPTIONS): ...to this.  Use ARRAY_SIZE.
1519         (get_arm_regname_num_options): Delete.
1520         (set_arm_regname_option): Likewise.
1521         (get_arm_regnames): Likewise.
1522         (parse_disassembler_options): Likewise.
1523         (parse_arm_disassembler_option): Rename from this...
1524         (parse_arm_disassembler_options): ...to this.  Make static.
1525         Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
1526         (print_insn): Use parse_arm_disassembler_options.
1527         (disassembler_options_arm): New function.
1528         (print_arm_disassembler_options): Handle updated regnames.
1529         * ppc-dis.c: Include "libiberty.h".
1530         (ppc_opts): Add "32" and "64" entries.
1531         (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
1532         (powerpc_init_dialect): Add break to switch statement.
1533         Use new FOR_EACH_DISASSEMBLER_OPTION macro.
1534         (disassembler_options_powerpc): New function.
1535         (print_ppc_disassembler_options): Use ARRAY_SIZE.
1536         Remove printing of "32" and "64".
1537         * s390-dis.c: Include "libiberty.h".
1538         (init_flag): Remove unneeded variable.
1539         (struct s390_options_t): New structure type.
1540         (options): New structure.
1541         (init_disasm): Rename from this...
1542         (disassemble_init_s390): ...to this.  Add initializations for
1543         current_arch_mask and option_use_insn_len_bits_p.  Remove init_flag.
1544         (print_insn_s390): Delete call to init_disasm.
1545         (disassembler_options_s390): New function.
1546         (print_s390_disassembler_options): Print using information from
1547         struct 'options'.
1548         * po/opcodes.pot: Regenerate.
1549
1550 2017-02-28  Jan Beulich  <jbeulich@suse.com>
1551
1552         * i386-dis.c (PCMPESTR_Fixup): New.
1553         (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
1554         (prefix_table): Use PCMPESTR_Fixup.
1555         (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
1556         PCMPESTR_Fixup.
1557         (vex_w_table): Delete VPCMPESTR{I,M} entries.
1558         * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
1559         Split 64-bit and non-64-bit variants.
1560         * opcodes/i386-tbl.h: Re-generate.
1561
1562 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
1563
1564         * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
1565         (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
1566         (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
1567         (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
1568         (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
1569         (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
1570         (OP_SVE_V_HSD): New macros.
1571         (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
1572         (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
1573         (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
1574         (aarch64_opcode_table): Add new SVE instructions.
1575         (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
1576         for rotation operands.  Add new SVE operands.
1577         * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
1578         (ins_sve_quad_index): Likewise.
1579         (ins_imm_rotate): Split into...
1580         (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
1581         * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
1582         (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
1583         functions.
1584         (aarch64_ins_sve_addr_ri_s4): New function.
1585         (aarch64_ins_sve_quad_index): Likewise.
1586         (do_misc_encoding): Handle "MOV Zn.Q, Qm".
1587         * aarch64-asm-2.c: Regenerate.
1588         * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
1589         (ext_sve_quad_index): Likewise.
1590         (ext_imm_rotate): Split into...
1591         (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
1592         * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
1593         (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
1594         functions.
1595         (aarch64_ext_sve_addr_ri_s4): New function.
1596         (aarch64_ext_sve_quad_index): Likewise.
1597         (aarch64_ext_sve_index): Allow quad indices.
1598         (do_misc_decoding): Likewise.
1599         * aarch64-dis-2.c: Regenerate.
1600         * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
1601         aarch64_field_kinds.
1602         (OPD_F_OD_MASK): Widen by one bit.
1603         (OPD_F_NO_ZR): Bump accordingly.
1604         (get_operand_field_width): New function.
1605         * aarch64-opc.c (fields): Add new SVE fields.
1606         (operand_general_constraint_met_p): Handle new SVE operands.
1607         (aarch64_print_operand): Likewise.
1608         * aarch64-opc-2.c: Regenerate.
1609
1610 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
1611
1612         * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
1613         (aarch64_feature_compnum): ...this.
1614         (SIMD_V8_3): Replace with...
1615         (COMPNUM): ...this.
1616         (CNUM_INSN): New macro.
1617         (aarch64_opcode_table): Use it for the complex number instructions.
1618
1619 2017-02-24  Jan Beulich  <jbeulich@suse.com>
1620
1621         * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
1622
1623 2017-02-23  Sheldon Lobo <sheldon.lobo@oracle.com>
1624
1625         Add support for associating SPARC ASIs with an architecture level.
1626         * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
1627         * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
1628         decoding of SPARC ASIs.
1629
1630 2017-02-23  Jan Beulich  <jbeulich@suse.com>
1631
1632         * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
1633         82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
1634
1635 2017-02-21  Jan Beulich  <jbeulich@suse.com>
1636
1637         * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
1638         1 (instead of to itself). Correct typo.
1639
1640 2017-02-14  Andrew Waterman  <andrew@sifive.com>
1641
1642         * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
1643         pseudoinstructions.
1644
1645 2017-02-15  Richard Sandiford  <richard.sandiford@arm.com>
1646
1647         * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
1648         (aarch64_sys_reg_supported_p): Handle them.
1649
1650 2017-02-15  Claudiu Zissulescu  <claziss@synopsys.com>
1651
1652         * arc-opc.c (UIMM6_20R): Define.
1653         (SIMM12_20): Use above.
1654         (SIMM12_20R): Define.
1655         (SIMM3_5_S): Use above.
1656         (UIMM7_A32_11R_S): Define.
1657         (UIMM7_9_S): Use above.
1658         (UIMM3_13R_S): Define.
1659         (SIMM11_A32_7_S): Use above.
1660         (SIMM9_8R): Define.
1661         (UIMM10_A32_8_S): Use above.
1662         (UIMM8_8R_S): Define.
1663         (W6): Use above.
1664         (arc_relax_opcodes): Use all above defines.
1665
1666 2017-02-15  Vineet Gupta <vgupta@synopsys.com>
1667
1668         * arc-regs.h: Distinguish some of the registers different on
1669         ARC700 and HS38 cpus.
1670
1671 2017-02-14  Alan Modra  <amodra@gmail.com>
1672
1673         PR 21118
1674         * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
1675         with PPC_OPERAND_SPR.  Flag PSQ and PSQM with PPC_OPERAND_GQR.
1676
1677 2017-02-11  Stafford Horne  <shorne@gmail.com>
1678             Alan Modra  <amodra@gmail.com>
1679
1680         * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
1681         Use insn_bytes_value and insn_int_value directly instead.  Don't
1682         free allocated memory until function exit.
1683
1684 2017-02-10  Nicholas Piggin  <npiggin@gmail.com>
1685
1686         * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
1687
1688 2017-02-03  Nick Clifton  <nickc@redhat.com>
1689
1690         PR 21096
1691         * aarch64-opc.c (print_register_list): Ensure that the register
1692         list index will fir into the tb buffer.
1693         (print_register_offset_address): Likewise.
1694         * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
1695
1696 2017-01-27  Alexis Deruell  <alexis.deruelle@gmail.com>
1697
1698         PR 21056
1699         * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
1700         instructions when the previous fetch packet ends with a 32-bit
1701         instruction.
1702
1703 2017-01-24  Dimitar Dimitrov  <dimitar@dinux.eu>
1704
1705         * pru-opc.c: Remove vague reference to a future GDB port.
1706
1707 2017-01-20  Nick Clifton  <nickc@redhat.com>
1708
1709         * po/ga.po: Updated Irish translation.
1710
1711 2017-01-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
1712
1713         * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
1714
1715 2017-01-13  Yao Qi  <yao.qi@linaro.org>
1716
1717         * m68k-dis.c (match_insn_m68k): Extend comments.  Return -1
1718         if FETCH_DATA returns 0.
1719         (m68k_scan_mask): Likewise.
1720         (print_insn_m68k): Update code to handle -1 return value.
1721
1722 2017-01-13  Yao Qi  <yao.qi@linaro.org>
1723
1724         * m68k-dis.c (enum print_insn_arg_error): New.
1725         (NEXTBYTE): Replace -3 with
1726         PRINT_INSN_ARG_MEMORY_ERROR.
1727         (NEXTULONG): Likewise.
1728         (NEXTSINGLE): Likewise.
1729         (NEXTDOUBLE): Likewise.
1730         (NEXTDOUBLE): Likewise.
1731         (NEXTPACKED): Likewise.
1732         (FETCH_ARG): Likewise.
1733         (FETCH_DATA): Update comments.
1734         (print_insn_arg): Update comments. Replace magic numbers with
1735         enum.
1736         (match_insn_m68k): Likewise.
1737
1738 2017-01-12  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1739
1740         * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
1741         * i386-dis-evex.h (evex_table): Updated.
1742         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
1743         CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
1744         (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
1745         * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
1746         (i386_cpu_flags): Add cpuavx512_vpopcntdq.
1747         * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
1748         * i386-init.h: Regenerate.
1749         * i386-tbl.h: Ditto.
1750
1751 2017-01-12  Yao Qi  <yao.qi@linaro.org>
1752
1753         * msp430-dis.c (msp430_singleoperand): Return -1 if
1754         msp430dis_opcode_signed returns false.
1755         (msp430_doubleoperand): Likewise.
1756         (msp430_branchinstr): Return -1 if
1757         msp430dis_opcode_unsigned returns false.
1758         (msp430x_calla_instr): Likewise.
1759         (print_insn_msp430): Likewise.
1760
1761 2017-01-05  Nick Clifton  <nickc@redhat.com>
1762
1763         PR 20946
1764         * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
1765         could not be matched.
1766         (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
1767         NULL.
1768
1769 2017-01-04  Szabolcs Nagy  <szabolcs.nagy@arm.com>
1770
1771         * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
1772         (aarch64_opcode_table): Use RCPC_INSN.
1773
1774 2017-01-03  Kito Cheng  <kito.cheng@gmail.com>
1775
1776         * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
1777         extension.
1778         * riscv-opcodes/all-opcodes: Likewise.
1779
1780 2017-01-03  Dilyan Palauzov  <dilyan.palauzov@aegee.org>
1781
1782         * riscv-dis.c (print_insn_args): Add fall through comment.
1783
1784 2017-01-03  Nick Clifton  <nickc@redhat.com>
1785
1786         * po/sr.po: New Serbian translation.
1787         * configure.ac (ALL_LINGUAS): Add sr.
1788         * configure: Regenerate.
1789
1790 2017-01-02  Alan Modra  <amodra@gmail.com>
1791
1792         * epiphany-desc.h: Regenerate.
1793         * epiphany-opc.h: Regenerate.
1794         * fr30-desc.h: Regenerate.
1795         * fr30-opc.h: Regenerate.
1796         * frv-desc.h: Regenerate.
1797         * frv-opc.h: Regenerate.
1798         * ip2k-desc.h: Regenerate.
1799         * ip2k-opc.h: Regenerate.
1800         * iq2000-desc.h: Regenerate.
1801         * iq2000-opc.h: Regenerate.
1802         * lm32-desc.h: Regenerate.
1803         * lm32-opc.h: Regenerate.
1804         * m32c-desc.h: Regenerate.
1805         * m32c-opc.h: Regenerate.
1806         * m32r-desc.h: Regenerate.
1807         * m32r-opc.h: Regenerate.
1808         * mep-desc.h: Regenerate.
1809         * mep-opc.h: Regenerate.
1810         * mt-desc.h: Regenerate.
1811         * mt-opc.h: Regenerate.
1812         * or1k-desc.h: Regenerate.
1813         * or1k-opc.h: Regenerate.
1814         * xc16x-desc.h: Regenerate.
1815         * xc16x-opc.h: Regenerate.
1816         * xstormy16-desc.h: Regenerate.
1817         * xstormy16-opc.h: Regenerate.
1818
1819 2017-01-02  Alan Modra  <amodra@gmail.com>
1820
1821         Update year range in copyright notice of all files.
1822
1823 For older changes see ChangeLog-2016
1824 \f
1825 Copyright (C) 2017 Free Software Foundation, Inc.
1826
1827 Copying and distribution of this file, with or without modification,
1828 are permitted in any medium without royalty provided the copyright
1829 notice and this notice are preserved.
1830
1831 Local Variables:
1832 mode: change-log
1833 left-margin: 8
1834 fill-column: 74
1835 version-control: never
1836 End: