opcodes/ChangeLog

   1 2006-08-04      Dwarakanath Rajagopal   <dwarak.rajagopal@amd.com>
   2
   3         * i386-dis.c (MXC,EMC): Define.
   4         (OP_MXC): New function to handle cvt* (convert instructions) between
   5         %xmm and %mm register correctly.
   6         (OP_EMC): ditto.
   7         (prefix_user_table): Modified  cvtpi2pd,cvtpd2pi and cvttpd2pi
   8         instruction operands in PREGRP2,PREGRP3,PREGRP4 appropriately
   9         with EMC/MXC.
  10
  11 2006-07-29  Richard Sandiford  <richard@codesourcery.com>
  12
  13         * m68k-opc.c (m68k_opcodes): Fix operand specificer in the Coldfire
  14         "fdaddl" entry.
  15
  16 2006-07-19  Paul Brook  <paul@codesourcery.com>
  17
  18         * armd-dis.c (arm_opcodes): Fix rbit opcode.
  19
  20 2006-07-18  H.J. Lu  <hongjiu.lu@intel.com>
  21
  22         * i386-dis.c (grps): Change "sldtQ", "strQ" and "smswQ" to
  23         "sldt", "str" and "smsw".
  24
  25 2006-07-15  H.J. Lu  <hongjiu.lu@intel.com>
  26
  27         PR binutils/2829
  28         * i386-dis.c (GRP11_C6): NEW.
  29         (GRP11_C7): Likewise.
  30         (GRP12): Updated.
  31         (GRP13): Likewise.
  32         (GRP14): Likewise.
  33         (GRP15): Likewise.
  34         (GRP16): Likewise.
  35         (GRPAMD): Likewise.
  36         (GRPPADLCK1): Likewise.
  37         (GRPPADLCK2): Likewise.
  38         (dis386): Use GRP11_C6 and GRP11_C7 for entres 0xc6 and 0xc7,
  39         respectively.
  40         (grps): Add entries for GRP11_C6 and GRP11_C7.
  41
  42 2006-07-10 Dwarakanath Rajagopal        <dwarak.rajagopal@amd.com>
  43            Michael Meissner             <michael.meissner@amd.com>
  44
  45         * i386-dis.c (dis386): Add support for 4 operand instructions. Add
  46         support for amdfam10 SSE4a/ABM instructions. Modify all
  47         initializer macros to have additional arguments. Disallow REP
  48         prefix for non-string instructions.
  49         (print_insn): Ditto.
  50
  51
  52 2006-07-05  Julian Brown  <julian@codesourcery.com>
  53
  54         * arm-dis.c (coprocessor): Alter fmsrr disassembly syntax.
  55
  56 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
  57
  58         * i386-dis.c (dis386_twobyte): Use "nopQ" for 0x1f.
  59         (twobyte_has_modrm): Set 1 for 0x1f.
  60
  61 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
  62
  63         * i386-dis.c (NOP_Fixup): Removed.
  64         (NOP_Fixup1): New.
  65         (NOP_Fixup2): Likewise.
  66         (dis386): Use NOP_Fixup1 and NOP_Fixup2 on 0x90.
  67
  68 2006-06-12  Julian Brown  <julian@codesourcery.com>
  69
  70         * arm-dis.c (print_insn_neon): Disassemble 32-bit immediates as signed
  71         on 64-bit hosts.
  72
  73 2006-06-10  H.J. Lu  <hongjiu.lu@intel.com>
  74
  75         * i386.c (GRP10): Renamed to ...
  76         (GRP12): This.
  77         (GRP11): Renamed to ...
  78         (GRP13): This.
  79         (GRP12): Renamed to ...
  80         (GRP14): This.
  81         (GRP13): Renamed to ...
  82         (GRP15): This.
  83         (GRP14): Renamed to ...
  84         (GRP16): This.
  85         (dis386_twobyte): Updated.
  86         (grps): Likewise.
  87
  88 2006-06-09  Nick Clifton  <nickc@redhat.com>
  89
  90         * po/fi.po: Updated Finnish translation.
  91
  92 2006-06-07  Joseph S. Myers  <joseph@codesourcery.com>
  93
  94         * po/Make-in (pdf, ps): New dummy targets.
  95
  96 2006-06-06  Paul Brook  <paul@codesourcery.com>
  97
  98         * arm-dis.c (coprocessor_opcodes): Add %c to unconditional arm
  99         instructions.
 100         (neon_opcodes): Add conditional execution specifiers.
 101         (thumb_opcodes): Ditto.
 102         (thumb32_opcodes): Ditto.
 103         (arm_conditional): Change 0xe to "al" and add "" to end.
 104         (ifthen_state, ifthen_next_state, ifthen_address): New.
 105         (IFTHEN_COND): Define.
 106         (print_insn_coprocessor, print_insn_neon): Print thumb conditions.
 107         (print_insn_arm): Change %c to use new values of arm_conditional.
 108         (print_insn_thumb16): Print thumb conditions.  Add %I.
 109         (print_insn_thumb32): Print thumb conditions.
 110         (find_ifthen_state): New function.
 111         (print_insn): Track IT block state.
 112
 113 2006-06-06  Ben Elliston  <bje@au.ibm.com>
 114             Anton Blanchard  <anton@samba.org>
 115             Peter Bergner  <bergner@vnet.ibm.com>
 116
 117         * ppc-dis.c (powerpc_dialect): Handle power6 option.
 118         (print_ppc_disassembler_options): Mention power6.
 119
 120 2006-06-06  Thiemo Seufer  <ths@mips.com>
 121             Chao-ying Fu  <fu@mips.com>
 122
 123         * mips-dis.c: Disassemble DSP64 instructions for MIPS64R2.
 124         * mips-opc.c: Add DSP64 instructions.
 125
 126 2006-06-06  Alan Modra  <amodra@bigpond.net.au>
 127
 128         * m68hc11-dis.c (print_insn): Warning fix.
 129
 130 2006-06-05  Daniel Jacobowitz  <dan@codesourcery.com>
 131
 132         * po/Make-in (top_builddir): Define.
 133
 134 2006-06-05  Alan Modra  <amodra@bigpond.net.au>
 135
 136         * Makefile.am: Run "make dep-am".
 137         * Makefile.in: Regenerate.
 138         * config.in: Regenerate.
 139
 140 2006-05-31  Daniel Jacobowitz  <dan@codesourcery.com>
 141
 142         * Makefile.am (INCLUDES): Use @INCINTL@.
 143         * acinclude.m4: Include new gettext macros.
 144         * configure.in: Use ZW_GNU_GETTEXT_SISTER_DIR and AM_PO_SUBDIRS.
 145         Remove local code for po/Makefile.
 146         * Makefile.in, aclocal.m4, configure: Regenerated.
 147
 148 2006-05-30  Nick Clifton  <nickc@redhat.com>
 149
 150         * po/es.po: Updated Spanish translation.
 151
 152 2006-05-25  Richard Sandiford  <richard@codesourcery.com>
 153
 154         * m68k-opc.c (m68k_opcodes): Fix the masks of the Coldfire fmovemd
 155         and fmovem entries.  Put register list entries before immediate
 156         mask entries.  Use "l" rather than "L" in the fmovem entries.
 157         * m68k-dis.c (match_insn_m68k): Remove the PRIV argument and work it
 158         out from INFO.
 159         (m68k_scan_mask): New function, split out from...
 160         (print_insn_m68k): ...here.  If no architecture has been set,
 161         first try printing an m680x0 instruction, then try a Coldfire one.
 162
 163 2006-05-24  Nick Clifton  <nickc@redhat.com>
 164
 165         * po/ga.po: Updated Irish translation.
 166
 167 2006-05-22  Nick Clifton  <nickc@redhat.com>
 168
 169         * crx-dis.c (EXTRACT): Make macro work on 64-bit hosts.
 170
 171 2006-05-22  Nick Clifton  <nickc@redhat.com>
 172
 173         * po/nl.po: Updated translation.
 174
 175 2006-05-18  Alan Modra  <amodra@bigpond.net.au>
 176
 177         * avr-dis.c: Formatting fix.
 178
 179 2006-05-14  Thiemo Seufer  <ths@mips.com>
 180
 181         * mips16-opc.c (I1, I32, I64): New shortcut defines.
 182         (mips16_opcodes): Change membership of instructions to their
 183         lowest baseline ISA.
 184
 185 2006-05-09  H.J. Lu  <hongjiu.lu@intel.com>
 186
 187         * i386-dis.c (grps): Update sgdt/sidt for 64bit.
 188
 189 2006-05-05  Julian Brown  <julian@codesourcery.com>
 190
 191         * arm-dis.c (coprocessor_opcodes): Don't interpret fldmx/fstmx as
 192         vldm/vstm.
 193
 194 2006-05-05  Thiemo Seufer  <ths@mips.com>
 195             David Ung  <davidu@mips.com>
 196
 197         * mips-opc.c: Add macro for cache instruction.
 198
 199 2006-05-04  Thiemo Seufer  <ths@mips.com>
 200             Nigel Stephens  <nigel@mips.com>
 201             David Ung  <davidu@mips.com>
 202
 203         * mips-dis.c (mips_arch_choices): Add smartmips instruction
 204         decoding to MIPS32 and MIPS32R2.  Limit DSP decoding to release
 205         2 ISAs.  Add MIPS3D decoding to MIPS32R2.  Add MT decoding to
 206         MIPS64R2.
 207         * mips-opc.c: fix random typos in comments.
 208         (INSN_SMARTMIPS): New defines.
 209         (mips_builtin_opcodes): Add paired single support for MIPS32R2.
 210         Move bc3f, bc3fl, bc3t, bc3tl downwards.  Move flushi, flushd,
 211         flushid, wb upwards.  Move cfc3, ctc3 downwards.  Rework the
 212         FP_S and FP_D flags to denote single and double register
 213         accesses separately.  Move dmfc3, dmtc3, mfc3, mtc3 downwards.
 214         Allow jr.hb and jalr.hb for release 1 ISAs.  Allow luxc1, suxc1
 215         for MIPS32R2.  Add SmartMIPS instructions.  Add two-argument
 216         variants of bc2f, bc2fl, bc2t, bc2tl.  Add mfhc2, mthc2 to
 217         release 2 ISAs.
 218         * mips16-opc.c (mips16_opcodes): Add sdbbp instruction.
 219
 220 2006-05-03  Thiemo Seufer  <ths@mips.com>
 221
 222         * mips-opc.c (mips_builtin_opcodes): Fix mftr argument order.
 223
 224 2006-05-02  Thiemo Seufer  <ths@mips.com>
 225             Nigel Stephens  <nigel@mips.com>
 226             David Ung  <davidu@mips.com>
 227
 228         * mips-dis.c (print_insn_args): Force mips16 to odd addresses.
 229         (print_mips16_insn_arg): Force mips16 to odd addresses.
 230
 231 2006-04-30  Thiemo Seufer  <ths@mips.com>
 232             David Ung  <davidu@mips.com>
 233
 234         * mips-opc.c (mips_builtin_opcodes): Add udi instructions
 235         "udi0" to "udi15".
 236         * mips-dis.c (print_insn_args): Adds udi argument handling.
 237
 238 2006-04-28  James E Wilson  <wilson@specifix.com>
 239
 240         * m68k-dis.c (match_insn_m68k): Restore fprintf_func before printing
 241         error message.
 242
 243 2006-04-28  Thiemo Seufer  <ths@mips.com>
 244             David Ung  <davidu@mips.com>
 245             Nigel Stephens  <nigel@mips.com>
 246
 247         * mips-dis.c (mips_cp0sel_names_mips3264r2): Add MT register
 248         names.
 249
 250 2006-04-28  Thiemo Seufer  <ths@mips.com>
 251             Nigel Stephens  <nigel@mips.com>
 252             David Ung  <davidu@mips.com>
 253
 254         * mips-dis.c (print_insn_args): Add mips_opcode argument.
 255         (print_insn_mips):  Adjust print_insn_args call.
 256
 257 2006-04-28  Thiemo Seufer  <ths@mips.com>
 258             Nigel Stephens  <nigel@mips.com>
 259
 260         * mips-dis.c (print_insn_args): Print $fcc only for FP
 261         instructions, use $cc elsewise.
 262
 263 2006-04-28  Thiemo Seufer  <ths@mips.com>
 264             Nigel Stephens  <nigel@mips.com>
 265
 266         * opcodes/mips-dis.c (mips16_to_32_reg_map, mips16_reg_names):
 267         Map MIPS16 registers to O32 names.
 268         (print_mips16_insn_arg): Use mips16_reg_names.
 269
 270 2006-04-26  Julian Brown  <julian@codesourcery.com>
 271
 272         * arm-dis.c (print_insn_neon): Disassemble floating-point constant
 273         VMOV.
 274
 275 2006-04-26  Nathan Sidwell  <nathan@codesourcery.com>
 276             Julian Brown  <julian@codesourcery.com>
 277
 278         * opcodes/arm-dis.c (coprocessor_opcodes): Add %A, %B, %k, convert
 279         %<code>[zy] into %[zy]<code>.  Expand meaning of %<bitfield>['`?].
 280         Add unified load/store instruction names.
 281         (neon_opcode_table): New.
 282         (arm_opcodes): Expand meaning of %<bitfield>['`?].
 283         (arm_decode_bitfield): New.
 284         (print_insn_coprocessor): Add pc argument. Add %A & %B specifiers.
 285         Use arm_decode_bitfield and adjust numeric specifiers. Adjust %z & %y.
 286         (print_insn_neon): New.
 287         (print_insn_arm): Adjust print_insn_coprocessor call. Call
 288         print_insn_neon. Use arm_decode_bitfield and adjust numeric specifiers.
 289         (print_insn_thumb32): Likewise.
 290
 291 2006-04-19  Alan Modra  <amodra@bigpond.net.au>
 292
 293         * Makefile.am: Run "make dep-am".
 294         * Makefile.in: Regenerate.
 295
 296 2006-04-19  Alan Modra  <amodra@bigpond.net.au>
 297
 298         * avr-dis.c (avr_operand): Warning fix.
 299
 300         * configure: Regenerate.
 301
 302 2006-04-16  Daniel Jacobowitz  <dan@codesourcery.com>
 303
 304         * po/POTFILES.in: Regenerated.
 305
 306 2006-04-12   Hochstein  <hochstein@algo.informatik.tu-darmstadt.de>
 307
 308         PR binutils/2454
 309         * avr-dis.c (avr_operand): Arrange for a comment to appear before
 310         the symolic form of an address, so that the output of objdump -d
 311         can be reassembled.
 312
 313 2006-04-10  DJ Delorie  <dj@redhat.com>
 314
 315         * m32c-asm.c: Regenerate.
 316
 317 2006-04-06  Carlos O'Donell  <carlos@codesourcery.com>
 318
 319         * Makefile.am: Add install-html target.
 320         * Makefile.in: Regenerate.
 321
 322 2006-04-06  Nick Clifton  <nickc@redhat.com>
 323
 324         * po/vi/po: Updated Vietnamese translation.
 325
 326 2006-03-31  Paul Koning  <ni1d@arrl.net>
 327
 328         * pdp11-opc.c (pdp11_opcodes): Fix opcode for SEC instruction.
 329
 330 2006-03-16  Bernd Schmidt  <bernd.schmidt@analog.com>
 331
 332         * bfin-dis.c (decode_dsp32shiftimm_0): Simplify and correct the
 333         logic to identify halfword shifts.
 334
 335 2006-03-16  Paul Brook  <paul@codesourcery.com>
 336
 337         * arm-dis.c (arm_opcodes): Rename swi to svc.
 338         (thumb_opcodes): Ditto.
 339
 340 2006-03-13  DJ Delorie  <dj@redhat.com>
 341
 342         * m32c-asm.c: Regenerate.
 343         * m32c-desc.c: Likewise.
 344         * m32c-desc.h: Likewise.
 345         * m32c-dis.c: Likewise.
 346         * m32c-ibld.c: Likewise.
 347         * m32c-opc.c: Likewise.
 348         * m32c-opc.h: Likewise.
 349
 350 2006-03-10  DJ Delorie  <dj@redhat.com>
 351
 352         * m32c-desc.c: Regenerate with mul.l, mulu.l.
 353         * m32c-opc.c: Likewise.
 354         * m32c-opc.h: Likewise.
 355
 356
 357 2006-03-09  Nick Clifton  <nickc@redhat.com>
 358
 359         * po/sv.po: Updated Swedish translation.
 360
 361 2006-03-07  H.J. Lu  <hongjiu.lu@intel.com>
 362
 363         PR binutils/2428
 364         * i386-dis.c (REP_Fixup): New function.
 365         (AL): Remove duplicate.
 366         (Xbr): New.
 367         (Xvr): Likewise.
 368         (Ybr): Likewise.
 369         (Yvr): Likewise.
 370         (indirDXr): Likewise.
 371         (ALr): Likewise.
 372         (eAXr): Likewise.
 373         (dis386): Updated entries of ins, outs, movs, lods and stos.
 374
 375 2006-03-05  Nick Clifton  <nickc@redhat.com>
 376
 377         * cgen-ibld.in (insert_normal): Cope with attempts to insert a
 378         signed 32-bit value into an unsigned 32-bit field when the host is
 379         a 64-bit machine.
 380         * fr30-ibld.c: Regenerate.
 381         * frv-ibld.c: Regenerate.
 382         * ip2k-ibld.c: Regenerate.
 383         * iq2000-asm.c: Regenerate.
 384         * iq2000-ibld.c: Regenerate.
 385         * m32c-ibld.c: Regenerate.
 386         * m32r-ibld.c: Regenerate.
 387         * openrisc-ibld.c: Regenerate.
 388         * xc16x-ibld.c: Regenerate.
 389         * xstormy16-ibld.c: Regenerate.
 390
 391 2006-03-03 Shrirang Khisti <shrirangk@kpitcummins.com)
 392
 393         * xc16x-asm.c: Regenerate.
 394         * xc16x-dis.c: Regenerate.
 395
 396 2006-02-27  Carlos O'Donell  <carlos@codesourcery.com>
 397
 398         * po/Make-in: Add html target.
 399
 400 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
 401
 402         * i386-dis.c (IS_3BYTE_OPCODE): New for 3-byte opcodes used by
 403         Intel Merom New Instructions.
 404         (THREE_BYTE_0): Likewise.
 405         (THREE_BYTE_1): Likewise.
 406         (three_byte_table): Likewise.
 407         (dis386_twobyte): Use THREE_BYTE_0 for entry 0x38. Use
 408         THREE_BYTE_1 for entry 0x3a.
 409         (twobyte_has_modrm): Updated.
 410         (twobyte_uses_SSE_prefix): Likewise.
 411         (print_insn): Handle 3-byte opcodes used by Intel Merom New
 412         Instructions.
 413
 414 2006-02-24  David S. Miller  <davem@sunset.davemloft.net>
 415
 416         * sparc-dis.c (v9_priv_reg_names): Add "gl" entry.
 417         (v9_hpriv_reg_names): New table.
 418         (print_insn_sparc): Allow values up to 16 for '?' and '!'.
 419         New cases '$' and '%' for read/write hyperprivileged register.
 420         * sparc-opc.c (sparc_opcodes): Add new entries for UA2005
 421         window handling and rdhpr/wrhpr instructions.
 422
 423 2006-02-24  DJ Delorie  <dj@redhat.com>
 424
 425         * m32c-desc.c: Regenerate with linker relaxation attributes.
 426         * m32c-desc.h: Likewise.
 427         * m32c-dis.c: Likewise.
 428         * m32c-opc.c: Likewise.
 429
 430 2006-02-24  Paul Brook  <paul@codesourcery.com>
 431
 432         * arm-dis.c (arm_opcodes): Add V7 instructions.
 433         (thumb32_opcodes): Ditto.  Handle V7M MSR/MRS variants.
 434         (print_arm_address): New function.
 435         (print_insn_arm): Use it.  Add 'P' and 'U' cases.
 436         (psr_name): New function.
 437         (print_insn_thumb32): Add 'U', 'C' and 'D' cases.
 438
 439 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
 440
 441         * ia64-opc-i.c (bXc): New.
 442         (mXc): Likewise.
 443         (OpX2TaTbYaXcC): Likewise.
 444         (TF). Likewise.
 445         (TFCM). Likewise.
 446         (ia64_opcodes_i): Add instructions for tf.
 447
 448         * ia64-opc.h (IMMU5b): New.
 449
 450         * ia64-asmtab.c: Regenerated.
 451
 452 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
 453
 454         * ia64-gen.c: Update copyright years.
 455         * ia64-opc-b.c: Likewise.
 456
 457 2006-02-22  H.J. Lu  <hongjiu.lu@intel.com>
 458
 459         * ia64-gen.c (lookup_regindex): Handle ".vm".
 460         (print_dependency_table): Handle '\"'.
 461
 462         * ia64-ic.tbl: Updated from SDM 2.2.
 463         * ia64-raw.tbl: Likewise.
 464         * ia64-waw.tbl: Likewise.
 465         * ia64-asmtab.c: Regenerated.
 466
 467         * ia64-opc-b.c (ia64_opcodes_b): Add vmsw.0 and vmsw.1.
 468
 469 2006-02-17  Shrirang Khisti  <shrirangk@kpitcummins.com>
 470             Anil Paranjape   <anilp1@kpitcummins.com>
 471             Shilin Shakti    <shilins@kpitcummins.com>
 472
 473         * xc16x-desc.h: New file
 474         * xc16x-desc.c: New file
 475         * xc16x-opc.h: New file
 476         * xc16x-opc.c: New file
 477         * xc16x-ibld.c: New file
 478         * xc16x-asm.c: New file
 479         * xc16x-dis.c: New file
 480         * Makefile.am: Entries for xc16x
 481         * Makefile.in: Regenerate
 482         * cofigure.in: Add xc16x target information.
 483         * configure: Regenerate.
 484         * disassemble.c: Add xc16x target information.
 485
 486 2006-02-11  H.J. Lu  <hongjiu.lu@intel.com>
 487
 488         * i386-dis.c (dis386_twobyte): Use "movZ" for debug register
 489         moves.
 490
 491 2006-02-11  H.J. Lu  <hongjiu.lu@intel.com>
 492
 493         * i386-dis.c ('Z'): Add a new macro.
 494         (dis386_twobyte): Use "movZ" for control register moves.
 495
 496 2006-02-10  Nick Clifton  <nickc@redhat.com>
 497
 498         * iq2000-asm.c: Regenerate.
 499
 500 2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
 501
 502         * m68k-dis.c (print_insn_m68k): Use bfd_m68k_mach_to_features.
 503
 504 2006-01-26  David Ung  <davidu@mips.com>
 505
 506         * mips-opc.c: Add I33 masks to these MIPS32R2 instructions: prefx,
 507         ceil.l.d, ceil.l.s, cvt.d.l, cvt.l.d, cvt.l.s, cvt.s.l, floor.l.d,
 508         floor.l.s, ldxc1, lwxc1, madd.d, madd.s, msub.d, msub.s, nmadd.d,
 509         nmadd.s, nmsub.d, nmsub.s, recip.d, recip.s, round.l.d, rsqrt.d,
 510         rsqrt.s, sdxc1, swxc1, trunc.l.d, trunc.l.s.
 511
 512 2006-01-18  Arnold Metselaar  <arnoldm@sourceware.org>
 513
 514         * z80-dis.c (struct buffer, prt_d, prt_d_n, arit_d, ld_r_d,
 515         ld_d_r, pref_xd_cb): Use signed char to hold data to be
 516         disassembled.
 517         * z80-dis.c (TXTSIZ): Increase buffer size to 24, this fixes
 518         buffer overflows when disassembling instructions like
 519         ld (ix+123),0x23
 520         * z80-dis.c (opc_ind, pref_xd_cb): Suppress '+' in an indexed
 521         operand, if the offset is negative.
 522
 523 2006-01-17  Arnold Metselaar  <arnoldm@sourceware.org>
 524
 525         * z80-dis.c (struct buffer, prt_d, prt_d_n, pref_xd_cb): Use
 526         unsigned char to hold data to be disassembled.
 527
 528 2006-01-17  Andreas Schwab  <schwab@suse.de>
 529
 530         PR binutils/1486
 531         * disassemble.c (disassemble_init_for_target): Set
 532         disassembler_needs_relocs for bfd_arch_arm.
 533
 534 2006-01-16  Paul Brook  <paul@codesourcery.com>
 535
 536         * m68k-opc.c (m68k_opcodes): Fix opcodes for ColdFire f?abss,
 537         f?add?, and f?sub? instructions.
 538
 539 2006-01-16  Nick Clifton  <nickc@redhat.com>
 540
 541         * po/zh_CN.po: New Chinese (simplified) translation.
 542         * configure.in (ALL_LINGUAS): Add "zh_CH".
 543         * configure: Regenerate.
 544
 545 2006-01-05  Paul Brook  <paul@codesourcery.com>
 546
 547         * m68k-opc.c (m68k_opcodes): Add missing ColdFire fdsqrtd entry.
 548
 549 2006-01-06  DJ Delorie  <dj@redhat.com>
 550
 551         * m32c-desc.c: Regenerate.
 552         * m32c-opc.c: Regenerate.
 553         * m32c-opc.h: Regenerate.
 554
 555 2006-01-03  DJ Delorie  <dj@redhat.com>
 556
 557         * cgen-ibld.in (extract_normal): Avoid memory range errors.
 558         * m32c-ibld.c: Regenerated.
 559
 560 For older changes see ChangeLog-2005
 561 \f
 562 Local Variables:
 563 mode: change-log
 564 left-margin: 8
 565 fill-column: 74
 566 version-control: never
 567 End: