opcodes/ChangeLog

   1 2021-06-22  Andrew Burgess  <andrew.burgess@embecosm.com>
   2
   3         * cgen-dis.c (count_decodable_bits): Use __builtin_popcount when
   4         available.
   5
   6 2021-06-22  Alan Modra  <amodra@gmail.com>
   7
   8         * pj-dis.c (print_insn_pj): Don't print trailing tab.  Do
   9         print separator for pcrel insns.
  10
  11 2021-06-19  Alan Modra  <amodra@gmail.com>
  12
  13         * vax-dis.c (print_insn_vax): Avoid pointer overflow.
  14
  15 2021-06-19  Alan Modra  <amodra@gmail.com>
  16
  17         * tic30-dis.c (get_register_operand): Don't ask strncpy to fill
  18         entire buffer.
  19
  20 2021-06-17  Alan Modra  <amodra@gmail.com>
  21
  22         * ppc-opc.c (powerpc_opcodes): Move cell db*cyc to proper location
  23         in table.
  24
  25 2021-06-03  Alan Modra  <amodra@gmail.com>
  26
  27         PR 1202
  28         * mcore-dis.c (print_insn_mcore): Correct loopt disassembly.
  29         Use unsigned int for inst.
  30
  31 2021-06-02  Shahab Vahedi  <shahab@synopsys.com>
  32
  33         * arc-dis.c (arc_option_arg_t): New enumeration.
  34         (arc_options): New variable.
  35         (disassembler_options_arc): New function.
  36         (print_arc_disassembler_options): Reimplement in terms of
  37         "disassembler_options_arc".
  38
  39 2021-05-29  Alan Modra  <amodra@gmail.com>
  40
  41         * ppc-dis.c (lookup_powerpc): Test deprecated field when -Many.
  42         Don't special case PPC_OPCODE_RAW.
  43         (lookup_prefix): Likewise.
  44         (lookup_vle, lookup_spe2): Similarly.  Add dialect parameter and..
  45         (print_insn_powerpc): ..update caller.
  46         * ppc-opc.c (EXT): Define.
  47         (powerpc_opcodes): Mark extended mnemonics with EXT.
  48         (prefix_opcodes, vle_opcodes): Likewise.
  49         (XISEL, XISEL_MASK): Add cr field and simplify.
  50         (powerpc_opcodes): Use XISEL with extended isel mnemonics and sort
  51         all isel variants to where the base mnemonic belongs.  Sort dstt,
  52         dststt and dssall.
  53
  54 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
  55
  56         * mips-opc.c (mips_builtin_opcodes): Reorder legacy COP0, COP2,
  57         COP3 opcode instructions.
  58
  59 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
  60
  61         * mips-opc.c (mips_builtin_opcodes): Update exclusion list for
  62         "ldc2", "ldc3", "lwc0", "lwc2", "lwc3", "sdc2", "sdc3", "swc0",
  63         "swc2", "swc3", "cfc0", "ctc0", "bc2f", "bc2fl", "bc2t",
  64         "bc2tl", "cfc2", "ctc2", "dmfc2", "dmtc2", "mfc2", "mtc2",
  65         "bc3f", "bc3fl", "bc3t", "bc3tl", "cfc3", "ctc3", "mfc3",
  66         "mtc3", "bc0f", "bc0fl", "bc0t", "bc0tl", "rfe", "c2", "c3",
  67         "cop2", and "cop3" entries.
  68
  69 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
  70
  71         * mips-opc.c (mips_builtin_opcodes): Remove "dmfc3" and "dmtc3"
  72         entries and associated comments.
  73
  74 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
  75
  76         * mips-opc.c (mips_builtin_opcodes): Move the "rfe" entry ahead
  77         of "c0".
  78
  79 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
  80
  81         * mips-dis.c (mips_cp1_names_mips): New variable.
  82         (mips_arch_choices): Use it rather than `mips_cp1_names_numeric'
  83         for "r3000", "r4000", "r4010", "vr4100", "vr4111", "vr4120",
  84         "r4300", "r4400", "r4600", "r4650", "r5000", "vr5400", "vr5500",
  85         "r5900", "r6000", "rm7000", "rm9000", "r8000", "r10000",
  86         "r12000", "r14000", "r16000", "mips5", "loongson2e", and
  87         "loongson2f".
  88
  89 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
  90
  91         * mips-dis.c (print_reg) <OP_REG_COPRO>: Move control register
  92         handling code over to...
  93         <OP_REG_CONTROL>: ... this new case.
  94         * mips-opc.c (decode_mips_operand) <'g', 'y'>: New cases.
  95         (mips_builtin_opcodes): Update "cfc1", "ctc1", "cttc1", "cttc2",
  96         "cfc0", "ctc0", "cfc2", "ctc2", "cfc3", and "ctc3" entries
  97         replacing the `G' operand code with `g'.  Update "cftc1" and
  98         "cftc2" entries replacing the `E' operand code with `y'.
  99         * micromips-opc.c (decode_micromips_operand) <'g'>: New case.
 100         (micromips_opcodes): Update "cfc1", "cfc2", "ctc1", and "ctc2"
 101         entries replacing the `G' operand code with `g'.
 102
 103 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 104
 105         * mips-dis.c (mips_cp0_names_r3900): New variable.
 106         (mips_arch_choices): Use it rather than `mips_cp0_names_numeric'
 107         for "r3900".
 108
 109 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 110
 111         * mips-opc.c (mips_builtin_opcodes): Switch "cttc2", "mttc2",
 112         and "mtthc2" to using the `G' rather than `g' operand code for
 113         the coprocessor control register referred.
 114
 115 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 116
 117         * micromips-opc.c (micromips_opcodes): Swap the two "dmtc1"
 118         entries with each other.
 119
 120 2021-05-27  Peter Bergner  <bergner@linux.ibm.com>
 121
 122         * ppc-opc.c (powerpc_opcodes) <xxmr, xxlnot>: New extended mnemonics.
 123
 124 2021-05-25  Alan Modra  <amodra@gmail.com>
 125
 126         * cris-desc.c: Regenerate.
 127         * cris-desc.h: Regenerate.
 128         * cris-opc.h: Regenerate.
 129         * po/POTFILES.in: Regenerate.
 130
 131 2021-05-24  Mike Frysinger  <vapier@gentoo.org>
 132
 133         * Makefile.am (HFILES): Add cris-desc.h & cris-opc.h.
 134         (TARGET_LIBOPCODES_CFILES): Add cris-desc.c.
 135         (CGEN_CPUS): Add cris.
 136         (CRIS_DEPS): Define.
 137         (stamp-cris): New rule.
 138         * cgen.sh: Handle desc action.
 139         * configure.ac (bfd_cris_arch): Add cris-desc.lo.
 140         * Makefile.in, configure: Regenerate.
 141
 142 2021-05-18  Job Noorman  <mtvec@pm.me>
 143
 144         PR 27814
 145         * riscv-dis.c (riscv_get_disassembler): Get elf attributes only for
 146         the elf objects.
 147
 148 2021-05-17  Alex Coplan  <alex.coplan@arm.com>
 149
 150         * arm-dis.c (mve_opcodes): Fix disassembly of
 151         MVE_VMOV2_GP_TO_VEC_LANE when idx == 1.
 152         (is_mve_encoding_conflict): MVE vector loads should not match
 153         when P = W = 0.
 154         (is_mve_unpredictable): It's not unpredictable to use the same
 155         source register twice (for MVE_VMOV2_GP_TO_VEC_LANE).
 156
 157 2021-05-11  Nick Clifton  <nickc@redhat.com>
 158
 159         PR 27840
 160         * tic30-dis.c (print_insn_tic30): Prevent attempts to read beyond
 161         the end of the code buffer.
 162
 163 2021-05-06  Stafford Horne  <shorne@gmail.com>
 164
 165         PR 21464
 166         * or1k-asm.c: Regenerate.
 167
 168 2021-05-01  Max Filippov  <jcmvbkbc@gmail.com>
 169
 170         * xtensa-dis.c (print_insn_xtensa): Fill in info->insn_type and
 171         info->insn_info_valid.
 172
 173 2021-04-26  Jan Beulich  <jbeulich@suse.com>
 174
 175         * i386-opc.tbl (lea): Add Optimize.
 176         * opcodes/i386-tbl.h: Re-generate.
 177
 178 2020-04-23  Max Filippov  <jcmvbkbc@gmail.com>
 179
 180         * xtensa-dis.c (print_xtensa_operand): For PC-relative operand
 181         of l32r fetch and display referenced literal value.
 182
 183 2021-04-23  Max Filippov  <jcmvbkbc@gmail.com>
 184
 185         * xtensa-dis.c (print_insn_xtensa): Set info->bytes_per_chunk
 186         to 4 for literal disassembly.
 187
 188 2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 189
 190         * aarch64-opc.c: Add new registers (RPAOS, RPALOS, PAALLOS, PAALL) support
 191         for TLBI instruction.
 192
 193 2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 194
 195         * aarch64-opc.c: Add new register (CIPAPA, CIGDPAPA) support for
 196         DC instruction.
 197
 198 2021-04-19  Jan Beulich  <jbeulich@suse.com>
 199
 200         * aarch64-asm.c (encode_asimd_fcvt): Add initializer for
 201         "qualifier".
 202         (convert_mov_to_movewide): Add initializer for "value".
 203
 204 2021-04-16  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 205
 206         * aarch64-opc.c: Add RME system registers.
 207
 208 2021-04-16  Lifang Xia <lifang_xia@c-sky.com>
 209
 210         * riscv-opc.c (riscv_opcodes): New insn alias for addi. Compress
 211         "addi d,CV,z" to "c.mv d,CV".
 212
 213 2021-04-12  Alan Modra  <amodra@gmail.com>
 214
 215         * configure.ac (--enable-checking): Add support.
 216         * config.in: Regenerate.
 217         * configure: Regenerate.
 218
 219 2021-04-09  Tejas Belagod  <tejas.belagod@arm.com>
 220
 221         * aarch64-tbl.h (struct aarch64_opcode aarch64_opcode_table): Reclassify
 222         LD64/ST64 instructions to lse_atomic instead of ldstexcl.
 223
 224 2021-04-09  Alan Modra  <amodra@gmail.com>
 225
 226         * ppc-dis.c (struct dis_private): Add "special".
 227         (POWERPC_DIALECT): Delete.  Replace uses with..
 228         (private_data): ..this.  New inline function.
 229         (disassemble_init_powerpc): Init "special" names.
 230         (skip_optional_operands): Add is_pcrel arg, set when detecting R
 231         field of prefix instructions.
 232         (bsearch_reloc, print_got_plt): New functions.
 233         (print_insn_powerpc): For pcrel instructions, print target address
 234         and symbol if known, and decode plt and got loads too.
 235
 236 2021-04-08  Alan Modra  <amodra@gmail.com>
 237
 238         PR 27684
 239         * ppc-opc.c (powerpc_opcodes): Correct usprg typos, add mfpir.
 240
 241 2021-04-08  Alan Modra  <amodra@gmail.com>
 242
 243         PR 27676
 244         * ppc-opc.c (DCBT_EO): Move earlier.
 245         (insert_thct, extract_thct, insert_thds, extract_thds): New functions.
 246         (powerpc_operands): Add THCT and THDS entries.
 247         (powerpc_opcodes): Add dcbtstct, dcbtstds, dcbna, dcbtct, dcbtds.
 248
 249 2021-04-06  Alan Modra  <amodra@gmail.com>
 250
 251         * dis-buf.c (generic_symbol_at_address): Return symbol* NULL.
 252         * s12z-dis.c (decode_possible_symbol): Use symbol returned from
 253         symbol_at_address_func.
 254
 255 2021-04-05  Alan Modra  <amodra@gmail.com>
 256
 257         * configure.ac: Don't check for limits.h, string.h, strings.h or
 258         stdlib.h.
 259         (AC_ISC_POSIX): Don't invoke.
 260         * sysdep.h: Include stdlib.h and string.h unconditionally.
 261         * i386-opc.h: Include limits.h unconditionally.
 262         * wasm32-dis.c: Likewise.
 263         * cgen-opc.c: Don't include alloca-conf.h.
 264         * config.in: Regenerate.
 265         * configure: Regenerate.
 266
 267 2021-04-01  Martin Liska  <mliska@suse.cz>
 268
 269         * arm-dis.c (strneq): Remove strneq and use startswith.
 270         * cr16-dis.c (print_insn_cr16): Likewise.
 271         * score-dis.c (streq): Likewise.
 272         (strneq): Likewise.
 273         * score7-dis.c (strneq): Likewise.
 274
 275 2021-04-01  Alan Modra  <amodra@gmail.com>
 276
 277         PR 27675
 278         * ppc-opc.c (powerpc_opcodes): Add mfummcr2 and mfmmcr2.
 279
 280 2021-03-31  Alan Modra  <amodra@gmail.com>
 281
 282         * sysdep.h (POISON_BFD_BOOLEAN): Define.
 283         * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h,
 284         * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h,
 285         * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c,
 286         * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c,
 287         * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c,
 288         * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c,
 289         * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c,
 290         * microblaze-dis.h, * micromips-opc.c, * mips-dis.c,
 291         * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c,
 292         * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c,
 293         * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c,
 294         * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c,
 295         * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false,
 296         and TRUE with true throughout.
 297
 298 2021-03-31  Alan Modra  <amodra@gmail.com>
 299
 300         * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h.
 301         * aarch64-dis.h: Likewise.
 302         * aarch64-opc.c: Likewise.
 303         * avr-dis.c: Likewise.
 304         * csky-dis.c: Likewise.
 305         * nds32-asm.c: Likewise.
 306         * nds32-dis.c: Likewise.
 307         * nfp-dis.c: Likewise.
 308         * riscv-dis.c: Likewise.
 309         * s12z-dis.c: Likewise.
 310         * wasm32-dis.c: Likewise.
 311
 312 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 313
 314         * i386-opc.c (cs, ds, ss, es, fs, gs): Delete.
 315         (i386_seg_prefixes): New.
 316         * i386-opc.h (cs, ds, ss, es, fs, gs): Delete.
 317         (i386_seg_prefixes): Declare.
 318
 319 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 320
 321         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Delete.
 322
 323 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 324
 325         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Adjust values.
 326         * i386-reg.tbl (st): Move down.
 327         (st(0)): Delete. Extend comment.
 328         * i386-tbl.h: Re-generate.
 329
 330 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 331
 332         * i386-opc.tbl (movq, movabs): Move next to mov counterparts.
 333         (cmpsd): Move next to cmps.
 334         (movsd): Move next to movs.
 335         (cmpxchg16b): Move to separate section.
 336         (fisttp, fisttpll): Likewise.
 337         (monitor, mwait): Likewise.
 338         * i386-tbl.h: Re-generate.
 339
 340 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 341
 342         * i386-opc.tbl (psadbw): Add <sse2:comm>.
 343         (vpsadbw): Add C.
 344         * i386-tbl.h: Re-generate.
 345
 346 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 347
 348         * i386-opc.tbl (mmx, sse, sse2, sse3, ssse3, sse41, sse42, aes,
 349         pclmul, gfni): New templates. Use them wherever possible. Move
 350         SSE4.1 pextrw into respective section.
 351         * i386-tbl.h: Re-generate.
 352
 353 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 354
 355         * i386-gen.c (output_i386_opcode): Widen type of "opcode". Use
 356         strtoull(). Bump upper loop bound. Widen masks. Sanity check
 357         "length".
 358         * i386-opc.tbl (Prefix_0X66, Prefix_0XF2, Prefix_0XF3): Delete.
 359         Convert all of their uses to representation in opcode.
 360
 361 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 362
 363         * i386-opc.h (struct insn_template): Shrink base_opcode to 16
 364         bits. Shrink extension_opcode to 9 bits. Make it signed. Change
 365         value of None. Shrink operands to 3 bits.
 366
 367 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 368
 369         * i386-gen.c (process_i386_opcode_modifier): New parameter
 370         "space".
 371         (output_i386_opcode): New local variable "space". Adjust
 372         process_i386_opcode_modifier() invocation.
 373         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 374         invocation.
 375         * i386-tbl.h: Re-generate.
 376
 377 2021-03-29  Alan Modra  <amodra@gmail.com>
 378
 379         * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
 380         (fp_qualifier_p, get_data_pattern): Likewise.
 381         (aarch64_get_operand_modifier_from_value): Likewise.
 382         (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
 383         (operand_variant_qualifier_p): Likewise.
 384         (qualifier_value_in_range_constraint_p): Likewise.
 385         (aarch64_get_qualifier_esize): Likewise.
 386         (aarch64_get_qualifier_nelem): Likewise.
 387         (aarch64_get_qualifier_standard_value): Likewise.
 388         (get_lower_bound, get_upper_bound): Likewise.
 389         (aarch64_find_best_match, match_operands_qualifier): Likewise.
 390         (aarch64_print_operand): Likewise.
 391         * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
 392         (operand_need_sign_extension, operand_need_shift_by_two): Likewise.
 393         (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
 394         * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
 395         * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
 396         (print_insn_tic6x): Likewise.
 397
 398 2021-03-29  Alan Modra  <amodra@gmail.com>
 399
 400         * arc-dis.c (extract_operand_value): Correct NULL cast.
 401         * frv-opc.h: Regenerate.
 402
 403 2021-03-26  Jan Beulich  <jbeulich@suse.com>
 404
 405         * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to
 406         MMX form.
 407         * i386-tbl.h: Re-generate.
 408
 409 2021-03-25  Abid Qadeer  <abidh@codesourcery.com>
 410
 411         * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
 412         immediate in br.n instruction.
 413
 414 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 415
 416         * i386-dis.c (XMGatherD, VexGatherD): New.
 417         (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
 418         (print_insn): Check masking for S/G insns.
 419         (OP_E_memory): New local variable check_gather. Extend mandatory
 420         SIB check. Check register conflicts for (EVEX-encoded) gathers.
 421         Extend check for disallowed 16-bit addressing.
 422         (OP_VEX): New local variables modrm_reg and sib_index. Convert
 423         if()s to switch(). Check register conflicts for (VEX-encoded)
 424         gathers. Drop no longer reachable cases.
 425         * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
 426         vgatherdp*.
 427
 428 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 429
 430         * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
 431         zeroing-masking without masking.
 432
 433 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 434
 435         * i386-opc.tbl (invlpgb): Fix multi-operand form.
 436         (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
 437         single-operand forms as deprecated.
 438         * i386-tbl.h: Re-generate.
 439
 440 2021-03-25  Alan Modra  <amodra@gmail.com>
 441
 442         PR 27647
 443         * ppc-opc.c (XLOCB_MASK): Delete.
 444         (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
 445         XLBH_MASK.
 446         (powerpc_opcodes): Accept a BH field on all extended forms of
 447         bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
 448
 449 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 450
 451         * i386-gen.c (output_i386_opcode): Drop processing of
 452         opcode_length. Calculate length from base_opcode. Adjust prefix
 453         encoding determination.
 454         (process_i386_opcodes): Drop output of fake opcode_length.
 455         * i386-opc.h (struct insn_template): Drop opcode_length field.
 456         * i386-opc.tbl: Drop opcode length field from all templates.
 457         * i386-tbl.h: Re-generate.
 458
 459 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 460
 461         * i386-gen.c (process_i386_opcode_modifier): Return void. New
 462         parameter "prefix". Drop local variable "regular_encoding".
 463         Record prefix setting / check for consistency.
 464         (output_i386_opcode): Parse opcode_length and base_opcode
 465         earlier. Derive prefix encoding. Drop no longer applicable
 466         consistency checking. Adjust process_i386_opcode_modifier()
 467         invocation.
 468         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 469         invocation.
 470         * i386-tbl.h: Re-generate.
 471
 472 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 473
 474         * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
 475         check.
 476         * i386-opc.h (Prefix_*): Move #define-s.
 477         * i386-opc.tbl: Move pseudo prefix enumerator values to
 478         extension opcode field. Introduce pseudopfx template.
 479         * i386-tbl.h: Re-generate.
 480
 481 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 482
 483         * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
 484         comment.
 485         * i386-tbl.h: Re-generate.
 486
 487 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 488
 489         * i386-opc.h (struct insn_template): Move cpu_flags field past
 490         opcode_modifier one.
 491         * i386-tbl.h: Re-generate.
 492
 493 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 494
 495         * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
 496         * i386-opc.h (OpcodeSpace): New enumerator.
 497         (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
 498         (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
 499         SPACE_XOP09, SPACE_XOP0A): ... respectively.
 500         (struct i386_opcode_modifier): New field opcodespace. Shrink
 501         opcodeprefix field.
 502         i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
 503         SpaceXOP09, SpaceXOP0A): Define. Use them to replace
 504         OpcodePrefix uses.
 505         * i386-tbl.h: Re-generate.
 506
 507 2021-03-22  Martin Liska  <mliska@suse.cz>
 508
 509         * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
 510         * arc-dis.c (parse_option): Likewise.
 511         * arm-dis.c (parse_arm_disassembler_options): Likewise.
 512         * cris-dis.c (print_with_operands): Likewise.
 513         * h8300-dis.c (bfd_h8_disassemble): Likewise.
 514         * i386-dis.c (print_insn): Likewise.
 515         * ia64-gen.c (fetch_insn_class): Likewise.
 516         (parse_resource_users): Likewise.
 517         (in_iclass): Likewise.
 518         (lookup_specifier): Likewise.
 519         (insert_opcode_dependencies): Likewise.
 520         * mips-dis.c (parse_mips_ase_option): Likewise.
 521         (parse_mips_dis_option): Likewise.
 522         * s390-dis.c (disassemble_init_s390): Likewise.
 523         * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
 524
 525 2021-03-16  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
 526
 527         * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
 528
 529 2021-03-12  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 530
 531         * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
 532         icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
 533
 534 2021-03-12  Alan Modra  <amodra@gmail.com>
 535
 536         * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
 537
 538 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 539
 540         * i386-dis.c (OP_XMM): Re-order checks.
 541
 542 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 543
 544         * i386-dis.c (putop): Drop need_vex check when also checking
 545         vex.evex.
 546         (intel_operand_size, OP_E_memory): Drop vex.evex check when also
 547         checking vex.b.
 548
 549 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 550
 551         * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
 552         checks. Move case label past broadcast check.
 553
 554 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 555
 556         * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
 557         vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
 558         REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
 559         EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
 560         EVEX_W_0F38C7_M_0_L_2): Delete.
 561         (REG_EVEX_0F38C7_M_0_L_2): New.
 562         (intel_operand_size): Handle VEX and EVEX the same for
 563         vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
 564         vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
 565         (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
 566         vex_vsib_q_w_d_mode uses.
 567         * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
 568         0F38A1, and 0F38A3 entries.
 569         * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
 570         entry.
 571         * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
 572         * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
 573         0F38A3 entries.
 574
 575 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 576
 577         * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
 578         REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
 579         MOD_VEX_0FXOP_09_12): Rename to ...
 580         (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
 581         REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
 582         (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
 583         RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
 584         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 585         X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
 586         (reg_table): Adjust comments.
 587         (x86_64_table): Move X86_64_0F24, X86_64_0F26,
 588         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 589         X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
 590         (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
 591         (vex_len_table): Adjust opcode 0A_12 entry.
 592         (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
 593         MOD_C5_32BIT, and MOD_XOP_09_12 entries.
 594         (rm_table): Move hreset entry.
 595
 596 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 597
 598         * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
 599         EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
 600         EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
 601         EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
 602         EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
 603         (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
 604         (get_valid_dis386): Also handle 512-bit vector length when
 605         vectoring into vex_len_table[].
 606         * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
 607         0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
 608         entries.
 609         * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
 610         0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
 611         * i386-dis-evex-prefix.h: Adjust 0F7E entry.
 612         * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
 613         entries.
 614
 615 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 616
 617         * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
 618         Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
 619         EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
 620         * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
 621         entries.
 622         * i386-dis-evex-len.h (evex_len_table): Likewise.
 623         * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
 624
 625 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 626
 627         * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
 628         MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
 629         MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
 630         MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
 631         MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
 632         MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
 633         MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
 634         MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
 635         EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
 636         EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
 637         EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
 638         EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
 639         EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
 640         EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
 641         EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
 642         EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
 643         EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
 644         EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
 645         EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
 646         EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
 647         EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
 648         EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
 649         EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
 650         EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
 651         EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
 652         EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
 653         EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
 654         EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
 655         EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
 656         EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
 657         EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
 658         EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
 659         REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
 660         REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
 661         MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
 662         MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
 663         EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
 664         EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
 665         EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
 666         EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
 667         EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
 668         EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
 669         EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
 670         EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
 671         EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
 672         EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
 673         EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
 674         EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
 675         EVEX_W_0F3A43_L_n): New.
 676         * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
 677         0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
 678         0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
 679         * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
 680         for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
 681         0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
 682         0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
 683         * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
 684         0F385B, 0F38C6, and 0F38C7 entries.
 685         * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
 686         0F38C6 and 0F38C7.
 687         * i386-dis-evex-w.h: No longer link to evex_len_table[] for
 688         opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
 689         0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
 690         evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
 691
 692 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 693
 694         * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
 695         MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
 696         MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
 697         MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
 698         MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
 699         MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
 700         MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
 701         MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
 702         MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
 703         MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
 704         MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
 705         MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
 706         MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
 707         MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
 708         MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
 709         MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
 710         MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
 711         MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
 712         MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
 713         MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
 714         MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
 715         MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
 716         MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
 717         MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
 718         MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
 719         PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
 720         PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
 721         PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
 722         PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
 723         PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
 724         VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
 725         VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
 726         VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
 727         VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
 728         VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
 729         VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
 730         VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
 731         VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
 732         VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
 733         VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
 734         VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
 735         VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
 736         VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
 737         VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
 738         VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
 739         VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
 740         VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
 741         VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
 742         VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
 743         VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
 744         VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
 745         VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
 746         VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
 747         VEX_W_0F99_P_2_LEN_0): Delete.
 748         MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
 749         MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
 750         MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
 751         MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
 752         MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
 753         PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
 754         PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
 755         PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
 756         PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
 757         PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
 758         PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
 759         PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
 760         PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
 761         PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
 762         PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
 763         PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
 764         PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
 765         PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
 766         PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
 767         VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
 768         VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
 769         VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
 770         VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
 771         VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
 772         VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
 773         VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
 774         VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
 775         (prefix_table): No longer link to vex_len_table[] for opcodes
 776         0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
 777         0F92, 0F93, 0F98, and 0F99.
 778         (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
 779         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 780         0F98, and 0F99.
 781         (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
 782         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 783         0F98, and 0F99.
 784         (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
 785         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 786         0F98, and 0F99.
 787         (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
 788         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 789         0F98, and 0F99.
 790
 791 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 792
 793         * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
 794         Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
 795         REG_VEX_0F73_M_0 respectively.
 796         (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
 797         MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
 798         MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
 799         MOD_VEX_0F73_REG_7): Delete.
 800         (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
 801         (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
 802         PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
 803         PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
 804         PREFIX_VEX_0F3AF0_L_0 respectively.
 805         (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
 806         VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
 807         VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
 808         VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
 809         (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
 810         VEX_LEN_0F38F7): New.
 811         (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
 812         (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
 813         0F72, and 0F73. No longer link to vex_len_table[] for opcode
 814         0F38F3.
 815         (prefix_table): No longer link to vex_len_table[] for opcodes
 816         0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 817         (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
 818         0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
 819         0F38F6, 0F38F7, and 0F3AF0.
 820         (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
 821         prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 822         (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
 823         0F73.
 824
 825 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 826
 827         * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
 828         REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
 829         (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
 830         MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
 831         MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
 832         (MOD_0F71, MOD_0F72, MOD_0F73): New.
 833         (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
 834         73.
 835         (reg_table): No longer link to mod_table[] for opcodes 0F71,
 836         0F72, and 0F73.
 837         (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
 838         0F73.
 839
 840 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 841
 842         * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
 843         MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
 844         (reg_table): Don't link to mod_table[] where not needed. Add
 845         PREFIX_IGNORED to nop entries.
 846         (prefix_table): Replace PREFIX_OPCODE in nop entries.
 847         (mod_table): Add nop entries next to prefetch ones. Drop
 848         MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
 849         MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
 850         (rm_table): Add PREFIX_IGNORED to nop entries. Drop
 851         PREFIX_OPCODE from endbr* entries.
 852         (get_valid_dis386): Also consider entry's name when zapping
 853         vindex.
 854         (print_insn): Handle PREFIX_IGNORED.
 855
 856 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 857
 858         * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
 859         IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
 860         element.
 861         * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
 862         HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
 863         (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
 864         PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
 865         (struct i386_opcode_modifier): Delete notrackprefixok,
 866         islockable, hleprefixok, and repprefixok fields. Add prefixok
 867         field.
 868         * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
 869         HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
 870         (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
 871         not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
 872         Replace HLEPrefixOk.
 873         * opcodes/i386-tbl.h: Re-generate.
 874
 875 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 876
 877         * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
 878         * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
 879         64-bit form.
 880         * opcodes/i386-tbl.h: Re-generate.
 881
 882 2021-03-03  Jan Beulich  <jbeulich@suse.com>
 883
 884         * i386-gen.c (output_i386_opcode): Don't get operand count. Look
 885         for {} instead of {0}. Don't look for '0'.
 886         * i386-opc.tbl: Drop operand count field. Drop redundant operand
 887         size specifiers.
 888
 889 2021-02-19  Nelson Chu  <nelson.chu@sifive.com>
 890
 891         PR 27158
 892         * riscv-dis.c (print_insn_args): Updated encoding macros.
 893         * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
 894         (match_c_addi16sp): Updated encoding macros.
 895         (match_c_lui): Likewise.
 896         (match_c_lui_with_hint): Likewise.
 897         (match_c_addi4spn): Likewise.
 898         (match_c_slli): Likewise.
 899         (match_slli_as_c_slli): Likewise.
 900         (match_c_slli64): Likewise.
 901         (match_srxi_as_c_srxi): Likewise.
 902         (riscv_insn_types): Added .insn css/cl/cs.
 903
 904 2021-02-18  Nelson Chu  <nelson.chu@sifive.com>
 905
 906         * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
 907         (default_priv_spec): Updated type to riscv_spec_class.
 908         (parse_riscv_dis_option): Updated.
 909         * riscv-opc.c: Moved stuff and make the file tidy.
 910
 911 2021-02-17  Alan Modra  <amodra@gmail.com>
 912
 913         * wasm32-dis.c: Include limits.h.
 914         (CHAR_BIT): Provide backup define.
 915         (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
 916         Correct signed overflow checking.
 917
 918 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 919
 920         * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
 921         * i386-tbl.h: Re-generate.
 922
 923 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 924
 925         * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
 926         Oword.
 927         * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
 928
 929 2021-02-15  Andreas Krebbel  <krebbel@linux.ibm.com>
 930
 931         * s390-mkopc.c (main): Accept arch14 as cpu string.
 932         * s390-opc.txt: Add new arch14 instructions.
 933
 934 2021-02-04  Nick Alcock  <nick.alcock@oracle.com>
 935
 936         * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
 937         favour of LIBINTL.
 938         * configure: Regenerated.
 939
 940 2021-02-08  Mike Frysinger  <vapier@gentoo.org>
 941
 942         * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
 943         * tic54x-opc.c (regs): Rename to ...
 944         (tic54x_regs): ... this.
 945         (mmregs): Rename to ...
 946         (tic54x_mmregs): ... this.
 947         (condition_codes): Rename to ...
 948         (tic54x_condition_codes): ... this.
 949         (cc2_codes): Rename to ...
 950         (tic54x_cc2_codes): ... this.
 951         (cc3_codes): Rename to ...
 952         (tic54x_cc3_codes): ... this.
 953         (status_bits): Rename to ...
 954         (tic54x_status_bits): ... this.
 955         (misc_symbols): Rename to ...
 956         (tic54x_misc_symbols): ... this.
 957
 958 2021-02-04  Nelson Chu  <nelson.chu@sifive.com>
 959
 960         * riscv-opc.c (MASK_RVB_IMM): Removed.
 961         (riscv_opcodes): Removed zb* instructions.
 962         (riscv_ext_version_table): Removed versions for zb*.
 963
 964 2021-01-26  Alan Modra  <amodra@gmail.com>
 965
 966         * i386-gen.c (parse_template): Ensure entire template_instance
 967         is initialised.
 968
 969 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 970
 971         * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
 972         (riscv_fpr_names_abi): Likewise.
 973         (riscv_opcodes): Likewise.
 974         (riscv_insn_types): Likewise.
 975
 976 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 977
 978         * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
 979
 980 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 981
 982         * riscv-dis.c: Comments tidy and improvement.
 983         * riscv-opc.c: Likewise.
 984
 985 2021-01-13  Alan Modra  <amodra@gmail.com>
 986
 987         * Makefile.in: Regenerate.
 988
 989 2021-01-12  H.J. Lu  <hongjiu.lu@intel.com>
 990
 991         PR binutils/26792
 992         * configure.ac: Use GNU_MAKE_JOBSERVER.
 993         * aclocal.m4: Regenerated.
 994         * configure: Likewise.
 995
 996 2021-01-12  Nick Clifton  <nickc@redhat.com>
 997
 998         * po/sr.po: Updated Serbian translation.
 999
1000 2021-01-11  H.J. Lu  <hongjiu.lu@intel.com>
1001
1002         PR ld/27173
1003         * configure: Regenerated.
1004
1005 2021-01-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
1006
1007         * aarch64-asm-2.c: Regenerate.
1008         * aarch64-dis-2.c: Likewise.
1009         * aarch64-opc-2.c: Likewise.
1010         * aarch64-opc.c (aarch64_print_operand):
1011         Delete handling of AARCH64_OPND_CSRE_CSR.
1012         * aarch64-tbl.h (aarch64_feature_csre): Delete.
1013         (CSRE): Likewise.
1014         (_CSRE_INSN): Likewise.
1015         (aarch64_opcode_table): Delete csr.
1016
1017 2021-01-11  Nick Clifton  <nickc@redhat.com>
1018
1019         * po/de.po: Updated German translation.
1020         * po/fr.po: Updated French translation.
1021         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1022         * po/sv.po: Updated Swedish translation.
1023         * po/uk.po: Updated Ukranian translation.
1024
1025 2021-01-09  H.J. Lu  <hongjiu.lu@intel.com>
1026
1027         * configure: Regenerated.
1028
1029 2021-01-09  Nick Clifton  <nickc@redhat.com>
1030
1031         * configure: Regenerate.
1032         * po/opcodes.pot: Regenerate.
1033
1034 2021-01-09  Nick Clifton  <nickc@redhat.com>
1035
1036         * 2.36 release branch crated.
1037
1038 2021-01-08  Peter Bergner  <bergner@linux.ibm.com>
1039
1040         * ppc-opc.c (insert_dw, (extract_dw): New functions.
1041         (DW, (XRC_MASK): Define.
1042         (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
1043
1044 2021-01-09  Alan Modra  <amodra@gmail.com>
1045
1046         * configure: Regenerate.
1047
1048 2021-01-08  Nick Clifton  <nickc@redhat.com>
1049
1050         * po/sv.po: Updated Swedish translation.
1051
1052 2021-01-08  Nick Clifton  <nickc@redhat.com>
1053
1054         PR 27129
1055         * aarch64-dis.c (determine_disassembling_preference): Move call to
1056         aarch64_match_operands_constraint outside of the assertion.
1057         * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
1058         Replace with a return of FALSE.
1059
1060         PR 27139
1061         * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
1062         core system register.
1063
1064 2021-01-07  Samuel Thibault  <samuel.thibault@gnu.org>
1065
1066         * configure: Regenerate.
1067
1068 2021-01-07  Nick Clifton  <nickc@redhat.com>
1069
1070         * po/fr.po: Updated French translation.
1071
1072 2021-01-07  Fredrik Noring  <noring@nocrew.org>
1073
1074         * m68k-opc.c (chkl): Change minimum architecture requirement to
1075         m68020.
1076
1077 2021-01-07  Philipp Tomsich  <prt@gnu.org>
1078
1079         * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
1080
1081 2021-01-07  Claire Xenia Wolf  <claire@symbioticeda.com>
1082             Jim Wilson  <jimw@sifive.com>
1083             Andrew Waterman  <andrew@sifive.com>
1084             Maxim Blinov  <maxim.blinov@embecosm.com>
1085             Kito Cheng  <kito.cheng@sifive.com>
1086             Nelson Chu  <nelson.chu@sifive.com>
1087
1088         * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
1089         (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
1090
1091 2021-01-01  Alan Modra  <amodra@gmail.com>
1092
1093         Update year range in copyright notice of all files.
1094
1095 For older changes see ChangeLog-2020
1096 \f
1097 Copyright (C) 2021 Free Software Foundation, Inc.
1098
1099 Copying and distribution of this file, with or without modification,
1100 are permitted in any medium without royalty provided the copyright
1101 notice and this notice are preserved.
1102
1103 Local Variables:
1104 mode: change-log
1105 left-margin: 8
1106 fill-column: 74
1107 version-control: never
1108 End: