1 2018-10-03 Tamar Christina <tamar.christina@arm.com>
3 * aarch64-opc.c (init_insn_block): New.
4 (verify_constraints, aarch64_is_destructive_by_operands): New.
5 * aarch64-opc.h (verify_constraints): New.
7 2018-10-03 Tamar Christina <tamar.christina@arm.com>
9 * aarch64-dis.c (aarch64_opcode_decode): Update verifier call.
10 * aarch64-opc.c (verify_ldpsw): Update arguments.
12 2018-10-03 Tamar Christina <tamar.christina@arm.com>
14 * aarch64-dis.c (ERR_OK, ERR_UND, ERR_UNP, ERR_NYI): Remove.
15 (aarch64_decode_insn, print_insn_aarch64_word): Use err_type.
17 2018-10-03 Tamar Christina <tamar.christina@arm.com>
19 * aarch64-asm.c (aarch64_opcode_encode): Add insn_sequence.
20 * aarch64-dis.c (insn_sequence): New.
22 2018-10-03 Tamar Christina <tamar.christina@arm.com>
24 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN, _CRC_INSN,
25 _LSE_INSN, _LOR_INSN, RDMA_INSN, FF16_INSN, SF16_INSN, V8_2_INSN,
26 _SVE_INSN, V8_3_INSN, CNUM_INSN, RCPC_INSN, SHA2_INSN, AES_INSN,
27 V8_4_INSN, SHA3_INSN, SM4_INSN, FP16_V8_2_INSN, DOT_INSN): Initialize
30 (struct aarch64_opcode): (fjcvtzs, ldpsw, ldpsw, esb, psb): Initialize
32 (movprfx): Change _SVE_INSN into _SVE_INSNC, add C_SCAN_MOVPRFX and
34 (msb, mul, neg, not, orr, rbit, revb, revh, revw, sabd, scvtf,
35 sdiv, sdivr, sdot, smax, smin, smulh, splice, sqadd, sqdecd, sqdech,
36 sqdecp, sqdecw, sqincd, sqinch, sqincp, sqincw, sqsub, sub, subr, sxtb,
37 sxth, sxtw, uabd, ucvtf, udiv, udivr, udot, umax, umin, umulh, uqadd,
38 uqdecd, uqdech, uqdecp, uqdecw, uqincd, uqinch, uqincp, uqincw, uqsub,
39 uxtb, uxth, uxtw, bic, eon, orn, mov, fmov): Change _SVE_INSN into _SVE_INSNC and add
40 C_SCAN_MOVPRFX and C_MAX_ELEM constraints.
42 2018-10-02 Palmer Dabbelt <palmer@sifive.com>
44 * riscv-opc.c (riscv_opcodes) <fence.tso>: New opcode.
46 2018-09-23 Sandra Loosemore <sandra@codesourcery.com>
48 * nios2-dis.c (nios2_print_insn_arg): Make sure signed conversions
49 are used when extracting signed fields and converting them to
50 potentially 64-bit types.
52 2018-09-21 Simon Marchi <simon.marchi@ericsson.com>
54 * Makefile.am: Remove NO_WMISSING_FIELD_INITIALIZERS.
55 * Makefile.in: Re-generate.
56 * aclocal.m4: Re-generate.
57 * configure: Re-generate.
58 * configure.ac: Remove check for -Wno-missing-field-initializers.
59 * csky-opc.h (csky_v1_opcodes): Initialize all fields of last element.
60 (csky_v2_opcodes): Likewise.
62 2018-09-20 Maciej W. Rozycki <macro@linux-mips.org>
64 * arc-nps400-tbl.h: Append `ull' to large constants throughout.
66 2018-09-20 Nelson Chu <nelson.chu1990@gmail.com>
68 * nds32-asm.c (operand_fields): Remove the unused fields.
69 (nds32_opcodes): Remove the unused instructions.
70 * nds32-dis.c (nds32_ex9_info): Removed.
71 (nds32_parse_opcode): Updated.
72 (print_insn_nds32): Likewise.
73 * nds32-asm.c (config.h, stdlib.h, string.h): New includes.
74 (LEX_SET_FIELD, LEX_GET_FIELD): Update defines.
75 (nds32_asm_init, build_operand_hash_table, build_keyword_hash_table,
76 build_opcode_hash_table): New functions.
77 (nds32_keyword_table, nds32_keyword_count_table, nds32_field_table,
78 nds32_opcode_table): New.
79 (hw_ktabs): Declare it to a pointer rather than an array.
80 (build_hash_table): Removed.
81 * nds32-asm.h (enum): Add SYN_INPUT, SYN_OUTPUT, SYN_LOPT,
82 SYN_ROPT and upadte HW_GPR and HW_INT.
83 * nds32-dis.c (keywords): Remove const.
84 (match_field): New function.
85 (nds32_parse_opcode): Updated.
86 * disassemble.c (disassemble_init_for_target):
87 Add disassemble_init_nds32.
88 * nds32-dis.c (eum map_type): New.
89 (nds32_private_data): Likewise.
90 (get_mapping_symbol_type, is_mapping_symbol, nds32_symbol_is_valid,
91 nds32_add_opcode_hash_table, disassemble_init_nds32): New functions.
92 (print_insn_nds32): Updated.
93 * nds32-asm.c (parse_aext_reg): Add new parameter.
94 (parse_re, parse_re2, parse_aext_reg): Only reduced registers
97 * nds32-asm.c (keyword_usr, keyword_sr): Updated.
98 (operand_fields): Add new fields.
99 (nds32_opcodes): Add new instructions.
100 (keyword_aridxi_mx): New keyword.
101 * nds32-asm.h (enum): Add NASM_ATTR_DSP_ISAEXT, HW_AEXT_ARIDXI_MX
103 (ALU2_1, ALU2_2, ALU2_3): New macros.
104 * nds32-dis.c (nds32_filter_unknown_insn): Updated.
106 2018-09-17 Kito Cheng <kito@andestech.com>
108 * riscv-opc.c (riscv_opcodes): Adjust the order of ble and bleu.
110 2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
113 * i386-dis-evex.h (evex_table): Use EVEX_LEN_0F6E_P_2,
114 EVEX_LEN_0F7E_P_1, EVEX_LEN_0F7E_P_2 and EVEX_LEN_0FD6_P_2.
115 (EVEX_LEN_0F6E_P_2): New EVEX_LEN_TABLE entry.
116 (EVEX_LEN_0F7E_P_1): Likewise.
117 (EVEX_LEN_0F7E_P_2): Likewise.
118 (EVEX_LEN_0FD6_P_2): Likewise.
119 * i386-dis.c (USE_EVEX_LEN_TABLE): New.
120 (EVEX_LEN_TABLE): Likewise.
121 (EVEX_LEN_0F6E_P_2): New enum.
122 (EVEX_LEN_0F7E_P_1): Likewise.
123 (EVEX_LEN_0F7E_P_2): Likewise.
124 (EVEX_LEN_0FD6_P_2): Likewise.
125 (evex_len_table): New.
126 (get_valid_dis386): Handle USE_EVEX_LEN_TABLE.
127 * i386-opc.tbl: Set EVex=2 on EVEX.128 only vmovd and vmovq.
128 * i386-tbl.h: Regenerated.
130 2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
133 * i386-dis.c (vex_len_table): Update VEX_LEN_0F6E_P_2 and
134 VEX_LEN_0F7E_P_2 entries.
135 * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovd and vmovq.
136 * i386-tbl.h: Regenerated.
138 2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
140 * i386-dis.c (VZERO_Fixup): Removed.
142 (VEX_LEN_0F10_P_1): Likewise.
143 (VEX_LEN_0F10_P_3): Likewise.
144 (VEX_LEN_0F11_P_1): Likewise.
145 (VEX_LEN_0F11_P_3): Likewise.
146 (VEX_LEN_0F2E_P_0): Likewise.
147 (VEX_LEN_0F2E_P_2): Likewise.
148 (VEX_LEN_0F2F_P_0): Likewise.
149 (VEX_LEN_0F2F_P_2): Likewise.
150 (VEX_LEN_0F51_P_1): Likewise.
151 (VEX_LEN_0F51_P_3): Likewise.
152 (VEX_LEN_0F52_P_1): Likewise.
153 (VEX_LEN_0F53_P_1): Likewise.
154 (VEX_LEN_0F58_P_1): Likewise.
155 (VEX_LEN_0F58_P_3): Likewise.
156 (VEX_LEN_0F59_P_1): Likewise.
157 (VEX_LEN_0F59_P_3): Likewise.
158 (VEX_LEN_0F5A_P_1): Likewise.
159 (VEX_LEN_0F5A_P_3): Likewise.
160 (VEX_LEN_0F5C_P_1): Likewise.
161 (VEX_LEN_0F5C_P_3): Likewise.
162 (VEX_LEN_0F5D_P_1): Likewise.
163 (VEX_LEN_0F5D_P_3): Likewise.
164 (VEX_LEN_0F5E_P_1): Likewise.
165 (VEX_LEN_0F5E_P_3): Likewise.
166 (VEX_LEN_0F5F_P_1): Likewise.
167 (VEX_LEN_0F5F_P_3): Likewise.
168 (VEX_LEN_0FC2_P_1): Likewise.
169 (VEX_LEN_0FC2_P_3): Likewise.
170 (VEX_LEN_0F3A0A_P_2): Likewise.
171 (VEX_LEN_0F3A0B_P_2): Likewise.
172 (VEX_W_0F10_P_0): Likewise.
173 (VEX_W_0F10_P_1): Likewise.
174 (VEX_W_0F10_P_2): Likewise.
175 (VEX_W_0F10_P_3): Likewise.
176 (VEX_W_0F11_P_0): Likewise.
177 (VEX_W_0F11_P_1): Likewise.
178 (VEX_W_0F11_P_2): Likewise.
179 (VEX_W_0F11_P_3): Likewise.
180 (VEX_W_0F12_P_0_M_0): Likewise.
181 (VEX_W_0F12_P_0_M_1): Likewise.
182 (VEX_W_0F12_P_1): Likewise.
183 (VEX_W_0F12_P_2): Likewise.
184 (VEX_W_0F12_P_3): Likewise.
185 (VEX_W_0F13_M_0): Likewise.
186 (VEX_W_0F14): Likewise.
187 (VEX_W_0F15): Likewise.
188 (VEX_W_0F16_P_0_M_0): Likewise.
189 (VEX_W_0F16_P_0_M_1): Likewise.
190 (VEX_W_0F16_P_1): Likewise.
191 (VEX_W_0F16_P_2): Likewise.
192 (VEX_W_0F17_M_0): Likewise.
193 (VEX_W_0F28): Likewise.
194 (VEX_W_0F29): Likewise.
195 (VEX_W_0F2B_M_0): Likewise.
196 (VEX_W_0F2E_P_0): Likewise.
197 (VEX_W_0F2E_P_2): Likewise.
198 (VEX_W_0F2F_P_0): Likewise.
199 (VEX_W_0F2F_P_2): Likewise.
200 (VEX_W_0F50_M_0): Likewise.
201 (VEX_W_0F51_P_0): Likewise.
202 (VEX_W_0F51_P_1): Likewise.
203 (VEX_W_0F51_P_2): Likewise.
204 (VEX_W_0F51_P_3): Likewise.
205 (VEX_W_0F52_P_0): Likewise.
206 (VEX_W_0F52_P_1): Likewise.
207 (VEX_W_0F53_P_0): Likewise.
208 (VEX_W_0F53_P_1): Likewise.
209 (VEX_W_0F58_P_0): Likewise.
210 (VEX_W_0F58_P_1): Likewise.
211 (VEX_W_0F58_P_2): Likewise.
212 (VEX_W_0F58_P_3): Likewise.
213 (VEX_W_0F59_P_0): Likewise.
214 (VEX_W_0F59_P_1): Likewise.
215 (VEX_W_0F59_P_2): Likewise.
216 (VEX_W_0F59_P_3): Likewise.
217 (VEX_W_0F5A_P_0): Likewise.
218 (VEX_W_0F5A_P_1): Likewise.
219 (VEX_W_0F5A_P_3): Likewise.
220 (VEX_W_0F5B_P_0): Likewise.
221 (VEX_W_0F5B_P_1): Likewise.
222 (VEX_W_0F5B_P_2): Likewise.
223 (VEX_W_0F5C_P_0): Likewise.
224 (VEX_W_0F5C_P_1): Likewise.
225 (VEX_W_0F5C_P_2): Likewise.
226 (VEX_W_0F5C_P_3): Likewise.
227 (VEX_W_0F5D_P_0): Likewise.
228 (VEX_W_0F5D_P_1): Likewise.
229 (VEX_W_0F5D_P_2): Likewise.
230 (VEX_W_0F5D_P_3): Likewise.
231 (VEX_W_0F5E_P_0): Likewise.
232 (VEX_W_0F5E_P_1): Likewise.
233 (VEX_W_0F5E_P_2): Likewise.
234 (VEX_W_0F5E_P_3): Likewise.
235 (VEX_W_0F5F_P_0): Likewise.
236 (VEX_W_0F5F_P_1): Likewise.
237 (VEX_W_0F5F_P_2): Likewise.
238 (VEX_W_0F5F_P_3): Likewise.
239 (VEX_W_0F60_P_2): Likewise.
240 (VEX_W_0F61_P_2): Likewise.
241 (VEX_W_0F62_P_2): Likewise.
242 (VEX_W_0F63_P_2): Likewise.
243 (VEX_W_0F64_P_2): Likewise.
244 (VEX_W_0F65_P_2): Likewise.
245 (VEX_W_0F66_P_2): Likewise.
246 (VEX_W_0F67_P_2): Likewise.
247 (VEX_W_0F68_P_2): Likewise.
248 (VEX_W_0F69_P_2): Likewise.
249 (VEX_W_0F6A_P_2): Likewise.
250 (VEX_W_0F6B_P_2): Likewise.
251 (VEX_W_0F6C_P_2): Likewise.
252 (VEX_W_0F6D_P_2): Likewise.
253 (VEX_W_0F6F_P_1): Likewise.
254 (VEX_W_0F6F_P_2): Likewise.
255 (VEX_W_0F70_P_1): Likewise.
256 (VEX_W_0F70_P_2): Likewise.
257 (VEX_W_0F70_P_3): Likewise.
258 (VEX_W_0F71_R_2_P_2): Likewise.
259 (VEX_W_0F71_R_4_P_2): Likewise.
260 (VEX_W_0F71_R_6_P_2): Likewise.
261 (VEX_W_0F72_R_2_P_2): Likewise.
262 (VEX_W_0F72_R_4_P_2): Likewise.
263 (VEX_W_0F72_R_6_P_2): Likewise.
264 (VEX_W_0F73_R_2_P_2): Likewise.
265 (VEX_W_0F73_R_3_P_2): Likewise.
266 (VEX_W_0F73_R_6_P_2): Likewise.
267 (VEX_W_0F73_R_7_P_2): Likewise.
268 (VEX_W_0F74_P_2): Likewise.
269 (VEX_W_0F75_P_2): Likewise.
270 (VEX_W_0F76_P_2): Likewise.
271 (VEX_W_0F77_P_0): Likewise.
272 (VEX_W_0F7C_P_2): Likewise.
273 (VEX_W_0F7C_P_3): Likewise.
274 (VEX_W_0F7D_P_2): Likewise.
275 (VEX_W_0F7D_P_3): Likewise.
276 (VEX_W_0F7E_P_1): Likewise.
277 (VEX_W_0F7F_P_1): Likewise.
278 (VEX_W_0F7F_P_2): Likewise.
279 (VEX_W_0FAE_R_2_M_0): Likewise.
280 (VEX_W_0FAE_R_3_M_0): Likewise.
281 (VEX_W_0FC2_P_0): Likewise.
282 (VEX_W_0FC2_P_1): Likewise.
283 (VEX_W_0FC2_P_2): Likewise.
284 (VEX_W_0FC2_P_3): Likewise.
285 (VEX_W_0FD0_P_2): Likewise.
286 (VEX_W_0FD0_P_3): Likewise.
287 (VEX_W_0FD1_P_2): Likewise.
288 (VEX_W_0FD2_P_2): Likewise.
289 (VEX_W_0FD3_P_2): Likewise.
290 (VEX_W_0FD4_P_2): Likewise.
291 (VEX_W_0FD5_P_2): Likewise.
292 (VEX_W_0FD6_P_2): Likewise.
293 (VEX_W_0FD7_P_2_M_1): Likewise.
294 (VEX_W_0FD8_P_2): Likewise.
295 (VEX_W_0FD9_P_2): Likewise.
296 (VEX_W_0FDA_P_2): Likewise.
297 (VEX_W_0FDB_P_2): Likewise.
298 (VEX_W_0FDC_P_2): Likewise.
299 (VEX_W_0FDD_P_2): Likewise.
300 (VEX_W_0FDE_P_2): Likewise.
301 (VEX_W_0FDF_P_2): Likewise.
302 (VEX_W_0FE0_P_2): Likewise.
303 (VEX_W_0FE1_P_2): Likewise.
304 (VEX_W_0FE2_P_2): Likewise.
305 (VEX_W_0FE3_P_2): Likewise.
306 (VEX_W_0FE4_P_2): Likewise.
307 (VEX_W_0FE5_P_2): Likewise.
308 (VEX_W_0FE6_P_1): Likewise.
309 (VEX_W_0FE6_P_2): Likewise.
310 (VEX_W_0FE6_P_3): Likewise.
311 (VEX_W_0FE7_P_2_M_0): Likewise.
312 (VEX_W_0FE8_P_2): Likewise.
313 (VEX_W_0FE9_P_2): Likewise.
314 (VEX_W_0FEA_P_2): Likewise.
315 (VEX_W_0FEB_P_2): Likewise.
316 (VEX_W_0FEC_P_2): Likewise.
317 (VEX_W_0FED_P_2): Likewise.
318 (VEX_W_0FEE_P_2): Likewise.
319 (VEX_W_0FEF_P_2): Likewise.
320 (VEX_W_0FF0_P_3_M_0): Likewise.
321 (VEX_W_0FF1_P_2): Likewise.
322 (VEX_W_0FF2_P_2): Likewise.
323 (VEX_W_0FF3_P_2): Likewise.
324 (VEX_W_0FF4_P_2): Likewise.
325 (VEX_W_0FF5_P_2): Likewise.
326 (VEX_W_0FF6_P_2): Likewise.
327 (VEX_W_0FF7_P_2): Likewise.
328 (VEX_W_0FF8_P_2): Likewise.
329 (VEX_W_0FF9_P_2): Likewise.
330 (VEX_W_0FFA_P_2): Likewise.
331 (VEX_W_0FFB_P_2): Likewise.
332 (VEX_W_0FFC_P_2): Likewise.
333 (VEX_W_0FFD_P_2): Likewise.
334 (VEX_W_0FFE_P_2): Likewise.
335 (VEX_W_0F3800_P_2): Likewise.
336 (VEX_W_0F3801_P_2): Likewise.
337 (VEX_W_0F3802_P_2): Likewise.
338 (VEX_W_0F3803_P_2): Likewise.
339 (VEX_W_0F3804_P_2): Likewise.
340 (VEX_W_0F3805_P_2): Likewise.
341 (VEX_W_0F3806_P_2): Likewise.
342 (VEX_W_0F3807_P_2): Likewise.
343 (VEX_W_0F3808_P_2): Likewise.
344 (VEX_W_0F3809_P_2): Likewise.
345 (VEX_W_0F380A_P_2): Likewise.
346 (VEX_W_0F380B_P_2): Likewise.
347 (VEX_W_0F3817_P_2): Likewise.
348 (VEX_W_0F381C_P_2): Likewise.
349 (VEX_W_0F381D_P_2): Likewise.
350 (VEX_W_0F381E_P_2): Likewise.
351 (VEX_W_0F3820_P_2): Likewise.
352 (VEX_W_0F3821_P_2): Likewise.
353 (VEX_W_0F3822_P_2): Likewise.
354 (VEX_W_0F3823_P_2): Likewise.
355 (VEX_W_0F3824_P_2): Likewise.
356 (VEX_W_0F3825_P_2): Likewise.
357 (VEX_W_0F3828_P_2): Likewise.
358 (VEX_W_0F3829_P_2): Likewise.
359 (VEX_W_0F382A_P_2_M_0): Likewise.
360 (VEX_W_0F382B_P_2): Likewise.
361 (VEX_W_0F3830_P_2): Likewise.
362 (VEX_W_0F3831_P_2): Likewise.
363 (VEX_W_0F3832_P_2): Likewise.
364 (VEX_W_0F3833_P_2): Likewise.
365 (VEX_W_0F3834_P_2): Likewise.
366 (VEX_W_0F3835_P_2): Likewise.
367 (VEX_W_0F3837_P_2): Likewise.
368 (VEX_W_0F3838_P_2): Likewise.
369 (VEX_W_0F3839_P_2): Likewise.
370 (VEX_W_0F383A_P_2): Likewise.
371 (VEX_W_0F383B_P_2): Likewise.
372 (VEX_W_0F383C_P_2): Likewise.
373 (VEX_W_0F383D_P_2): Likewise.
374 (VEX_W_0F383E_P_2): Likewise.
375 (VEX_W_0F383F_P_2): Likewise.
376 (VEX_W_0F3840_P_2): Likewise.
377 (VEX_W_0F3841_P_2): Likewise.
378 (VEX_W_0F38DB_P_2): Likewise.
379 (VEX_W_0F3A08_P_2): Likewise.
380 (VEX_W_0F3A09_P_2): Likewise.
381 (VEX_W_0F3A0A_P_2): Likewise.
382 (VEX_W_0F3A0B_P_2): Likewise.
383 (VEX_W_0F3A0C_P_2): Likewise.
384 (VEX_W_0F3A0D_P_2): Likewise.
385 (VEX_W_0F3A0E_P_2): Likewise.
386 (VEX_W_0F3A0F_P_2): Likewise.
387 (VEX_W_0F3A21_P_2): Likewise.
388 (VEX_W_0F3A40_P_2): Likewise.
389 (VEX_W_0F3A41_P_2): Likewise.
390 (VEX_W_0F3A42_P_2): Likewise.
391 (VEX_W_0F3A62_P_2): Likewise.
392 (VEX_W_0F3A63_P_2): Likewise.
393 (VEX_W_0F3ADF_P_2): Likewise.
394 (VEX_LEN_0F77_P_0): New.
395 (prefix_table): Update PREFIX_VEX_0F10, PREFIX_VEX_0F11,
396 PREFIX_VEX_0F12, PREFIX_VEX_0F16, PREFIX_VEX_0F2E,
397 PREFIX_VEX_0F2F, PREFIX_VEX_0F51, PREFIX_VEX_0F52,
398 PREFIX_VEX_0F53, PREFIX_VEX_0F58, PREFIX_VEX_0F59,
399 PREFIX_VEX_0F5A, PREFIX_VEX_0F5B, PREFIX_VEX_0F5C,
400 PREFIX_VEX_0F5D, PREFIX_VEX_0F5E, PREFIX_VEX_0F5F,
401 PREFIX_VEX_0F60, PREFIX_VEX_0F61, PREFIX_VEX_0F62,
402 PREFIX_VEX_0F63, PREFIX_VEX_0F64, PREFIX_VEX_0F65,
403 PREFIX_VEX_0F66, PREFIX_VEX_0F67, PREFIX_VEX_0F68,
404 PREFIX_VEX_0F69, PREFIX_VEX_0F6A, PREFIX_VEX_0F6B,
405 PREFIX_VEX_0F6C, PREFIX_VEX_0F6D, PREFIX_VEX_0F6F,
406 PREFIX_VEX_0F70, PREFIX_VEX_0F71_REG_2, PREFIX_VEX_0F71_REG_4,
407 PREFIX_VEX_0F71_REG_6, PREFIX_VEX_0F72_REG_4,
408 PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
409 PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
410 PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74, PREFIX_VEX_0F75,
411 PREFIX_VEX_0F76, PREFIX_VEX_0F77, PREFIX_VEX_0F7C,
412 PREFIX_VEX_0F7D, PREFIX_VEX_0F7F, PREFIX_VEX_0FC2,
413 PREFIX_VEX_0FD0, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
414 PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
415 PREFIX_VEX_0FD8, PREFIX_VEX_0FD9, PREFIX_VEX_0FDA,
416 PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
417 PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
418 PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
419 PREFIX_VEX_0FE5, PREFIX_VEX_0FE6, PREFIX_VEX_0FE8,
420 PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
421 PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
422 PREFIX_VEX_0FEF, PREFIX_VEX_0FF1. PREFIX_VEX_0FF2,
423 PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
424 PREFIX_VEX_0FF6, PREFIX_VEX_0FF8, PREFIX_VEX_0FF9,
425 PREFIX_VEX_0FFA, PREFIX_VEX_0FFB, PREFIX_VEX_0FFC,
426 PREFIX_VEX_0FFD, PREFIX_VEX_0FFE, PREFIX_VEX_0F3800,
427 PREFIX_VEX_0F3801, PREFIX_VEX_0F3802, PREFIX_VEX_0F3803,
428 PREFIX_VEX_0F3804, PREFIX_VEX_0F3805, PREFIX_VEX_0F3806,
429 PREFIX_VEX_0F3807, PREFIX_VEX_0F3808, PREFIX_VEX_0F3809,
430 PREFIX_VEX_0F380A, PREFIX_VEX_0F380B, PREFIX_VEX_0F3817,
431 PREFIX_VEX_0F381C, PREFIX_VEX_0F381D, PREFIX_VEX_0F381E,
432 PREFIX_VEX_0F3820, PREFIX_VEX_0F3821, PREFIX_VEX_0F3822,
433 PREFIX_VEX_0F3823, PREFIX_VEX_0F3824, PREFIX_VEX_0F3825,
434 PREFIX_VEX_0F3828, PREFIX_VEX_0F3829, PREFIX_VEX_0F382B,
435 PREFIX_VEX_0F382C, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
436 PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
437 PREFIX_VEX_0F3837, PREFIX_VEX_0F3838, PREFIX_VEX_0F3839,
438 PREFIX_VEX_0F383A, PREFIX_VEX_0F383B, PREFIX_VEX_0F383C,
439 PREFIX_VEX_0F383D, PREFIX_VEX_0F383E, PREFIX_VEX_0F383F,
440 PREFIX_VEX_0F3840, PREFIX_VEX_0F3A08, PREFIX_VEX_0F3A09,
441 PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B, PREFIX_VEX_0F3A0C,
442 PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E, PREFIX_VEX_0F3A0F,
443 PREFIX_VEX_0F3A40 and PREFIX_VEX_0F3A42 entries.
444 (vex_table): Update VEX 0F28 and 0F29 entries.
445 (vex_len_table): Update VEX_LEN_0F10_P_1, VEX_LEN_0F10_P_3,
446 VEX_LEN_0F11_P_1, VEX_LEN_0F11_P_3, VEX_LEN_0F2E_P_0,
447 VEX_LEN_0F2E_P_2, VEX_LEN_0F2F_P_0, VEX_LEN_0F2F_P_2,
448 VEX_LEN_0F51_P_1, VEX_LEN_0F51_P_3, VEX_LEN_0F52_P_1,
449 VEX_LEN_0F53_P_1, VEX_LEN_0F58_P_1, VEX_LEN_0F58_P_3,
450 VEX_LEN_0F59_P_1, VEX_LEN_0F59_P_3, VEX_LEN_0F5A_P_1,
451 VEX_LEN_0F5A_P_3, VEX_LEN_0F5C_P_1, VEX_LEN_0F5C_P_3,
452 VEX_LEN_0F5D_P_1, VEX_LEN_0F5D_P_3, VEX_LEN_0F5E_P_1,
453 VEX_LEN_0F5E_P_3, VEX_LEN_0F5F_P_1, VEX_LEN_0F5F_P_3,
454 VEX_LEN_0FC2_P_1, VEX_LEN_0FC2_P_3, VEX_LEN_0F3A0A_P_2 and
455 VEX_LEN_0F3A0B_P_2 entries.
456 (vex_w_table): Remove VEX_W_0F10_P_0, VEX_W_0F10_P_1,
457 VEX_W_0F10_P_2, VEX_W_0F10_P_3, VEX_W_0F11_P_0, VEX_W_0F11_P_1,
458 VEX_W_0F11_P_2, VEX_W_0F11_P_3, VEX_W_0F12_P_0_M_0,
459 VEX_W_0F12_P_0_M_1, VEX_W_0F12_P_1, VEX_W_0F12_P_2,
460 VEX_W_0F12_P_3, VEX_W_0F13_M_0, VEX_W_0F14, VEX_W_0F15,
461 VEX_W_0F16_P_0_M_0, VEX_W_0F16_P_0_M_1, VEX_W_0F16_P_1,
462 VEX_W_0F16_P_2, VEX_W_0F17_M_0, VEX_W_0F28, VEX_W_0F29,
463 VEX_W_0F2B_M_0, VEX_W_0F2E_P_0, VEX_W_0F2E_P_2, VEX_W_0F2F_P_0,
464 VEX_W_0F2F_P_2, VEX_W_0F50_M_0, VEX_W_0F51_P_0, VEX_W_0F51_P_1,
465 VEX_W_0F51_P_2, VEX_W_0F51_P_3, VEX_W_0F52_P_0, VEX_W_0F52_P_1,
466 VEX_W_0F53_P_0, VEX_W_0F53_P_1, VEX_W_0F58_P_0, VEX_W_0F58_P_1,
467 VEX_W_0F58_P_2, VEX_W_0F58_P_3, VEX_W_0F59_P_0, VEX_W_0F59_P_1,
468 VEX_W_0F59_P_2, VEX_W_0F59_P_3, VEX_W_0F5A_P_0, VEX_W_0F5A_P_1,
469 VEX_W_0F5A_P_3, VEX_W_0F5B_P_0, VEX_W_0F5B_P_1, VEX_W_0F5B_P_2,
470 VEX_W_0F5C_P_0, VEX_W_0F5C_P_1, VEX_W_0F5C_P_2, VEX_W_0F5C_P_3,
471 VEX_W_0F5D_P_0, VEX_W_0F5D_P_1, VEX_W_0F5D_P_2, VEX_W_0F5D_P_3,
472 VEX_W_0F5E_P_0, VEX_W_0F5E_P_1, VEX_W_0F5E_P_2, VEX_W_0F5E_P_3,
473 VEX_W_0F5F_P_0, VEX_W_0F5F_P_1, VEX_W_0F5F_P_2, VEX_W_0F5F_P_3,
474 VEX_W_0F60_P_2, VEX_W_0F61_P_2, VEX_W_0F62_P_2, VEX_W_0F63_P_2,
475 VEX_W_0F64_P_2, VEX_W_0F65_P_2, VEX_W_0F66_P_2, VEX_W_0F67_P_2,
476 VEX_W_0F68_P_2, VEX_W_0F69_P_2, VEX_W_0F6A_P_2, VEX_W_0F6B_P_2,
477 VEX_W_0F6C_P_2, VEX_W_0F6D_P_2, VEX_W_0F6F_P_1, VEX_W_0F6F_P_2,
478 VEX_W_0F70_P_1, VEX_W_0F70_P_2, VEX_W_0F70_P_3,
479 VEX_W_0F71_R_2_P_2, VEX_W_0F71_R_4_P_2, VEX_W_0F71_R_6_P_2,
480 VEX_W_0F72_R_2_P_2, VEX_W_0F72_R_4_P_2, VEX_W_0F72_R_6_P_2,
481 VEX_W_0F73_R_2_P_2, VEX_W_0F73_R_3_P_2, VEX_W_0F73_R_6_P_2,
482 VEX_W_0F73_R_7_P_2, VEX_W_0F74_P_2, VEX_W_0F75_P_2,
483 VEX_W_0F76_P_2, VEX_W_0F77_P_0, VEX_W_0F7C_P_2, VEX_W_0F7C_P_3,
484 VEX_W_0F7D_P_2, VEX_W_0F7D_P_3, VEX_W_0F7E_P_1, VEX_W_0F7F_P_1,
485 VEX_W_0F7F_P_2, VEX_W_0FAE_R_2_M_0, VEX_W_0FAE_R_3_M_0,
486 VEX_W_0FC2_P_0, VEX_W_0FC2_P_1, VEX_W_0FC2_P_2, VEX_W_0FC2_P_3,
487 VEX_W_0FD0_P_2, VEX_W_0FD0_P_3, VEX_W_0FD1_P_2, VEX_W_0FD2_P_2,
488 VEX_W_0FD3_P_2, VEX_W_0FD4_P_2, VEX_W_0FD5_P_2, VEX_W_0FD6_P_2,
489 VEX_W_0FD7_P_2_M_1, VEX_W_0FD8_P_2, VEX_W_0FD9_P_2,
490 VEX_W_0FDA_P_2, VEX_W_0FDB_P_2, VEX_W_0FDC_P_2, VEX_W_0FDD_P_2,
491 VEX_W_0FDE_P_2, VEX_W_0FDF_P_2, VEX_W_0FE0_P_2, VEX_W_0FE1_P_2,
492 VEX_W_0FE2_P_2, VEX_W_0FE3_P_2, VEX_W_0FE4_P_2, VEX_W_0FE5_P_2,
493 VEX_W_0FE6_P_1, VEX_W_0FE6_P_2, VEX_W_0FE6_P_3,
494 VEX_W_0FE7_P_2_M_0, VEX_W_0FE8_P_2, VEX_W_0FE9_P_2,
495 VEX_W_0FEA_P_2, VEX_W_0FEB_P_2, VEX_W_0FEC_P_2, VEX_W_0FED_P_2,
496 VEX_W_0FEE_P_2, VEX_W_0FEF_P_2, VEX_W_0FF0_P_3_M_0,
497 VEX_W_0FF1_P_2, VEX_W_0FF2_P_2, VEX_W_0FF3_P_2, VEX_W_0FF4_P_2,
498 VEX_W_0FF5_P_2, VEX_W_0FF6_P_2, VEX_W_0FF7_P_2, VEX_W_0FF8_P_2,
499 VEX_W_0FF9_P_2, VEX_W_0FFA_P_2, VEX_W_0FFB_P_2, VEX_W_0FFC_P_2,
500 VEX_W_0FFD_P_2, VEX_W_0FFE_P_2, VEX_W_0F3800_P_2,
501 VEX_W_0F3801_P_2, VEX_W_0F3802_P_2, VEX_W_0F3803_P_2,
502 VEX_W_0F3804_P_2, VEX_W_0F3805_P_2, VEX_W_0F3806_P_2,
503 VEX_W_0F3807_P_2, VEX_W_0F3808_P_2, VEX_W_0F3809_P_2,
504 VEX_W_0F380A_P_2, VEX_W_0F380B_P_2, VEX_W_0F3817_P_2,
505 VEX_W_0F381C_P_2, VEX_W_0F381D_P_2, VEX_W_0F381E_P_2,
506 VEX_W_0F3820_P_2, VEX_W_0F3821_P_2, VEX_W_0F3822_P_2,
507 VEX_W_0F3823_P_2, VEX_W_0F3824_P_2, VEX_W_0F3825_P_2,
508 VEX_W_0F3828_P_2, VEX_W_0F3829_P_2, VEX_W_0F382A_P_2_M_0,
509 VEX_W_0F382B_P_2, VEX_W_0F3830_P_2, VEX_W_0F3831_P_2,
510 VEX_W_0F3832_P_2, VEX_W_0F3833_P_2, VEX_W_0F3834_P_2,
511 VEX_W_0F3835_P_2, VEX_W_0F3837_P_2, VEX_W_0F3838_P_2,
512 VEX_W_0F3839_P_2, VEX_W_0F383A_P_2, VEX_W_0F383B_P_2,
513 VEX_W_0F383C_P_2, VEX_W_0F383D_P_2, VEX_W_0F383E_P_2,
514 VEX_W_0F383F_P_2, VEX_W_0F3840_P_2, VEX_W_0F3841_P_2,
515 VEX_W_0F38DB_P_2, VEX_W_0F3A08_P_2, VEX_W_0F3A09_P_2,
516 VEX_W_0F3A0A_P_2, VEX_W_0F3A0B_P_2, VEX_W_0F3A0C_P_2,
517 VEX_W_0F3A0D_P_2, VEX_W_0F3A0E_P_2, VEX_W_0F3A0F_P_2,
518 VEX_W_0F3A21_P_2, VEX_W_0F3A40_P_2, VEX_W_0F3A41_P_2,
519 VEX_W_0F3A42_P_2, VEX_W_0F3A62_P_2, VEX_W_0F3A63_P_2 and
520 VEX_W_0F3ADF_P_2 entries.
521 (mod_table): Update MOD_VEX_0F2B, MOD_VEX_0F50,
522 MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
523 MOD_VEX_0FF0_PREFIX_3 and MOD_VEX_0F382A_PREFIX_2 entries.
525 2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
527 * i386-opc.tbl (VexWIG): New.
528 Replace VexW=3 with VexWIG.
530 2018-09-15 H.J. Lu <hongjiu.lu@intel.com>
532 * i386-opc.tbl: Set VexW=3 on AVX vrsqrtss.
533 * i386-tbl.h: Regenerated.
535 2018-09-15 H.J. Lu <hongjiu.lu@intel.com>
538 * i386-dis.c (vex_len_table): Update VEX_LEN_0F7E_P_1 and
539 VEX_LEN_0FD6_P_2 entries.
540 * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovq.
541 * i386-tbl.h: Regenerated.
543 2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
546 * i386-opc.h (VEXWIG): New.
547 * i386-opc.tbl: Set VexW=3 on VEX/EVEX WIG instructions.
548 * i386-tbl.h: Regenerated.
550 2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
553 * i386-dis-evex.h: Replace EXxEVexR with EXxEVexR64 for
554 vcvtsi2sd%LQ and vcvtusi2sd%LQ.
555 * i386-dis.c (EXxEVexR64): New.
556 (evex_rounding_64_mode): Likewise.
557 (OP_Rounding): Handle evex_rounding_64_mode.
559 2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
562 * i386-dis-evex.h (evex_table): Replace Eq with Edqa for
563 vcvtsi2ss%LQ, vcvtsi2sd%LQ, vcvtusi2ss%LQ and vcvtusi2sd%LQ.
564 * i386-dis.c (Edqa): New.
565 (dqa_mode): Likewise.
566 (intel_operand_size): Handle dqa_mode as m_mode.
567 (OP_E_register): Handle dqa_mode as dq_mode.
568 (OP_E_memory): Set shift for dqa_mode based on address_mode.
570 2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
572 * i386-dis.c (OP_E_memory): Reformat.
574 2018-09-14 Jan Beulich <jbeulich@suse.com>
576 * i386-opc.tbl (crc32): Fold byte and word forms.
577 * i386-tbl.h: Re-generate.
579 2018-09-13 H.J. Lu <hongjiu.lu@intel.com>
581 * i386-opc.tbl: Add VexW=1 to VEX.W0 VEX movd, cvtsi2ss, cvtsi2sd,
582 pextrd, pinsrd, vcvtsi2sd, vcvtsi2ss, vmovd, vpextrd and vpinsrd.
583 Add VexW=2 to VEX.W1 VEX movq, pextrq, pinsrq, vmovq, vpextrq and
584 vpinsrq. Remove VexW=1 from WIG VEX movq and vmovq.
585 * i386-tbl.h: Regenerated.
587 2018-09-13 Jan Beulich <jbeulich@suse.com>
589 * i386-opc.tbl (mov, movq, movdir64b): Drop IgnoreSize where
591 (invept, invvpid, vcvtph2ps, vcvtps2ph, bndmov, xrstors,
592 xrstors64, xsaves, xsaves64, xsavec, xsavec64, rdpid, incsspq,
593 rdsspq, saveprevssp, setssbsy, endbr32, endbr64): Drop IgnoreSize.
594 * i386-tbl.h: Re-generate.
596 2018-09-13 Jan Beulich <jbeulich@suse.com>
598 * i386-opc.tbl: Drop IgnoreSize from AVX512_4FMAPS and
600 * i386-tbl.h: Re-generate.
602 2018-09-13 Jan Beulich <jbeulich@suse.com>
604 * i386-opc.tbl: Drop IgnoreSize from AVX512DQ insns where
606 * i386-tbl.h: Re-generate.
608 2018-09-13 Jan Beulich <jbeulich@suse.com>
610 * i386-opc.tbl: Drop IgnoreSize from AVX512BW insns where
612 * i386-tbl.h: Re-generate.
614 2018-09-13 Jan Beulich <jbeulich@suse.com>
616 * i386-opc.tbl: Drop IgnoreSize from AVX512VL insns where
618 * i386-tbl.h: Re-generate.
620 2018-09-13 Jan Beulich <jbeulich@suse.com>
622 * i386-opc.tbl: Drop IgnoreSize from AVX512ER insns where
624 * i386-tbl.h: Re-generate.
626 2018-09-13 Jan Beulich <jbeulich@suse.com>
628 * i386-opc.tbl: Drop IgnoreSize from AVX512F insns where
630 * i386-tbl.h: Re-generate.
632 2018-09-13 Jan Beulich <jbeulich@suse.com>
634 * i386-opc.tbl: Drop IgnoreSize from SHA insns.
635 * i386-tbl.h: Re-generate.
637 2018-09-13 Jan Beulich <jbeulich@suse.com>
639 * i386-opc.tbl: Drop IgnoreSize from XOP and SSE4a insns.
640 * i386-tbl.h: Re-generate.
642 2018-09-13 Jan Beulich <jbeulich@suse.com>
644 * i386-opc.tbl: Drop IgnoreSize from AVX2 insns where
646 * i386-tbl.h: Re-generate.
648 2018-09-13 Jan Beulich <jbeulich@suse.com>
650 * i386-opc.tbl: Drop IgnoreSize from AVX insns where
652 * i386-tbl.h: Re-generate.
654 2018-09-13 Jan Beulich <jbeulich@suse.com>
656 * i386-opc.tbl: Drop IgnoreSize from GNFI insns.
657 * i386-tbl.h: Re-generate.
659 2018-09-13 Jan Beulich <jbeulich@suse.com>
661 * i386-opc.tbl: Drop IgnoreSize from PCLMUL/VPCLMUL insns.
662 * i386-tbl.h: Re-generate.
664 2018-09-13 Jan Beulich <jbeulich@suse.com>
666 * i386-opc.tbl: Drop IgnoreSize from AES/VAES insns.
667 * i386-tbl.h: Re-generate.
669 2018-09-13 Jan Beulich <jbeulich@suse.com>
671 * i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where
673 * i386-tbl.h: Re-generate.
675 2018-09-13 Jan Beulich <jbeulich@suse.com>
677 * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where
679 * i386-tbl.h: Re-generate.
681 2018-09-13 Jan Beulich <jbeulich@suse.com>
683 * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where
685 * i386-tbl.h: Re-generate.
687 2018-09-13 Jan Beulich <jbeulich@suse.com>
689 * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
690 * i386-tbl.h: Re-generate.
692 2018-09-13 Jan Beulich <jbeulich@suse.com>
694 * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
695 * i386-tbl.h: Re-generate.
697 2018-09-13 Jan Beulich <jbeulich@suse.com>
699 * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
700 * i386-tbl.h: Re-generate.
702 2018-09-13 Jan Beulich <jbeulich@suse.com>
704 * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
705 (vpbroadcastw, rdpid): Drop NoRex64.
706 * i386-tbl.h: Re-generate.
708 2018-09-13 Jan Beulich <jbeulich@suse.com>
710 * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
711 store templates, adding D.
712 * i386-tbl.h: Re-generate.
714 2018-09-13 Jan Beulich <jbeulich@suse.com>
716 * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
717 movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
718 movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
719 vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
720 vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
721 Fold load and store templates where possible, adding D. Drop
722 IgnoreSize where it was pointlessly present. Drop redundant
724 * i386-tbl.h: Re-generate.
726 2018-09-13 Jan Beulich <jbeulich@suse.com>
728 * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
729 (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
730 (intel_operand_size): Handle v_bndmk_mode.
731 (OP_E_memory): Likewise. Produce (bad) when also riprel.
733 2018-09-08 John Darrington <john@darrington.wattle.id.au>
735 * disassemble.c (ARCH_s12z): Define if ARCH_all.
737 2018-08-31 Kito Cheng <kito@andestech.com>
739 * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
740 compressed floating point instructions.
742 2018-08-30 Kito Cheng <kito@andestech.com>
744 * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
745 riscv_opcode.xlen_requirement.
746 * riscv-opc.c (riscv_opcodes): Update for struct change.
748 2018-08-29 Martin Aberg <maberg@gaisler.com>
750 * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
751 psr (PWRPSR) instruction.
753 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
755 * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
757 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
759 * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
761 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
763 * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
764 loongson3a as an alias of gs464 for compatibility.
765 * mips-opc.c (mips_opcodes): Change Comments.
767 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
769 * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
771 (print_mips_disassembler_options): Document -M loongson-ext.
772 * mips-opc.c (LEXT2): New macro.
773 (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
775 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
777 * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
779 (parse_mips_ase_option): Handle -M loongson-ext option.
780 (print_mips_disassembler_options): Document -M loongson-ext.
781 * mips-opc.c (IL3A): Delete.
782 * mips-opc.c (LEXT): New macro.
783 (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
786 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
788 * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
790 (parse_mips_ase_option): Handle -M loongson-cam option.
791 (print_mips_disassembler_options): Document -M loongson-cam.
792 * mips-opc.c (LCAM): New macro.
793 (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
796 2018-08-21 Alan Modra <amodra@gmail.com>
798 * ppc-dis.c (operand_value_powerpc): Init "invalid".
799 (skip_optional_operands): Count optional operands, and update
800 ppc_optional_operand_value call.
801 * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
802 (extract_vlensi): Likewise.
803 (extract_fxm): Return default value for missing optional operand.
804 (extract_ls, extract_raq, extract_tbr): Likewise.
805 (insert_sxl, extract_sxl): New functions.
806 (insert_esync, extract_esync): Remove Power9 handling and simplify.
807 (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
808 flag and extra entry.
809 (powerpc_operands <SXL>): Likewise, and use insert_sxl and
812 2018-08-20 Alan Modra <amodra@gmail.com>
814 * sh-opc.h (MASK): Simplify.
816 2018-08-18 John Darrington <john@darrington.wattle.id.au>
818 * s12z-dis.c (bm_decode): Deal with cases where the mode is
819 BM_RESERVED0 or BM_RESERVED1
820 (bm_rel_decode, bm_n_bytes): Ditto.
822 2018-08-18 John Darrington <john@darrington.wattle.id.au>
826 2018-08-14 H.J. Lu <hongjiu.lu@intel.com>
828 * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
829 address with the addr32 prefix and without base nor index
832 2018-08-11 H.J. Lu <hongjiu.lu@intel.com>
834 * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
835 CPU_I686_FLAGS. Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
836 CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
837 (cpu_flags): Add CpuCMOV and CpuFXSR.
838 * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
839 fxrstor and fxrstor64. Replace Cpu686 with CpuCMOV on cmovCC.
840 * i386-init.h: Regenerated.
841 * i386-tbl.h: Likewise.
843 2018-08-06 Claudiu Zissulescu <claziss@synopsys.com>
845 * arc-regs.h: Update auxiliary registers.
847 2018-08-06 Jan Beulich <jbeulich@suse.com>
849 * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
850 (RegIP, RegIZ): Define.
851 * i386-reg.tbl: Adjust comments.
852 (rip): Use Qword instead of BaseIndex. Use RegIP.
853 (eip): Use Dword instead of BaseIndex. Use RegIP.
854 (riz): Add Qword. Use RegIZ.
855 (eiz): Add Dword. Use RegIZ.
856 * i386-tbl.h: Re-generate.
858 2018-08-03 Jan Beulich <jbeulich@suse.com>
860 * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
861 pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
862 vpmovzxdq, vpmovzxwd): Remove NoRex64.
863 * i386-tbl.h: Re-generate.
865 2018-08-03 Jan Beulich <jbeulich@suse.com>
867 * i386-gen.c (operand_types): Remove Mem field.
868 * i386-opc.h (union i386_operand_type): Remove mem field.
869 * i386-init.h, i386-tbl.h: Re-generate.
871 2018-08-01 Alan Modra <amodra@gmail.com>
873 * po/POTFILES.in: Regenerate.
875 2018-07-31 Nick Clifton <nickc@redhat.com>
877 * po/sv.po: Updated Swedish translation.
879 2018-07-31 Jan Beulich <jbeulich@suse.com>
881 * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
882 * i386-init.h, i386-tbl.h: Re-generate.
884 2018-07-31 Jan Beulich <jbeulich@suse.com>
886 * i386-opc.h (ZEROING_MASKING) Rename to ...
887 (DYNAMIC_MASKING): ... this. Adjust comment.
888 * i386-opc.tbl (MaskingMorZ): Define.
889 (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
890 vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
891 vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
892 vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
893 vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
894 vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
895 vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
896 vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
897 vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
899 2018-07-31 Jan Beulich <jbeulich@suse.com>
901 * i386-opc.tbl: Use element rather than vector size for AVX512*
902 scatter/gather insns.
903 * i386-tbl.h: Re-generate.
905 2018-07-31 Jan Beulich <jbeulich@suse.com>
907 * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
908 (cpu_flags): Drop CpuVREX.
909 * i386-opc.h (CpuVREX): Delete.
910 (union i386_cpu_flags): Remove cpuvrex.
911 * i386-init.h, i386-tbl.h: Re-generate.
913 2018-07-30 Jim Wilson <jimw@sifive.com>
915 * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
917 * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
919 2018-07-30 Andrew Jenner <andrew@codesourcery.com>
921 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
922 * Makefile.in: Regenerated.
923 * configure.ac: Add C-SKY.
924 * configure: Regenerated.
925 * csky-dis.c: New file.
926 * csky-opc.h: New file.
927 * disassemble.c (ARCH_csky): Define.
928 (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
929 * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
931 2018-07-27 Alan Modra <amodra@gmail.com>
933 * ppc-opc.c (insert_sprbat): Correct function parameter and
935 (extract_sprbat): Likewise, variable too.
937 2018-07-26 Alex Chadwick <Alex.Chadwick@cl.cam.ac.uk>
938 Alan Modra <amodra@gmail.com>
940 * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
941 (powerpc_init_dialect): Handle bfd_mach_ppc_750.
942 * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
943 support disjointed BAT.
944 (powerpc_operands): Allow extra bit in SPRBAT_MASK. Add SPRGQR.
945 (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
946 (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
948 2018-07-25 H.J. Lu <hongjiu.lu@intel.com>
949 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
951 * i386-gen.c (adjust_broadcast_modifier): New function.
952 (process_i386_opcode_modifier): Add an argument for operands.
953 Adjust the Broadcast value based on operands.
954 (output_i386_opcode): Pass operand_types to
955 process_i386_opcode_modifier.
956 (process_i386_opcodes): Pass NULL as operands to
957 process_i386_opcode_modifier.
958 * i386-opc.h (BYTE_BROADCAST): New.
959 (WORD_BROADCAST): Likewise.
960 (DWORD_BROADCAST): Likewise.
961 (QWORD_BROADCAST): Likewise.
962 (i386_opcode_modifier): Expand broadcast to 3 bits.
963 * i386-tbl.h: Regenerated.
965 2018-07-24 Alan Modra <amodra@gmail.com>
968 * or1k-desc.h: Regenerate.
970 2018-07-24 Jan Beulich <jbeulich@suse.com>
972 * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
973 vcvtusi2ss, and vcvtusi2sd.
974 * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
975 Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
976 * i386-tbl.h: Re-generate.
978 2018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
980 * arc-opc.c (extract_w6): Fix extending the sign.
982 2018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
984 * arc-tbl.h (vewt): Allow it for ARC EM family.
986 2018-07-23 Alan Modra <amodra@gmail.com>
989 * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
990 opcode variants for mtspr/mfspr encodings.
992 2018-07-20 Chenghua Xu <paul.hua.gm@gmail.com>
993 Maciej W. Rozycki <macro@mips.com>
995 * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
996 loongson3a descriptors.
997 (parse_mips_ase_option): Handle -M loongson-mmi option.
998 (print_mips_disassembler_options): Document -M loongson-mmi.
999 * mips-opc.c (LMMI): New macro.
1000 (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
1003 2018-07-19 Jan Beulich <jbeulich@suse.com>
1005 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
1006 vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
1007 IgnoreSize and [XYZ]MMword where applicable.
1008 * i386-tbl.h: Re-generate.
1010 2018-07-19 Jan Beulich <jbeulich@suse.com>
1012 * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
1013 (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
1014 (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
1015 (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
1016 * i386-tbl.h: Re-generate.
1018 2018-07-19 Jan Beulich <jbeulich@suse.com>
1020 * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
1021 AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
1022 VPCLMULQDQ templates into their respective AVX512VL counterparts
1023 where possible, using Disp8ShiftVL and CheckRegSize instead of
1024 Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
1025 * i386-tbl.h: Re-generate.
1027 2018-07-19 Jan Beulich <jbeulich@suse.com>
1029 * i386-opc.tbl: Fold AVX512DQ templates into their respective
1030 AVX512VL counterparts where possible, using Disp8ShiftVL and
1031 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1032 IgnoreSize) as appropriate.
1033 * i386-tbl.h: Re-generate.
1035 2018-07-19 Jan Beulich <jbeulich@suse.com>
1037 * i386-opc.tbl: Fold AVX512BW templates into their respective
1038 AVX512VL counterparts where possible, using Disp8ShiftVL and
1039 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1040 IgnoreSize) as appropriate.
1041 * i386-tbl.h: Re-generate.
1043 2018-07-19 Jan Beulich <jbeulich@suse.com>
1045 * i386-opc.tbl: Fold AVX512CD templates into their respective
1046 AVX512VL counterparts where possible, using Disp8ShiftVL and
1047 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1048 IgnoreSize) as appropriate.
1049 * i386-tbl.h: Re-generate.
1051 2018-07-19 Jan Beulich <jbeulich@suse.com>
1053 * i386-opc.h (DISP8_SHIFT_VL): New.
1054 * i386-opc.tbl (Disp8ShiftVL): Define.
1055 (various): Fold AVX512VL templates into their respective
1056 AVX512F counterparts where possible, using Disp8ShiftVL and
1057 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1058 IgnoreSize) as appropriate.
1059 * i386-tbl.h: Re-generate.
1061 2018-07-19 Jan Beulich <jbeulich@suse.com>
1063 * Makefile.am: Change dependencies and rule for
1064 $(srcdir)/i386-init.h.
1065 * Makefile.in: Re-generate.
1066 * i386-gen.c (process_i386_opcodes): New local variable
1067 "marker". Drop opening of input file. Recognize marker and line
1069 * i386-opc.tbl (OPCODE_I386_H): Define.
1070 (i386-opc.h): Include it.
1073 2018-07-18 H.J. Lu <hongjiu.lu@intel.com>
1076 * i386-opc.h (Byte): Update comments.
1082 (Xmmword): Likewise.
1083 (Ymmword): Likewise.
1084 (Zmmword): Likewise.
1085 * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
1087 * i386-tbl.h: Regenerated.
1089 2018-07-12 Sudakshina Das <sudi.das@arm.com>
1091 * aarch64-tbl.h (aarch64_opcode_table): Add entry for
1092 ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
1093 * aarch64-asm-2.c: Regenerate.
1094 * aarch64-dis-2.c: Regenerate.
1095 * aarch64-opc-2.c: Regenerate.
1097 2018-07-12 Tamar Christina <tamar.christina@arm.com>
1100 * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
1101 mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
1102 umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
1103 sqdmulh, sqrdmulh): Use Em16.
1105 2018-07-11 Sudakshina Das <sudi.das@arm.com>
1107 * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
1108 csdb together with them.
1109 (thumb32_opcodes): Likewise.
1111 2018-07-11 Jan Beulich <jbeulich@suse.com>
1113 * i386-opc.tbl (monitor, monitorx): Add 64-bit template
1114 requiring 32-bit registers as operands 2 and 3. Improve
1116 (mwait, mwaitx): Fold templates. Improve comments.
1117 OPERAND_TYPE_INOUTPORTREG.
1118 * i386-tbl.h: Re-generate.
1120 2018-07-11 Jan Beulich <jbeulich@suse.com>
1122 * i386-gen.c (operand_type_init): Remove
1123 OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
1124 OPERAND_TYPE_INOUTPORTREG.
1125 * i386-init.h: Re-generate.
1127 2018-07-11 Jan Beulich <jbeulich@suse.com>
1129 * i386-opc.tbl (wrssd, wrussd): Add Dword.
1130 (wrssq, wrussq): Add Qword.
1131 * i386-tbl.h: Re-generate.
1133 2018-07-11 Jan Beulich <jbeulich@suse.com>
1135 * i386-opc.h: Rename OTMax to OTNum.
1136 (OTNumOfUints): Adjust calculation.
1137 (OTUnused): Directly alias to OTNum.
1139 2018-07-09 Maciej W. Rozycki <macro@mips.com>
1141 * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
1143 (lea_reg_xys): Likewise.
1144 (print_insn_loop_primitive): Rename `reg' local variable to
1147 2018-07-06 Tamar Christina <tamar.christina@arm.com>
1150 * aarch64-tbl.h (ldarh): Fix disassembly mask.
1152 2018-07-06 Tamar Christina <tamar.christina@arm.com>
1155 * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
1156 vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
1158 2018-07-02 Maciej W. Rozycki <macro@mips.com>
1161 * mips-dis.c (mips_option_arg_t): New enumeration.
1162 (mips_options): New variable.
1163 (disassembler_options_mips): New function.
1164 (print_mips_disassembler_options): Reimplement in terms of
1165 `disassembler_options_mips'.
1166 * arm-dis.c (disassembler_options_arm): Adapt to using the
1167 `disasm_options_and_args_t' structure.
1168 * ppc-dis.c (disassembler_options_powerpc): Likewise.
1169 * s390-dis.c (disassembler_options_s390): Likewise.
1171 2018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
1173 * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
1175 * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
1176 * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
1177 * testsuite/ld-arm/tls-longplt.d: Likewise.
1179 2018-06-29 Tamar Christina <tamar.christina@arm.com>
1182 * aarch64-asm-2.c: Regenerate.
1183 * aarch64-dis-2.c: Likewise.
1184 * aarch64-opc-2.c: Likewise.
1185 * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
1186 * aarch64-opc.c (operand_general_constraint_met_p,
1187 aarch64_print_operand): Likewise.
1188 * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
1189 smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
1191 (AARCH64_OPERANDS): Add Em2.
1193 2018-06-26 Nick Clifton <nickc@redhat.com>
1195 * po/uk.po: Updated Ukranian translation.
1196 * po/de.po: Updated German translation.
1197 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1199 2018-06-26 Nick Clifton <nickc@redhat.com>
1201 * nfp-dis.c: Fix spelling mistake.
1203 2018-06-24 Nick Clifton <nickc@redhat.com>
1205 * configure: Regenerate.
1206 * po/opcodes.pot: Regenerate.
1208 2018-06-24 Nick Clifton <nickc@redhat.com>
1210 2.31 branch created.
1212 2018-06-19 Tamar Christina <tamar.christina@arm.com>
1214 * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
1215 * aarch64-asm-2.c: Regenerate.
1216 * aarch64-dis-2.c: Likewise.
1218 2018-06-21 Maciej W. Rozycki <macro@mips.com>
1220 * mips-dis.c (print_mips_disassembler_options): Fix a typo in
1221 `-M ginv' option description.
1223 2018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
1226 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
1229 2018-06-19 Simon Marchi <simon.marchi@ericsson.com>
1231 * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
1232 * configure.ac: Remove AC_PREREQ.
1233 * Makefile.in: Re-generate.
1234 * aclocal.m4: Re-generate.
1235 * configure: Re-generate.
1237 2018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
1239 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
1240 mips64r6 descriptors.
1241 (parse_mips_ase_option): Handle -Mginv option.
1242 (print_mips_disassembler_options): Document -Mginv.
1243 * mips-opc.c (decode_mips_operand) <+\>: New operand format.
1245 (mips_opcodes): Define ginvi and ginvt.
1247 2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
1248 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
1250 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
1251 * mips-opc.c (CRC, CRC64): New macros.
1252 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
1253 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
1256 2018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
1259 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1260 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1262 2018-06-06 Alan Modra <amodra@gmail.com>
1264 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
1265 setjmp. Move init for some other vars later too.
1267 2018-06-04 Max Filippov <jcmvbkbc@gmail.com>
1269 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
1270 (dis_private): Add new fields for property section tracking.
1271 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
1272 (xtensa_instruction_fits): New functions.
1273 (fetch_data): Bump minimal fetch size to 4.
1274 (print_insn_xtensa): Make struct dis_private static.
1275 Load and prepare property table on section change.
1276 Don't disassemble literals. Don't disassemble instructions that
1277 cross property table boundaries.
1279 2018-06-01 H.J. Lu <hongjiu.lu@intel.com>
1281 * configure: Regenerated.
1283 2018-06-01 Jan Beulich <jbeulich@suse.com>
1285 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
1286 * i386-tbl.h: Re-generate.
1288 2018-06-01 Jan Beulich <jbeulich@suse.com>
1290 * i386-opc.tbl (sldt, str): Add NoRex64.
1291 * i386-tbl.h: Re-generate.
1293 2018-06-01 Jan Beulich <jbeulich@suse.com>
1295 * i386-opc.tbl (invpcid): Add Oword.
1296 * i386-tbl.h: Re-generate.
1298 2018-06-01 Alan Modra <amodra@gmail.com>
1300 * sysdep.h (_bfd_error_handler): Don't declare.
1301 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
1302 * rl78-decode.opc: Likewise.
1303 * msp430-decode.c: Regenerate.
1304 * rl78-decode.c: Regenerate.
1306 2018-05-30 Amit Pawar <Amit.Pawar@amd.com>
1308 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
1309 * i386-init.h : Regenerated.
1311 2018-05-25 Alan Modra <amodra@gmail.com>
1313 * Makefile.in: Regenerate.
1314 * po/POTFILES.in: Regenerate.
1316 2018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
1318 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
1319 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
1320 (insert_bab, extract_bab, insert_btab, extract_btab,
1321 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
1322 (BAT, BBA VBA RBS XB6S): Delete macros.
1323 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
1324 (BB, BD, RBX, XC6): Update for new macros.
1325 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
1326 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
1327 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
1328 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
1330 2018-05-18 John Darrington <john@darrington.wattle.id.au>
1332 * Makefile.am: Add support for s12z architecture.
1333 * configure.ac: Likewise.
1334 * disassemble.c: Likewise.
1335 * disassemble.h: Likewise.
1336 * Makefile.in: Regenerate.
1337 * configure: Regenerate.
1338 * s12z-dis.c: New file.
1341 2018-05-18 Alan Modra <amodra@gmail.com>
1343 * nfp-dis.c: Don't #include libbfd.h.
1344 (init_nfp3200_priv): Use bfd_get_section_contents.
1345 (nit_nfp6000_mecsr_sec): Likewise.
1347 2018-05-17 Nick Clifton <nickc@redhat.com>
1349 * po/zh_CN.po: Updated simplified Chinese translation.
1351 2018-05-16 Tamar Christina <tamar.christina@arm.com>
1354 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
1355 * aarch64-dis-2.c: Regenerate.
1357 2018-05-15 Tamar Christina <tamar.christina@arm.com>
1360 * aarch64-asm.c (opintl.h): Include.
1361 (aarch64_ins_sysreg): Enforce read/write constraints.
1362 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
1363 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
1364 (F_REG_READ, F_REG_WRITE): New.
1365 * aarch64-opc.c (aarch64_print_operand): Generate notes for
1366 AARCH64_OPND_SYSREG.
1367 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
1368 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
1369 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
1370 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
1371 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
1372 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
1373 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
1374 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
1375 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
1376 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
1377 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
1378 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
1379 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
1380 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
1381 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
1382 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
1383 msr (F_SYS_WRITE), mrs (F_SYS_READ).
1385 2018-05-15 Tamar Christina <tamar.christina@arm.com>
1388 * aarch64-dis.c (no_notes: New.
1389 (parse_aarch64_dis_option): Support notes.
1390 (aarch64_decode_insn, print_operands): Likewise.
1391 (print_aarch64_disassembler_options): Document notes.
1392 * aarch64-opc.c (aarch64_print_operand): Support notes.
1394 2018-05-15 Tamar Christina <tamar.christina@arm.com>
1397 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
1398 and take error struct.
1399 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
1400 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
1401 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
1402 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
1403 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
1404 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
1405 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
1406 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
1407 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
1408 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
1409 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
1410 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
1411 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
1412 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
1413 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
1414 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
1415 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
1416 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1417 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
1418 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
1419 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
1420 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
1421 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
1422 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
1423 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
1424 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
1425 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
1426 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
1427 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
1428 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
1429 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
1430 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
1431 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
1432 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
1433 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
1434 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
1435 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
1436 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
1437 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
1438 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
1439 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
1440 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
1441 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
1442 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1443 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
1444 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
1445 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
1446 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
1447 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
1448 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
1449 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
1450 (determine_disassembling_preference, aarch64_decode_insn,
1451 print_insn_aarch64_word, print_insn_data): Take errors struct.
1452 (print_insn_aarch64): Use errors.
1453 * aarch64-asm-2.c: Regenerate.
1454 * aarch64-dis-2.c: Regenerate.
1455 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
1456 boolean in aarch64_insert_operan.
1457 (print_operand_extractor): Likewise.
1458 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
1460 2018-05-15 Francois H. Theron <francois.theron@netronome.com>
1462 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
1464 2018-05-09 H.J. Lu <hongjiu.lu@intel.com>
1466 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
1468 2018-05-09 Sebastian Rasmussen <sebras@gmail.com>
1470 * cr16-opc.c (cr16_instruction): Comment typo fix.
1471 * hppa-dis.c (print_insn_hppa): Likewise.
1473 2018-05-08 Jim Wilson <jimw@sifive.com>
1475 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
1476 (match_c_slli64, match_srxi_as_c_srxi): New.
1477 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
1478 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
1479 <c.slli, c.srli, c.srai>: Use match_s_slli.
1480 <c.slli64, c.srli64, c.srai64>: New.
1482 2018-05-08 Alan Modra <amodra@gmail.com>
1484 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
1485 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
1486 partition opcode space for index lookup.
1488 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
1490 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
1491 <insn_length>: ...with this. Update usage.
1492 Remove duplicate call to *info->memory_error_func.
1494 2018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1495 H.J. Lu <hongjiu.lu@intel.com>
1497 * i386-dis.c (Gva): New.
1498 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
1499 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
1500 (prefix_table): New instructions (see prefix above).
1501 (mod_table): New instructions (see prefix above).
1502 (OP_G): Handle va_mode.
1503 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
1504 CPU_MOVDIR64B_FLAGS.
1505 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
1506 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
1507 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
1508 * i386-opc.tbl: Add movidir{i,64b}.
1509 * i386-init.h: Regenerated.
1510 * i386-tbl.h: Likewise.
1512 2018-05-07 H.J. Lu <hongjiu.lu@intel.com>
1514 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
1516 * i386-opc.h (AddrPrefixOp0): Renamed to ...
1517 (AddrPrefixOpReg): This.
1518 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
1519 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
1521 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
1523 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
1524 (vle_num_opcodes): Likewise.
1525 (spe2_num_opcodes): Likewise.
1526 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
1527 initialization loop.
1528 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
1529 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
1532 2018-05-01 Tamar Christina <tamar.christina@arm.com>
1534 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
1536 2018-04-30 Francois H. Theron <francois.theron@netronome.com>
1538 Makefile.am: Added nfp-dis.c.
1539 configure.ac: Added bfd_nfp_arch.
1540 disassemble.h: Added print_insn_nfp prototype.
1541 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
1542 nfp-dis.c: New, for NFP support.
1543 po/POTFILES.in: Added nfp-dis.c to the list.
1544 Makefile.in: Regenerate.
1545 configure: Regenerate.
1547 2018-04-26 Jan Beulich <jbeulich@suse.com>
1549 * i386-opc.tbl: Fold various non-memory operand AVX512VL
1550 templates into their base ones.
1551 * i386-tlb.h: Re-generate.
1553 2018-04-26 Jan Beulich <jbeulich@suse.com>
1555 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
1556 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
1557 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
1558 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
1559 * i386-init.h: Re-generate.
1561 2018-04-26 Jan Beulich <jbeulich@suse.com>
1563 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
1564 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
1565 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
1566 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
1568 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1570 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1572 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
1573 cpuregzmm, and cpuregmask.
1574 * i386-init.h: Re-generate.
1575 * i386-tbl.h: Re-generate.
1577 2018-04-26 Jan Beulich <jbeulich@suse.com>
1579 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
1580 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
1581 * i386-init.h: Re-generate.
1583 2018-04-26 Jan Beulich <jbeulich@suse.com>
1585 * i386-gen.c (VexImmExt): Delete.
1586 * i386-opc.h (VexImmExt, veximmext): Delete.
1587 * i386-opc.tbl: Drop all VexImmExt uses.
1588 * i386-tlb.h: Re-generate.
1590 2018-04-25 Jan Beulich <jbeulich@suse.com>
1592 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
1593 register-only forms.
1594 * i386-tlb.h: Re-generate.
1596 2018-04-25 Tamar Christina <tamar.christina@arm.com>
1598 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
1600 2018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1602 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
1604 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
1605 (cpu_flags): Add CpuCLDEMOTE.
1606 * i386-init.h: Regenerate.
1607 * i386-opc.h (enum): Add CpuCLDEMOTE,
1608 (i386_cpu_flags): Add cpucldemote.
1609 * i386-opc.tbl: Add cldemote.
1610 * i386-tbl.h: Regenerate.
1612 2018-04-16 Alan Modra <amodra@gmail.com>
1614 * Makefile.am: Remove sh5 and sh64 support.
1615 * configure.ac: Likewise.
1616 * disassemble.c: Likewise.
1617 * disassemble.h: Likewise.
1618 * sh-dis.c: Likewise.
1619 * sh64-dis.c: Delete.
1620 * sh64-opc.c: Delete.
1621 * sh64-opc.h: Delete.
1622 * Makefile.in: Regenerate.
1623 * configure: Regenerate.
1624 * po/POTFILES.in: Regenerate.
1626 2018-04-16 Alan Modra <amodra@gmail.com>
1628 * Makefile.am: Remove w65 support.
1629 * configure.ac: Likewise.
1630 * disassemble.c: Likewise.
1631 * disassemble.h: Likewise.
1632 * w65-dis.c: Delete.
1633 * w65-opc.h: Delete.
1634 * Makefile.in: Regenerate.
1635 * configure: Regenerate.
1636 * po/POTFILES.in: Regenerate.
1638 2018-04-16 Alan Modra <amodra@gmail.com>
1640 * configure.ac: Remove we32k support.
1641 * configure: Regenerate.
1643 2018-04-16 Alan Modra <amodra@gmail.com>
1645 * Makefile.am: Remove m88k support.
1646 * configure.ac: Likewise.
1647 * disassemble.c: Likewise.
1648 * disassemble.h: Likewise.
1649 * m88k-dis.c: Delete.
1650 * Makefile.in: Regenerate.
1651 * configure: Regenerate.
1652 * po/POTFILES.in: Regenerate.
1654 2018-04-16 Alan Modra <amodra@gmail.com>
1656 * Makefile.am: Remove i370 support.
1657 * configure.ac: Likewise.
1658 * disassemble.c: Likewise.
1659 * disassemble.h: Likewise.
1660 * i370-dis.c: Delete.
1661 * i370-opc.c: Delete.
1662 * Makefile.in: Regenerate.
1663 * configure: Regenerate.
1664 * po/POTFILES.in: Regenerate.
1666 2018-04-16 Alan Modra <amodra@gmail.com>
1668 * Makefile.am: Remove h8500 support.
1669 * configure.ac: Likewise.
1670 * disassemble.c: Likewise.
1671 * disassemble.h: Likewise.
1672 * h8500-dis.c: Delete.
1673 * h8500-opc.h: Delete.
1674 * Makefile.in: Regenerate.
1675 * configure: Regenerate.
1676 * po/POTFILES.in: Regenerate.
1678 2018-04-16 Alan Modra <amodra@gmail.com>
1680 * configure.ac: Remove tahoe support.
1681 * configure: Regenerate.
1683 2018-04-15 H.J. Lu <hongjiu.lu@intel.com>
1685 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
1687 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
1689 * i386-tbl.h: Regenerated.
1691 2018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1693 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
1694 PREFIX_MOD_1_0FAE_REG_6.
1696 (OP_E_register): Use va_mode.
1697 * i386-dis-evex.h (prefix_table):
1698 New instructions (see prefixes above).
1699 * i386-gen.c (cpu_flag_init): Add WAITPKG.
1700 (cpu_flags): Likewise.
1701 * i386-opc.h (enum): Likewise.
1702 (i386_cpu_flags): Likewise.
1703 * i386-opc.tbl: Add umonitor, umwait, tpause.
1704 * i386-init.h: Regenerate.
1705 * i386-tbl.h: Likewise.
1707 2018-04-11 Alan Modra <amodra@gmail.com>
1709 * opcodes/i860-dis.c: Delete.
1710 * opcodes/i960-dis.c: Delete.
1711 * Makefile.am: Remove i860 and i960 support.
1712 * configure.ac: Likewise.
1713 * disassemble.c: Likewise.
1714 * disassemble.h: Likewise.
1715 * Makefile.in: Regenerate.
1716 * configure: Regenerate.
1717 * po/POTFILES.in: Regenerate.
1719 2018-04-04 H.J. Lu <hongjiu.lu@intel.com>
1722 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
1724 (print_insn): Clear vex instead of vex.evex.
1726 2018-04-04 Nick Clifton <nickc@redhat.com>
1728 * po/es.po: Updated Spanish translation.
1730 2018-03-28 Jan Beulich <jbeulich@suse.com>
1732 * i386-gen.c (opcode_modifiers): Delete VecESize.
1733 * i386-opc.h (VecESize): Delete.
1734 (struct i386_opcode_modifier): Delete vecesize.
1735 * i386-opc.tbl: Drop VecESize.
1736 * i386-tlb.h: Re-generate.
1738 2018-03-28 Jan Beulich <jbeulich@suse.com>
1740 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
1741 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
1742 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
1743 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
1744 * i386-tlb.h: Re-generate.
1746 2018-03-28 Jan Beulich <jbeulich@suse.com>
1748 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
1750 * i386-tlb.h: Re-generate.
1752 2018-03-28 Jan Beulich <jbeulich@suse.com>
1754 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
1755 (vex_len_table): Drop Y for vcvt*2si.
1756 (putop): Replace plain 'Y' handling by abort().
1758 2018-03-28 Nick Clifton <nickc@redhat.com>
1761 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
1762 instructions with only a base address register.
1763 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
1764 handle AARHC64_OPND_SVE_ADDR_R.
1765 (aarch64_print_operand): Likewise.
1766 * aarch64-asm-2.c: Regenerate.
1767 * aarch64_dis-2.c: Regenerate.
1768 * aarch64-opc-2.c: Regenerate.
1770 2018-03-22 Jan Beulich <jbeulich@suse.com>
1772 * i386-opc.tbl: Drop VecESize from register only insn forms and
1773 memory forms not allowing broadcast.
1774 * i386-tlb.h: Re-generate.
1776 2018-03-22 Jan Beulich <jbeulich@suse.com>
1778 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
1779 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
1780 sha256*): Drop Disp<N>.
1782 2018-03-22 Jan Beulich <jbeulich@suse.com>
1784 * i386-dis.c (EbndS, bnd_swap_mode): New.
1785 (prefix_table): Use EbndS.
1786 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
1787 * i386-opc.tbl (bndmov): Move misplaced Load.
1788 * i386-tlb.h: Re-generate.
1790 2018-03-22 Jan Beulich <jbeulich@suse.com>
1792 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
1793 templates allowing memory operands and folded ones for register
1795 * i386-tlb.h: Re-generate.
1797 2018-03-22 Jan Beulich <jbeulich@suse.com>
1799 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
1800 256-bit templates. Drop redundant leftover Disp<N>.
1801 * i386-tlb.h: Re-generate.
1803 2018-03-14 Kito Cheng <kito.cheng@gmail.com>
1805 * riscv-opc.c (riscv_insn_types): New.
1807 2018-03-13 Nick Clifton <nickc@redhat.com>
1809 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1811 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1813 * i386-opc.tbl: Add Optimize to clr.
1814 * i386-tbl.h: Regenerated.
1816 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1818 * i386-gen.c (opcode_modifiers): Remove OldGcc.
1819 * i386-opc.h (OldGcc): Removed.
1820 (i386_opcode_modifier): Remove oldgcc.
1821 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
1822 instructions for old (<= 2.8.1) versions of gcc.
1823 * i386-tbl.h: Regenerated.
1825 2018-03-08 Jan Beulich <jbeulich@suse.com>
1827 * i386-opc.h (EVEXDYN): New.
1828 * i386-opc.tbl: Fold various AVX512VL templates.
1829 * i386-tlb.h: Re-generate.
1831 2018-03-08 Jan Beulich <jbeulich@suse.com>
1833 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1834 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1835 vpexpandd, vpexpandq): Fold AFX512VF templates.
1836 * i386-tlb.h: Re-generate.
1838 2018-03-08 Jan Beulich <jbeulich@suse.com>
1840 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
1841 Fold 128- and 256-bit VEX-encoded templates.
1842 * i386-tlb.h: Re-generate.
1844 2018-03-08 Jan Beulich <jbeulich@suse.com>
1846 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1847 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1848 vpexpandd, vpexpandq): Fold AVX512F templates.
1849 * i386-tlb.h: Re-generate.
1851 2018-03-08 Jan Beulich <jbeulich@suse.com>
1853 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
1854 64-bit templates. Drop Disp<N>.
1855 * i386-tlb.h: Re-generate.
1857 2018-03-08 Jan Beulich <jbeulich@suse.com>
1859 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
1860 and 256-bit templates.
1861 * i386-tlb.h: Re-generate.
1863 2018-03-08 Jan Beulich <jbeulich@suse.com>
1865 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
1866 * i386-tlb.h: Re-generate.
1868 2018-03-08 Jan Beulich <jbeulich@suse.com>
1870 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
1872 * i386-tlb.h: Re-generate.
1874 2018-03-08 Jan Beulich <jbeulich@suse.com>
1876 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
1877 * i386-tlb.h: Re-generate.
1879 2018-03-08 Jan Beulich <jbeulich@suse.com>
1881 * i386-gen.c (opcode_modifiers): Delete FloatD.
1882 * i386-opc.h (FloatD): Delete.
1883 (struct i386_opcode_modifier): Delete floatd.
1884 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
1886 * i386-tlb.h: Re-generate.
1888 2018-03-08 Jan Beulich <jbeulich@suse.com>
1890 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
1892 2018-03-08 Jan Beulich <jbeulich@suse.com>
1894 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
1895 * i386-tlb.h: Re-generate.
1897 2018-03-08 Jan Beulich <jbeulich@suse.com>
1899 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
1901 * i386-tlb.h: Re-generate.
1903 2018-03-07 Alan Modra <amodra@gmail.com>
1905 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
1907 * disassemble.h (print_insn_rs6000): Delete.
1908 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
1909 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
1910 (print_insn_rs6000): Delete.
1912 2018-03-03 Alan Modra <amodra@gmail.com>
1914 * sysdep.h (opcodes_error_handler): Define.
1915 (_bfd_error_handler): Declare.
1916 * Makefile.am: Remove stray #.
1917 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
1919 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
1920 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
1921 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
1922 opcodes_error_handler to print errors. Standardize error messages.
1923 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
1924 and include opintl.h.
1925 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
1926 * i386-gen.c: Standardize error messages.
1927 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
1928 * Makefile.in: Regenerate.
1929 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
1930 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
1931 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
1932 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
1933 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
1934 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
1935 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
1936 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
1937 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
1938 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
1939 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
1940 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
1941 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
1943 2018-03-01 H.J. Lu <hongjiu.lu@intel.com>
1945 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
1946 vpsub[bwdq] instructions.
1947 * i386-tbl.h: Regenerated.
1949 2018-03-01 Alan Modra <amodra@gmail.com>
1951 * configure.ac (ALL_LINGUAS): Sort.
1952 * configure: Regenerate.
1954 2018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
1956 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
1957 macro by assignements.
1959 2018-02-27 H.J. Lu <hongjiu.lu@intel.com>
1962 * i386-gen.c (opcode_modifiers): Add Optimize.
1963 * i386-opc.h (Optimize): New enum.
1964 (i386_opcode_modifier): Add optimize.
1965 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
1966 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
1967 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
1968 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
1969 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
1971 * i386-tbl.h: Regenerated.
1973 2018-02-26 Alan Modra <amodra@gmail.com>
1975 * crx-dis.c (getregliststring): Allocate a large enough buffer
1976 to silence false positive gcc8 warning.
1978 2018-02-22 Shea Levy <shea@shealevy.com>
1980 * disassemble.c (ARCH_riscv): Define if ARCH_all.
1982 2018-02-22 H.J. Lu <hongjiu.lu@intel.com>
1984 * i386-opc.tbl: Add {rex},
1985 * i386-tbl.h: Regenerated.
1987 2018-02-20 Maciej W. Rozycki <macro@mips.com>
1989 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
1990 (mips16_opcodes): Replace `M' with `m' for "restore".
1992 2018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
1994 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
1996 2018-02-13 Maciej W. Rozycki <macro@mips.com>
1998 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
1999 variable to `function_index'.
2001 2018-02-13 Nick Clifton <nickc@redhat.com>
2004 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
2005 about truncation of printing.
2007 2018-02-12 Henry Wong <henry@stuffedcow.net>
2009 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
2011 2018-02-05 Nick Clifton <nickc@redhat.com>
2013 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2015 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2017 * i386-dis.c (enum): Add pconfig.
2018 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
2019 (cpu_flags): Add CpuPCONFIG.
2020 * i386-opc.h (enum): Add CpuPCONFIG.
2021 (i386_cpu_flags): Add cpupconfig.
2022 * i386-opc.tbl: Add PCONFIG instruction.
2023 * i386-init.h: Regenerate.
2024 * i386-tbl.h: Likewise.
2026 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2028 * i386-dis.c (enum): Add PREFIX_0F09.
2029 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
2030 (cpu_flags): Add CpuWBNOINVD.
2031 * i386-opc.h (enum): Add CpuWBNOINVD.
2032 (i386_cpu_flags): Add cpuwbnoinvd.
2033 * i386-opc.tbl: Add WBNOINVD instruction.
2034 * i386-init.h: Regenerate.
2035 * i386-tbl.h: Likewise.
2037 2018-01-17 Jim Wilson <jimw@sifive.com>
2039 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
2041 2018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2043 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
2044 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
2045 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
2046 (cpu_flags): Add CpuIBT, CpuSHSTK.
2047 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
2048 (i386_cpu_flags): Add cpuibt, cpushstk.
2049 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
2050 * i386-init.h: Regenerate.
2051 * i386-tbl.h: Likewise.
2053 2018-01-16 Nick Clifton <nickc@redhat.com>
2055 * po/pt_BR.po: Updated Brazilian Portugese translation.
2056 * po/de.po: Updated German translation.
2058 2018-01-15 Jim Wilson <jimw@sifive.com>
2060 * riscv-opc.c (match_c_nop): New.
2061 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
2063 2018-01-15 Nick Clifton <nickc@redhat.com>
2065 * po/uk.po: Updated Ukranian translation.
2067 2018-01-13 Nick Clifton <nickc@redhat.com>
2069 * po/opcodes.pot: Regenerated.
2071 2018-01-13 Nick Clifton <nickc@redhat.com>
2073 * configure: Regenerate.
2075 2018-01-13 Nick Clifton <nickc@redhat.com>
2077 2.30 branch created.
2079 2018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2081 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
2082 * i386-tbl.h: Regenerate.
2084 2018-01-10 Jan Beulich <jbeulich@suse.com>
2086 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
2087 * i386-tbl.h: Re-generate.
2089 2018-01-10 Jan Beulich <jbeulich@suse.com>
2091 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
2092 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
2093 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
2094 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
2095 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
2096 Disp8MemShift of AVX512VL forms.
2097 * i386-tbl.h: Re-generate.
2099 2018-01-09 Jim Wilson <jimw@sifive.com>
2101 * riscv-dis.c (maybe_print_address): If base_reg is zero,
2102 then the hi_addr value is zero.
2104 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
2106 * arm-dis.c (arm_opcodes): Add csdb.
2107 (thumb32_opcodes): Add csdb.
2109 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
2111 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
2112 * aarch64-asm-2.c: Regenerate.
2113 * aarch64-dis-2.c: Regenerate.
2114 * aarch64-opc-2.c: Regenerate.
2116 2018-01-08 H.J. Lu <hongjiu.lu@intel.com>
2119 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
2120 Remove AVX512 vmovd with 64-bit operands.
2121 * i386-tbl.h: Regenerated.
2123 2018-01-05 Jim Wilson <jimw@sifive.com>
2125 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
2128 2018-01-03 Alan Modra <amodra@gmail.com>
2130 Update year range in copyright notice of all files.
2132 2018-01-02 Jan Beulich <jbeulich@suse.com>
2134 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
2135 and OPERAND_TYPE_REGZMM entries.
2137 For older changes see ChangeLog-2017
2139 Copyright (C) 2018 Free Software Foundation, Inc.
2141 Copying and distribution of this file, with or without modification,
2142 are permitted in any medium without royalty provided the copyright
2143 notice and this notice are preserved.
2149 version-control: never