1 2020-09-28 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
3 * aarch64-opc.c: Add TRBE system registers TRBIDR_EL1 , TRBBASER_EL1 ,
4 TRBLIMITR_EL1 , TRBMAR_EL1 , TRBPTR_EL1, TRBSR_EL1 and TRBTRG_EL1.
6 2020-09-26 Alan Modra <amodra@gmail.com>
8 * csky-opc.h: Formatting.
9 (GENERAL_REG_BANK): Correct spelling. Update use throughout file.
10 (get_register_name): Mask arch with CSKY_ARCH_MASK for shift,
12 (get_register_number): Likewise.
13 * csky-dis.c (get_gr_name, get_cr_name): Don't mask mach_flag.
15 2020-09-24 Lili Cui <lili.cui@intel.com>
18 * i386-dis.c (enum): Put MOD_VEX_0F38* together.
20 2020-09-24 Andrew Burgess <andrew.burgess@embecosm.com>
22 * csky-dis.c (csky_output_operand): Enclose body of if in curly
25 2020-09-24 Lili Cui <lili.cui@intel.com>
27 * i386-dis.c (enum): Add PREFIX_0F01_REG_1_RM_5,
28 PREFIX_0F01_REG_1_RM_6, PREFIX_0F01_REG_1_RM_7,
29 X86_64_0F01_REG_1_RM_5_P_2, X86_64_0F01_REG_1_RM_6_P_2,
30 X86_64_0F01_REG_1_RM_7_P_2.
31 (prefix_table): Likewise.
32 (x86_64_table): Likewise.
34 * i386-gen.c (cpu_flag_init): Add CPU_TDX_FLAGS
35 and CPU_ANY_TDX_FLAGS.
36 (cpu_flags): Add CpuTDX.
37 * i386-opc.h (enum): Add CpuTDX.
38 (i386_cpu_flags): Add cputdx.
39 * i386-opc.tbl: Add TDX insns.
40 * i386-init.h: Regenerate.
41 * i386-tbl.h: Likewise.
43 2020-09-17 Cooper Qu <<cooper.qu@linux.alibaba.com>>
45 * csky-dis.c (using_abi): New.
46 (parse_csky_dis_options): New function.
47 (get_gr_name): New function.
48 (get_cr_name): New function.
49 (csky_output_operand): Use get_gr_name and get_cr_name to
50 disassemble and add handle of OPRND_TYPE_IMM5b_LS.
51 (print_insn_csky): Parse disassembler options.
52 * csky-opc.h (OPRND_TYPE_IMM5b_LS): New enum.
53 (GENARAL_REG_BANK): Define.
54 (REG_SUPPORT_ALL): Define.
55 (REG_SUPPORT_ALL): New.
57 (REG_SUPPORT_A): Define.
58 (REG_SUPPORT_B): Define.
59 (REG_SUPPORT_C): Define.
60 (REG_SUPPORT_D): Define.
61 (REG_SUPPORT_E): Define.
62 (csky_abiv1_general_regs): New.
63 (csky_abiv1_control_regs): New.
64 (csky_abiv2_general_regs): New.
65 (csky_abiv2_control_regs): New.
66 (get_register_name): New function.
67 (get_register_number): New function.
68 (csky_get_general_reg_name): New function.
69 (csky_get_general_regno): New function.
70 (csky_get_control_reg_name): New function.
71 (csky_get_control_regno): New function.
72 (csky_v2_opcodes): Prefer two oprerans format for bclri and
73 bseti, strengthen the operands legality check of addc, zext
76 2020-09-23 Lili Cui <lili.cui@intel.com>
78 * i386-dis.c (enum): Add REG_0F38D8_PREFIX_1,
79 MOD_0F38FA_PREFIX_1, MOD_0F38FB_PREFIX_1,
80 MOD_0F38DC_PREFIX_1, MOD_0F38DD_PREFIX_1,
81 MOD_0F38DE_PREFIX_1, MOD_0F38DF_PREFIX_1,
82 PREFIX_0F38D8, PREFIX_0F38FA, PREFIX_0F38FB.
83 (reg_table): New instructions (see prefixes above).
84 (prefix_table): Likewise.
85 (three_byte_table): Likewise.
87 * i386-gen.c (cpu_flag_init): Add CPU_KL_FLAGS, CPU_WIDE_KL_FLAGS,
88 CPU_ANY_KL_FLAGS and CPU_ANY_WIDE_KL_FLAGS.
89 (cpu_flags): Likewise.
90 (operand_type_init): Likewise.
91 * i386-opc.h (enum): Add CpuKL and CpuWide_KL.
92 (i386_cpu_flags): Add cpukl and cpuwide_kl.
93 * i386-opc.tbl: Add KL and WIDE_KL insns.
94 * i386-init.h: Regenerate.
95 * i386-tbl.h: Likewise.
97 2020-09-21 Alan Modra <amodra@gmail.com>
99 * rx-dis.c (flag_names): Add missing comma.
100 (register_names, flag_names, double_register_names),
101 (double_register_high_names, double_register_low_names),
102 (double_control_register_names, double_condition_names): Remove
105 2020-09-18 David Faust <david.faust@oracle.com>
107 * bpf-desc.c: Regenerate.
108 * bpf-desc.h: Likewise.
109 * bpf-opc.c: Likewise.
110 * bpf-opc.h: Likewise.
112 2020-09-16 Andrew Burgess <andrew.burgess@embecosm.com>
114 * csky-dis.c (csky_get_disassembler): Don't return NULL when there
117 2020-09-16 Alan Modra <amodra@gmail.com>
119 * ppc-dis.c (ppc_symbol_is_valid): Adjust elf_symbol_from invocation.
121 2020-09-10 Nick Clifton <nickc@redhat.com>
123 * ppc-dis.c (ppc_symbol_is_valid): New function. Returns false
124 for hidden, local, no-type symbols.
125 (disassemble_init_powerpc): Point the symbol_is_valid field in the
126 info structure at the new function.
128 2020-09-10 Cooper Qu <cooper.qu@linux.alibaba.com>
130 * csky-opc.h (csky_v2_opcodes): Add L2Cache instructions.
131 * testsuite/gas/csky/cskyv2_ck860.d : Adjust to icache.iva
134 2020-09-10 Nick Clifton <nickc@redhat.com>
136 * csky-dis.c (csky_output_operand): Coerce the immediate values to
137 long before printing.
139 2020-09-10 Alan Modra <amodra@gmail.com>
141 * csky-dis.c (csky_output_operand): Don't sprintf str to itself.
143 2020-09-07 Cooper Qu <cooper.qu@linux.alibaba.com>
145 * csky-opc.h (csky_v2_opcodes): Change mvtc and mulsw's
148 2020-09-07 Cooper Qu <cooper.qu@linux.alibaba.com>
150 * csky-dis.c (csky_output_operand): Add handlers for
151 OPRND_TYPE_HFLOAT_FMOVI, OPRND_TYPE_SFLOAT_FMOVI and
152 OPRND_TYPE_DFLOAT_FMOVI. Refine OPRND_TYPE_FREGLIST_DASH
153 to support FPUV3 instructions.
154 * csky-opc.h (enum operand_type): New enum OPRND_TYPE_IMM9b,
155 OPRND_TYPE_HFLOAT_FMOVI, OPRND_TYPE_SFLOAT_FMOVI and
156 OPRND_TYPE_DFLOAT_FMOVI.
157 (OPRND_MASK_4_5, OPRND_MASK_6, OPRND_MASK_6_7, OPRND_MASK_6_8,
158 OPRND_MASK_7, OPRND_MASK_7_8, OPRND_MASK_17_24,
159 OPRND_MASK_20, OPRND_MASK_20_21, OPRND_MASK_20_22,
160 OPRND_MASK_20_23, OPRND_MASK_20_24, OPRND_MASK_20_25,
161 OPRND_MASK_0_3or5_8, OPRND_MASK_0_3or6_7, OPRND_MASK_0_3or25,
162 OPRND_MASK_0_4or21_24, OPRND_MASK_5or20_21,
163 OPRND_MASK_5or20_22, OPRND_MASK_5or20_23, OPRND_MASK_5or20_24,
164 OPRND_MASK_5or20_25, OPRND_MASK_8_9or21_25,
165 OPRND_MASK_8_9or16_25, OPRND_MASK_4_6or20, OPRND_MASK_5_7or20,
166 OPRND_MASK_4_5or20or25, OPRND_MASK_4_6or20or25,
167 OPRND_MASK_4_7or20or25, OPRND_MASK_6_9or17_24,
168 OPRND_MASK_6_7or20, OPRND_MASK_6or20, OPRND_MASK_7or20,
169 OPRND_MASK_5or8_9or16_25, OPRND_MASK_5or8_9or20_25): Define.
170 (csky_v2_opcodes): Add FPUV3 instructions.
172 2020-09-08 Alex Coplan <alex.coplan@arm.com>
174 * aarch64-dis.c (print_operands): Pass CPU features to
175 aarch64_print_operand().
176 * aarch64-opc.c (aarch64_print_operand): Use CPU features to determine
177 preferred disassembly of system registers.
178 (SR_RNG): Refactor to use new SR_FEAT2 macro.
184 (SR_EXPAND_ELx): New.
185 (SR_EXPAND_EL12): New.
186 (aarch64_sys_regs): Specify which registers are only on
187 A-profile, add R-profile system registers.
191 (aarch64_sys_ins_reg_supported_p): Reject EL3 registers for
194 2020-09-08 Alex Coplan <alex.coplan@arm.com>
196 * aarch64-tbl.h (aarch64_feature_v8_r): New.
199 (aarch64_opcode_table): Add dfb.
200 * aarch64-opc-2.c: Regenerate.
201 * aarch64-asm-2.c: Regenerate.
202 * aarch64-dis-2.c: Regenerate.
204 2020-09-08 Alex Coplan <alex.coplan@arm.com>
206 * aarch64-dis.c (arch_variant): New.
207 (determine_disassembling_preference): Disassemble according to
209 (select_aarch64_variant): New.
210 (print_insn_aarch64): Set feature set.
212 2020-09-02 Alan Modra <amodra@gmail.com>
214 * v850-opc.c (insert_i5div1, insert_i5div2, insert_i5div3),
215 (insert_d5_4, insert_d8_6, insert_d8_7, insert_v8, insert_d9),
216 (insert_u16_loop, insert_d16_15, insert_d16_16, insert_d17_16),
217 (insert_d22, insert_d23, insert_d23_align1, insert_i9, insert_u9),
218 (insert_spe, insert_r4, insert_POS, insert_WIDTH, insert_SELID),
219 (insert_VECTOR8, insert_VECTOR5, insert_CACHEOP, insert_PREFOP),
220 (nsert_IMM10U, insert_SRSEL1, insert_SRSEL2): Use unsigned long
221 for value parameter and update code to suit.
222 (extract_d9, extract_d16_15, extract_d16_16, extract_d17_16),
223 (extract_d22, extract_d23, extract_i9): Use unsigned long variables.
225 2020-09-02 Alan Modra <amodra@gmail.com>
227 * i386-dis.c (OP_E_memory): Don't cast to signed type when
229 (get32, get32s): Use unsigned types in shift expressions.
231 2020-09-02 Alan Modra <amodra@gmail.com>
233 * csky-dis.c (print_insn_csky): Use unsigned type for "given".
235 2020-09-02 Alan Modra <amodra@gmail.com>
237 * crx-dis.c: Whitespace.
238 (print_arg): Use unsigned type for longdisp and mask variables,
239 and for left shift constant.
241 2020-09-02 Alan Modra <amodra@gmail.com>
243 * cgen-ibld.in (insert_normal, extract_normal): Use 1UL in left shift.
244 * bpf-ibld.c: Regenerate.
245 * epiphany-ibld.c: Regenerate.
246 * fr30-ibld.c: Regenerate.
247 * frv-ibld.c: Regenerate.
248 * ip2k-ibld.c: Regenerate.
249 * iq2000-ibld.c: Regenerate.
250 * lm32-ibld.c: Regenerate.
251 * m32c-ibld.c: Regenerate.
252 * m32r-ibld.c: Regenerate.
253 * mep-ibld.c: Regenerate.
254 * mt-ibld.c: Regenerate.
255 * or1k-ibld.c: Regenerate.
256 * xc16x-ibld.c: Regenerate.
257 * xstormy16-ibld.c: Regenerate.
259 2020-09-02 Alan Modra <amodra@gmail.com>
261 * bfin-dis.c (MASKBITS): Use SIGNBIT.
263 2020-09-02 Cooper Qu <cooper.qu@linux.alibaba.com>
265 * csky-opc.h (csky_v2_opcodes): Move divul and divsl
266 to CSKYV2_ISA_3E3R3 instruction set.
268 2020-09-02 Cooper Qu <cooper.qu@linux.alibaba.com>
270 * csky-opc.h (csky_v2_opcodes): Fix Encode of mulsws.
272 2020-09-01 Alan Modra <amodra@gmail.com>
274 * mep-ibld.c: Regenerate.
276 2020-08-31 Cooper Qu <cooper.qu@linux.alibaba.com>
278 * csky-dis.c (csky_output_operand): Assign dis_info.value for
281 2020-08-30 Alan Modra <amodra@gmail.com>
283 * cr16-dis.c: Formatting.
284 (parameter): Delete struct typedef. Use dwordU instead
286 (make_argument <arg_idxr>): Simplify detection of cbitb, sbitb
288 (make_argument <arg_cr>): Extract 20-bit field not 16-bit.
290 2020-08-29 Alan Modra <amodra@gmail.com>
293 * csky-opc.h (MAX_OPRND_NUM): Define to 5.
294 (union csky_operand): Use MAX_OPRND_NUM to size oprnds array.
296 2020-08-28 Alan Modra <amodra@gmail.com>
300 * cgen-ibld.in (insert_1): Use 1UL in forming mask.
301 (extract_normal): Likewise.
302 (insert_normal): Likewise, and move past zero length test.
303 (put_insn_int_value): Handle mask for zero length, use 1UL.
304 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
305 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
306 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
307 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
309 2020-08-28 Cooper Qu <cooper.qu@linux.alibaba.com>
311 * csky-dis.c (CSKY_DEFAULT_ISA): Define.
312 (csky_dis_info): Add member isa.
313 (csky_find_inst_info): Skip instructions that do not belong to
315 (csky_get_disassembler): Get infomation from attribute section.
316 (print_insn_csky): Set defualt ISA flag.
317 * csky.h (CSKY_ISA_VDSP_2): Rename from CSKY_ISA_VDSP_V2.
318 * csky-opc.h (struct csky_opcode): Change isa_flag16 and
319 isa_flag32'type to unsigned 64 bits.
321 2020-08-26 Jose E. Marchesi <jemarch@gnu.org>
323 * disassemble.c (enum epbf_isa_attr): Add ISA_XBPFBE, ISA_EBPFMAX.
325 2020-08-26 David Faust <david.faust@oracle.com>
327 * bpf-desc.c: Regenerate.
328 * bpf-desc.h: Likewise.
329 * bpf-opc.c: Likewise.
330 * bpf-opc.h: Likewise.
331 * disassemble.c (disassemble_init_for_target): Set bits for xBPF
332 ISA when appropriate.
334 2020-08-25 Alan Modra <amodra@gmail.com>
337 * vax-dis.c (parse_disassembler_options): Always add at least one
338 to entry_addr_total_slots.
340 2020-08-24 Cooper Qu <cooper.qu@linux.alibaba.com>
342 * csky-dis.c (csky_find_inst_info): Skip CK860's instructions
343 in other CPUs to speed up disassembling.
344 * csky-opc.h (csky_v2_opcodes): Add CK860's instructions,
345 Change plsli.u16 to plsli.16, change sync's operand format.
347 2020-08-21 Cooper Qu <cooper.qu@linux.alibaba.com>
349 * csky-opc.h (csky_v2_opcodes): Add instruction bnezad.
351 2020-08-21 Nick Clifton <nickc@redhat.com>
353 * aarch64-dis.c (get_sym_code_type): Return FALSE for non-ELF
356 2020-08-21 Cooper Qu <cooper.qu@linux.alibaba.com>
358 * csky-opc.h (csky_v2_opcodes): Add two operands form for bloop.
360 2020-08-19 Alan Modra <amodra@gmail.com>
362 * ppc-opc.c (powerpc_opcodes): Replace OBF with BF for vcmpsq,
365 2020-08-18 Peter Bergner <bergner@linux.ibm.com>
367 * ppc-opc.c (powerpc_opcodes) <xvcvbf16sp>: Rename from this...
368 <xvcvbf16spn>: ...to this.
370 2020-08-12 Alex Coplan <alex.coplan@arm.com>
372 * aarch64-opc.c (aarch64_sys_regs): Add MPAM registers.
374 2020-08-12 Nick Clifton <nickc@redhat.com>
376 * po/sr.po: Updated Serbian translation.
378 2020-08-11 Alan Modra <amodra@gmail.com>
380 * ppc-opc.c (powerpc_opcodes): Move cctpl, cctpm and cctph.
382 2020-08-10 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
384 * aarch64-opc.c (aarch64_print_operand):
385 (aarch64_sys_reg_deprecated_p): Functions paramaters changed.
386 (aarch64_sys_reg_supported_p): Function removed.
387 (aarch64_sys_ins_reg_supported_p): Functions paramaters changed.
388 (aarch64_sys_ins_reg_supported_p): Merged aarch64_sys_reg_supported_p
391 2020-08-10 Alan Modra <amodra@gmail.com>
393 * ppc-opc.c (powerpc_opcodes): Add many mtspr and mfspr extended
396 2020-08-10 Alan Modra <amodra@gmail.com>
398 * ppc-opc.c (powerpc_opcodes): Add exser, msgsndu, msgclru.
399 Enable icbt for power5, miso for power8.
401 2020-08-10 Alan Modra <amodra@gmail.com>
403 * ppc-opc.c (powerpc_opcodes): Prioritise mtfprd and mtvrd over
404 mtvsrd, and similarly for mfvsrd.
406 2020-08-04 Christian Groessler <chris@groessler.org>
407 Tadashi G. Takaoka <tadashi.g.takaoka@gmail.com>
409 * z8kgen.c (opt): Fix "sout imm16,rs" and "soutb imm16,rbs"
410 opcodes (special "out" to absolute address).
411 * z8k-opc.h: Regenerate.
413 2020-07-30 H.J. Lu <hongjiu.lu@intel.com>
416 * i386-opc.h (Prefix_Disp8): New.
417 (Prefix_Disp16): Likewise.
418 (Prefix_Disp32): Likewise.
419 (Prefix_Load): Likewise.
420 (Prefix_Store): Likewise.
421 (Prefix_VEX): Likewise.
422 (Prefix_VEX3): Likewise.
423 (Prefix_EVEX): Likewise.
424 (Prefix_REX): Likewise.
425 (Prefix_NoOptimize): Likewise.
426 * i386-opc.tbl: Use Prefix_XXX on pseudo prefixes. Add {disp16}.
427 * i386-tbl.h: Regenerated.
429 2020-07-29 Andreas Arnez <arnez@linux.ibm.com>
431 * s390-mkopc.c (insertExpandedMnemonic): Handle unreachable
432 default case with abort() instead of printing an error message and
433 continuing, to avoid a maybe-uninitialized warning.
435 2020-07-24 Nick Clifton <nickc@redhat.com>
437 * po/de.po: Updated German translation.
439 2020-07-21 Jan Beulich <jbeulich@suse.com>
441 * i386-dis.c (OP_E_memory): Revert previous change.
443 2020-07-15 H.J. Lu <hongjiu.lu@intel.com>
446 * i386-dis.c (OP_E_memory): Don't display eiz with no scale
447 without base nor index registers.
449 2020-07-15 Jan Beulich <jbeulich@suse.com>
451 * i386-dis.c (putop): Move 'V' and 'W' handling.
453 2020-07-15 Jan Beulich <jbeulich@suse.com>
455 * i386-dis.c (dis386): Adjust 'V' description. Use P-based
456 construct for push/pop of register.
457 (putop): Honor cond when handling 'P'. Drop handling of plain
460 2020-07-15 Jan Beulich <jbeulich@suse.com>
462 * i386-dis.c (dis386): Adjust 'P', 'T', 'U', and '@'
463 description. Drop '&' description. Use P for push of immediate,
464 pushf/popf, enter, and leave. Use %LP for lret/retf.
465 (dis386_twobyte): Use P for push/pop of fs/gs.
466 (reg_table): Use P for push/pop. Use @ for near call/jmp.
467 (x86_64_table): Use P for far call/jmp.
468 (putop): Drop handling of 'U' and '&'. Move and adjust handling
469 of '@'. Adjust handling of 'P' and 'T'. Drop case_P and case_Q
471 (OP_J): Drop marking of REX_W as used for v_mode (ISA-dependent)
472 and dqw_mode (unconditional).
474 2020-07-14 H.J. Lu <hongjiu.lu@intel.com>
477 * i386-dis.c (OP_E_memory): Without base nor index registers,
478 32-bit displacement to 64 bits.
480 2020-07-14 Claudiu Zissulescu <claziss@gmail.com>
482 * arc-dis.c (print_insn_arc): Detect and emit a warning when a
483 faulty double register pair is detected.
485 2020-07-14 Jan Beulich <jbeulich@suse.com>
487 * i386-dis.c (OP_D): Print dr<N> instead of db<N> in Intel mode.
489 2020-07-14 Jan Beulich <jbeulich@suse.com>
491 * i386-dis.c (OP_R, Rm): Delete.
492 (MOD_0F24, MOD_0F26): Rename to ...
493 (X86_64_0F24, X86_64_0F26): ... respectively.
494 (dis386): Update 'L' and 'Z' comments.
495 (dis386_twobyte): Replace Rm by Em. Change opcode 0F24 and 0F26
497 (mod_table): Move opcode 0F24 and 0F26 entries ...
498 (x86_64_table): ... here.
499 (putop): Drop handling of 'L'. Set modrm.mod to 3 for 'Z'. Move
502 2020-07-14 Jan Beulich <jbeulich@suse.com>
504 * i386-dis.c (Rd, Rdq, MaskR): Delete.
505 (MOD_EVEX_0F3828_P_1, MOD_EVEX_0F382A_P_1_W_1,
506 MOD_EVEX_0F3838_P_1, MOD_EVEX_0F383A_P_1_W_0,
507 MOD_EVEX_0F387A_W_0, MOD_EVEX_0F387B_W_0,
508 MOD_EVEX_0F387C): New enumerators.
509 (reg_table): Use Edq for rdssp.
510 (prefix_table): Use Edq for incssp.
511 (mod_table): Use Rm for move to/from %tr. Use MaskE for kand*,
512 kandn*, knot*, kor*, kxnor*, kxor*, kadd*, kunpck*, kortest*,
513 ktest*, and kshift*. Use Edq / MaskE for kmov*.
514 * i386-dis-evex.h: Reference mod_table[] for opcode 0F387C.
515 * i386-dis-evex-mod.h: New entries for opcodes 0F3828, 0F382A,
516 0F3838, 0F383A, 0F387A, 0F387B, and 0F387C.
517 * i386-dis-evex-prefix.h: Reference mod_table[] for opcodes
518 0F3828_P_1 and 0F3838_P_1.
519 * i386-dis-evex-w.h: Reference mod_table[] for opcodes
520 0F382A_P_1, 0F383A_P_1, 0F387A, and 0F387B.
522 2020-07-14 Jan Beulich <jbeulich@suse.com>
524 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_3,
525 PREFIX_0FAE_REG_5_MOD_0, PREFIX_0FC3_MOD_0, PREFIX_0F38C8,
526 PREFIX_0F38C9, PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC,
527 PREFIX_0F38CD, PREFIX_0F38F9, PREFIX_0F3ACC, PREFIX_VEX_0F77,
528 PREFIX_VEX_0F38F2, PREFIX_VEX_0F38F3_REG_1,
529 PREFIX_VEX_0F38F3_REG_2, PREFIX_VEX_0F38F3_REG_3): Delete.
530 (MOD_0F38F9_PREFIX_0, VEX_LEN_0F77_P_0, VEX_LEN_0F38F2_P_0,
531 VEX_LEN_0F38F3_R_1_P_0, VEX_LEN_0F38F3_R_2_P_0,
532 VEX_LEN_0F38F3_R_3_P_0): Rename to ...
533 (MOD_0F38F9, VEX_LEN_0F77, VEX_LEN_0F38F2, VEX_LEN_0F38F3_R_1,
534 VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3): ... these respectively.
535 (reg_table, prefix_table, three_byte_table, vex_table,
536 vex_len_table, mod_table, rm_table): Replace / remove respective
538 (intel_operand_size, OP_E_register, OP_G): Avoid undue setting
539 of PREFIX_DATA in used_prefixes.
541 2020-07-14 Jan Beulich <jbeulich@suse.com>
543 * i386-dis.c (MOD_VEX_0F3A30_L_0_W_0, MOD_VEX_0F3A30_L_0_W_1,
544 MOD_VEX_0F3A31_L_0_W_0, MOD_VEX_0F3A31_L_0_W_1,
545 MOD_VEX_0F3A32_L_0_W_0, MOD_VEX_0F3A32_L_0_W_1,
546 MOD_VEX_0F3A33_L_0_W_0, MOD_VEX_0F3A33_L_0_W_1): Replace by ...
547 (MOD_VEX_0F3A30_L_0, MOD_VEX_0F3A31_L_0,
548 MOD_VEX_0F3A32_L_0, MOD_VEX_0F3A33_L_0): ... these.
549 (VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
550 VEX_W_0F3A33_L_0): Delete.
551 (dis386): Adjust "BW" description.
552 (vex_len_table): Refer to mod_table[] for opcodes 0F3A30,
553 0F3A31, 0F3A32, and 0F3A33.
554 (vex_w_table): Delete opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
556 (mod_table): Replace opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
559 2020-07-14 Jan Beulich <jbeulich@suse.com>
561 * i386-dis.c (PREFIX_0F6C, PREFIX_0F6D, PREFIX_0F73_REG_3,
562 PREFIX_0F73_REG_7, PREFIX_0F3810, PREFIX_0F3814, PREFIX_0F3815,
563 PREFIX_0F3817, PREFIX_0F3820, PREFIX_0F3821, PREFIX_0F3822,
564 PREFIX_0F3823, PREFIX_0F3824, PREFIX_0F3825, PREFIX_0F3828,
565 PREFIX_0F3829, PREFIX_0F382A, PREFIX_0F382B, PREFIX_0F3830,
566 PREFIX_0F3831, PREFIX_0F3832, PREFIX_0F3833, PREFIX_0F3834,
567 PREFIX_0F3835, PREFIX_0F3837, PREFIX_0F3838, PREFIX_0F3839,
568 PREFIX_0F383A, PREFIX_0F383B, PREFIX_0F383C, PREFIX_0F383D,
569 PREFIX_0F383E, PREFIX_0F383F, PREFIX_0F3840, PREFIX_0F3841,
570 PREFIX_0F3880, PREFIX_0F3881, PREFIX_0F3882, PREFIX_0F38CF,
571 PREFIX_0F38DB, PREFIX_0F38DC, PREFIX_0F38DD, PREFIX_0F38DE,
572 PREFIX_0F38DF, PREFIX_0F38F5, PREFIX_0F3A08, PREFIX_0F3A09,
573 PREFIX_0F3A0A, PREFIX_0F3A0B, PREFIX_0F3A0C, PREFIX_0F3A0D,
574 PREFIX_0F3A0E, PREFIX_0F3A14, PREFIX_0F3A15, PREFIX_0F3A16,
575 PREFIX_0F3A17, PREFIX_0F3A20, PREFIX_0F3A21, PREFIX_0F3A22,
576 PREFIX_0F3A40, PREFIX_0F3A41, PREFIX_0F3A42, PREFIX_0F3A44,
577 PREFIX_0F3A60, PREFIX_0F3A61, PREFIX_0F3A62, PREFIX_0F3A63,
578 PREFIX_0F3ACE, PREFIX_0F3ACF, PREFIX_0F3ADF, PREFIX_VEX_0F60,
579 PREFIX_VEX_0F61, PREFIX_VEX_0F62, PREFIX_VEX_0F63,
580 PREFIX_VEX_0F64, PREFIX_VEX_0F65, PREFIX_VEX_0F66,
581 PREFIX_VEX_0F67, PREFIX_VEX_0F68, PREFIX_VEX_0F69,
582 PREFIX_VEX_0F6A, PREFIX_VEX_0F6B, PREFIX_VEX_0F6C,
583 PREFIX_VEX_0F6D, PREFIX_VEX_0F6E, PREFIX_VEX_0F71_REG_2,
584 PREFIX_VEX_0F71_REG_4, PREFIX_VEX_0F71_REG_6,
585 PREFIX_VEX_0F72_REG_2, PREFIX_VEX_0F72_REG_4,
586 PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
587 PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
588 PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74,
589 PREFIX_VEX_0F75, PREFIX_VEX_0F76, PREFIX_VEX_0FC4,
590 PREFIX_VEX_0FC5, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
591 PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
592 PREFIX_VEX_0FD6, PREFIX_VEX_0FD7, PREFIX_VEX_0FD8,
593 PREFIX_VEX_0FD9, PREFIX_VEX_0FDA, PREFIX_VEX_0FDB,
594 PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
595 PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
596 PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
597 PREFIX_VEX_0FE5, PREFIX_VEX_0FE7, PREFIX_VEX_0FE8,
598 PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
599 PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
600 PREFIX_VEX_0FEF, PREFIX_VEX_0FF1, PREFIX_VEX_0FF2,
601 PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
602 PREFIX_VEX_0FF6, PREFIX_VEX_0FF7, PREFIX_VEX_0FF8,
603 PREFIX_VEX_0FF9, PREFIX_VEX_0FFA, PREFIX_VEX_0FFB,
604 PREFIX_VEX_0FFC, PREFIX_VEX_0FFD, PREFIX_VEX_0FFE,
605 PREFIX_VEX_0F3800, PREFIX_VEX_0F3801, PREFIX_VEX_0F3802,
606 PREFIX_VEX_0F3803, PREFIX_VEX_0F3804, PREFIX_VEX_0F3805,
607 PREFIX_VEX_0F3806, PREFIX_VEX_0F3807, PREFIX_VEX_0F3808,
608 PREFIX_VEX_0F3809, PREFIX_VEX_0F380A, PREFIX_VEX_0F380B,
609 PREFIX_VEX_0F380C, PREFIX_VEX_0F380D, PREFIX_VEX_0F380E,
610 PREFIX_VEX_0F380F, PREFIX_VEX_0F3813, PREFIX_VEX_0F3816,
611 PREFIX_VEX_0F3817, PREFIX_VEX_0F3818, PREFIX_VEX_0F3819,
612 PREFIX_VEX_0F381A, PREFIX_VEX_0F381C, PREFIX_VEX_0F381D,
613 PREFIX_VEX_0F381E, PREFIX_VEX_0F3820, PREFIX_VEX_0F3821,
614 PREFIX_VEX_0F3822, PREFIX_VEX_0F3823, PREFIX_VEX_0F3824,
615 PREFIX_VEX_0F3825, PREFIX_VEX_0F3828, PREFIX_VEX_0F3829,
616 PREFIX_VEX_0F382A, PREFIX_VEX_0F382B, PREFIX_VEX_0F382C,
617 PREFIX_VEX_0F382D, PREFIX_VEX_0F382E, PREFIX_VEX_0F382F,
618 PREFIX_VEX_0F3830, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
619 PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
620 PREFIX_VEX_0F3836, PREFIX_VEX_0F3837, PREFIX_VEX_0F3838,
621 PREFIX_VEX_0F3839, PREFIX_VEX_0F383A, PREFIX_VEX_0F383B,
622 PREFIX_VEX_0F383C, PREFIX_VEX_0F383D, PREFIX_VEX_0F383E,
623 PREFIX_VEX_0F383F, PREFIX_VEX_0F3840, PREFIX_VEX_0F3841,
624 PREFIX_VEX_0F3845, PREFIX_VEX_0F3846, PREFIX_VEX_0F3847,
625 PREFIX_VEX_0F3858, PREFIX_VEX_0F3859, PREFIX_VEX_0F385A,
626 PREFIX_VEX_0F3878, PREFIX_VEX_0F3879, PREFIX_VEX_0F388C,
627 PREFIX_VEX_0F388E, PREFIX_VEX_0F3890, PREFIX_VEX_0F3891,
628 PREFIX_VEX_0F3892, PREFIX_VEX_0F3893, PREFIX_VEX_0F3896,
629 PREFIX_VEX_0F3897, PREFIX_VEX_0F3898, PREFIX_VEX_0F3899,
630 PREFIX_VEX_0F389A, PREFIX_VEX_0F389B, PREFIX_VEX_0F389C,
631 PREFIX_VEX_0F389D, PREFIX_VEX_0F389E, PREFIX_VEX_0F389F,
632 PREFIX_VEX_0F38A6, PREFIX_VEX_0F38A7, PREFIX_VEX_0F38A8,
633 PREFIX_VEX_0F38A9, PREFIX_VEX_0F38AA, PREFIX_VEX_0F38AB,
634 PREFIX_VEX_0F38AC, PREFIX_VEX_0F38AD, PREFIX_VEX_0F38AE,
635 PREFIX_VEX_0F38AF, PREFIX_VEX_0F38B6, PREFIX_VEX_0F38B7,
636 PREFIX_VEX_0F38B8, PREFIX_VEX_0F38B9, PREFIX_VEX_0F38BA,
637 PREFIX_VEX_0F38BB, PREFIX_VEX_0F38BC, PREFIX_VEX_0F38BD,
638 PREFIX_VEX_0F38BE, PREFIX_VEX_0F38BF, PREFIX_VEX_0F38CF,
639 PREFIX_VEX_0F38DB, PREFIX_VEX_0F38DC, PREFIX_VEX_0F38DD,
640 PREFIX_VEX_0F38DE, PREFIX_VEX_0F38DF, PREFIX_VEX_0F3A00,
641 PREFIX_VEX_0F3A01, PREFIX_VEX_0F3A02, PREFIX_VEX_0F3A04,
642 PREFIX_VEX_0F3A05, PREFIX_VEX_0F3A06, PREFIX_VEX_0F3A08,
643 PREFIX_VEX_0F3A09, PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B,
644 PREFIX_VEX_0F3A0C, PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E,
645 PREFIX_VEX_0F3A0F, PREFIX_VEX_0F3A14, PREFIX_VEX_0F3A15,
646 PREFIX_VEX_0F3A16, PREFIX_VEX_0F3A17, PREFIX_VEX_0F3A18,
647 PREFIX_VEX_0F3A19, PREFIX_VEX_0F3A1D, PREFIX_VEX_0F3A20,
648 PREFIX_VEX_0F3A21, PREFIX_VEX_0F3A22, PREFIX_VEX_0F3A30,
649 PREFIX_VEX_0F3A31, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3A33,
650 PREFIX_VEX_0F3A38, PREFIX_VEX_0F3A39, PREFIX_VEX_0F3A40,
651 PREFIX_VEX_0F3A41, PREFIX_VEX_0F3A42, PREFIX_VEX_0F3A44,
652 PREFIX_VEX_0F3A46, PREFIX_VEX_0F3A48, PREFIX_VEX_0F3A49,
653 PREFIX_VEX_0F3A4A, PREFIX_VEX_0F3A4B, PREFIX_VEX_0F3A4C,
654 PREFIX_VEX_0F3A5C, PREFIX_VEX_0F3A5D, PREFIX_VEX_0F3A5E,
655 PREFIX_VEX_0F3A5F, PREFIX_VEX_0F3A60, PREFIX_VEX_0F3A61,
656 PREFIX_VEX_0F3A62, PREFIX_VEX_0F3A63, PREFIX_VEX_0F3A68,
657 PREFIX_VEX_0F3A69, PREFIX_VEX_0F3A6A, PREFIX_VEX_0F3A6B,
658 PREFIX_VEX_0F3A6C, PREFIX_VEX_0F3A6D, PREFIX_VEX_0F3A6E,
659 PREFIX_VEX_0F3A6F, PREFIX_VEX_0F3A78, PREFIX_VEX_0F3A79,
660 PREFIX_VEX_0F3A7A, PREFIX_VEX_0F3A7B, PREFIX_VEX_0F3A7C,
661 PREFIX_VEX_0F3A7D, PREFIX_VEX_0F3A7E, PREFIX_VEX_0F3A7F,
662 PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF, PREFIX_VEX_0F3ADF,
663 PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F66,
664 PREFIX_EVEX_0F6E, PREFIX_EVEX_0F71_REG_2,
665 PREFIX_EVEX_0F71_REG_4, PREFIX_EVEX_0F71_REG_6,
666 PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
667 PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
668 PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
669 PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_6,
670 PREFIX_EVEX_0F73_REG_7, PREFIX_EVEX_0F74, PREFIX_EVEX_0F75,
671 PREFIX_EVEX_0F76, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5,
672 PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF,
673 PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB,
674 PREFIX_EVEX_0FEF, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3816,
675 PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B,
676 PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F382C,
677 PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
678 PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F,
679 PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843,
680 PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846,
681 PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D,
682 PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3850,
683 PREFIX_EVEX_0F3851, PREFIX_EVEX_0F3854, PREFIX_EVEX_0F3855,
684 PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B,
685 PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863, PREFIX_EVEX_0F3864,
686 PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3866, PREFIX_EVEX_0F3870,
687 PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3875,
688 PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387A,
689 PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387D,
690 PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3883,
691 PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
692 PREFIX_EVEX_0F388B, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F388F,
693 PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892,
694 PREFIX_EVEX_0F3893, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1,
695 PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38B4,
696 PREFIX_EVEX_0F38B5, PREFIX_EVEX_0F38C4,
697 PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2,
698 PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6,
699 PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2,
700 PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6,
701 PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB,
702 PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00,
703 PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A05,
704 PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A,
705 PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15,
706 PREFIX_EVEX_0F3A16, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18,
707 PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B,
708 PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A20,
709 PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A22, PREFIX_EVEX_0F3A23,
710 PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27,
711 PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A,
712 PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F,
713 PREFIX_EVEX_0F3A42, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A50,
714 PREFIX_EVEX_0F3A51, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55,
715 PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66,
716 PREFIX_EVEX_0F3A67, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
717 PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73): Delete.
718 (MOD_0F382A_PREFIX_2, MOD_0F38F5_PREFIX_2,
719 MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
720 MOD_VEX_0F381A_PREFIX_2, MOD_VEX_0F382A_PREFIX_2,
721 MOD_VEX_0F382C_PREFIX_2, MOD_VEX_0F382D_PREFIX_2,
722 MOD_VEX_0F382E_PREFIX_2, MOD_VEX_0F382F_PREFIX_2,
723 MOD_VEX_0F385A_PREFIX_2, MOD_VEX_0F388C_PREFIX_2,
724 MOD_VEX_0F388E_PREFIX_2, MOD_VEX_W_0_0F3A30_P_2_LEN_0,
725 MOD_VEX_W_1_0F3A30_P_2_LEN_0, MOD_VEX_W_0_0F3A31_P_2_LEN_0,
726 MOD_VEX_W_1_0F3A31_P_2_LEN_0, MOD_VEX_W_0_0F3A32_P_2_LEN_0,
727 MOD_VEX_W_1_0F3A32_P_2_LEN_0, MOD_VEX_W_0_0F3A33_P_2_LEN_0,
728 MOD_VEX_W_1_0F3A33_P_2_LEN_0, MOD_EVEX_0F381A_P_2_W_0,
729 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
730 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
731 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0,
732 MOD_EVEX_0F385B_P_2_W_1, VEX_LEN_0F6E_P_2,
733 VEX_LEN_0FC4_P_2, VEX_LEN_0FC5_P_2, VEX_LEN_0FD6_P_2,
734 VEX_LEN_0FF7_P_2, VEX_LEN_0F3816_P_2, VEX_LEN_0F3819_P_2,
735 VEX_LEN_0F381A_P_2_M_0, VEX_LEN_0F3836_P_2,
736 VEX_LEN_0F3841_P_2, VEX_LEN_0F385A_P_2_M_0,
737 VEX_LEN_0F38DB_P_2, VEX_LEN_0F3A00_P_2, VEX_LEN_0F3A01_P_2,
738 VEX_LEN_0F3A06_P_2, VEX_LEN_0F3A14_P_2, VEX_LEN_0F3A15_P_2,
739 VEX_LEN_0F3A16_P_2, VEX_LEN_0F3A17_P_2, VEX_LEN_0F3A18_P_2,
740 VEX_LEN_0F3A19_P_2, VEX_LEN_0F3A20_P_2, VEX_LEN_0F3A21_P_2,
741 VEX_LEN_0F3A22_P_2, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A31_P_2,
742 VEX_LEN_0F3A32_P_2, VEX_LEN_0F3A33_P_2, VEX_LEN_0F3A38_P_2,
743 VEX_LEN_0F3A39_P_2, VEX_LEN_0F3A41_P_2, VEX_LEN_0F3A46_P_2,
744 VEX_LEN_0F3A60_P_2, VEX_LEN_0F3A61_P_2, VEX_LEN_0F3A62_P_2,
745 VEX_LEN_0F3A63_P_2, VEX_LEN_0F3ADF_P_2, EVEX_LEN_0F6E_P_2,
746 EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2, EVEX_LEN_0FD6_P_2,
747 EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3819_P_2_W_0,
748 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0_M_0,
749 EVEX_LEN_0F381A_P_2_W_1_M_0, EVEX_LEN_0F381B_P_2_W_0_M_0,
750 EVEX_LEN_0F381B_P_2_W_1_M_0, EVEX_LEN_0F3836_P_2,
751 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
752 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0,
753 EVEX_LEN_0F38C6_REG_1_PREFIX_2, EVEX_LEN_0F38C6_REG_2_PREFIX_2,
754 EVEX_LEN_0F38C6_REG_5_PREFIX_2, EVEX_LEN_0F38C6_REG_6_PREFIX_2,
755 EVEX_LEN_0F38C7_R_1_P_2_W_0, EVEX_LEN_0F38C7_R_1_P_2_W_1,
756 EVEX_LEN_0F38C7_R_2_P_2_W_0, EVEX_LEN_0F38C7_R_2_P_2_W_1,
757 EVEX_LEN_0F38C7_R_5_P_2_W_0, EVEX_LEN_0F38C7_R_5_P_2_W_1,
758 EVEX_LEN_0F38C7_R_6_P_2_W_0, EVEX_LEN_0F38C7_R_6_P_2_W_1,
759 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1,
760 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
761 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A18_P_2_W_0,
762 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
763 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
764 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
765 EVEX_LEN_0F3A1B_P_2_W_1, EVEX_LEN_0F3A20_P_2,
766 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2,
767 EVEX_LEN_0F3A23_P_2_W_0, EVEX_LEN_0F3A23_P_2_W_1,
768 EVEX_LEN_0F3A38_P_2_W_0, EVEX_LEN_0F3A38_P_2_W_1,
769 EVEX_LEN_0F3A39_P_2_W_0, EVEX_LEN_0F3A39_P_2_W_1,
770 EVEX_LEN_0F3A3A_P_2_W_0, EVEX_LEN_0F3A3A_P_2_W_1,
771 EVEX_LEN_0F3A3B_P_2_W_0, EVEX_LEN_0F3A3B_P_2_W_1,
772 EVEX_LEN_0F3A43_P_2_W_0, EVEX_LEN_0F3A43_P_2_W_1
773 VEX_W_0F380C_P_2, VEX_W_0F380D_P_2, VEX_W_0F380E_P_2,
774 VEX_W_0F380F_P_2, VEX_W_0F3813_P_2, VEX_W_0F3816_P_2,
775 VEX_W_0F3818_P_2, VEX_W_0F3819_P_2,
776 VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F382C_P_2_M_0,
777 VEX_W_0F382D_P_2_M_0, VEX_W_0F382E_P_2_M_0,
778 VEX_W_0F382F_P_2_M_0, VEX_W_0F3836_P_2,
779 VEX_W_0F3846_P_2, VEX_W_0F3858_P_2, VEX_W_0F3859_P_2,
780 VEX_W_0F385A_P_2_M_0_L_0, VEX_W_0F3878_P_2,
781 VEX_W_0F3879_P_2, VEX_W_0F38CF_P_2, VEX_W_0F3A00_P_2,
782 VEX_W_0F3A01_P_2, VEX_W_0F3A02_P_2, VEX_W_0F3A04_P_2,
783 VEX_W_0F3A05_P_2, VEX_W_0F3A06_P_2_L_0,
784 VEX_W_0F3A18_P_2_L_0, VEX_W_0F3A19_P_2_L_0,
785 VEX_W_0F3A1D_P_2, VEX_W_0F3A30_P_2_LEN_0,
786 VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0,
787 VEX_W_0F3A33_P_2_LEN_0, VEX_W_0F3A38_P_2_L_0,
788 VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0,
789 VEX_W_0F3A4A_P_2, VEX_W_0F3A4B_P_2, VEX_W_0F3A4C_P_2,
790 VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2, EVEX_W_0F66_P_2,
791 EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2,
792 EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2,
793 EVEX_W_0F76_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE7_P_2,
794 EVEX_W_0F380D_P_2, EVEX_W_0F3819_P_2,
795 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2,
796 EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
797 EVEX_W_0F3837_P_2, EVEX_W_0F3859_P_2,
798 EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2,
799 EVEX_W_0F3870_P_2, EVEX_W_0F387A_P_2,
800 EVEX_W_0F387B_P_2, EVEX_W_0F3883_P_2,
801 EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2,
802 EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
803 EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2,
804 EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2,
805 EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
806 EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
807 EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2,
808 EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2,
809 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
810 EVEX_W_0F3A1B_P_2, EVEX_W_0F3A21_P_2,
811 EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2,
812 EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
813 EVEX_W_0F3A3B_P_2, EVEX_W_0F3A42_P_2,
814 EVEX_W_0F3A43_P_2, EVEX_W_0F3A70_P_2,
815 EVEX_W_0F3A72_P_2): Rename to ...
816 (MOD_0F382A, MOD_0F38F5, MOD_VEX_0FD7, MOD_VEX_0FE7,
817 MOD_VEX_0F381A, MOD_VEX_0F382A, MOD_VEX_0F382C, MOD_VEX_0F382D,
818 MOD_VEX_0F382E, MOD_VEX_0F382F, MOD_VEX_0F385A, MOD_VEX_0F388C,
819 MOD_VEX_0F388E, MOD_VEX_0F3A30_L_0_W_0,
820 MOD_VEX_0F3A30_L_0_W_1, MOD_VEX_0F3A31_L_0_W_0,
821 MOD_VEX_0F3A31_L_0_W_1, MOD_VEX_0F3A32_L_0_W_0,
822 MOD_VEX_0F3A32_L_0_W_1, MOD_VEX_0F3A33_L_0_W_0,
823 MOD_VEX_0F3A33_L_0_W_1, MOD_EVEX_0F381A_W_0,
824 MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0, MOD_EVEX_0F381B_W_1,
825 MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1, MOD_EVEX_0F385B_W_0,
826 MOD_EVEX_0F385B_W_1, VEX_LEN_0F6E, VEX_LEN_0FC4, VEX_LEN_0FC5,
827 VEX_LEN_0FD6, VEX_LEN_0FF7, VEX_LEN_0F3816, VEX_LEN_0F3819,
828 VEX_LEN_0F381A_M_0, VEX_LEN_0F3836, VEX_LEN_0F3841,
829 VEX_LEN_0F385A_M_0, VEX_LEN_0F38DB, VEX_LEN_0F3A00,
830 VEX_LEN_0F3A01, VEX_LEN_0F3A06, VEX_LEN_0F3A14, VEX_LEN_0F3A15,
831 VEX_LEN_0F3A16, VEX_LEN_0F3A17, VEX_LEN_0F3A18, VEX_LEN_0F3A19,
832 VEX_LEN_0F3A20, VEX_LEN_0F3A21, VEX_LEN_0F3A22, VEX_LEN_0F3A30,
833 VEX_LEN_0F3A31, VEX_LEN_0F3A32, VEX_LEN_0F3A33, VEX_LEN_0F3A38,
834 VEX_LEN_0F3A39, VEX_LEN_0F3A41, VEX_LEN_0F3A46, VEX_LEN_0F3A60,
835 VEX_LEN_0F3A61, VEX_LEN_0F3A62, VEX_LEN_0F3A63, VEX_LEN_0F3ADF,
836 EVEX_LEN_0F6E, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
837 EVEX_LEN_0F3816, EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
838 EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
839 EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
840 EVEX_LEN_0F3836, EVEX_LEN_0F385A_W_0_M_0,
841 EVEX_LEN_0F385A_W_1_M_0, EVEX_LEN_0F385B_W_0_M_0,
842 EVEX_LEN_0F385B_W_1_M_0, EVEX_LEN_0F38C6_R_1_M_0,
843 EVEX_LEN_0F38C6_R_2_M_0, EVEX_LEN_0F38C6_R_5_M_0,
844 EVEX_LEN_0F38C6_R_6_M_0, EVEX_LEN_0F38C7_R_1_M_0_W_0,
845 EVEX_LEN_0F38C7_R_1_M_0_W_1, EVEX_LEN_0F38C7_R_2_M_0_W_0,
846 EVEX_LEN_0F38C7_R_2_M_0_W_1, EVEX_LEN_0F38C7_R_5_M_0_W_0,
847 EVEX_LEN_0F38C7_R_5_M_0_W_1, EVEX_LEN_0F38C7_R_6_M_0_W_0,
848 EVEX_LEN_0F38C7_R_6_M_0_W_1, EVEX_LEN_0F3A00_W_1,
849 EVEX_LEN_0F3A01_W_1, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
850 EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A18_W_0,
851 EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
852 EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0,
853 EVEX_LEN_0F3A1A_W_1, EVEX_LEN_0F3A1B_W_0,
854 EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A20, EVEX_LEN_0F3A21_W_0,
855 EVEX_LEN_0F3A22, EVEX_LEN_0F3A23_W_0, EVEX_LEN_0F3A23_W_1,
856 EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
857 EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1,
858 EVEX_LEN_0F3A3A_W_0, EVEX_LEN_0F3A3A_W_1,
859 EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
860 EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1
861 VEX_W_0F380C, VEX_W_0F380D, VEX_W_0F380E, VEX_W_0F380F,
862 VEX_W_0F3813, VEX_W_0F3816_L_1, VEX_W_0F3818,
863 VEX_W_0F3819_L_1, VEX_W_0F381A_M_0_L_1, VEX_W_0F382C_M_0,
864 VEX_W_0F382D_M_0, VEX_W_0F382E_M_0, VEX_W_0F382F_M_0,
865 VEX_W_0F3836, VEX_W_0F3846, VEX_W_0F3858, VEX_W_0F3859,
866 VEX_W_0F385A_M_0_L_0, VEX_W_0F3878, VEX_W_0F3879,
867 VEX_W_0F38CF, VEX_W_0F3A00_L_1, VEX_W_0F3A01_L_1,
868 VEX_W_0F3A02, VEX_W_0F3A04, VEX_W_0F3A05, VEX_W_0F3A06_L_1,
869 VEX_W_0F3A18_L_1, VEX_W_0F3A19_L_1, VEX_W_0F3A1D,
870 VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
871 VEX_W_0F3A33_L_0, VEX_W_0F3A38_L_1, VEX_W_0F3A39_L_1,
872 VEX_W_0F3A46_L_1, VEX_W_0F3A4A, VEX_W_0F3A4B, VEX_W_0F3A4C,
873 VEX_W_0F3ACE, VEX_W_0F3ACF, EVEX_W_0F66, EVEX_W_0F72_R_2,
874 EVEX_W_0F72_R_6, EVEX_W_0F73_R_2, EVEX_W_0F73_R_6,
875 EVEX_W_0F76, EVEX_W_0FD6_L_0, EVEX_W_0FE7, EVEX_W_0F380D,
876 EVEX_W_0F3819, EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F381E,
877 EVEX_W_0F381F, EVEX_W_0F3837, EVEX_W_0F3859, EVEX_W_0F385A,
878 EVEX_W_0F385B, EVEX_W_0F3870, EVEX_W_0F387A, EVEX_W_0F387B,
879 EVEX_W_0F3883, EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1,
880 EVEX_W_0F38A3, EVEX_W_0F38C7_R_1_M_0,
881 EVEX_W_0F38C7_R_2_M_0, EVEX_W_0F38C7_R_5_M_0,
882 EVEX_W_0F38C7_R_6_M_0, EVEX_W_0F3A00, EVEX_W_0F3A01,
883 EVEX_W_0F3A05, EVEX_W_0F3A08, EVEX_W_0F3A09, EVEX_W_0F3A0A,
884 EVEX_W_0F3A0B, EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A,
885 EVEX_W_0F3A1B, EVEX_W_0F3A21, EVEX_W_0F3A23, EVEX_W_0F3A38,
886 EVEX_W_0F3A39, EVEX_W_0F3A3A, EVEX_W_0F3A3B, EVEX_W_0F3A42,
887 EVEX_W_0F3A43, EVEX_W_0F3A70, EVEX_W_0F3A72): ... these
889 (dis386_twobyte, three_byte_table, vex_table, vex_len_table,
890 vex_w_table, mod_table): Replace / remove respective entries.
891 (print_insn): Move up dp->prefix_requirement handling. Handle
893 * i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-mod.h,
894 i386-dis-evex-prefix.h, i386-dis-evex-reg.h, i386-dis-evex-w.h:
895 Replace / remove respective entries.
897 2020-07-14 Jan Beulich <jbeulich@suse.com>
899 * i386-dis.c (PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
900 PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F): Delete.
901 (prefix_table): Add EXxEVexS operand to vcvttss2si, vcvttsd2si,
902 vcvtss2si, vcvtsd2si, vucomiss, and vucomisd table entries.
903 Retain X macro and PREFIX_OPCODE use from tjhe EVEX table for
905 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
906 0F2C, 0F2D, 0F2E, and 0F2F.
907 * i386-dis-evex-prefix.h: Delete opcode 0F2C, 0F2D, 0F2E, and
910 2020-07-14 Jan Beulich <jbeulich@suse.com>
912 * i386-dis.c (OP_VexR, VexScalarR): New.
913 (OP_EX_Vex, OP_XMM_Vex, EXdVexScalarS, EXqVexScalarS,
914 XMVexScalar, d_scalar_swap_mode, q_scalar_swap_mode,
915 need_vex_reg): Delete.
916 (prefix_table): Replace VexScalar by VexScalarR and
917 XMVexScalar by XMScalar for vmovss and vmovsd. Replace
918 EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
919 (vex_len_table): Replace EXqVexScalarS by EXqS.
920 (get_valid_dis386): Don't set need_vex_reg.
921 (print_insn): Don't initialize need_vex_reg.
922 (intel_operand_size, OP_E_memory): Drop d_scalar_swap_mode and
923 q_scalar_swap_mode cases.
924 (OP_EX): Don't check for d_scalar_swap_mode and
926 (OP_VEX): Done check need_vex_reg.
927 * i386-dis-evex-w.h: Replace VexScalar by VexScalarR and
928 XMVexScalar by XMScalar for vmovss and vmovsd. Replace
929 EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
931 2020-07-14 Jan Beulich <jbeulich@suse.com>
933 * i386-dis.c (Vex128, Vex256, vex128_mode, vex256_mode): Delete.
934 (VEX_W_0F381A_P_2_M_0, VEX_W_0F385A_P_2_M_0, VEX_W_0F3A06_P_2,
935 VEX_W_0F3A18_P_2, VEX_W_0F3A19_P_2, VEX_W_0F3A38_P_2,
936 VEX_W_0F3A39_P_2, VEX_W_0F3A46_P_2): Rename to ...
937 (VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F385A_P_2_M_0_L_0,
938 VEX_W_0F3A06_P_2_L_0, VEX_W_0F3A18_P_2_L_0,
939 VEX_W_0F3A19_P_2_L_0, VEX_W_0F3A38_P_2_L_0,
940 VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0): ... respectively.
941 (vex_table): Replace Vex128 by Vex.
942 (vex_len_table): Likewise. Adjust referenced enum names.
943 (vex_w_table): Replace Vex128 and Vex256 by Vex. Adjust
944 referenced enum names.
945 (OP_VEX): Drop vex128_mode and vex256_mode cases.
946 * i386-dis-evex-len.h (evex_len_table): Replace Vex128 by Vex.
948 2020-07-14 Jan Beulich <jbeulich@suse.com>
950 * i386-dis.c (dis386): "LW" description now applies to "DQ".
951 (putop): Handle "DQ". Don't handle "LW" anymore.
952 (prefix_table, mod_table): Replace %LW by %DQ.
953 * i386-dis-evex-len.h, i386-dis-evex-prefix.h: Likewise.
955 2020-07-14 Jan Beulich <jbeulich@suse.com>
957 * i386-dis.c (OP_E_memory): Move xmm_mw_mode, xmm_mb_mode,
958 dqd_mode, xmm_md_mode, d_mode, d_swap_mode, and
959 d_scalar_swap_mode case handling. Move shift adjsutment into
960 the case its applicable to.
962 2020-07-14 Jan Beulich <jbeulich@suse.com>
964 * i386-dis.c (EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2): Delete.
965 (EXbScalar, EXwScalar): Fold to ...
966 (EXbwUnit): ... this.
967 (b_scalar_mode, w_scalar_mode): Fold to ...
968 (bw_unit_mode): ... this.
969 (intel_operand_size, OP_E_memory): Replace b_scalar_mode /
970 w_scalar_mode handling by bw_unit_mode one.
971 * i386-dis-evex-w.h: Move entries for opcodes 0F3862 and 0F3863
973 * i386-dis-evex-prefix.h: ... here.
975 2020-07-14 Jan Beulich <jbeulich@suse.com>
977 * i386-dis.c (PCMPESTR_Fixup): Delete.
978 (dis386): Adjust "LQ" description.
979 (prefix_table): Make %LQ apply to AT&T case only for cvtsi2ss,
980 cvtsi2sd, ptwrite, vcvtsi2ss, and vcvtsi2sd. Replace use of
981 PCMPESTR_Fixup by !%LQ and EXx for pcmpestrm, pcmpestri,
982 vpcmpestrm, and vpcmpestri.
983 (putop): Honor "cond" when handling LQ.
984 * i386-dis-evex-prefix.h: Make %LQ apply to AT&T case only for
985 vcvtsi2ss and vcvtusi2ss.
986 * i386-dis-evex-w.h: Make %LQ apply to AT&T case only for
987 vcvtsi2sd and vcvtusi2sd.
989 2020-07-14 Jan Beulich <jbeulich@suse.com>
991 * i386-dis.c (VCMP_Fixup, VCMP): Delete.
992 (simd_cmp_op): Add const.
993 (vex_cmp_op): Move up and drop initial 8 entries. Add const.
994 (CMP_Fixup): Handle VEX case.
995 (prefix_table): Replace VCMP by CMP.
996 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Likewise.
998 2020-07-14 Jan Beulich <jbeulich@suse.com>
1000 * i386-dis.c (MOVBE_Fixup): Delete.
1002 (prefix_table): Use Mv for movbe entries.
1004 2020-07-14 Jan Beulich <jbeulich@suse.com>
1006 * i386-dis.c (CRC32_Fixup): Delete.
1007 (prefix_table): Use Eb/Ev for crc32 entries.
1009 2020-07-14 Jan Beulich <jbeulich@suse.com>
1011 * i386-dis.c (OP_E_register, OP_G, OP_REG, CRC32_Fixup):
1012 Conditionalize invocations of "USED_REX (0)".
1014 2020-07-14 Jan Beulich <jbeulich@suse.com>
1016 * i386-dis.c (eBX, eCX, eDX, eSP, eBP, eSI, eDI, DL, BL, AH,
1017 CH, DH, BH, AX, DX): Delete.
1018 (OP_IMREG): Drop handling of eBX_reg, eCX_reg, eDX_reg, eSP_reg,
1019 eBP_reg, eSI_reg, eDI_reg, dl_reg, bl_reg, ah_reg, ch_reg,
1020 dh_reg, bh_reg, ax_reg, and dx_reg. Simplify what's left.
1022 2020-07-10 Lili Cui <lili.cui@intel.com>
1024 * i386-dis.c (TMM): New.
1027 (MVexSIBMEM): Likewise.
1028 (tmm_mode): Likewise.
1029 (vex_sibmem_mode): Likewise.
1030 (REG_VEX_0F3849_X86_64_P_0_W_0_M_1): Likewise.
1031 (MOD_VEX_0F3849_X86_64_P_0_W_0): Likewise.
1032 (MOD_VEX_0F3849_X86_64_P_2_W_0): Likewise.
1033 (MOD_VEX_0F3849_X86_64_P_3_W_0): Likewise.
1034 (MOD_VEX_0F384B_X86_64_P_1_W_0): Likewise.
1035 (MOD_VEX_0F384B_X86_64_P_2_W_0): Likewise.
1036 (MOD_VEX_0F384B_X86_64_P_3_W_0): Likewise.
1037 (MOD_VEX_0F385C_X86_64_P_1_W_0): Likewise.
1038 (MOD_VEX_0F385E_X86_64_P_0_W_0): Likewise.
1039 (MOD_VEX_0F385E_X86_64_P_1_W_0): Likewise.
1040 (MOD_VEX_0F385E_X86_64_P_2_W_0): Likewise.
1041 (MOD_VEX_0F385E_X86_64_P_3_W_0): Likewise.
1042 (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0): Likewise.
1043 (PREFIX_VEX_0F3849_X86_64): Likewise.
1044 (PREFIX_VEX_0F384B_X86_64): Likewise.
1045 (PREFIX_VEX_0F385C_X86_64): Likewise.
1046 (PREFIX_VEX_0F385E_X86_64): Likewise.
1047 (X86_64_VEX_0F3849): Likewise.
1048 (X86_64_VEX_0F384B): Likewise.
1049 (X86_64_VEX_0F385C): Likewise.
1050 (X86_64_VEX_0F385E): Likewise.
1051 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0): Likewise.
1052 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0): Likewise.
1053 (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0): Likewise.
1054 (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0): Likewise.
1055 (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0): Likewise.
1056 (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0): Likewise.
1057 (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0): Likewise.
1058 (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0): Likewise.
1059 (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0): Likewise.
1060 (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0): Likewise.
1061 (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0): Likewise.
1062 (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0): Likewise.
1063 (VEX_W_0F3849_X86_64_P_0): Likewise.
1064 (VEX_W_0F3849_X86_64_P_2): Likewise.
1065 (VEX_W_0F3849_X86_64_P_3): Likewise.
1066 (VEX_W_0F384B_X86_64_P_1): Likewise.
1067 (VEX_W_0F384B_X86_64_P_2): Likewise.
1068 (VEX_W_0F384B_X86_64_P_3): Likewise.
1069 (VEX_W_0F385C_X86_64_P_1): Likewise.
1070 (VEX_W_0F385E_X86_64_P_0): Likewise.
1071 (VEX_W_0F385E_X86_64_P_1): Likewise.
1072 (VEX_W_0F385E_X86_64_P_2): Likewise.
1073 (VEX_W_0F385E_X86_64_P_3): Likewise.
1074 (names_tmm): Likewise.
1075 (att_names_tmm): Likewise.
1076 (intel_operand_size): Handle void_mode.
1077 (OP_XMM): Handle tmm_mode.
1080 * i386-gen.c (cpu_flag_init): Add entries for CpuAMX_INT8,
1081 CpuAMX_BF16 and CpuAMX_TILE.
1082 (operand_type_shorthands): Add RegTMM.
1083 (operand_type_init): Likewise.
1084 (operand_types): Add Tmmword.
1085 (cpu_flag_init): Add CPU_AMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
1086 (cpu_flags): Add CpuAMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
1087 * i386-opc.h (CpuAMX_INT8): New.
1088 (CpuAMX_BF16): Likewise.
1089 (CpuAMX_TILE): Likewise.
1091 (Tmmword): Likewise.
1092 (i386_cpu_flags): Add cpuamx_int8, cpuamx_bf16 and cpuamx_tile.
1093 (i386_opcode_modifier): Extend width of fields vexvvvv and sib.
1094 (i386_operand_type): Add tmmword.
1095 * i386-opc.tbl: Add AMX instructions.
1096 * i386-reg.tbl: Add AMX registers.
1097 * i386-init.h: Regenerated.
1098 * i386-tbl.h: Likewise.
1100 2020-07-08 Jan Beulich <jbeulich@suse.com>
1102 * i386-dis.c (OP_LWPCB_E, OP_LWP_E): Delete.
1103 (REG_XOP_LWPCB, REG_XOP_LWP, REG_XOP_TBM_01, REG_XOP_TBM_02):
1105 (REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
1106 REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0): ... these
1108 (MOD_VEX_0FXOP_09_12, VEX_LEN_0FXOP_08_85, VEX_LEN_0FXOP_08_86,
1109 VEX_LEN_0FXOP_08_87, VEX_LEN_0FXOP_08_8E, VEX_LEN_0FXOP_08_8F,
1110 VEX_LEN_0FXOP_08_95, VEX_LEN_0FXOP_08_96, VEX_LEN_0FXOP_08_97,
1111 VEX_LEN_0FXOP_08_9E, VEX_LEN_0FXOP_08_9F, VEX_LEN_0FXOP_08_A3,
1112 VEX_LEN_0FXOP_08_A6, VEX_LEN_0FXOP_08_B6, VEX_LEN_0FXOP_08_C0,
1113 VEX_LEN_0FXOP_08_C1, VEX_LEN_0FXOP_08_C2, VEX_LEN_0FXOP_08_C3,
1114 VEX_LEN_0FXOP_09_01, VEX_LEN_0FXOP_09_02, VEX_LEN_0FXOP_09_12_M_1,
1115 VEX_LEN_0FXOP_09_90, VEX_LEN_0FXOP_09_91, VEX_LEN_0FXOP_09_92,
1116 VEX_LEN_0FXOP_09_93, VEX_LEN_0FXOP_09_94, VEX_LEN_0FXOP_09_95,
1117 VEX_LEN_0FXOP_09_96, VEX_LEN_0FXOP_09_97, VEX_LEN_0FXOP_09_98,
1118 VEX_LEN_0FXOP_09_99, VEX_LEN_0FXOP_09_9A, VEX_LEN_0FXOP_09_9B,
1119 VEX_LEN_0FXOP_09_C1, VEX_LEN_0FXOP_09_C2, VEX_LEN_0FXOP_09_C3,
1120 VEX_LEN_0FXOP_09_C6, VEX_LEN_0FXOP_09_C7, VEX_LEN_0FXOP_09_CB,
1121 VEX_LEN_0FXOP_09_D1, VEX_LEN_0FXOP_09_D2, VEX_LEN_0FXOP_09_D3,
1122 VEX_LEN_0FXOP_09_D6, VEX_LEN_0FXOP_09_D7, VEX_LEN_0FXOP_09_DB,
1123 VEX_LEN_0FXOP_09_E1, VEX_LEN_0FXOP_09_E2, VEX_LEN_0FXOP_09_E3,
1124 VEX_LEN_0FXOP_0A_12, VEX_W_0FXOP_08_85_L_0,
1125 VEX_W_0FXOP_08_86_L_0, VEX_W_0FXOP_08_87_L_0,
1126 VEX_W_0FXOP_08_8E_L_0, VEX_W_0FXOP_08_8F_L_0,
1127 VEX_W_0FXOP_08_95_L_0, VEX_W_0FXOP_08_96_L_0,
1128 VEX_W_0FXOP_08_97_L_0, VEX_W_0FXOP_08_9E_L_0,
1129 VEX_W_0FXOP_08_9F_L_0, VEX_W_0FXOP_08_A6_L_0,
1130 VEX_W_0FXOP_08_B6_L_0, VEX_W_0FXOP_08_C0_L_0,
1131 VEX_W_0FXOP_08_C1_L_0, VEX_W_0FXOP_08_C2_L_0,
1132 VEX_W_0FXOP_08_C3_L_0, VEX_W_0FXOP_08_CC_L_0,
1133 VEX_W_0FXOP_08_CD_L_0, VEX_W_0FXOP_08_CE_L_0,
1134 VEX_W_0FXOP_08_CF_L_0, VEX_W_0FXOP_08_EC_L_0,
1135 VEX_W_0FXOP_08_ED_L_0, VEX_W_0FXOP_08_EE_L_0,
1136 VEX_W_0FXOP_08_EF_L_0, VEX_W_0FXOP_09_C1_L_0,
1137 VEX_W_0FXOP_09_C2_L_0, VEX_W_0FXOP_09_C3_L_0,
1138 VEX_W_0FXOP_09_C6_L_0, VEX_W_0FXOP_09_C7_L_0,
1139 VEX_W_0FXOP_09_CB_L_0, VEX_W_0FXOP_09_D1_L_0,
1140 VEX_W_0FXOP_09_D2_L_0, VEX_W_0FXOP_09_D3_L_0,
1141 VEX_W_0FXOP_09_D6_L_0, VEX_W_0FXOP_09_D7_L_0,
1142 VEX_W_0FXOP_09_DB_L_0, VEX_W_0FXOP_09_E1_L_0,
1143 VEX_W_0FXOP_09_E2_L_0, VEX_W_0FXOP_09_E3_L_0): New enumerators.
1144 (reg_table): Re-order XOP entries. Adjust their operands.
1145 (xop_table): Replace 08_85, 08_86, 08_87, 08_8E, 08_8F, 08_95,
1146 08_96, 08_97, 08_9E, 08_9F, 08_A3, 08_A6, 08_B6, 08_C0, 08_C1,
1147 08_C2, 08_C3, 09_01, 09_02, 09_12, 09_90, 09_91, 09_92, 09_93,
1148 09_94, 09_95, 09_96, 09_97, 09_98, 09_99, 09_9A, 09_9B, 09_C1,
1149 09_C2, 09_C3, 09_C6, 09_C7, 09_CB, 09_D1, 09_D2, 09_D3, 09_D6,
1150 09_D7, 09_DB, 09_E1, 09_E2, 09_E3, and VEX_LEN_0FXOP_0A_12
1151 entries by references ...
1152 (vex_len_table): ... to resepctive new entries here. For several
1153 new and existing entries reference ...
1154 (vex_w_table): ... new entries here.
1155 (mod_table): New MOD_VEX_0FXOP_09_12 entry.
1157 2020-07-08 Jan Beulich <jbeulich@suse.com>
1159 * i386-dis.c (XMVexScalarI4): Define.
1160 (VEX_LEN_0F3A6A_P_2, VEX_LEN_0F3A6B_P_2, VEX_LEN_0F3A6E_P_2,
1161 VEX_LEN_0F3A6F_P_2, VEX_LEN_0F3A7A_P_2, VEX_LEN_0F3A7B_P_2,
1162 VEX_LEN_0F3A7E_P_2, VEX_LEN_0F3A7F_P_2): Delete.
1163 (vex_len_table): Move scalar FMA4 entries ...
1164 (prefix_table): ... here.
1165 (OP_REG_VexI4): Handle scalar_mode.
1166 * i386-opc.tbl: Use VexLIG for scalar FMA4 insns.
1167 * i386-tbl.h: Re-generate.
1169 2020-07-08 Jan Beulich <jbeulich@suse.com>
1171 * i386-dis.c (OP_Vex_2src_1, OP_Vex_2src_2, Vex_2src_1,
1172 Vex_2src_2): Delete.
1173 (OP_VexW, VexW): New.
1174 (xop_table): Use EXx for rotates by immediate. Use EXx and VexW
1175 for shifts and rotates by register.
1177 2020-07-08 Jan Beulich <jbeulich@suse.com>
1179 * i386-dis.c (OP_EX_VexImmW, OP_XMM_VexW, EXVexImmW, XMVexW,
1180 VEX_W_0F3A48_P_2, VEX_W_0F3A49_P_2, vex_w_done, get_vex_imm8,
1181 OP_EX_VexReg): Delete.
1182 (OP_VexI4, VexI4): New.
1183 (vex_w_table): Move vpermil2ps and vpermil2pd entries ...
1184 (prefix_table): ... here.
1185 (print_insn): Drop setting of vex_w_done.
1187 2020-07-08 Jan Beulich <jbeulich@suse.com>
1189 * i386-dis.c (OP_EX_VexW, EXVexW, EXdVexW, EXqVexW): Delete.
1190 (prefix_table, vex_len_table): Replace operands for FMA4 insns.
1191 (xop_table): Replace operands of 4-operand insns.
1192 (OP_REG_VexI4): Move VEX.W based operand swaping here.
1194 2020-07-07 Claudiu Zissulescu <claziss@synopsys.com>
1196 * arc-opc.c (insert_rbd): New function.
1199 * arc-tbl.h (vadd2, vadd4h, vmac2h, vmpy2h, vsub4h): Update
1202 2020-07-07 Jan Beulich <jbeulich@suse.com>
1204 * i386-dis.c (EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2,
1205 EVEX_W_0F3828_P_1, EVEX_W_0F3829_P_1, EVEX_W_0F3854_P_2,
1206 EVEX_W_0F3866_P_2, EVEX_W_0F3875_P_2, EVEX_W_0F387D_P_2,
1207 EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2, EVEX_W_0F3A3F_P_2):
1209 (putop): Handle "BW".
1210 * i386-dis-evex-w.h: Move entries for opcodes 0F3826, 0F3826,
1211 0F3828, 0F3829, 0F3854, 0F3866, 0F3875, 0F387D, 0F388D, 0F3A3E,
1213 * i386-dis-evex-prefix.h: ... here.
1215 2020-07-06 Jan Beulich <jbeulich@suse.com>
1217 * i386-dis.c (VEX_LEN_0FXOP_09_80, VEX_LEN_0FXOP_09_81): Delete.
1218 (VEX_LEN_0FXOP_09_82_W_0, VEX_LEN_0FXOP_09_83_W_0,
1219 VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81, VEX_W_0FXOP_09_82,
1220 VEX_W_0FXOP_09_83): New enumerators.
1221 (xop_table): Reference the above.
1222 (vex_len_table): Replace vfrczp* entries by vfrczs* ones.
1223 (vex_w_table): New VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81,
1224 VEX_W_0FXOP_09_82, and VEX_W_0FXOP_09_83 entries.
1225 (get_valid_dis386): Return bad_opcode for XOP.PP != 0.
1227 2020-07-06 Jan Beulich <jbeulich@suse.com>
1229 * i386-dis.c (EVEX_W_0F3838_P_1,
1230 EVEX_W_0F3839_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3855_P_2,
1231 EVEX_W_0F3868_P_3, EVEX_W_0F3871_P_2, EVEX_W_0F3873_P_2,
1232 EVEX_W_0F3A50_P_2, EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2,
1233 EVEX_W_0F3A57_P_2, EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2,
1234 EVEX_W_0F3A71_P_2, EVEX_W_0F3A73_P_2): Delete.
1235 (putop): Centralize management of last[]. Delete SAVE_LAST.
1236 * i386-dis-evex-w.h: Move entries for opcodes 0F3838, 0F3839,
1237 0F3840, 0F3855, 0F3868, 0F3871, 0F3873, 0F3A50, 0F3A51, 0F3A56,
1238 0F3A57, 0F3A66, 0F3A67, 0F3A71, and 0F3A73 ...
1239 * i386-dis-evex-prefix.h: here.
1241 2020-07-06 Jan Beulich <jbeulich@suse.com>
1243 * i386-dis.c (MOD_EVEX_0F381A_P_2_W_0, MOD_EVEX_0F381A_P_2_W_1,
1244 MOD_EVEX_0F381B_P_2_W_0, MOD_EVEX_0F381B_P_2_W_1,
1245 MOD_EVEX_0F385A_P_2_W_0, MOD_EVEX_0F385A_P_2_W_1,
1246 MOD_EVEX_0F385B_P_2_W_0, MOD_EVEX_0F385B_P_2_W_1): New
1248 (EVEX_LEN_0F381A_P_2_W_0, EVEX_LEN_0F381A_P_2_W_1,
1249 EVEX_LEN_0F381B_P_2_W_0, EVEX_LEN_0F381B_P_2_W_1,
1250 EVEX_LEN_0F385A_P_2_W_0, EVEX_LEN_0F385A_P_2_W_1,
1251 EVEX_LEN_0F385B_P_2_W_0, EVEX_LEN_0F385B_P_2_W_1): Rename to ...
1252 (EVEX_LEN_0F381A_P_2_W_0_M_0, EVEX_LEN_0F381A_P_2_W_1_M_0,
1253 EVEX_LEN_0F381B_P_2_W_0_M_0, EVEX_LEN_0F381B_P_2_W_1_M_0,
1254 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
1255 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0): ...
1256 these, respectively.
1257 * i386-dis-evex-len.h: Adjust comments.
1258 * i386-dis-evex-mod.h: New MOD_EVEX_0F381A_P_2_W_0,
1259 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
1260 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
1261 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0, and
1262 MOD_EVEX_0F385B_P_2_W_1 table entries.
1263 * i386-dis-evex-w.h: Reference mod_table[] for
1264 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2, and
1267 2020-07-06 Jan Beulich <jbeulich@suse.com>
1269 * i386-dis-evex-len.h (vbroadcastf32x8, vbroadcasti32x8,
1270 vinsertf32x8, vinsertf64x4, vextractf32x8, vextractf64x4): Use
1272 (vinserti32x8, vinserti64x4, vextracti32x8, vextracti64x4):
1273 Likewise. Mark 256-bit entries invalid.
1275 2020-07-06 Jan Beulich <jbeulich@suse.com>
1277 * i386-dis.c (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
1278 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
1279 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
1280 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
1281 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
1282 PREFIX_EVEX_0F382B): Delete.
1283 (EVEX_W_0F62_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6B_P_2,
1284 EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0FD2_P_2,
1285 EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FF2_P_2,
1286 EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2,
1287 EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F382B_P_2): Rename
1289 (EVEX_W_0F62, EVEX_W_0F6A, EVEX_W_0F6B, EVEX_W_0F6C,
1290 EVEX_W_0F6D, EVEX_W_0FD2, EVEX_W_0FD3, EVEX_W_0FD4,
1291 EVEX_W_0FF2, EVEX_W_0FF3, EVEX_W_0FF4, EVEX_W_0FFA,
1292 EVEX_W_0FFB, EVEX_W_0FFE, EVEX_W_0F382B): ... these
1294 * i386-dis-evex.h (evex_table): Reference VEX_W table entries
1295 for opcodes 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4,
1296 0FF2, 0FF3, 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
1297 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
1298 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
1299 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
1300 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
1301 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
1302 PREFIX_EVEX_0F382B): Remove table entries.
1303 * i386-dis-evex-w.h: Reference VEX table entries for opcodes
1304 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4, 0FF2, 0FF3,
1305 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
1307 2020-07-06 Jan Beulich <jbeulich@suse.com>
1309 * i386-dis.c (EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3836_P_2,
1310 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1): New
1312 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0F3816_P_2,
1313 EVEX_LEN_0F3836_P_2, EVEX_LEN_0F3A00_P_2_W_1, and
1314 EVEX_LEN_0F3A01_P_2_W_1 table entries.
1315 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
1318 2020-07-06 Jan Beulich <jbeulich@suse.com>
1320 * i386-dis.c (EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2,
1321 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
1322 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
1323 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2): New enumerators.
1324 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0FC4_P_2,
1325 EVEX_LEN_0FC5_P_2, EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2,
1326 EVEX_LEN_0F3A16_P_2, EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
1327 EVEX_LEN_0F3A21_P_2_W_0, and EVEX_LEN_0F3A22_P_2 table entries.
1328 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
1331 2020-07-06 Jan Beulich <jbeulich@suse.com>
1333 * i386-dis.c (PREFIX_EVEX_0F3A1D, EVEX_W_0F3A1D_P_2): Delete.
1334 (VEX_W_0F3813_P_2, VEX_W_0F3A1D_P_2): New enumerators.
1335 (prefix_table): Reference VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2
1337 (vex_w_table): New VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2 table
1339 * i386-dis-evex.h (evex_table): Reference VEX table entry for
1341 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F3A1D): Delete table
1343 * i386-dis-evex-w.h (EVEX_W_0F3A1D_P_2): Likewise.
1345 2020-07-06 Jan Beulich <jbeulich@suse.com>
1347 * i386-dis.c (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
1348 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
1349 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
1350 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
1351 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
1352 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
1353 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
1354 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
1355 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
1356 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
1357 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
1358 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
1359 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
1360 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
1361 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
1362 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
1363 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
1364 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
1365 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
1366 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
1367 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
1368 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
1369 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
1370 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
1371 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
1372 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
1373 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF,
1374 EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2, EVEX_W_0F3858_P_2,
1375 EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F3A04_P_2,
1376 EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2): Delete.
1377 (prefix_table): Add EXxEVexR to FMA table entries.
1378 (OP_Rounding): Move abort() invocation.
1379 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
1380 0F60, 0F61, 0F63, 0F67, 0F68, 0F69, 0FD1, 0FD5, 0FD8, 0FD9,
1381 0FDA, 0FDC, 0FDD, 0FDE, 0FE0, 0FE1, 0FE3, 0FE4, 0FE5, 0FE8,
1382 0FE9, 0FEA, 0FEC, 0FED, 0FEE, 0FF1, 0FF5, 0FF6, 0FF8, 0FF9,
1383 0FFC, 0FFD, 0F3800, 0F3804, 0F380B, 0F380C, 0F3818, 0F381C,
1384 0F381D, 0F383C, 0F383E, 0F3858, 0F3878, 0F3879, 0F3896, 0F3897,
1385 0F3898, 0F3899, 0F389C, 0F389D, 0F389E, 0F389F, 0F38A6, 0F38A7,
1386 0F38A8, 0F38A9, 0F38AC, 0F38AD, 0F38AE, 0F38AF, 0F38B6, 0F38B7,
1387 0F38B8, 0F38B9, 0F38BA, 0F38BB, 0F38BC, 0F38BD, 0F38BE, 0F38BF,
1388 0F38CF, 0F38DC, 0F38DD, 0F38DE, 0F38DF, 0F3A04, 0F3A0F, 0F3A44,
1390 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
1391 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
1392 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
1393 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
1394 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
1395 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
1396 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
1397 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
1398 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
1399 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
1400 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
1401 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
1402 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
1403 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
1404 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
1405 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
1406 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
1407 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
1408 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
1409 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
1410 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
1411 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
1412 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
1413 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
1414 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
1415 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
1416 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF):
1417 Delete table entries.
1418 * i386-dis-evex-w.h (EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2,
1419 EVEX_W_0F3858_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2,
1420 EVEX_W_0F3A04_P_2, EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2):
1423 2020-07-06 Jan Beulich <jbeulich@suse.com>
1425 * i386-dis.c (EXqScalarS): Delete.
1426 (vex_len_table): Replace EXqScalarS by EXqVexScalarS.
1427 * i386-dis-evex-w.h (vmovq): Use EXqVexScalarS.
1429 2020-07-06 Jan Beulich <jbeulich@suse.com>
1431 * i386-dis.c (safe-ctype.h): Include.
1432 (EXdScalar, EXqScalar): Delete.
1433 (d_scalar_mode, q_scalar_mode): Delete.
1434 (prefix_table, vex_len_table): Use EXxmm_md in place of
1435 EXdScalar and EXxmm_mq in place of EXqScalar.
1436 (intel_operand_size, OP_E_memory, OP_EX): Remove uses of
1437 d_scalar_mode and q_scalar_mode.
1438 * i386-dis-evex-w.h (vmovss): Use EXxmm_md.
1439 (vmovsd): Use EXxmm_mq.
1441 2020-07-06 Yuri Chornoivan <yurchor@ukr.net>
1444 * arc-dis.c: Fix spelling mistake.
1445 * po/opcodes.pot: Regenerate.
1447 2020-07-06 Nick Clifton <nickc@redhat.com>
1449 * po/pt_BR.po: Updated Brazilian Portugugese translation.
1450 * po/uk.po: Updated Ukranian translation.
1452 2020-07-04 Nick Clifton <nickc@redhat.com>
1454 * configure: Regenerate.
1455 * po/opcodes.pot: Regenerate.
1457 2020-07-04 Nick Clifton <nickc@redhat.com>
1459 Binutils 2.35 branch created.
1461 2020-07-02 H.J. Lu <hongjiu.lu@intel.com>
1463 * i386-gen.c (opcode_modifiers): Add VexSwapSources.
1464 * i386-opc.h (VexSwapSources): New.
1465 (i386_opcode_modifier): Add vexswapsources.
1466 * i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions
1467 with two source operands swapped.
1468 * i386-tbl.h: Regenerated.
1470 2020-06-30 Nelson Chu <nelson.chu@sifive.com>
1472 * riscv-dis.c (print_insn_args, case 'E'): Updated. Let the
1473 unprivileged CSR can also be initialized.
1475 2020-06-29 Alan Modra <amodra@gmail.com>
1477 * arm-dis.c: Use C style comments.
1478 * cr16-opc.c: Likewise.
1479 * ft32-dis.c: Likewise.
1480 * moxie-opc.c: Likewise.
1481 * tic54x-dis.c: Likewise.
1482 * s12z-opc.c: Remove useless comment.
1483 * xgate-dis.c: Likewise.
1485 2020-06-26 H.J. Lu <hongjiu.lu@intel.com>
1487 * i386-opc.tbl: Add a blank line.
1489 2020-06-26 H.J. Lu <hongjiu.lu@intel.com>
1491 * i386-gen.c (opcode_modifiers): Replace VecSIB with SIB.
1492 (VecSIB128): Renamed to ...
1494 (VecSIB256): Renamed to ...
1496 (VecSIB512): Renamed to ...
1498 (VecSIB): Renamed to ...
1500 (i386_opcode_modifier): Replace vecsib with sib.
1501 * i386-opc.tbl (VecSIB128): New.
1502 (VecSIB256): Likewise.
1503 (VecSIB512): Likewise.
1504 Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VecSIB128, VecSIB256
1505 and VecSIB512, respectively.
1507 2020-06-26 Jan Beulich <jbeulich@suse.com>
1509 * i386-dis.c: Adjust description of I macro.
1510 (x86_64_table): Drop use of I.
1511 (float_mem): Replace use of I.
1512 (putop): Remove handling of I. Adjust setting/clearing of "alt".
1514 2020-06-26 Jan Beulich <jbeulich@suse.com>
1516 * i386-dis.c: (print_insn): Avoid straight assignment to
1517 priv.orig_sizeflag when processing -M sub-options.
1519 2020-06-25 Jan Beulich <jbeulich@suse.com>
1521 * i386-dis.c: Adjust description of J macro.
1522 (dis386, x86_64_table, mod_table): Replace J.
1523 (putop): Remove handling of J.
1525 2020-06-25 Jan Beulich <jbeulich@suse.com>
1527 * i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt.
1529 2020-06-25 Jan Beulich <jbeulich@suse.com>
1531 * i386-dis.c: Adjust description of "LQ" macro.
1532 (dis386_twobyte): Use LQ for sysret.
1533 (putop): Adjust handling of LQ.
1535 2020-06-22 Nelson Chu <nelson.chu@sifive.com>
1537 * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
1538 * riscv-dis.c: Include elfxx-riscv.h.
1540 2020-06-18 H.J. Lu <hongjiu.lu@intel.com>
1542 * i386-dis.c (prefix_table): Revert the last vmgexit change.
1544 2020-06-17 Lili Cui <lili.cui@intel.com>
1546 * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
1548 2020-06-14 H.J. Lu <hongjiu.lu@intel.com>
1551 * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
1552 * i386-opc.tbl: Likewise.
1553 * i386-tbl.h: Regenerated.
1555 2020-06-12 Nelson Chu <nelson.chu@sifive.com>
1557 * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
1559 2020-06-11 Alex Coplan <alex.coplan@arm.com>
1561 * aarch64-opc.c (SYSREG): New macro for describing system registers.
1562 (SR_CORE): Likewise.
1563 (SR_FEAT): Likewise.
1565 (SR_V8_1): Likewise.
1566 (SR_V8_2): Likewise.
1567 (SR_V8_3): Likewise.
1568 (SR_V8_4): Likewise.
1571 (SR_SSBS): Likewise.
1573 (SR_ID_PFR2): Likewise.
1574 (SR_PROFILE): Likewise.
1575 (SR_MEMTAG): Likewise.
1576 (SR_SCXTNUM): Likewise.
1577 (aarch64_sys_regs): Refactor to store feature information in the table.
1578 (aarch64_sys_reg_supported_p): Collapse logic for system registers
1579 that now describe their own features.
1580 (aarch64_pstatefield_supported_p): Likewise.
1582 2020-06-09 H.J. Lu <hongjiu.lu@intel.com>
1584 * i386-dis.c (prefix_table): Fix a typo in comments.
1586 2020-06-09 Jan Beulich <jbeulich@suse.com>
1588 * i386-dis.c (rex_ignored): Delete.
1589 (ckprefix): Drop rex_ignored initialization.
1590 (get_valid_dis386): Drop setting of rex_ignored.
1591 (print_insn): Drop checking of rex_ignored. Don't record data
1592 size prefix as used with VEX-and-alike encodings.
1594 2020-06-09 Jan Beulich <jbeulich@suse.com>
1596 * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
1597 MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
1598 (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
1599 (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
1600 (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
1601 VEX_0F12, and VEX_0F16.
1602 (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
1603 VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
1604 (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
1605 from movlps and movhlps. New MOD_0F12_PREFIX_2,
1606 MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
1607 MOD_VEX_0F16_PREFIX_2 entries.
1609 2020-06-09 Jan Beulich <jbeulich@suse.com>
1611 * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
1612 MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
1613 (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1614 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
1615 PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
1616 PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
1617 EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
1618 EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
1619 EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
1620 EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
1621 EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
1622 EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
1623 EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
1624 EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
1625 EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
1626 EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
1627 EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
1628 EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
1629 EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
1630 EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
1631 EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
1632 EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
1633 EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
1634 EVEX_W_0FC6_P_2): Delete.
1635 (print_insn): Add EVEX.W vs embedded prefix consistency check
1636 to prefix validation.
1637 * i386-dis-evex.h (evex_table): Don't further descend for
1638 vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
1639 and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
1641 * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
1642 * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
1643 vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
1644 vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
1645 2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
1646 Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1647 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
1648 PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
1649 PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
1650 * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
1651 EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
1652 EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
1653 EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
1654 EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
1655 EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
1656 EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
1657 EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
1658 EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
1659 EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
1660 EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
1661 EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
1662 EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
1663 EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
1664 EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
1665 EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
1666 EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
1667 EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
1669 2020-06-09 Jan Beulich <jbeulich@suse.com>
1671 * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
1672 vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
1673 (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
1675 (print_insn): Drop pointless check against bad_opcode. Split
1676 prefix validation into legacy and VEX-and-alike parts.
1677 (putop): Re-work 'X' macro handling.
1679 2020-06-09 Jan Beulich <jbeulich@suse.com>
1681 * i386-dis.c (MOD_0F51): Rename to ...
1682 (MOD_0F50): ... this.
1684 2020-06-08 Alex Coplan <alex.coplan@arm.com>
1686 * arm-dis.c (arm_opcodes): Add dfb.
1687 (thumb32_opcodes): Add dfb.
1689 2020-06-08 Jan Beulich <jbeulich@suse.com>
1691 * i386-opc.h (reg_entry): Const-qualify reg_name field.
1693 2020-06-06 Alan Modra <amodra@gmail.com>
1695 * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
1697 2020-06-05 Alan Modra <amodra@gmail.com>
1699 * cgen-dis.c (hash_insn_array): Increase size of buf. Assert
1700 size is large enough.
1702 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
1704 * disassemble.c (disassemble_init_for_target): Set endian_code for
1706 * bpf-desc.c: Regenerate.
1707 * bpf-opc.c: Likewise.
1708 * bpf-dis.c: Likewise.
1710 2020-06-03 Jose E. Marchesi <jose.marchesi@oracle.com>
1712 * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
1713 (cgen_put_insn_value): Likewise.
1714 (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
1715 * cgen-dis.in (print_insn): Likewise.
1716 * cgen-ibld.in (insert_1): Likewise.
1717 (insert_1): Likewise.
1718 (insert_insn_normal): Likewise.
1719 (extract_1): Likewise.
1720 * bpf-dis.c: Regenerate.
1721 * bpf-ibld.c: Likewise.
1722 * bpf-ibld.c: Likewise.
1723 * cgen-dis.in: Likewise.
1724 * cgen-ibld.in: Likewise.
1725 * cgen-opc.c: Likewise.
1726 * epiphany-dis.c: Likewise.
1727 * epiphany-ibld.c: Likewise.
1728 * fr30-dis.c: Likewise.
1729 * fr30-ibld.c: Likewise.
1730 * frv-dis.c: Likewise.
1731 * frv-ibld.c: Likewise.
1732 * ip2k-dis.c: Likewise.
1733 * ip2k-ibld.c: Likewise.
1734 * iq2000-dis.c: Likewise.
1735 * iq2000-ibld.c: Likewise.
1736 * lm32-dis.c: Likewise.
1737 * lm32-ibld.c: Likewise.
1738 * m32c-dis.c: Likewise.
1739 * m32c-ibld.c: Likewise.
1740 * m32r-dis.c: Likewise.
1741 * m32r-ibld.c: Likewise.
1742 * mep-dis.c: Likewise.
1743 * mep-ibld.c: Likewise.
1744 * mt-dis.c: Likewise.
1745 * mt-ibld.c: Likewise.
1746 * or1k-dis.c: Likewise.
1747 * or1k-ibld.c: Likewise.
1748 * xc16x-dis.c: Likewise.
1749 * xc16x-ibld.c: Likewise.
1750 * xstormy16-dis.c: Likewise.
1751 * xstormy16-ibld.c: Likewise.
1753 2020-06-04 Jose E. Marchesi <jemarch@gnu.org>
1755 * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
1756 (print_insn_): Handle instruction endian.
1757 * bpf-dis.c: Regenerate.
1758 * bpf-desc.c: Regenerate.
1759 * epiphany-dis.c: Likewise.
1760 * epiphany-desc.c: Likewise.
1761 * fr30-dis.c: Likewise.
1762 * fr30-desc.c: Likewise.
1763 * frv-dis.c: Likewise.
1764 * frv-desc.c: Likewise.
1765 * ip2k-dis.c: Likewise.
1766 * ip2k-desc.c: Likewise.
1767 * iq2000-dis.c: Likewise.
1768 * iq2000-desc.c: Likewise.
1769 * lm32-dis.c: Likewise.
1770 * lm32-desc.c: Likewise.
1771 * m32c-dis.c: Likewise.
1772 * m32c-desc.c: Likewise.
1773 * m32r-dis.c: Likewise.
1774 * m32r-desc.c: Likewise.
1775 * mep-dis.c: Likewise.
1776 * mep-desc.c: Likewise.
1777 * mt-dis.c: Likewise.
1778 * mt-desc.c: Likewise.
1779 * or1k-dis.c: Likewise.
1780 * or1k-desc.c: Likewise.
1781 * xc16x-dis.c: Likewise.
1782 * xc16x-desc.c: Likewise.
1783 * xstormy16-dis.c: Likewise.
1784 * xstormy16-desc.c: Likewise.
1786 2020-06-03 Nick Clifton <nickc@redhat.com>
1788 * po/sr.po: Updated Serbian translation.
1790 2020-06-03 Nelson Chu <nelson.chu@sifive.com>
1792 * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
1793 (riscv_get_priv_spec_class): Likewise.
1795 2020-06-01 Alan Modra <amodra@gmail.com>
1797 * bpf-desc.c: Regenerate.
1799 2020-05-28 Jose E. Marchesi <jose.marchesi@oracle.com>
1800 David Faust <david.faust@oracle.com>
1802 * bpf-desc.c: Regenerate.
1803 * bpf-opc.h: Likewise.
1804 * bpf-opc.c: Likewise.
1805 * bpf-dis.c: Likewise.
1807 2020-05-28 Alan Modra <amodra@gmail.com>
1809 * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
1812 2020-05-28 Alan Modra <amodra@gmail.com>
1814 * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
1816 (print_insn_ns32k): Revert last change.
1818 2020-05-28 Nick Clifton <nickc@redhat.com>
1820 * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
1823 2020-05-26 Sandra Loosemore <sandra@codesourcery.com>
1825 Fix extraction of signed constants in nios2 disassembler (again).
1827 * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
1828 extractions of signed fields.
1830 2020-05-26 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
1832 * s390-opc.txt: Relocate vector load/store instructions with
1833 additional alignment parameter and change architecture level
1834 constraint from z14 to z13.
1836 2020-05-21 Alan Modra <amodra@gmail.com>
1838 * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
1839 * sparc-dis.c: Likewise.
1840 * tic4x-dis.c: Likewise.
1841 * xtensa-dis.c: Likewise.
1842 * bpf-desc.c: Regenerate.
1843 * epiphany-desc.c: Regenerate.
1844 * fr30-desc.c: Regenerate.
1845 * frv-desc.c: Regenerate.
1846 * ip2k-desc.c: Regenerate.
1847 * iq2000-desc.c: Regenerate.
1848 * lm32-desc.c: Regenerate.
1849 * m32c-desc.c: Regenerate.
1850 * m32r-desc.c: Regenerate.
1851 * mep-asm.c: Regenerate.
1852 * mep-desc.c: Regenerate.
1853 * mt-desc.c: Regenerate.
1854 * or1k-desc.c: Regenerate.
1855 * xc16x-desc.c: Regenerate.
1856 * xstormy16-desc.c: Regenerate.
1858 2020-05-20 Nelson Chu <nelson.chu@sifive.com>
1860 * riscv-opc.c (riscv_ext_version_table): The table used to store
1861 all information about the supported spec and the corresponding ISA
1862 versions. Currently, only Zicsr is supported to verify the
1863 correctness of Z sub extension settings. Others will be supported
1864 in the future patches.
1865 (struct isa_spec_t, isa_specs): List for all supported ISA spec
1866 classes and the corresponding strings.
1867 (riscv_get_isa_spec_class): New function. Get the corresponding ISA
1868 spec class by giving a ISA spec string.
1869 * riscv-opc.c (struct priv_spec_t): New structure.
1870 (struct priv_spec_t priv_specs): List for all supported privilege spec
1871 classes and the corresponding strings.
1872 (riscv_get_priv_spec_class): New function. Get the corresponding
1873 privilege spec class by giving a spec string.
1874 (riscv_get_priv_spec_name): New function. Get the corresponding
1875 privilege spec string by giving a CSR version class.
1876 * riscv-dis.c: Updated since DECLARE_CSR is changed.
1877 * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
1878 according to the chosen version. Build a hash table riscv_csr_hash to
1879 store the valid CSR for the chosen pirv verison. Dump the direct
1880 CSR address rather than it's name if it is invalid.
1881 (parse_riscv_dis_option_without_args): New function. Parse the options
1883 (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
1884 parse the options without arguments first, and then handle the options
1885 with arguments. Add the new option -Mpriv-spec, which has argument.
1886 * riscv-dis.c (print_riscv_disassembler_options): Add description
1887 about the new OBJDUMP option.
1889 2020-05-19 Peter Bergner <bergner@linux.ibm.com>
1891 * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
1892 WC values on POWER10 sync, dcbf and wait instructions.
1893 (insert_pl, extract_pl): New functions.
1894 (L2OPT, LS, WC): Use insert_ls and extract_ls.
1895 (LS3): New , 3-bit L for sync.
1896 (LS3, L3OPT): New, 3-bit L for sync and dcbf.
1897 (SC2, PL): New, 2-bit SC and PL for sync and wait.
1898 (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
1899 (XOPL3, XWCPL, XSYNCLS): New opcode macros.
1900 (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
1901 plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
1902 <wait>: Enable PL operand on POWER10.
1903 <dcbf>: Enable L3OPT operand on POWER10.
1904 <sync>: Enable SC2 operand on POWER10.
1906 2020-05-19 Stafford Horne <shorne@gmail.com>
1909 * or1k-asm.c: Regenerate.
1910 * or1k-desc.c: Regenerate.
1911 * or1k-desc.h: Regenerate.
1912 * or1k-dis.c: Regenerate.
1913 * or1k-ibld.c: Regenerate.
1914 * or1k-opc.c: Regenerate.
1915 * or1k-opc.h: Regenerate.
1916 * or1k-opinst.c: Regenerate.
1918 2020-05-11 Alan Modra <amodra@gmail.com>
1920 * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
1923 2020-05-11 Alan Modra <amodra@gmail.com>
1925 * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
1926 stxvrbx, stxvrhx, stxvrwx, stxvrdx.
1928 2020-05-11 Alan Modra <amodra@gmail.com>
1930 * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
1932 2020-05-11 Alan Modra <amodra@gmail.com>
1934 * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
1935 vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
1937 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
1939 * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
1942 2020-05-11 Alan Modra <amodra@gmail.com>
1944 * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
1945 (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
1946 vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
1947 (prefix_opcodes): Add xxeval.
1949 2020-05-11 Alan Modra <amodra@gmail.com>
1951 * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
1952 xxgenpcvwm, xxgenpcvdm.
1954 2020-05-11 Alan Modra <amodra@gmail.com>
1956 * ppc-opc.c (MP, VXVAM_MASK): Define.
1957 (VXVAPS_MASK): Use VXVA_MASK.
1958 (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
1959 vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
1960 vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
1961 vcntmbb, vcntmbh, vcntmbw, vcntmbd.
1963 2020-05-11 Alan Modra <amodra@gmail.com>
1964 Peter Bergner <bergner@linux.ibm.com>
1966 * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
1968 (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
1969 YMSK2, XA6a, XA6ap, XB6a entries.
1970 (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
1971 (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
1973 (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
1974 xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
1975 xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
1976 xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
1977 xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
1978 xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
1979 xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
1980 (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
1981 pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
1982 pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
1983 pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
1984 pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
1985 pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
1986 pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
1988 2020-05-11 Alan Modra <amodra@gmail.com>
1990 * ppc-opc.c (insert_imm32, extract_imm32): New functions.
1991 (insert_xts, extract_xts): New functions.
1992 (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
1993 (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
1994 (VXRC_MASK, VXSH_MASK): Define.
1995 (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
1996 vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
1997 vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
1998 vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
1999 vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
2000 (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
2001 xxblendvh, xxblendvw, xxblendvd, xxpermx.
2003 2020-05-11 Alan Modra <amodra@gmail.com>
2005 * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
2006 vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
2007 vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
2008 vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
2009 xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
2011 2020-05-11 Alan Modra <amodra@gmail.com>
2013 * ppc-opc.c (insert_xtp, extract_xtp): New functions.
2014 (XTP, DQXP, DQXP_MASK): Define.
2015 (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
2016 (prefix_opcodes): Add plxvp and pstxvp.
2018 2020-05-11 Alan Modra <amodra@gmail.com>
2020 * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
2021 vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
2022 vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
2024 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
2026 * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
2028 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
2030 * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
2032 (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
2034 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
2036 * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
2038 2020-05-11 Alan Modra <amodra@gmail.com>
2040 * ppc-dis.c (powerpc_init_dialect): Default to "power10".
2042 2020-05-11 Alan Modra <amodra@gmail.com>
2044 * ppc-dis.c (ppc_opts): Add "power10" entry.
2045 (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
2046 * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
2048 2020-05-11 Nick Clifton <nickc@redhat.com>
2050 * po/fr.po: Updated French translation.
2052 2020-04-30 Alex Coplan <alex.coplan@arm.com>
2054 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
2055 * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
2056 (operand_general_constraint_met_p): validate
2057 AARCH64_OPND_UNDEFINED.
2058 * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
2060 * aarch64-asm-2.c: Regenerated.
2061 * aarch64-dis-2.c: Regenerated.
2062 * aarch64-opc-2.c: Regenerated.
2064 2020-04-29 Nick Clifton <nickc@redhat.com>
2067 * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
2070 2020-04-29 Nick Clifton <nickc@redhat.com>
2072 * po/sv.po: Updated Swedish translation.
2074 2020-04-29 Nick Clifton <nickc@redhat.com>
2077 * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
2078 IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
2079 * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
2082 2020-04-21 Andreas Schwab <schwab@linux-m68k.org>
2085 * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
2086 cmpi only on m68020up and cpu32.
2088 2020-04-20 Sudakshina Das <sudi.das@arm.com>
2090 * aarch64-asm.c (aarch64_ins_none): New.
2091 * aarch64-asm.h (ins_none): New declaration.
2092 * aarch64-dis.c (aarch64_ext_none): New.
2093 * aarch64-dis.h (ext_none): New declaration.
2094 * aarch64-opc.c (aarch64_print_operand): Update case for
2095 AARCH64_OPND_BARRIER_PSB.
2096 * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
2097 (AARCH64_OPERANDS): Update inserter/extracter for
2098 AARCH64_OPND_BARRIER_PSB to use new dummy functions.
2099 * aarch64-asm-2.c: Regenerated.
2100 * aarch64-dis-2.c: Regenerated.
2101 * aarch64-opc-2.c: Regenerated.
2103 2020-04-20 Sudakshina Das <sudi.das@arm.com>
2105 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
2106 (aarch64_feature_ras, RAS): Likewise.
2107 (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
2108 (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
2109 autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
2110 autiaz, autiasp, autibz, autibsp to be CORE_INSN.
2111 * aarch64-asm-2.c: Regenerated.
2112 * aarch64-dis-2.c: Regenerated.
2113 * aarch64-opc-2.c: Regenerated.
2115 2020-04-17 Fredrik Strupe <fredrik@strupe.net>
2117 * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
2118 (print_insn_neon): Support disassembly of conditional
2121 2020-02-16 David Faust <david.faust@oracle.com>
2123 * bpf-desc.c: Regenerate.
2124 * bpf-desc.h: Likewise.
2125 * bpf-opc.c: Regenerate.
2126 * bpf-opc.h: Likewise.
2128 2020-04-07 Lili Cui <lili.cui@intel.com>
2130 * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
2131 (prefix_table): New instructions (see prefixes above).
2132 (rm_table): Likewise
2133 * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
2134 CPU_ANY_TSXLDTRK_FLAGS.
2135 (cpu_flags): Add CpuTSXLDTRK.
2136 * i386-opc.h (enum): Add CpuTSXLDTRK.
2137 (i386_cpu_flags): Add cputsxldtrk.
2138 * i386-opc.tbl: Add XSUSPLDTRK insns.
2139 * i386-init.h: Regenerate.
2140 * i386-tbl.h: Likewise.
2142 2020-04-02 Lili Cui <lili.cui@intel.com>
2144 * i386-dis.c (prefix_table): New instructions serialize.
2145 * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
2146 CPU_ANY_SERIALIZE_FLAGS.
2147 (cpu_flags): Add CpuSERIALIZE.
2148 * i386-opc.h (enum): Add CpuSERIALIZE.
2149 (i386_cpu_flags): Add cpuserialize.
2150 * i386-opc.tbl: Add SERIALIZE insns.
2151 * i386-init.h: Regenerate.
2152 * i386-tbl.h: Likewise.
2154 2020-03-26 Alan Modra <amodra@gmail.com>
2156 * disassemble.h (opcodes_assert): Declare.
2157 (OPCODES_ASSERT): Define.
2158 * disassemble.c: Don't include assert.h. Include opintl.h.
2159 (opcodes_assert): New function.
2160 * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
2161 (bfd_h8_disassemble): Reduce size of data array. Correctly
2162 calculate maxlen. Omit insn decoding when insn length exceeds
2163 maxlen. Exit from nibble loop when looking for E, before
2164 accessing next data byte. Move processing of E outside loop.
2165 Replace tests of maxlen in loop with assertions.
2167 2020-03-26 Alan Modra <amodra@gmail.com>
2169 * arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
2171 2020-03-25 Alan Modra <amodra@gmail.com>
2173 * z80-dis.c (suffix): Init mybuf.
2175 2020-03-22 Alan Modra <amodra@gmail.com>
2177 * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
2178 successflly read from section.
2180 2020-03-22 Alan Modra <amodra@gmail.com>
2182 * arc-dis.c (find_format): Use ISO C string concatenation rather
2183 than line continuation within a string. Don't access needs_limm
2184 before testing opcode != NULL.
2186 2020-03-22 Alan Modra <amodra@gmail.com>
2188 * ns32k-dis.c (print_insn_arg): Update comment.
2189 (print_insn_ns32k): Reduce size of index_offset array, and
2190 initialize, passing -1 to print_insn_arg for args that are not
2191 an index. Don't exit arg loop early. Abort on bad arg number.
2193 2020-03-22 Alan Modra <amodra@gmail.com>
2195 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
2196 * s12z-opc.c: Formatting.
2197 (operands_f): Return an int.
2198 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
2199 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
2200 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
2201 (exg_sex_discrim): Likewise.
2202 (create_immediate_operand, create_bitfield_operand),
2203 (create_register_operand_with_size, create_register_all_operand),
2204 (create_register_all16_operand, create_simple_memory_operand),
2205 (create_memory_operand, create_memory_auto_operand): Don't
2206 segfault on malloc failure.
2207 (z_ext24_decode): Return an int status, negative on fail, zero
2209 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
2210 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
2211 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
2212 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
2213 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
2214 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
2215 (loop_primitive_decode, shift_decode, psh_pul_decode),
2216 (bit_field_decode): Similarly.
2217 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
2218 to return value, update callers.
2219 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
2220 Don't segfault on NULL operand.
2221 (decode_operation): Return OP_INVALID on first fail.
2222 (decode_s12z): Check all reads, returning -1 on fail.
2224 2020-03-20 Alan Modra <amodra@gmail.com>
2226 * metag-dis.c (print_insn_metag): Don't ignore status from
2229 2020-03-20 Alan Modra <amodra@gmail.com>
2231 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
2232 Initialize parts of buffer not written when handling a possible
2233 2-byte insn at end of section. Don't attempt decoding of such
2234 an insn by the 4-byte machinery.
2236 2020-03-20 Alan Modra <amodra@gmail.com>
2238 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
2239 partially filled buffer. Prevent lookup of 4-byte insns when
2240 only VLE 2-byte insns are possible due to section size. Print
2241 ".word" rather than ".long" for 2-byte leftovers.
2243 2020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
2246 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
2248 2020-03-13 Jan Beulich <jbeulich@suse.com>
2250 * i386-dis.c (X86_64_0D): Rename to ...
2251 (X86_64_0E): ... this.
2253 2020-03-09 H.J. Lu <hongjiu.lu@intel.com>
2255 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
2256 * Makefile.in: Regenerated.
2258 2020-03-09 Jan Beulich <jbeulich@suse.com>
2260 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
2262 * i386-tbl.h: Re-generate.
2264 2020-03-09 Jan Beulich <jbeulich@suse.com>
2266 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
2267 vprot*, vpsha*, and vpshl*.
2268 * i386-tbl.h: Re-generate.
2270 2020-03-09 Jan Beulich <jbeulich@suse.com>
2272 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
2273 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
2274 * i386-tbl.h: Re-generate.
2276 2020-03-09 Jan Beulich <jbeulich@suse.com>
2278 * i386-gen.c (set_bitfield): Ignore zero-length field names.
2279 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
2280 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
2281 * i386-tbl.h: Re-generate.
2283 2020-03-09 Jan Beulich <jbeulich@suse.com>
2285 * i386-gen.c (struct template_arg, struct template_instance,
2286 struct template_param, struct template, templates,
2287 parse_template, expand_templates): New.
2288 (process_i386_opcodes): Various local variables moved to
2289 expand_templates. Call parse_template and expand_templates.
2290 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
2291 * i386-tbl.h: Re-generate.
2293 2020-03-06 Jan Beulich <jbeulich@suse.com>
2295 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
2296 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
2297 register and memory source templates. Replace VexW= by VexW*
2299 * i386-tbl.h: Re-generate.
2301 2020-03-06 Jan Beulich <jbeulich@suse.com>
2303 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
2304 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
2305 * i386-tbl.h: Re-generate.
2307 2020-03-06 Jan Beulich <jbeulich@suse.com>
2309 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
2310 * i386-tbl.h: Re-generate.
2312 2020-03-06 Jan Beulich <jbeulich@suse.com>
2314 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
2315 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
2316 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
2317 VexW0 on SSE2AVX variants.
2318 (vmovq): Drop NoRex64 from XMM/XMM variants.
2319 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
2320 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
2321 applicable use VexW0.
2322 * i386-tbl.h: Re-generate.
2324 2020-03-06 Jan Beulich <jbeulich@suse.com>
2326 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
2327 * i386-opc.h (Rex64): Delete.
2328 (struct i386_opcode_modifier): Remove rex64 field.
2329 * i386-opc.tbl (crc32): Drop Rex64.
2330 Replace Rex64 with Size64 everywhere else.
2331 * i386-tbl.h: Re-generate.
2333 2020-03-06 Jan Beulich <jbeulich@suse.com>
2335 * i386-dis.c (OP_E_memory): Exclude recording of used address
2336 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
2337 addressed memory operands for MPX insns.
2339 2020-03-06 Jan Beulich <jbeulich@suse.com>
2341 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
2342 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
2343 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
2344 (ptwrite): Split into non-64-bit and 64-bit forms.
2345 * i386-tbl.h: Re-generate.
2347 2020-03-06 Jan Beulich <jbeulich@suse.com>
2349 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
2351 * i386-tbl.h: Re-generate.
2353 2020-03-04 Jan Beulich <jbeulich@suse.com>
2355 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
2356 (prefix_table): Move vmmcall here. Add vmgexit.
2357 (rm_table): Replace vmmcall entry by prefix_table[] escape.
2358 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
2359 (cpu_flags): Add CpuSEV_ES entry.
2360 * i386-opc.h (CpuSEV_ES): New.
2361 (union i386_cpu_flags): Add cpusev_es field.
2362 * i386-opc.tbl (vmgexit): New.
2363 * i386-init.h, i386-tbl.h: Re-generate.
2365 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
2367 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
2369 * i386-opc.h (IGNORESIZE): New.
2370 (DEFAULTSIZE): Likewise.
2371 (IgnoreSize): Removed.
2372 (DefaultSize): Likewise.
2373 (MnemonicSize): New.
2374 (i386_opcode_modifier): Replace ignoresize/defaultsize with
2376 * i386-opc.tbl (IgnoreSize): New.
2377 (DefaultSize): Likewise.
2378 * i386-tbl.h: Regenerated.
2380 2020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
2383 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
2386 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
2389 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
2390 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
2391 * i386-tbl.h: Regenerated.
2393 2020-02-26 Alan Modra <amodra@gmail.com>
2395 * aarch64-asm.c: Indent labels correctly.
2396 * aarch64-dis.c: Likewise.
2397 * aarch64-gen.c: Likewise.
2398 * aarch64-opc.c: Likewise.
2399 * alpha-dis.c: Likewise.
2400 * i386-dis.c: Likewise.
2401 * nds32-asm.c: Likewise.
2402 * nfp-dis.c: Likewise.
2403 * visium-dis.c: Likewise.
2405 2020-02-25 Claudiu Zissulescu <claziss@gmail.com>
2407 * arc-regs.h (int_vector_base): Make it available for all ARC
2410 2020-02-20 Nelson Chu <nelson.chu@sifive.com>
2412 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
2415 2020-02-19 Nelson Chu <nelson.chu@sifive.com>
2417 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
2418 c.mv/c.li if rs1 is zero.
2420 2020-02-17 H.J. Lu <hongjiu.lu@intel.com>
2422 * i386-gen.c (cpu_flag_init): Replace CpuABM with
2423 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
2425 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
2426 * i386-opc.h (CpuABM): Removed.
2428 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
2429 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
2430 popcnt. Remove CpuABM from lzcnt.
2431 * i386-init.h: Regenerated.
2432 * i386-tbl.h: Likewise.
2434 2020-02-17 Jan Beulich <jbeulich@suse.com>
2436 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
2437 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
2438 VexW1 instead of open-coding them.
2439 * i386-tbl.h: Re-generate.
2441 2020-02-17 Jan Beulich <jbeulich@suse.com>
2443 * i386-opc.tbl (AddrPrefixOpReg): Define.
2444 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
2445 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
2446 templates. Drop NoRex64.
2447 * i386-tbl.h: Re-generate.
2449 2020-02-17 Jan Beulich <jbeulich@suse.com>
2452 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
2453 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
2454 into Intel syntax instance (with Unpsecified) and AT&T one
2456 (vcvtneps2bf16): Likewise, along with folding the two so far
2458 * i386-tbl.h: Re-generate.
2460 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
2462 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
2463 CPU_ANY_SSE4A_FLAGS.
2465 2020-02-17 Alan Modra <amodra@gmail.com>
2467 * i386-gen.c (cpu_flag_init): Correct last change.
2469 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
2471 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
2474 2020-02-14 H.J. Lu <hongjiu.lu@intel.com>
2476 * i386-opc.tbl (movsx): Remove Intel syntax comments.
2479 2020-02-14 Jan Beulich <jbeulich@suse.com>
2482 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
2483 destination for Cpu64-only variant.
2484 (movzx): Fold patterns.
2485 * i386-tbl.h: Re-generate.
2487 2020-02-13 Jan Beulich <jbeulich@suse.com>
2489 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
2490 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
2491 CPU_ANY_SSE4_FLAGS entry.
2492 * i386-init.h: Re-generate.
2494 2020-02-12 Jan Beulich <jbeulich@suse.com>
2496 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
2497 with Unspecified, making the present one AT&T syntax only.
2498 * i386-tbl.h: Re-generate.
2500 2020-02-12 Jan Beulich <jbeulich@suse.com>
2502 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
2503 * i386-tbl.h: Re-generate.
2505 2020-02-12 Jan Beulich <jbeulich@suse.com>
2508 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
2509 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
2510 Amd64 and Intel64 templates.
2511 (call, jmp): Likewise for far indirect variants. Dro
2513 * i386-tbl.h: Re-generate.
2515 2020-02-11 Jan Beulich <jbeulich@suse.com>
2517 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
2518 * i386-opc.h (ShortForm): Delete.
2519 (struct i386_opcode_modifier): Remove shortform field.
2520 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
2521 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
2522 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
2523 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
2525 * i386-tbl.h: Re-generate.
2527 2020-02-11 Jan Beulich <jbeulich@suse.com>
2529 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
2530 fucompi): Drop ShortForm from operand-less templates.
2531 * i386-tbl.h: Re-generate.
2533 2020-02-11 Alan Modra <amodra@gmail.com>
2535 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
2536 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
2537 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
2538 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
2539 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
2541 2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
2543 * arm-dis.c (print_insn_cde): Define 'V' parse character.
2544 (cde_opcodes): Add VCX* instructions.
2546 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
2547 Matthew Malcomson <matthew.malcomson@arm.com>
2549 * arm-dis.c (struct cdeopcode32): New.
2550 (CDE_OPCODE): New macro.
2551 (cde_opcodes): New disassembly table.
2552 (regnames): New option to table.
2553 (cde_coprocs): New global variable.
2554 (print_insn_cde): New
2555 (print_insn_thumb32): Use print_insn_cde.
2556 (parse_arm_disassembler_options): Parse coprocN args.
2558 2020-02-10 H.J. Lu <hongjiu.lu@intel.com>
2561 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
2563 * i386-opc.h (AMD64): Removed.
2564 (Intel64): Likewose.
2566 (INTEL64): Likewise.
2567 (INTEL64ONLY): Likewise.
2568 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
2569 * i386-opc.tbl (Amd64): New.
2570 (Intel64): Likewise.
2571 (Intel64Only): Likewise.
2572 Replace AMD64 with Amd64. Update sysenter/sysenter with
2573 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
2574 * i386-tbl.h: Regenerated.
2576 2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
2579 * z80-dis.c: Add support for GBZ80 opcodes.
2581 2020-02-04 Alan Modra <amodra@gmail.com>
2583 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
2585 2020-02-03 Alan Modra <amodra@gmail.com>
2587 * m32c-ibld.c: Regenerate.
2589 2020-02-01 Alan Modra <amodra@gmail.com>
2591 * frv-ibld.c: Regenerate.
2593 2020-01-31 Jan Beulich <jbeulich@suse.com>
2595 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
2596 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
2597 (OP_E_memory): Replace xmm_mdq_mode case label by
2598 vex_scalar_w_dq_mode one.
2599 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
2601 2020-01-31 Jan Beulich <jbeulich@suse.com>
2603 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
2604 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
2605 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
2606 (intel_operand_size): Drop vex_w_dq_mode case label.
2608 2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
2610 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
2611 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
2613 2020-01-30 Alan Modra <amodra@gmail.com>
2615 * m32c-ibld.c: Regenerate.
2617 2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
2619 * bpf-opc.c: Regenerate.
2621 2020-01-30 Jan Beulich <jbeulich@suse.com>
2623 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
2624 (dis386): Use them to replace C2/C3 table entries.
2625 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
2626 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
2627 ones. Use Size64 instead of DefaultSize on Intel64 ones.
2628 * i386-tbl.h: Re-generate.
2630 2020-01-30 Jan Beulich <jbeulich@suse.com>
2632 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
2634 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
2636 * i386-tbl.h: Re-generate.
2638 2020-01-30 Alan Modra <amodra@gmail.com>
2640 * tic4x-dis.c (tic4x_dp): Make unsigned.
2642 2020-01-27 H.J. Lu <hongjiu.lu@intel.com>
2643 Jan Beulich <jbeulich@suse.com>
2646 * i386-dis.c (MOVSXD_Fixup): New function.
2647 (movsxd_mode): New enum.
2648 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
2649 (intel_operand_size): Handle movsxd_mode.
2650 (OP_E_register): Likewise.
2652 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
2653 register on movsxd. Add movsxd with 16-bit destination register
2654 for AMD64 and Intel64 ISAs.
2655 * i386-tbl.h: Regenerated.
2657 2020-01-27 Tamar Christina <tamar.christina@arm.com>
2660 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
2661 * aarch64-asm-2.c: Regenerate
2662 * aarch64-dis-2.c: Likewise.
2663 * aarch64-opc-2.c: Likewise.
2665 2020-01-21 Jan Beulich <jbeulich@suse.com>
2667 * i386-opc.tbl (sysret): Drop DefaultSize.
2668 * i386-tbl.h: Re-generate.
2670 2020-01-21 Jan Beulich <jbeulich@suse.com>
2672 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
2674 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
2675 * i386-tbl.h: Re-generate.
2677 2020-01-20 Nick Clifton <nickc@redhat.com>
2679 * po/de.po: Updated German translation.
2680 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2681 * po/uk.po: Updated Ukranian translation.
2683 2020-01-20 Alan Modra <amodra@gmail.com>
2685 * hppa-dis.c (fput_const): Remove useless cast.
2687 2020-01-20 Alan Modra <amodra@gmail.com>
2689 * arm-dis.c (print_insn_arm): Wrap 'T' value.
2691 2020-01-18 Nick Clifton <nickc@redhat.com>
2693 * configure: Regenerate.
2694 * po/opcodes.pot: Regenerate.
2696 2020-01-18 Nick Clifton <nickc@redhat.com>
2698 Binutils 2.34 branch created.
2700 2020-01-17 Christian Biesinger <cbiesinger@google.com>
2702 * opintl.h: Fix spelling error (seperate).
2704 2020-01-17 H.J. Lu <hongjiu.lu@intel.com>
2706 * i386-opc.tbl: Add {vex} pseudo prefix.
2707 * i386-tbl.h: Regenerated.
2709 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
2712 * arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
2713 (neon_opcodes): Likewise.
2714 (select_arm_features): Make sure we enable MVE bits when selecting
2715 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
2718 2020-01-16 Jan Beulich <jbeulich@suse.com>
2720 * i386-opc.tbl: Drop stale comment from XOP section.
2722 2020-01-16 Jan Beulich <jbeulich@suse.com>
2724 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
2725 (extractps): Add VexWIG to SSE2AVX forms.
2726 * i386-tbl.h: Re-generate.
2728 2020-01-16 Jan Beulich <jbeulich@suse.com>
2730 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
2731 Size64 from and use VexW1 on SSE2AVX forms.
2732 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
2733 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
2734 * i386-tbl.h: Re-generate.
2736 2020-01-15 Alan Modra <amodra@gmail.com>
2738 * tic4x-dis.c (tic4x_version): Make unsigned long.
2739 (optab, optab_special, registernames): New file scope vars.
2740 (tic4x_print_register): Set up registernames rather than
2741 malloc'd registertable.
2742 (tic4x_disassemble): Delete optable and optable_special. Use
2743 optab and optab_special instead. Throw away old optab,
2744 optab_special and registernames when info->mach changes.
2746 2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
2749 * z80-dis.c (suffix): Use .db instruction to generate double
2752 2020-01-14 Alan Modra <amodra@gmail.com>
2754 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
2755 values to unsigned before shifting.
2757 2020-01-13 Thomas Troeger <tstroege@gmx.de>
2759 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
2761 (print_insn_thumb16, print_insn_thumb32): Likewise.
2762 (print_insn): Initialize the insn info.
2763 * i386-dis.c (print_insn): Initialize the insn info fields, and
2766 2020-01-13 Claudiu Zissulescu <claziss@gmail.com>
2768 * arc-opc.c (C_NE): Make it required.
2770 2020-01-13 Claudiu Zissulescu <claziss@gmail.com>
2772 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
2773 reserved register name.
2775 2020-01-13 Alan Modra <amodra@gmail.com>
2777 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
2778 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
2780 2020-01-13 Alan Modra <amodra@gmail.com>
2782 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
2783 result of wasm_read_leb128 in a uint64_t and check that bits
2784 are not lost when copying to other locals. Use uint32_t for
2785 most locals. Use PRId64 when printing int64_t.
2787 2020-01-13 Alan Modra <amodra@gmail.com>
2789 * score-dis.c: Formatting.
2790 * score7-dis.c: Formatting.
2792 2020-01-13 Alan Modra <amodra@gmail.com>
2794 * score-dis.c (print_insn_score48): Use unsigned variables for
2795 unsigned values. Don't left shift negative values.
2796 (print_insn_score32): Likewise.
2797 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
2799 2020-01-13 Alan Modra <amodra@gmail.com>
2801 * tic4x-dis.c (tic4x_print_register): Remove dead code.
2803 2020-01-13 Alan Modra <amodra@gmail.com>
2805 * fr30-ibld.c: Regenerate.
2807 2020-01-13 Alan Modra <amodra@gmail.com>
2809 * xgate-dis.c (print_insn): Don't left shift signed value.
2810 (ripBits): Formatting, use 1u.
2812 2020-01-10 Alan Modra <amodra@gmail.com>
2814 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
2815 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
2817 2020-01-10 Alan Modra <amodra@gmail.com>
2819 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
2820 and XRREG value earlier to avoid a shift with negative exponent.
2821 * m10200-dis.c (disassemble): Similarly.
2823 2020-01-09 Nick Clifton <nickc@redhat.com>
2826 * z80-dis.c (ld_ii_ii): Use correct cast.
2828 2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
2831 * z80-dis.c (ld_ii_ii): Use character constant when checking
2834 2020-01-09 Jan Beulich <jbeulich@suse.com>
2836 * i386-dis.c (SEP_Fixup): New.
2838 (dis386_twobyte): Use it for sysenter/sysexit.
2839 (enum x86_64_isa): Change amd64 enumerator to value 1.
2840 (OP_J): Compare isa64 against intel64 instead of amd64.
2841 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
2843 * i386-tbl.h: Re-generate.
2845 2020-01-08 Alan Modra <amodra@gmail.com>
2847 * z8k-dis.c: Include libiberty.h
2848 (instr_data_s): Make max_fetched unsigned.
2849 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
2850 Don't exceed byte_info bounds.
2851 (output_instr): Make num_bytes unsigned.
2852 (unpack_instr): Likewise for nibl_count and loop.
2853 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
2855 * z8k-opc.h: Regenerate.
2857 2020-01-07 Shahab Vahedi <shahab@synopsys.com>
2859 * arc-tbl.h (llock): Use 'LLOCK' as class.
2861 (scond): Use 'SCOND' as class.
2863 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
2866 2020-01-06 Alan Modra <amodra@gmail.com>
2868 * m32c-ibld.c: Regenerate.
2870 2020-01-06 Alan Modra <amodra@gmail.com>
2873 * z80-dis.c (suffix): Don't use a local struct buffer copy.
2874 Peek at next byte to prevent recursion on repeated prefix bytes.
2875 Ensure uninitialised "mybuf" is not accessed.
2876 (print_insn_z80): Don't zero n_fetch and n_used here,..
2877 (print_insn_z80_buf): ..do it here instead.
2879 2020-01-04 Alan Modra <amodra@gmail.com>
2881 * m32r-ibld.c: Regenerate.
2883 2020-01-04 Alan Modra <amodra@gmail.com>
2885 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
2887 2020-01-04 Alan Modra <amodra@gmail.com>
2889 * crx-dis.c (match_opcode): Avoid shift left of signed value.
2891 2020-01-04 Alan Modra <amodra@gmail.com>
2893 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
2895 2020-01-03 Jan Beulich <jbeulich@suse.com>
2897 * aarch64-tbl.h (aarch64_opcode_table): Use
2898 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
2900 2020-01-03 Jan Beulich <jbeulich@suse.com>
2902 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
2903 forms of SUDOT and USDOT.
2905 2020-01-03 Jan Beulich <jbeulich@suse.com>
2907 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
2909 * aarch64-dis-2.c: Re-generate.
2911 2020-01-03 Jan Beulich <jbeulich@suse.com>
2913 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
2915 * aarch64-dis-2.c: Re-generate.
2917 2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
2919 * z80-dis.c: Add support for eZ80 and Z80 instructions.
2921 2020-01-01 Alan Modra <amodra@gmail.com>
2923 Update year range in copyright notice of all files.
2925 For older changes see ChangeLog-2019
2927 Copyright (C) 2020 Free Software Foundation, Inc.
2929 Copying and distribution of this file, with or without modification,
2930 are permitted in any medium without royalty provided the copyright
2931 notice and this notice are preserved.
2937 version-control: never
projects / binutils-gdb.git / blob