opcodes/ChangeLog

   1 2015-08-25  Jose E. Marchesi  <jose.marchesi@oracle.com>
   2
   3         * sparc-dis.c (print_insn_sparc): Handle the privileged register
   4         %pmcdper.
   5
   6 2015-08-24  Jan Stancek  <jstancek@redhat.com>
   7
   8         * i386-dis.c (print_insn): Fix decoding of three byte operands.
   9
  10 2015-08-21  Alexander Fomin  <alexander.fomin@intel.com>
  11
  12         PR binutils/18257
  13         * i386-dis.c: Use MOD_TABLE for most of mask instructions.
  14         (MOD enum): Add MOD_VEX_W_0_0F41_P_0_LEN_1,
  15         MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
  16         MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
  17         MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
  18         MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
  19         MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
  20         MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
  21         MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
  22         MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
  23         MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
  24         MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
  25         MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
  26         MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
  27         MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
  28         MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
  29         MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
  30         MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
  31         MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
  32         MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
  33         MOD_VEX_W_0_0F92_P_3_LEN_0, MOD_VEX_W_1_0F92_P_3_LEN_0,
  34         MOD_VEX_W_0_0F93_P_0_LEN_0, MOD_VEX_W_0_0F93_P_2_LEN_0,
  35         MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0,
  36         MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
  37         MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
  38         MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
  39         MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
  40         MOD_VEX_W_0_0F3A30_P_2_LEN_0, MOD_VEX_W_1_0F3A30_P_2_LEN_0,
  41         MOD_VEX_W_0_0F3A31_P_2_LEN_0, MOD_VEX_W_1_0F3A31_P_2_LEN_0,
  42         MOD_VEX_W_0_0F3A32_P_2_LEN_0, MOD_VEX_W_1_0F3A32_P_2_LEN_0,
  43         MOD_VEX_W_0_0F3A33_P_2_LEN_0, MOD_VEX_W_1_0F3A33_P_2_LEN_0.
  44         (vex_w_table): Replace terminals with MOD_TABLE entries for
  45         most of mask instructions.
  46
  47 2015-08-17  Alan Modra  <amodra@gmail.com>
  48
  49         * cgen.sh: Trim trailing space from cgen output.
  50         * ia64-gen.c (print_dependency_table): Don't generate trailing space.
  51         (print_dis_table): Likewise.
  52         * opc2c.c (dump_lines): Likewise.
  53         (orig_filename): Warning fix.
  54         * ia64-asmtab.c: Regenerate.
  55
  56 2015-08-13  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  57
  58         * arm-dis.c (print_insn_arm): Disassembling for all targets V6
  59         and higher with ARM instruction set will now mark the 26-bit
  60         versions of teq,tst,cmn and cmp as UNPREDICTABLE.
  61         (arm_opcodes): Fix for unpredictable nop being recognized as a
  62         teq.
  63
  64 2015-08-12  Simon Dardis  <simon.dardis@imgtec.com>
  65
  66         * micromips-opc.c (micromips_opcodes): Re-order table so that move
  67         based on 'or' is first.
  68         * mips-opc.c (mips_builtin_opcodes): Ditto.
  69
  70 2015-08-11  Nick Clifton  <nickc@redhat.com>
  71
  72         PR 18800
  73         * aarch64-tbl.h (aarch64_opcode_table): Fix mask for SIMD EXT
  74         instruction.
  75
  76 2015-08-10  Robert Suchanek  <robert.suchanek@imgtec.com>
  77
  78         * mips-opc.c (mips_builtin_opcodes): Add "sigrie".
  79
  80 2015-08-07  Amit Pawar <Amit.Pawar@amd.com>
  81
  82         * i386-gen.c: Remove CpuFMA4 from CPU_ZNVER1_FLAGS.
  83         * i386-init.h: Regenerated.
  84
  85 2015-07-30  H.J. Lu  <hongjiu.lu@intel.com>
  86
  87         PR binutils/13571
  88         * i386-dis.c (MOD_0FC3): New.
  89         (PREFIX_0FC3): Renamed to ...
  90         (PREFIX_MOD_0_0FC3): This.
  91         (dis386_twobyte): Replace PREFIX_0FC3 with MOD_0FC3.
  92         (prefix_table): Replace Ma with Ev on movntiS.
  93         (mod_table): Add MOD_0FC3.
  94
  95 2015-07-27  H.J. Lu  <hongjiu.lu@intel.com>
  96
  97         * configure: Regenerated.
  98
  99 2015-07-23  Alan Modra  <amodra@gmail.com>
 100
 101         PR 18708
 102         * i386-dis.c (get64): Avoid signed integer overflow.
 103
 104 2015-07-22  Alexander Fomin  <alexander.fomin@intel.com>
 105
 106         PR binutils/18631
 107         * i386-dis-evex.h (EVEX_W_0F78_P_2): Replace "EXxmmq" with
 108         "EXEvexHalfBcstXmmq" for the second operand.
 109         (EVEX_W_0F79_P_2): Likewise.
 110         (EVEX_W_0F7A_P_2): Likewise.
 111         (EVEX_W_0F7B_P_2): Likewise.
 112
 113 2015-07-16  Alessandro Marzocchi  <alessandro.marzocchi@gmail.com>
 114
 115         * arm-dis.c (print_insn_coprocessor): Added support for quarter
 116         float bitfield format.
 117         (coprocessor_opcodes): Changed VFP vmov reg,immediate to use new
 118         quarter float bitfield format.
 119
 120 2015-07-14  H.J. Lu  <hongjiu.lu@intel.com>
 121
 122         * configure: Regenerated.
 123
 124 2015-07-03  Alan Modra  <amodra@gmail.com>
 125
 126         * ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
 127         * ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries.  Add
 128         PPC_OPCODE_7450 to 7450 entry.  Add PPC_OPCODE_750 to 750cl entry.
 129
 130 2015-07-01  Sandra Loosemore  <sandra@codesourcery.com>
 131             Cesar Philippidis  <cesar@codesourcery.com>
 132
 133         * nios2-dis.c (nios2_extract_opcode): New.
 134         (nios2_disassembler_state): New.
 135         (nios2_find_opcode_hash): Use mach parameter to select correct
 136         disassembler state.
 137         (nios2_print_insn_arg): Extend to support new R2 argument letters
 138         and formats.
 139         (print_insn_nios2): Check for 16-bit instruction at end of memory.
 140         * nios2-opc.c (nios2_builtin_regs): Add R2 register attributes.
 141         (NIOS2_NUM_OPCODES): Rename to...
 142         (NIOS2_NUM_R1_OPCODES): This.
 143         (nios2_r2_opcodes): New.
 144         (NIOS2_NUM_R2_OPCODES): New.
 145         (nios2_num_r2_opcodes): New.
 146         (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New.
 147         (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New.
 148         (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New.
 149         (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New.
 150         (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): New.
 151
 152 2015-06-30  Amit Pawar  <Amit.Pawar@amd.com>
 153
 154         * i386-dis.c (OP_Mwaitx): New.
 155         (rm_table): Add monitorx/mwaitx.
 156         * i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS
 157         and CPU_ZNVER1_FLAGS.  Add CPU_MWAITX_FLAGS.
 158         (operand_type_init): Add CpuMWAITX.
 159         * i386-opc.h (CpuMWAITX): New.
 160         (i386_cpu_flags): Add cpumwaitx.
 161         * i386-opc.tbl: Add monitorx and mwaitx.
 162         * i386-init.h: Regenerated.
 163         * i386-tbl.h: Likewise.
 164
 165 2015-06-22  Peter Bergner  <bergner@vnet.ibm.com>
 166
 167         * ppc-opc.c (insert_ls): Test for invalid LS operands.
 168         (insert_esync): New function.
 169         (LS, WC): Use insert_ls.
 170         (ESYNC): Use insert_esync.
 171
 172 2015-06-22  Nick Clifton  <nickc@redhat.com>
 173
 174         * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
 175         requested region lies beyond it.
 176         * bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
 177         looking for 32-bit insns.
 178         * mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
 179         data.
 180         * sh-dis.c (print_insn_sh): Likewise.
 181         * tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
 182         blocks of instructions.
 183         * vax-dis.c (print_insn_vax): Check that the requested address
 184         does not clash with the stop_vma.
 185
 186 2015-06-19  Peter Bergner  <bergner@vnet.ibm.com>
 187
 188         * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
 189         * ppc-opc.c (FXM4): Add non-zero optional value.
 190         (TBR): Likewise.
 191         (SXL): Likewise.
 192         (insert_fxm): Handle new default operand value.
 193         (extract_fxm): Likewise.
 194         (insert_tbr): Likewise.
 195         (extract_tbr): Likewise.
 196
 197 2015-06-16  Matthew Wahab  <matthew.wahab@arm.com>
 198
 199         * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
 200
 201 2015-06-16  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 202
 203         * arm-dis.c (print_insn_coprocessor): Avoid negative shift.
 204
 205 2015-06-12  Peter Bergner  <bergner@vnet.ibm.com>
 206
 207         * ppc-opc.c: Add comment accidentally removed by old commit.
 208         (MTMSRD_L): Delete.
 209
 210 2015-06-04  Peter Bergner  <bergner@vnet.ibm.com>
 211
 212         * ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.
 213
 214 2015-06-04  Nick Clifton  <nickc@redhat.com>
 215
 216         PR 18474
 217         * msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
 218
 219 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 220
 221         * arm-dis.c (arm_opcodes): Add "setpan".
 222         (thumb_opcodes): Add "setpan".
 223
 224 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 225
 226         * arm-dis.c (select_arm_features): Rework to avoid used of redefined
 227         macros.
 228
 229 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 230
 231         * aarch64-tbl.h (aarch64_feature_rdma): New.
 232         (RDMA): New.
 233         (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
 234         * aarch64-asm-2.c: Regenerate.
 235         * aarch64-dis-2.c: Regenerate.
 236         * aarch64-opc-2.c: Regenerate.
 237
 238 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 239
 240         * aarch64-tbl.h (aarch64_feature_lor): New.
 241         (LOR): New.
 242         (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
 243         "stllrb", "stllrh".
 244         * aarch64-asm-2.c: Regenerate.
 245         * aarch64-dis-2.c: Regenerate.
 246         * aarch64-opc-2.c: Regenerate.
 247
 248 2015-06-01  Matthew Wahab  <matthew.wahab@arm.com>
 249
 250         * aarch64-opc.c (F_ARCHEXT): New.
 251         (aarch64_sys_regs): Add "pan".
 252         (aarch64_sys_reg_supported_p): New.
 253         (aarch64_pstatefields): Add "pan".
 254         (aarch64_pstatefield_supported_p): New.
 255
 256 2015-06-01  Jan Beulich  <jbeulich@suse.com>
 257
 258         * i386-tbl.h: Regenerate.
 259
 260 2015-06-01  Jan Beulich  <jbeulich@suse.com>
 261
 262         * i386-dis.c (print_insn): Swap rounding mode specifier and
 263         general purpose register in Intel mode.
 264
 265 2015-06-01  Jan Beulich  <jbeulich@suse.com>
 266
 267         * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
 268         * i386-tbl.h: Regenerate.
 269
 270 2015-05-18  H.J. Lu  <hongjiu.lu@intel.com>
 271
 272         * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
 273         * i386-init.h: Regenerated.
 274
 275 2015-05-15  H.J. Lu  <hongjiu.lu@intel.com>
 276
 277         PR binutis/18386
 278         * i386-dis.c: Add comments for '@'.
 279         (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
 280         (enum x86_64_isa): New.
 281         (isa64): Likewise.
 282         (print_i386_disassembler_options): Add amd64 and intel64.
 283         (print_insn): Handle amd64 and intel64.
 284         (putop): Handle '@'.
 285         (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
 286         * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
 287         * i386-opc.h (AMD64): New.
 288         (CpuIntel64): Likewise.
 289         (i386_cpu_flags): Add cpuamd64 and cpuintel64.
 290         * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
 291         Mark direct call/jmp without Disp16|Disp32 as Intel64.
 292         * i386-init.h: Regenerated.
 293         * i386-tbl.h: Likewise.
 294
 295 2015-05-14  Peter Bergner  <bergner@vnet.ibm.com>
 296
 297         * ppc-opc.c (IH) New define.
 298         (powerpc_opcodes) <wait>: Do not enable for POWER7.
 299         <tlbie>: Add RS operand for POWER7.
 300         <slbia>: Add IH operand for POWER6.
 301
 302 2015-05-11  H.J. Lu  <hongjiu.lu@intel.com>
 303
 304         * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
 305         direct branch.
 306         (jmp): Likewise.
 307         * i386-tbl.h: Regenerated.
 308
 309 2015-05-11  H.J. Lu  <hongjiu.lu@intel.com>
 310
 311         * configure.ac: Support bfd_iamcu_arch.
 312         * disassemble.c (disassembler): Support bfd_iamcu_arch.
 313         * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
 314         CPU_IAMCU_COMPAT_FLAGS.
 315         (cpu_flags): Add CpuIAMCU.
 316         * i386-opc.h (CpuIAMCU): New.
 317         (i386_cpu_flags): Add cpuiamcu.
 318         * configure: Regenerated.
 319         * i386-init.h: Likewise.
 320         * i386-tbl.h: Likewise.
 321
 322 2015-05-08  H.J. Lu  <hongjiu.lu@intel.com>
 323
 324         PR binutis/18386
 325         * i386-dis.c (X86_64_E8): New.
 326         (X86_64_E9): Likewise.
 327         Update comments on 'T', 'U', 'V'.  Add comments for '^'.
 328         (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
 329         (x86_64_table): Add X86_64_E8 and X86_64_E9.
 330         (mod_table): Replace {T|} with ^ on Jcall/Jmp.
 331         (putop): Handle '^'.
 332         (OP_J): Ignore the operand size prefix in 64-bit.  Don't check
 333         REX_W.
 334
 335 2015-04-30  DJ Delorie  <dj@redhat.com>
 336
 337         * disassemble.c (disassembler): Choose suitable disassembler based
 338         on E_ABI.
 339         * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter.  Use
 340         it to decode mul/div insns.
 341         * rl78-decode.c: Regenerate.
 342         * rl78-dis.c (print_insn_rl78): Rename to...
 343         (print_insn_rl78_common): ...this, take ISA parameter.
 344         (print_insn_rl78): New.
 345         (print_insn_rl78_g10): New.
 346         (print_insn_rl78_g13): New.
 347         (print_insn_rl78_g14): New.
 348         (rl78_get_disassembler): New.
 349
 350 2015-04-29  Nick Clifton  <nickc@redhat.com>
 351
 352         * po/fr.po: Updated French translation.
 353
 354 2015-04-27  Peter Bergner  <bergner@vnet.ibm.com>
 355
 356         * ppc-opc.c (DCBT_EO): New define.
 357         (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
 358         <lharx>: Likewise.
 359         <stbcx.>: Likewise.
 360         <sthcx.>: Likewise.
 361         <waitrsv>: Do not enable for POWER7 and later.
 362         <waitimpl>: Likewise.
 363         <dcbt>: Default to the two operand form of the instruction for all
 364         "old" cpus.  For "new" cpus, use the operand ordering that matches
 365         whether the cpu is server or embedded.
 366         <dcbtst>: Likewise.
 367
 368 2015-04-27  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 369
 370         * s390-opc.c: New instruction type VV0UU2.
 371         * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
 372         and WFC.
 373
 374 2015-04-23  Jan Beulich  <jbeulich@suse.com>
 375
 376         * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
 377         * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
 378         vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
 379         (vfpclasspd, vfpclassps): Add %XZ.
 380
 381 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 382
 383         * i386-dis.c (PREFIX_UD_SHIFT): Removed.
 384         (PREFIX_UD_REPZ): Likewise.
 385         (PREFIX_UD_REPNZ): Likewise.
 386         (PREFIX_UD_DATA): Likewise.
 387         (PREFIX_UD_ADDR): Likewise.
 388         (PREFIX_UD_LOCK): Likewise.
 389
 390 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 391
 392         * i386-dis.c (prefix_requirement): Removed.
 393         (print_insn): Don't set prefix_requirement.  Check
 394         dp->prefix_requirement instead of prefix_requirement.
 395
 396 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 397
 398         PR binutils/17898
 399         * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
 400         (PREFIX_MOD_0_0FC7_REG_6): This.
 401         (PREFIX_MOD_3_0FC7_REG_6): New.
 402         (PREFIX_MOD_3_0FC7_REG_7): Likewise.
 403         (prefix_table): Replace PREFIX_0FC7_REG_6 with
 404         PREFIX_MOD_0_0FC7_REG_6.  Add PREFIX_MOD_3_0FC7_REG_6 and
 405         PREFIX_MOD_3_0FC7_REG_7.
 406         (mod_table): Replace PREFIX_0FC7_REG_6 with
 407         PREFIX_MOD_0_0FC7_REG_6.  Use PREFIX_MOD_3_0FC7_REG_6 and
 408         PREFIX_MOD_3_0FC7_REG_7.
 409
 410 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 411
 412         * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
 413         (PREFIX_MANDATORY_REPNZ): Likewise.
 414         (PREFIX_MANDATORY_DATA): Likewise.
 415         (PREFIX_MANDATORY_ADDR): Likewise.
 416         (PREFIX_MANDATORY_LOCK): Likewise.
 417         (PREFIX_MANDATORY): Likewise.
 418         (PREFIX_UD_SHIFT): Set to 8
 419         (PREFIX_UD_REPZ): Updated.
 420         (PREFIX_UD_REPNZ): Likewise.
 421         (PREFIX_UD_DATA): Likewise.
 422         (PREFIX_UD_ADDR): Likewise.
 423         (PREFIX_UD_LOCK): Likewise.
 424         (PREFIX_IGNORED_SHIFT): New.
 425         (PREFIX_IGNORED_REPZ): Likewise.
 426         (PREFIX_IGNORED_REPNZ): Likewise.
 427         (PREFIX_IGNORED_DATA): Likewise.
 428         (PREFIX_IGNORED_ADDR): Likewise.
 429         (PREFIX_IGNORED_LOCK): Likewise.
 430         (PREFIX_OPCODE): Likewise.
 431         (PREFIX_IGNORED): Likewise.
 432         (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
 433         (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
 434         (three_byte_table): Likewise.
 435         (mod_table): Likewise.
 436         (mandatory_prefix): Renamed to ...
 437         (prefix_requirement): This.
 438         (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
 439         Update PREFIX_90 entry.
 440         (get_valid_dis386): Check prefix_requirement to see if a prefix
 441         should be ignored.
 442         (print_insn): Replace mandatory_prefix with prefix_requirement.
 443
 444 2015-04-15  Renlin Li  <renlin.li@arm.com>
 445
 446         * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
 447         use it for ssat and ssat16.
 448         (print_insn_thumb32): Add handle case for 'D' control code.
 449
 450 2015-04-06  Ilya Tocar  <ilya.tocar@intel.com>
 451             H.J. Lu  <hongjiu.lu@intel.com>
 452
 453         * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
 454         * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
 455         PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
 456         PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
 457         PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
 458         (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
 459         Fill prefix_requirement field.
 460         (struct dis386): Add prefix_requirement field.
 461         (dis386): Fill prefix_requirement field.
 462         (dis386_twobyte): Ditto.
 463         (twobyte_has_mandatory_prefix_: Remove.
 464         (reg_table): Fill prefix_requirement field.
 465         (prefix_table): Ditto.
 466         (x86_64_table): Ditto.
 467         (three_byte_table): Ditto.
 468         (xop_table): Ditto.
 469         (vex_table): Ditto.
 470         (vex_len_table): Ditto.
 471         (vex_w_table): Ditto.
 472         (mod_table): Ditto.
 473         (bad_opcode): Ditto.
 474         (print_insn): Use prefix_requirement.
 475         (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
 476         FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
 477         (float_reg): Ditto.
 478
 479 2015-03-30  Mike Frysinger  <vapier@gentoo.org>
 480
 481         * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
 482
 483 2015-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 484
 485         * Makefile.in: Regenerated.
 486
 487 2015-03-25  Anton Blanchard  <anton@samba.org>
 488
 489         * ppc-dis.c (disassemble_init_powerpc): Only initialise
 490         powerpc_opcd_indices and vle_opcd_indices once.
 491
 492 2015-03-25  Anton Blanchard  <anton@samba.org>
 493
 494         * ppc-opc.c (powerpc_opcodes): Add slbfee.
 495
 496 2015-03-24  Terry Guo  <terry.guo@arm.com>
 497
 498         * arm-dis.c (opcode32): Updated to use new arm feature struct.
 499         (opcode16): Likewise.
 500         (coprocessor_opcodes): Replace bit with feature struct.
 501         (neon_opcodes): Likewise.
 502         (arm_opcodes): Likewise.
 503         (thumb_opcodes): Likewise.
 504         (thumb32_opcodes): Likewise.
 505         (print_insn_coprocessor): Likewise.
 506         (print_insn_arm): Likewise.
 507         (select_arm_features): Follow new feature struct.
 508
 509 2015-03-17  Ganesh Gopalasubramanian  <Ganesh.Gopalasubramanian@amd.com>
 510
 511         * i386-dis.c (rm_table): Add clzero.
 512         * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
 513         Add CPU_CLZERO_FLAGS.
 514         (cpu_flags): Add CpuCLZERO.
 515         * i386-opc.h: Add CpuCLZERO.
 516         * i386-opc.tbl: Add clzero.
 517         * i386-init.h: Re-generated.
 518         * i386-tbl.h: Re-generated.
 519
 520 2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>
 521
 522         * mips-opc.c (decode_mips_operand): Fix constraint issues
 523         with u and y operands.
 524
 525 2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>
 526
 527         * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
 528
 529 2015-03-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 530
 531         * s390-opc.c: Add new IBM z13 instructions.
 532         * s390-opc.txt: Likewise.
 533
 534 2015-03-10  Renlin Li  <renlin.li@arm.com>
 535
 536         * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
 537         stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
 538         related alias.
 539         * aarch64-asm-2.c: Regenerate.
 540         * aarch64-dis-2.c: Likewise.
 541         * aarch64-opc-2.c: Likewise.
 542
 543 2015-03-03  Jiong Wang  <jiong.wang@arm.com>
 544
 545         * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
 546
 547 2015-02-25  Oleg Endo  <olegendo@gcc.gnu.org>
 548
 549         * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
 550         arch_sh_up.
 551         (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
 552         arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
 553
 554 2015-02-23  Vinay  <Vinay.G@kpit.com>
 555
 556         * rl78-decode.opc (MOV): Added space between two operands for
 557         'mov' instruction in index addressing mode.
 558         * rl78-decode.c: Regenerate.
 559
 560 2015-02-19  Pedro Alves  <palves@redhat.com>
 561
 562         * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
 563
 564 2015-02-10  Pedro Alves  <palves@redhat.com>
 565             Tom Tromey  <tromey@redhat.com>
 566
 567         * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
 568         microblaze_and, microblaze_xor.
 569         * microblaze-opc.h (opcodes): Adjust.
 570
 571 2015-01-28  James Bowman  <james.bowman@ftdichip.com>
 572
 573         * Makefile.am: Add FT32 files.
 574         * configure.ac: Handle FT32.
 575         * disassemble.c (disassembler): Call print_insn_ft32.
 576         * ft32-dis.c: New file.
 577         * ft32-opc.c: New file.
 578         * Makefile.in: Regenerate.
 579         * configure: Regenerate.
 580         * po/POTFILES.in: Regenerate.
 581
 582 2015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
 583
 584         * nds32-asm.c (keyword_sr): Add new system registers.
 585
 586 2015-01-16  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 587
 588         * s390-dis.c (s390_extract_operand): Support vector register
 589         operands.
 590         (s390_print_insn_with_opcode): Support new operands types and add
 591         new handling of optional operands.
 592         * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
 593         and include opcode/s390.h instead.
 594         (struct op_struct): New field `flags'.
 595         (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
 596         (dumpTable): Dump flags.
 597         (main): Parse flags from the s390-opc.txt file.  Add z13 as cpu
 598         string.
 599         * s390-opc.c: Add new operands types, instruction formats, and
 600         instruction masks.
 601         (s390_opformats): Add new formats for .insn.
 602         * s390-opc.txt: Add new instructions.
 603
 604 2015-01-01  Alan Modra  <amodra@gmail.com>
 605
 606         Update year range in copyright notice of all files.
 607
 608 For older changes see ChangeLog-2014
 609 \f
 610 Copyright (C) 2015 Free Software Foundation, Inc.
 611
 612 Copying and distribution of this file, with or without modification,
 613 are permitted in any medium without royalty provided the copyright
 614 notice and this notice are preserved.
 615
 616 Local Variables:
 617 mode: change-log
 618 left-margin: 8
 619 fill-column: 74
 620 version-control: never
 621 End: