opcodes/ChangeLog

   1 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
   2             Michael Collison <michael.collison@arm.com>
   3
   4         * arm-dis.c (thumb32_opcodes): Add new instructions.
   5         (enum mve_instructions): Likewise.
   6         (is_mve_encoding_conflict): Likewise.
   7         (is_mve_unpredictable): Likewise.
   8         (print_mve_size): Likewise.
   9
  10 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  11             Michael Collison <michael.collison@arm.com>
  12
  13         * arm-dis.c (thumb32_opcodes): Add new instructions.
  14         (enum mve_instructions): Likewise.
  15         (is_mve_encoding_conflict): Handle new instructions.
  16         (is_mve_undefined): Likewise.
  17         (is_mve_unpredictable): Likewise.
  18         (print_mve_size): Likewise.
  19
  20 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  21             Michael Collison <michael.collison@arm.com>
  22
  23         * arm-dis.c (thumb32_opcodes): Add new instructions.
  24         (enum mve_instructions): Likewise.
  25         (is_mve_encoding_conflict): Handle new instructions.
  26         (is_mve_undefined): Likewise.
  27         (is_mve_unpredictable): Likewise.
  28         (print_mve_size): Likewise.
  29         (print_insn_mve): Likewise.
  30
  31 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  32             Michael Collison <michael.collison@arm.com>
  33
  34         * arm-dis.c (thumb32_opcodes): Add new instructions.
  35         (print_insn_thumb32): Handle new instructions.
  36
  37 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  38             Michael Collison <michael.collison@arm.com>
  39
  40         * arm-dis.c (enum mve_instructions): Add new instructions.
  41         (enum mve_undefined): Add new reasons.
  42         (is_mve_encoding_conflict): Handle new instructions.
  43         (is_mve_undefined): Likewise.
  44         (is_mve_unpredictable): Likewise.
  45         (print_mve_undefined): Likewise.
  46         (print_mve_size): Likewise.
  47         (print_mve_shift_n): Likewise.
  48         (print_insn_mve): Likewise.
  49
  50 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  51             Michael Collison <michael.collison@arm.com>
  52
  53         * arm-dis.c (enum mve_instructions): Add new instructions.
  54         (is_mve_encoding_conflict): Handle new instructions.
  55         (is_mve_unpredictable): Likewise.
  56         (print_mve_rotate): Likewise.
  57         (print_mve_size): Likewise.
  58         (print_insn_mve): Likewise.
  59
  60 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  61             Michael Collison <michael.collison@arm.com>
  62
  63         * arm-dis.c (enum mve_instructions): Add new instructions.
  64         (is_mve_encoding_conflict): Handle new instructions.
  65         (is_mve_unpredictable): Likewise.
  66         (print_mve_size): Likewise.
  67         (print_insn_mve): Likewise.
  68
  69 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  70             Michael Collison <michael.collison@arm.com>
  71
  72         * arm-dis.c (enum mve_instructions): Add new instructions.
  73         (enum mve_undefined): Add new reasons.
  74         (is_mve_encoding_conflict): Handle new instructions.
  75         (is_mve_undefined): Likewise.
  76         (is_mve_unpredictable): Likewise.
  77         (print_mve_undefined): Likewise.
  78         (print_mve_size): Likewise.
  79         (print_insn_mve): Likewise.
  80
  81 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  82             Michael Collison <michael.collison@arm.com>
  83
  84         * arm-dis.c (enum mve_instructions): Add new instructions.
  85         (is_mve_encoding_conflict): Handle new instructions.
  86         (is_mve_undefined): Likewise.
  87         (is_mve_unpredictable): Likewise.
  88         (print_mve_size): Likewise.
  89         (print_insn_mve): Likewise.
  90
  91 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  92             Michael Collison <michael.collison@arm.com>
  93
  94         * arm-dis.c (enum mve_instructions): Add new instructions.
  95         (enum mve_unpredictable): Add new reasons.
  96         (enum mve_undefined): Likewise.
  97         (is_mve_okay_in_it): Handle new isntructions.
  98         (is_mve_encoding_conflict): Likewise.
  99         (is_mve_undefined): Likewise.
 100         (is_mve_unpredictable): Likewise.
 101         (print_mve_vmov_index): Likewise.
 102         (print_simd_imm8): Likewise.
 103         (print_mve_undefined): Likewise.
 104         (print_mve_unpredictable): Likewise.
 105         (print_mve_size): Likewise.
 106         (print_insn_mve): Likewise.
 107
 108 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 109             Michael Collison <michael.collison@arm.com>
 110
 111         * arm-dis.c (enum mve_instructions): Add new instructions.
 112         (enum mve_unpredictable): Add new reasons.
 113         (enum mve_undefined): Likewise.
 114         (is_mve_encoding_conflict): Handle new instructions.
 115         (is_mve_undefined): Likewise.
 116         (is_mve_unpredictable): Likewise.
 117         (print_mve_undefined): Likewise.
 118         (print_mve_unpredictable): Likewise.
 119         (print_mve_rounding_mode): Likewise.
 120         (print_mve_vcvt_size): Likewise.
 121         (print_mve_size): Likewise.
 122         (print_insn_mve): Likewise.
 123
 124 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 125             Michael Collison <michael.collison@arm.com>
 126
 127         * arm-dis.c (enum mve_instructions): Add new instructions.
 128         (enum mve_unpredictable): Add new reasons.
 129         (enum mve_undefined): Likewise.
 130         (is_mve_undefined): Handle new instructions.
 131         (is_mve_unpredictable): Likewise.
 132         (print_mve_undefined): Likewise.
 133         (print_mve_unpredictable): Likewise.
 134         (print_mve_size): Likewise.
 135         (print_insn_mve): Likewise.
 136
 137 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 138             Michael Collison <michael.collison@arm.com>
 139
 140         * arm-dis.c (enum mve_instructions): Add new instructions.
 141         (enum mve_undefined): Add new reasons.
 142         (insns): Add new instructions.
 143         (is_mve_encoding_conflict):
 144         (print_mve_vld_str_addr): New print function.
 145         (is_mve_undefined): Handle new instructions.
 146         (is_mve_unpredictable): Likewise.
 147         (print_mve_undefined): Likewise.
 148         (print_mve_size): Likewise.
 149         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
 150         (print_insn_mve):  Handle new operands.
 151
 152 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 153             Michael Collison <michael.collison@arm.com>
 154
 155         * arm-dis.c (enum mve_instructions): Add new instructions.
 156         (enum mve_unpredictable): Add new reasons.
 157         (is_mve_encoding_conflict): Handle new instructions.
 158         (is_mve_unpredictable): Likewise.
 159         (mve_opcodes): Add new instructions.
 160         (print_mve_unpredictable): Handle new reasons.
 161         (print_mve_register_blocks): New print function.
 162         (print_mve_size): Handle new instructions.
 163         (print_insn_mve): Likewise.
 164
 165 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 166             Michael Collison <michael.collison@arm.com>
 167
 168         * arm-dis.c (enum mve_instructions): Add new instructions.
 169         (enum mve_unpredictable): Add new reasons.
 170         (enum mve_undefined): Likewise.
 171         (is_mve_encoding_conflict): Handle new instructions.
 172         (is_mve_undefined): Likewise.
 173         (is_mve_unpredictable): Likewise.
 174         (coprocessor_opcodes): Move NEON VDUP from here...
 175         (neon_opcodes): ... to here.
 176         (mve_opcodes): Add new instructions.
 177         (print_mve_undefined):  Handle new reasons.
 178         (print_mve_unpredictable): Likewise.
 179         (print_mve_size): Handle new instructions.
 180         (print_insn_neon): Handle vdup.
 181         (print_insn_mve): Handle new operands.
 182
 183 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 184             Michael Collison <michael.collison@arm.com>
 185
 186         * arm-dis.c (enum mve_instructions): Add new instructions.
 187         (enum mve_unpredictable): Add new values.
 188         (mve_opcodes): Add new instructions.
 189         (vec_condnames): New array with vector conditions.
 190         (mve_predicatenames): New array with predicate suffixes.
 191         (mve_vec_sizename): New array with vector sizes.
 192         (enum vpt_pred_state): New enum with vector predication states.
 193         (struct vpt_block): New struct type for vpt blocks.
 194         (vpt_block_state): Global struct to keep track of state.
 195         (mve_extract_pred_mask): New helper function.
 196         (num_instructions_vpt_block): Likewise.
 197         (mark_outside_vpt_block): Likewise.
 198         (mark_inside_vpt_block): Likewise.
 199         (invert_next_predicate_state): Likewise.
 200         (update_next_predicate_state): Likewise.
 201         (update_vpt_block_state): Likewise.
 202         (is_vpt_instruction): Likewise.
 203         (is_mve_encoding_conflict): Add entries for new instructions.
 204         (is_mve_unpredictable): Likewise.
 205         (print_mve_unpredictable): Handle new cases.
 206         (print_instruction_predicate): Likewise.
 207         (print_mve_size): New function.
 208         (print_vec_condition): New function.
 209         (print_insn_mve): Handle vpt blocks and new print operands.
 210
 211 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 212
 213         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
 214         8, 14 and 15 for Armv8.1-M Mainline.
 215
 216 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 217             Michael Collison <michael.collison@arm.com>
 218
 219         * arm-dis.c (enum mve_instructions): New enum.
 220         (enum mve_unpredictable): Likewise.
 221         (enum mve_undefined): Likewise.
 222         (struct mopcode32): New struct.
 223         (is_mve_okay_in_it): New function.
 224         (is_mve_architecture): Likewise.
 225         (arm_decode_field): Likewise.
 226         (arm_decode_field_multiple): Likewise.
 227         (is_mve_encoding_conflict): Likewise.
 228         (is_mve_undefined): Likewise.
 229         (is_mve_unpredictable): Likewise.
 230         (print_mve_undefined): Likewise.
 231         (print_mve_unpredictable): Likewise.
 232         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
 233         (print_insn_mve): New function.
 234         (print_insn_thumb32): Handle MVE architecture.
 235         (select_arm_features): Force thumb for Armv8.1-m Mainline.
 236
 237 2019-05-10  Nick Clifton  <nickc@redhat.com>
 238
 239         PR 24538
 240         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
 241         end of the table prematurely.
 242
 243 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 244
 245         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
 246         macros for R6.
 247
 248 2019-05-11  Alan Modra  <amodra@gmail.com>
 249
 250         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
 251         when -Mraw is in effect.
 252
 253 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 254
 255         * aarch64-dis-2.c: Regenerate.
 256         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
 257         (OP_SVE_BBB): New variant set.
 258         (OP_SVE_DDDD): New variant set.
 259         (OP_SVE_HHH): New variant set.
 260         (OP_SVE_HHHU): New variant set.
 261         (OP_SVE_SSS): New variant set.
 262         (OP_SVE_SSSU): New variant set.
 263         (OP_SVE_SHH): New variant set.
 264         (OP_SVE_SBBU): New variant set.
 265         (OP_SVE_DSS): New variant set.
 266         (OP_SVE_DHHU): New variant set.
 267         (OP_SVE_VMV_HSD_BHS): New variant set.
 268         (OP_SVE_VVU_HSD_BHS): New variant set.
 269         (OP_SVE_VVVU_SD_BH): New variant set.
 270         (OP_SVE_VVVU_BHSD): New variant set.
 271         (OP_SVE_VVV_QHD_DBS): New variant set.
 272         (OP_SVE_VVV_HSD_BHS): New variant set.
 273         (OP_SVE_VVV_HSD_BHS2): New variant set.
 274         (OP_SVE_VVV_BHS_HSD): New variant set.
 275         (OP_SVE_VV_BHS_HSD): New variant set.
 276         (OP_SVE_VVV_SD): New variant set.
 277         (OP_SVE_VVU_BHS_HSD): New variant set.
 278         (OP_SVE_VZVV_SD): New variant set.
 279         (OP_SVE_VZVV_BH): New variant set.
 280         (OP_SVE_VZV_SD): New variant set.
 281         (aarch64_opcode_table): Add sve2 instructions.
 282
 283 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 284
 285         * aarch64-asm-2.c: Regenerated.
 286         * aarch64-dis-2.c: Regenerated.
 287         * aarch64-opc-2.c: Regenerated.
 288         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 289         for SVE_SHLIMM_UNPRED_22.
 290         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
 291         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
 292         operand.
 293
 294 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 295
 296         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 297         sve_size_tsz_bhs iclass encode.
 298         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 299         sve_size_tsz_bhs iclass decode.
 300
 301 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 302
 303         * aarch64-asm-2.c: Regenerated.
 304         * aarch64-dis-2.c: Regenerated.
 305         * aarch64-opc-2.c: Regenerated.
 306         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 307         for SVE_Zm4_11_INDEX.
 308         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
 309         (fields): Handle SVE_i2h field.
 310         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
 311         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
 312
 313 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 314
 315         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 316         sve_shift_tsz_bhsd iclass encode.
 317         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 318         sve_shift_tsz_bhsd iclass decode.
 319
 320 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 321
 322         * aarch64-asm-2.c: Regenerated.
 323         * aarch64-dis-2.c: Regenerated.
 324         * aarch64-opc-2.c: Regenerated.
 325         * aarch64-asm.c (aarch64_ins_sve_shrimm):
 326         (aarch64_encode_variant_using_iclass): Handle
 327         sve_shift_tsz_hsd iclass encode.
 328         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 329         sve_shift_tsz_hsd iclass decode.
 330         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 331         for SVE_SHRIMM_UNPRED_22.
 332         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
 333         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
 334         operand.
 335
 336 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 337
 338         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 339         sve_size_013 iclass encode.
 340         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 341         sve_size_013 iclass decode.
 342
 343 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 344
 345         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 346         sve_size_bh iclass encode.
 347         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 348         sve_size_bh iclass decode.
 349
 350 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 351
 352         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 353         sve_size_sd2 iclass encode.
 354         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 355         sve_size_sd2 iclass decode.
 356         * aarch64-opc.c (fields): Handle SVE_sz2 field.
 357         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
 358
 359 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 360
 361         * aarch64-asm-2.c: Regenerated.
 362         * aarch64-dis-2.c: Regenerated.
 363         * aarch64-opc-2.c: Regenerated.
 364         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 365         for SVE_ADDR_ZX.
 366         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
 367         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
 368
 369 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 370
 371         * aarch64-asm-2.c: Regenerated.
 372         * aarch64-dis-2.c: Regenerated.
 373         * aarch64-opc-2.c: Regenerated.
 374         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 375         for SVE_Zm3_11_INDEX.
 376         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
 377         (fields): Handle SVE_i3l and SVE_i3h2 fields.
 378         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
 379         fields.
 380         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
 381
 382 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 383
 384         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 385         sve_size_hsd2 iclass encode.
 386         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 387         sve_size_hsd2 iclass decode.
 388         * aarch64-opc.c (fields): Handle SVE_size field.
 389         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
 390
 391 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 392
 393         * aarch64-asm-2.c: Regenerated.
 394         * aarch64-dis-2.c: Regenerated.
 395         * aarch64-opc-2.c: Regenerated.
 396         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 397         for SVE_IMM_ROT3.
 398         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
 399         (fields): Handle SVE_rot3 field.
 400         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
 401         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
 402
 403 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 404
 405         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
 406         instructions.
 407
 408 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 409
 410         * aarch64-tbl.h
 411         (aarch64_feature_sve2, aarch64_feature_sve2aes,
 412         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
 413         aarch64_feature_sve2bitperm): New feature sets.
 414         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
 415         for feature set addresses.
 416         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
 417         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
 418
 419 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
 420             Faraz Shahbazker  <fshahbazker@wavecomp.com>
 421
 422         * mips-dis.c (mips_calculate_combination_ases): Add ISA
 423         argument and set ASE_EVA_R6 appropriately.
 424         (set_default_mips_dis_options): Pass ISA to above.
 425         (parse_mips_dis_option): Likewise.
 426         * mips-opc.c (EVAR6): New macro.
 427         (mips_builtin_opcodes): Add llwpe, scwpe.
 428
 429 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
 430
 431         * aarch64-asm-2.c: Regenerated.
 432         * aarch64-dis-2.c: Regenerated.
 433         * aarch64-opc-2.c: Regenerated.
 434         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
 435         AARCH64_OPND_TME_UIMM16.
 436         (aarch64_print_operand): Likewise.
 437         * aarch64-tbl.h (QL_IMM_NIL): New.
 438         (TME): New.
 439         (_TME_INSN): New.
 440         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
 441
 442 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
 443
 444         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
 445
 446 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
 447             Faraz Shahbazker  <fshahbazker@wavecomp.com>
 448
 449         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
 450
 451 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
 452
 453         * s12z-opc.h: Add extern "C" bracketing to help
 454         users who wish to use this interface in c++ code.
 455
 456 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
 457
 458         * s12z-opc.c (bm_decode): Handle bit map operations with the
 459         "reserved0" mode.
 460
 461 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 462
 463         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
 464         specifier.  Add entries for VLDR and VSTR of system registers.
 465         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
 466         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
 467         of %J and %K format specifier.
 468
 469 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 470
 471         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
 472         Add new entries for VSCCLRM instruction.
 473         (print_insn_coprocessor): Handle new %C format control code.
 474
 475 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 476
 477         * arm-dis.c (enum isa): New enum.
 478         (struct sopcode32): New structure.
 479         (coprocessor_opcodes): change type of entries to struct sopcode32 and
 480         set isa field of all current entries to ANY.
 481         (print_insn_coprocessor): Change type of insn to struct sopcode32.
 482         Only match an entry if its isa field allows the current mode.
 483
 484 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 485
 486         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
 487         CLRM.
 488         (print_insn_thumb32): Add logic to print %n CLRM register list.
 489
 490 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 491
 492         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
 493         and %Q patterns.
 494
 495 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 496
 497         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
 498         (print_insn_thumb32): Edit the switch case for %Z.
 499
 500 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 501
 502         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
 503
 504 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 505
 506         * arm-dis.c (thumb32_opcodes): New instruction bfl.
 507
 508 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 509
 510         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
 511
 512 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 513
 514         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
 515         Arm register with r13 and r15 unpredictable.
 516         (thumb32_opcodes): New instructions for bfx and bflx.
 517
 518 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 519
 520         * arm-dis.c (thumb32_opcodes): New instructions for bf.
 521
 522 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 523
 524         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
 525
 526 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 527
 528         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
 529
 530 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 531
 532         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
 533
 534 2019-04-12  John Darrington <john@darrington.wattle.id.au>
 535
 536         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
 537         "optr". ("operator" is a reserved word in c++).
 538
 539 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
 540
 541         * aarch64-opc.c (aarch64_print_operand): Add case for
 542         AARCH64_OPND_Rt_SP.
 543         (verify_constraints): Likewise.
 544         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
 545         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
 546         to accept Rt|SP as first operand.
 547         (AARCH64_OPERANDS): Add new Rt_SP.
 548         * aarch64-asm-2.c: Regenerated.
 549         * aarch64-dis-2.c: Regenerated.
 550         * aarch64-opc-2.c: Regenerated.
 551
 552 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
 553
 554         * aarch64-asm-2.c: Regenerated.
 555         * aarch64-dis-2.c: Likewise.
 556         * aarch64-opc-2.c: Likewise.
 557         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
 558
 559 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
 560
 561         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
 562
 563 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
 564
 565         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
 566         * i386-init.h: Regenerated.
 567
 568 2019-04-07  Alan Modra  <amodra@gmail.com>
 569
 570         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
 571         op_separator to control printing of spaces, comma and parens
 572         rather than need_comma, need_paren and spaces vars.
 573
 574 2019-04-07  Alan Modra  <amodra@gmail.com>
 575
 576         PR 24421
 577         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
 578         (print_insn_neon, print_insn_arm): Likewise.
 579
 580 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
 581
 582         * i386-dis-evex.h (evex_table): Updated to support BF16
 583         instructions.
 584         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
 585         and EVEX_W_0F3872_P_3.
 586         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
 587         (cpu_flags): Add bitfield for CpuAVX512_BF16.
 588         * i386-opc.h (enum): Add CpuAVX512_BF16.
 589         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
 590         * i386-opc.tbl: Add AVX512 BF16 instructions.
 591         * i386-init.h: Regenerated.
 592         * i386-tbl.h: Likewise.
 593
 594 2019-04-05  Alan Modra  <amodra@gmail.com>
 595
 596         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
 597         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
 598         to favour printing of "-" branch hint when using the "y" bit.
 599         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
 600
 601 2019-04-05  Alan Modra  <amodra@gmail.com>
 602
 603         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
 604         opcode until first operand is output.
 605
 606 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
 607
 608         PR gas/24349
 609         * ppc-opc.c (valid_bo_pre_v2): Add comments.
 610         (valid_bo_post_v2): Add support for 'at' branch hints.
 611         (insert_bo): Only error on branch on ctr.
 612         (get_bo_hint_mask): New function.
 613         (insert_boe): Add new 'branch_taken' formal argument.  Add support
 614         for inserting 'at' branch hints.
 615         (extract_boe): Add new 'branch_taken' formal argument.  Add support
 616         for extracting 'at' branch hints.
 617         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
 618         (BOE): Delete operand.
 619         (BOM, BOP): New operands.
 620         (RM): Update value.
 621         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
 622         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
 623         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
 624         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
 625         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
 626         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
 627         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
 628         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
 629         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
 630         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
 631         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
 632         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
 633         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
 634         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
 635         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
 636         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
 637         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
 638         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
 639         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
 640         bttarl+>: New extended mnemonics.
 641
 642 2019-03-28  Alan Modra  <amodra@gmail.com>
 643
 644         PR 24390
 645         * ppc-opc.c (BTF): Define.
 646         (powerpc_opcodes): Use for mtfsb*.
 647         * ppc-dis.c (print_insn_powerpc): Print fields with both
 648         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
 649
 650 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 651
 652         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
 653         (mapping_symbol_for_insn): Implement new algorithm.
 654         (print_insn): Remove duplicate code.
 655
 656 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 657
 658         * aarch64-dis.c (print_insn_aarch64):
 659         Implement override.
 660
 661 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 662
 663         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
 664         order.
 665
 666 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 667
 668         * aarch64-dis.c (last_stop_offset): New.
 669         (print_insn_aarch64): Use stop_offset.
 670
 671 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
 672
 673         PR gas/24359
 674         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
 675         CPU_ANY_AVX2_FLAGS.
 676         * i386-init.h: Regenerated.
 677
 678 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
 679
 680         PR gas/24348
 681         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
 682         vmovdqu16, vmovdqu32 and vmovdqu64.
 683         * i386-tbl.h: Regenerated.
 684
 685 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
 686
 687         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
 688         from vstrszb, vstrszh, and vstrszf.
 689
 690 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
 691
 692         * s390-opc.txt: Add instruction descriptions.
 693
 694 2019-02-08  Jim Wilson  <jimw@sifive.com>
 695
 696         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
 697         <bne>: Likewise.
 698
 699 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
 700
 701         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
 702
 703 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
 704
 705         PR binutils/23212
 706         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
 707         * aarch64-opc.c (verify_elem_sd): New.
 708         (fields): Add FLD_sz entr.
 709         * aarch64-tbl.h (_SIMD_INSN): New.
 710         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
 711         fmulx scalar and vector by element isns.
 712
 713 2019-02-07  Nick Clifton  <nickc@redhat.com>
 714
 715         * po/sv.po: Updated Swedish translation.
 716
 717 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
 718
 719         * s390-mkopc.c (main): Accept arch13 as cpu string.
 720         * s390-opc.c: Add new instruction formats and instruction opcode
 721         masks.
 722         * s390-opc.txt: Add new arch13 instructions.
 723
 724 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 725
 726         * aarch64-tbl.h (QL_LDST_AT): Update macro.
 727         (aarch64_opcode): Change encoding for stg, stzg
 728         st2g and st2zg.
 729         * aarch64-asm-2.c: Regenerated.
 730         * aarch64-dis-2.c: Regenerated.
 731         * aarch64-opc-2.c: Regenerated.
 732
 733 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 734
 735         * aarch64-asm-2.c: Regenerated.
 736         * aarch64-dis-2.c: Likewise.
 737         * aarch64-opc-2.c: Likewise.
 738         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
 739
 740 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 741             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
 742
 743         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
 744         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
 745         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
 746         * aarch64-dis.h (ext_addr_simple_2): Likewise.
 747         * aarch64-opc.c (operand_general_constraint_met_p): Remove
 748         case for ldstgv_indexed.
 749         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
 750         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
 751         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
 752         * aarch64-asm-2.c: Regenerated.
 753         * aarch64-dis-2.c: Regenerated.
 754         * aarch64-opc-2.c: Regenerated.
 755
 756 2019-01-23  Nick Clifton  <nickc@redhat.com>
 757
 758         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 759
 760 2019-01-21  Nick Clifton  <nickc@redhat.com>
 761
 762         * po/de.po: Updated German translation.
 763         * po/uk.po: Updated Ukranian translation.
 764
 765 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
 766         * mips-dis.c (mips_arch_choices): Fix typo in
 767         gs464, gs464e and gs264e descriptors.
 768
 769 2019-01-19  Nick Clifton  <nickc@redhat.com>
 770
 771         * configure: Regenerate.
 772         * po/opcodes.pot: Regenerate.
 773
 774 2018-06-24  Nick Clifton  <nickc@redhat.com>
 775
 776         2.32 branch created.
 777
 778 2019-01-09  John Darrington <john@darrington.wattle.id.au>
 779
 780         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
 781         if it is null.
 782         -dis.c (opr_emit_disassembly): Do not omit an index if it is
 783         zero.
 784
 785 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
 786
 787         * configure: Regenerate.
 788
 789 2019-01-07  Alan Modra  <amodra@gmail.com>
 790
 791         * configure: Regenerate.
 792         * po/POTFILES.in: Regenerate.
 793
 794 2019-01-03  John Darrington <john@darrington.wattle.id.au>
 795
 796         * s12z-opc.c: New file.
 797         * s12z-opc.h: New file.
 798         * s12z-dis.c: Removed all code not directly related to display
 799         of instructions.  Used the interface provided by the new files
 800         instead.
 801         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
 802         * Makefile.in: Regenerate.
 803         * configure.ac (bfd_s12z_arch): Correct the dependencies.
 804         * configure: Regenerate.
 805
 806 2019-01-01  Alan Modra  <amodra@gmail.com>
 807
 808         Update year range in copyright notice of all files.
 809
 810 For older changes see ChangeLog-2018
 811 \f
 812 Copyright (C) 2019 Free Software Foundation, Inc.
 813
 814 Copying and distribution of this file, with or without modification,
 815 are permitted in any medium without royalty provided the copyright
 816 notice and this notice are preserved.
 817
 818 Local Variables:
 819 mode: change-log
 820 left-margin: 8
 821 fill-column: 74
 822 version-control: never
 823 End: