1 2022-07-08 Nick Clifton <nickc@redhat.com>
5 2022-07-04 Marcus Nilsson <brainbomb@gmail.com>
7 * disassemble.c: (disassemble_init_for_target): Set
8 created_styled_output for AVR based targets.
9 * avr-dis.c: (print_insn_avr): Use fprintf_styled_ftype
10 instead of fprintf_ftype throughout.
11 (avr_operand): Pass in and fill disassembler_style when
14 2022-04-07 Andreas Krebbel <krebbel@linux.ibm.com>
16 * s390-mkopc.c (main): Enable z16 as CPU string in the opcode
19 2022-03-16 Simon Marchi <simon.marchi@efficios.com>
21 * configure.ac: Handle bfd_amdgcn_arch.
22 * configure: Re-generate.
24 2022-03-06 Sagar Patel <sagarmp@cs.unc.edu>
25 Maciej W. Rozycki <macro@orcam.me.uk>
27 * mips-opc.c (mips_builtin_opcodes): Fix INSN2_ALIAS annotation
28 for "bal", "beqz", "beqzl", "bnez" and "bnezl" instructions.
29 * micromips-opc.c (micromips_opcodes): Likewise for "beqz" and
32 2022-02-17 Nick Clifton <nickc@redhat.com>
34 * po/sr.po: Updated Serbian translation.
36 2022-02-14 Sergei Trofimovich <siarheit@google.com>
38 * microblaze-opcm.h: Renamed 'fsqrt' to 'microblaze_fsqrt'.
39 * microblaze-opc.h: Follow 'fsqrt' rename.
41 2022-01-24 Nick Clifton <nickc@redhat.com>
43 * po/ro.po: Updated Romanian translation.
44 * po/uk.po: Updated Ukranian translation.
46 2022-01-22 Nick Clifton <nickc@redhat.com>
48 * configure: Regenerate.
49 * po/opcodes.pot: Regenerate.
51 2022-01-22 Nick Clifton <nickc@redhat.com>
53 * 2.38 release branch created.
55 2022-01-17 Nick Clifton <nickc@redhat.com>
57 * Makefile.in: Regenerate.
58 * po/opcodes.pot: Regenerate.
60 2021-12-02 Marcus Nilsson <brainbomb@gmail.com>
62 * avr-dis.c (avr_operand); Pass in disassemble_info and fill
63 in insn_type on branching instructions.
65 2021-11-25 Andrew Burgess <aburgess@redhat.com>
66 Simon Cook <simon.cook@embecosm.com>
68 * riscv-dis.c (enum riscv_option_arg_t): New enum typedef.
69 (riscv_options): New static global.
70 (disassembler_options_riscv): New function.
71 (print_riscv_disassembler_options): Rewrite to use
72 disassembler_options_riscv.
74 2021-11-25 Nick Clifton <nickc@redhat.com>
77 * aarch64-asm.c: Replace assert(0) with real code.
78 * aarch64-dis.c: Likewise.
79 * aarch64-opc.c: Likewise.
81 2021-11-25 Nick Clifton <nickc@redhat.com>
83 * po/fr.po; Updated French translation.
85 2021-10-27 Maciej W. Rozycki <macro@embecosm.com>
87 * Makefile.am: Remove obsolete comment.
88 * configure.ac: Refer `libbfd.la' to link shared BFD library
90 * Makefile.in: Regenerate.
91 * configure: Regenerate.
93 2021-09-27 Nick Alcock <nick.alcock@oracle.com>
95 * configure: Regenerate.
97 2021-09-25 Peter Bergner <bergner@linux.ibm.com>
99 * ppc-opc.c (powerpc_opcodes) <mfppr, mfppr32, mtppr, mtppr32>: Enable
102 2021-09-20 Andrew Burgess <andrew.burgess@embecosm.com>
104 * riscv-dis.c (riscv_disassemble_insn): Print a .%dbyte opcode
105 before an unknown instruction, '%d' is replaced with the
108 2021-09-02 Nick Clifton <nickc@redhat.com>
111 * v850-opc.c (D16): Use BFD_RELOC_V850_LO16_SPLIT_OFFSET in place
114 2021-08-17 Shahab Vahedi <shahab@synopsys.com>
116 * arc-regs.h (DEF): Fix the register numbers.
118 2021-08-10 Nick Clifton <nickc@redhat.com>
120 * po/sr.po: Updated Serbian translation.
122 2021-07-26 Chenghua Xu <xuchenghua@loongson.cn>
124 * mips-dis.c (mips_arch_choices): Correct gs264e bfd_mach.
126 2021-06-07 Andreas Krebbel <krebbel@linux.ibm.com>
128 * s390-opc.txt: Add qpaci.
130 2021-07-03 Nick Clifton <nickc@redhat.com>
132 * configure: Regenerate.
133 * po/opcodes.pot: Regenerate.
135 2021-07-03 Nick Clifton <nickc@redhat.com>
137 * 2.37 release branch created.
139 2021-07-02 Alan Modra <amodra@gmail.com>
141 * nds32-dis.c (nds32_find_reg_keyword): Constify arg and return.
142 (nds32_parse_audio_ext, nds32_parse_opcode): Constify psys_reg.
143 (nds32_field_table, nds32_opcode_table, nds32_keyword_table),
144 (nds32_opcodes, nds32_operand_fields, nds32_keywords),
145 (nds32_keyword_gpr): Move declarations to..
146 * nds32-asm.h: ..here, constifying to match definitions.
148 2021-07-01 Mike Frysinger <vapier@gentoo.org>
150 * Makefile.am (GUILE): New variable.
151 (CGEN): Use $(GUILE).
152 * Makefile.in: Regenerate.
154 2021-07-01 Mike Frysinger <vapier@gentoo.org>
156 * mep-asm.c (macros): Mark static & const.
157 (lookup_macro): Change return & m to const.
158 (expand_macro): Change mac to const.
159 (expand_string): Change pmacro to const.
161 2021-07-01 Mike Frysinger <vapier@gentoo.org>
163 * nds32-asm.c (operand_fields): Rename to ...
164 (nds32_operand_fields): ... this.
165 (keyword_gpr): Rename to ...
166 (nds32_keyword_gpr): ... this.
167 (keyword_usr, keyword_dxr, keyword_sr, keyword_cp, keyword_cpr,
168 keyword_fsr, keyword_fdr, keyword_abdim, keyword_abm,
169 keyword_dpref_st, keyword_cctl_lv, keyword_standby_st,
170 keyword_msync_st, keyword_im5_i, keyword_im5_m, keyword_accumulator,
171 keyword_aridx, keyword_aridx2, keyword_aridxi, keyword_aridxi_mx):
173 (keywords): Rename to ...
174 (nds32_keywords): ... this.
175 * nds32-dis.c: Rename operand_fields to nds32_operand_fields,
176 keywords to nds32_keywords, and keyword_gpr to nds32_keyword_gpr.
178 2021-07-01 Mike Frysinger <vapier@gentoo.org>
180 * z80-dis.c (opc_ed): Make const.
181 (pref_ed): Make p const.
183 2021-07-01 Mike Frysinger <vapier@gentoo.org>
185 * microblaze-dis.c (get_field_special): Make op const.
186 (read_insn_microblaze): Make opr & op const. Rename opcodes to
188 (print_insn_microblaze): Make op & pop const.
189 (get_insn_microblaze): Make op const. Rename opcodes to
191 (microblaze_get_target_address): Likewise.
192 * microblaze-opc.h (struct op_code_struct): Make const.
193 Rename opcodes to microblaze_opcodes.
195 2021-07-01 Mike Frysinger <vapier@gentoo.org>
197 * aarch64-gen.c (aarch64_opcode_table): Add const.
198 * aarch64-tbl.h (aarch64_opcode_table): Likewise.
200 2021-06-22 Andrew Burgess <andrew.burgess@embecosm.com>
202 * cgen-dis.c (count_decodable_bits): Use __builtin_popcount when
205 2021-06-22 Alan Modra <amodra@gmail.com>
207 * pj-dis.c (print_insn_pj): Don't print trailing tab. Do
208 print separator for pcrel insns.
210 2021-06-19 Alan Modra <amodra@gmail.com>
212 * vax-dis.c (print_insn_vax): Avoid pointer overflow.
214 2021-06-19 Alan Modra <amodra@gmail.com>
216 * tic30-dis.c (get_register_operand): Don't ask strncpy to fill
219 2021-06-17 Alan Modra <amodra@gmail.com>
221 * ppc-opc.c (powerpc_opcodes): Move cell db*cyc to proper location
224 2021-06-03 Alan Modra <amodra@gmail.com>
227 * mcore-dis.c (print_insn_mcore): Correct loopt disassembly.
228 Use unsigned int for inst.
230 2021-06-02 Shahab Vahedi <shahab@synopsys.com>
232 * arc-dis.c (arc_option_arg_t): New enumeration.
233 (arc_options): New variable.
234 (disassembler_options_arc): New function.
235 (print_arc_disassembler_options): Reimplement in terms of
236 "disassembler_options_arc".
238 2021-05-29 Alan Modra <amodra@gmail.com>
240 * ppc-dis.c (lookup_powerpc): Test deprecated field when -Many.
241 Don't special case PPC_OPCODE_RAW.
242 (lookup_prefix): Likewise.
243 (lookup_vle, lookup_spe2): Similarly. Add dialect parameter and..
244 (print_insn_powerpc): ..update caller.
245 * ppc-opc.c (EXT): Define.
246 (powerpc_opcodes): Mark extended mnemonics with EXT.
247 (prefix_opcodes, vle_opcodes): Likewise.
248 (XISEL, XISEL_MASK): Add cr field and simplify.
249 (powerpc_opcodes): Use XISEL with extended isel mnemonics and sort
250 all isel variants to where the base mnemonic belongs. Sort dstt,
253 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
255 * mips-opc.c (mips_builtin_opcodes): Reorder legacy COP0, COP2,
256 COP3 opcode instructions.
258 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
260 * mips-opc.c (mips_builtin_opcodes): Update exclusion list for
261 "ldc2", "ldc3", "lwc0", "lwc2", "lwc3", "sdc2", "sdc3", "swc0",
262 "swc2", "swc3", "cfc0", "ctc0", "bc2f", "bc2fl", "bc2t",
263 "bc2tl", "cfc2", "ctc2", "dmfc2", "dmtc2", "mfc2", "mtc2",
264 "bc3f", "bc3fl", "bc3t", "bc3tl", "cfc3", "ctc3", "mfc3",
265 "mtc3", "bc0f", "bc0fl", "bc0t", "bc0tl", "rfe", "c2", "c3",
266 "cop2", and "cop3" entries.
268 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
270 * mips-opc.c (mips_builtin_opcodes): Remove "dmfc3" and "dmtc3"
271 entries and associated comments.
273 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
275 * mips-opc.c (mips_builtin_opcodes): Move the "rfe" entry ahead
278 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
280 * mips-dis.c (mips_cp1_names_mips): New variable.
281 (mips_arch_choices): Use it rather than `mips_cp1_names_numeric'
282 for "r3000", "r4000", "r4010", "vr4100", "vr4111", "vr4120",
283 "r4300", "r4400", "r4600", "r4650", "r5000", "vr5400", "vr5500",
284 "r5900", "r6000", "rm7000", "rm9000", "r8000", "r10000",
285 "r12000", "r14000", "r16000", "mips5", "loongson2e", and
288 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
290 * mips-dis.c (print_reg) <OP_REG_COPRO>: Move control register
291 handling code over to...
292 <OP_REG_CONTROL>: ... this new case.
293 * mips-opc.c (decode_mips_operand) <'g', 'y'>: New cases.
294 (mips_builtin_opcodes): Update "cfc1", "ctc1", "cttc1", "cttc2",
295 "cfc0", "ctc0", "cfc2", "ctc2", "cfc3", and "ctc3" entries
296 replacing the `G' operand code with `g'. Update "cftc1" and
297 "cftc2" entries replacing the `E' operand code with `y'.
298 * micromips-opc.c (decode_micromips_operand) <'g'>: New case.
299 (micromips_opcodes): Update "cfc1", "cfc2", "ctc1", and "ctc2"
300 entries replacing the `G' operand code with `g'.
302 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
304 * mips-dis.c (mips_cp0_names_r3900): New variable.
305 (mips_arch_choices): Use it rather than `mips_cp0_names_numeric'
308 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
310 * mips-opc.c (mips_builtin_opcodes): Switch "cttc2", "mttc2",
311 and "mtthc2" to using the `G' rather than `g' operand code for
312 the coprocessor control register referred.
314 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
316 * micromips-opc.c (micromips_opcodes): Swap the two "dmtc1"
317 entries with each other.
319 2021-05-27 Peter Bergner <bergner@linux.ibm.com>
321 * ppc-opc.c (powerpc_opcodes) <xxmr, xxlnot>: New extended mnemonics.
323 2021-05-25 Alan Modra <amodra@gmail.com>
325 * cris-desc.c: Regenerate.
326 * cris-desc.h: Regenerate.
327 * cris-opc.h: Regenerate.
328 * po/POTFILES.in: Regenerate.
330 2021-05-24 Mike Frysinger <vapier@gentoo.org>
332 * Makefile.am (HFILES): Add cris-desc.h & cris-opc.h.
333 (TARGET_LIBOPCODES_CFILES): Add cris-desc.c.
334 (CGEN_CPUS): Add cris.
336 (stamp-cris): New rule.
337 * cgen.sh: Handle desc action.
338 * configure.ac (bfd_cris_arch): Add cris-desc.lo.
339 * Makefile.in, configure: Regenerate.
341 2021-05-18 Job Noorman <mtvec@pm.me>
344 * riscv-dis.c (riscv_get_disassembler): Get elf attributes only for
347 2021-05-17 Alex Coplan <alex.coplan@arm.com>
349 * arm-dis.c (mve_opcodes): Fix disassembly of
350 MVE_VMOV2_GP_TO_VEC_LANE when idx == 1.
351 (is_mve_encoding_conflict): MVE vector loads should not match
353 (is_mve_unpredictable): It's not unpredictable to use the same
354 source register twice (for MVE_VMOV2_GP_TO_VEC_LANE).
356 2021-05-11 Nick Clifton <nickc@redhat.com>
359 * tic30-dis.c (print_insn_tic30): Prevent attempts to read beyond
360 the end of the code buffer.
362 2021-05-06 Stafford Horne <shorne@gmail.com>
365 * or1k-asm.c: Regenerate.
367 2021-05-01 Max Filippov <jcmvbkbc@gmail.com>
369 * xtensa-dis.c (print_insn_xtensa): Fill in info->insn_type and
370 info->insn_info_valid.
372 2021-04-26 Jan Beulich <jbeulich@suse.com>
374 * i386-opc.tbl (lea): Add Optimize.
375 * opcodes/i386-tbl.h: Re-generate.
377 2020-04-23 Max Filippov <jcmvbkbc@gmail.com>
379 * xtensa-dis.c (print_xtensa_operand): For PC-relative operand
380 of l32r fetch and display referenced literal value.
382 2021-04-23 Max Filippov <jcmvbkbc@gmail.com>
384 * xtensa-dis.c (print_insn_xtensa): Set info->bytes_per_chunk
385 to 4 for literal disassembly.
387 2021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
389 * aarch64-opc.c: Add new registers (RPAOS, RPALOS, PAALLOS, PAALL) support
390 for TLBI instruction.
392 2021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
394 * aarch64-opc.c: Add new register (CIPAPA, CIGDPAPA) support for
397 2021-04-19 Jan Beulich <jbeulich@suse.com>
399 * aarch64-asm.c (encode_asimd_fcvt): Add initializer for
401 (convert_mov_to_movewide): Add initializer for "value".
403 2021-04-16 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
405 * aarch64-opc.c: Add RME system registers.
407 2021-04-16 Lifang Xia <lifang_xia@c-sky.com>
409 * riscv-opc.c (riscv_opcodes): New insn alias for addi. Compress
410 "addi d,CV,z" to "c.mv d,CV".
412 2021-04-12 Alan Modra <amodra@gmail.com>
414 * configure.ac (--enable-checking): Add support.
415 * config.in: Regenerate.
416 * configure: Regenerate.
418 2021-04-09 Tejas Belagod <tejas.belagod@arm.com>
420 * aarch64-tbl.h (struct aarch64_opcode aarch64_opcode_table): Reclassify
421 LD64/ST64 instructions to lse_atomic instead of ldstexcl.
423 2021-04-09 Alan Modra <amodra@gmail.com>
425 * ppc-dis.c (struct dis_private): Add "special".
426 (POWERPC_DIALECT): Delete. Replace uses with..
427 (private_data): ..this. New inline function.
428 (disassemble_init_powerpc): Init "special" names.
429 (skip_optional_operands): Add is_pcrel arg, set when detecting R
430 field of prefix instructions.
431 (bsearch_reloc, print_got_plt): New functions.
432 (print_insn_powerpc): For pcrel instructions, print target address
433 and symbol if known, and decode plt and got loads too.
435 2021-04-08 Alan Modra <amodra@gmail.com>
438 * ppc-opc.c (powerpc_opcodes): Correct usprg typos, add mfpir.
440 2021-04-08 Alan Modra <amodra@gmail.com>
443 * ppc-opc.c (DCBT_EO): Move earlier.
444 (insert_thct, extract_thct, insert_thds, extract_thds): New functions.
445 (powerpc_operands): Add THCT and THDS entries.
446 (powerpc_opcodes): Add dcbtstct, dcbtstds, dcbna, dcbtct, dcbtds.
448 2021-04-06 Alan Modra <amodra@gmail.com>
450 * dis-buf.c (generic_symbol_at_address): Return symbol* NULL.
451 * s12z-dis.c (decode_possible_symbol): Use symbol returned from
452 symbol_at_address_func.
454 2021-04-05 Alan Modra <amodra@gmail.com>
456 * configure.ac: Don't check for limits.h, string.h, strings.h or
458 (AC_ISC_POSIX): Don't invoke.
459 * sysdep.h: Include stdlib.h and string.h unconditionally.
460 * i386-opc.h: Include limits.h unconditionally.
461 * wasm32-dis.c: Likewise.
462 * cgen-opc.c: Don't include alloca-conf.h.
463 * config.in: Regenerate.
464 * configure: Regenerate.
466 2021-04-01 Martin Liska <mliska@suse.cz>
468 * arm-dis.c (strneq): Remove strneq and use startswith.
469 * cr16-dis.c (print_insn_cr16): Likewise.
470 * score-dis.c (streq): Likewise.
472 * score7-dis.c (strneq): Likewise.
474 2021-04-01 Alan Modra <amodra@gmail.com>
477 * ppc-opc.c (powerpc_opcodes): Add mfummcr2 and mfmmcr2.
479 2021-03-31 Alan Modra <amodra@gmail.com>
481 * sysdep.h (POISON_BFD_BOOLEAN): Define.
482 * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h,
483 * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h,
484 * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c,
485 * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c,
486 * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c,
487 * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c,
488 * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c,
489 * microblaze-dis.h, * micromips-opc.c, * mips-dis.c,
490 * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c,
491 * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c,
492 * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c,
493 * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c,
494 * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false,
495 and TRUE with true throughout.
497 2021-03-31 Alan Modra <amodra@gmail.com>
499 * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h.
500 * aarch64-dis.h: Likewise.
501 * aarch64-opc.c: Likewise.
502 * avr-dis.c: Likewise.
503 * csky-dis.c: Likewise.
504 * nds32-asm.c: Likewise.
505 * nds32-dis.c: Likewise.
506 * nfp-dis.c: Likewise.
507 * riscv-dis.c: Likewise.
508 * s12z-dis.c: Likewise.
509 * wasm32-dis.c: Likewise.
511 2021-03-30 Jan Beulich <jbeulich@suse.com>
513 * i386-opc.c (cs, ds, ss, es, fs, gs): Delete.
514 (i386_seg_prefixes): New.
515 * i386-opc.h (cs, ds, ss, es, fs, gs): Delete.
516 (i386_seg_prefixes): Declare.
518 2021-03-30 Jan Beulich <jbeulich@suse.com>
520 * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Delete.
522 2021-03-30 Jan Beulich <jbeulich@suse.com>
524 * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Adjust values.
525 * i386-reg.tbl (st): Move down.
526 (st(0)): Delete. Extend comment.
527 * i386-tbl.h: Re-generate.
529 2021-03-29 Jan Beulich <jbeulich@suse.com>
531 * i386-opc.tbl (movq, movabs): Move next to mov counterparts.
532 (cmpsd): Move next to cmps.
533 (movsd): Move next to movs.
534 (cmpxchg16b): Move to separate section.
535 (fisttp, fisttpll): Likewise.
536 (monitor, mwait): Likewise.
537 * i386-tbl.h: Re-generate.
539 2021-03-29 Jan Beulich <jbeulich@suse.com>
541 * i386-opc.tbl (psadbw): Add <sse2:comm>.
543 * i386-tbl.h: Re-generate.
545 2021-03-29 Jan Beulich <jbeulich@suse.com>
547 * i386-opc.tbl (mmx, sse, sse2, sse3, ssse3, sse41, sse42, aes,
548 pclmul, gfni): New templates. Use them wherever possible. Move
549 SSE4.1 pextrw into respective section.
550 * i386-tbl.h: Re-generate.
552 2021-03-29 Jan Beulich <jbeulich@suse.com>
554 * i386-gen.c (output_i386_opcode): Widen type of "opcode". Use
555 strtoull(). Bump upper loop bound. Widen masks. Sanity check
557 * i386-opc.tbl (Prefix_0X66, Prefix_0XF2, Prefix_0XF3): Delete.
558 Convert all of their uses to representation in opcode.
560 2021-03-29 Jan Beulich <jbeulich@suse.com>
562 * i386-opc.h (struct insn_template): Shrink base_opcode to 16
563 bits. Shrink extension_opcode to 9 bits. Make it signed. Change
564 value of None. Shrink operands to 3 bits.
566 2021-03-29 Jan Beulich <jbeulich@suse.com>
568 * i386-gen.c (process_i386_opcode_modifier): New parameter
570 (output_i386_opcode): New local variable "space". Adjust
571 process_i386_opcode_modifier() invocation.
572 (process_i386_opcodes): Adjust process_i386_opcode_modifier()
574 * i386-tbl.h: Re-generate.
576 2021-03-29 Alan Modra <amodra@gmail.com>
578 * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
579 (fp_qualifier_p, get_data_pattern): Likewise.
580 (aarch64_get_operand_modifier_from_value): Likewise.
581 (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
582 (operand_variant_qualifier_p): Likewise.
583 (qualifier_value_in_range_constraint_p): Likewise.
584 (aarch64_get_qualifier_esize): Likewise.
585 (aarch64_get_qualifier_nelem): Likewise.
586 (aarch64_get_qualifier_standard_value): Likewise.
587 (get_lower_bound, get_upper_bound): Likewise.
588 (aarch64_find_best_match, match_operands_qualifier): Likewise.
589 (aarch64_print_operand): Likewise.
590 * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
591 (operand_need_sign_extension, operand_need_shift_by_two): Likewise.
592 (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
593 * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
594 * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
595 (print_insn_tic6x): Likewise.
597 2021-03-29 Alan Modra <amodra@gmail.com>
599 * arc-dis.c (extract_operand_value): Correct NULL cast.
600 * frv-opc.h: Regenerate.
602 2021-03-26 Jan Beulich <jbeulich@suse.com>
604 * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to
606 * i386-tbl.h: Re-generate.
608 2021-03-25 Abid Qadeer <abidh@codesourcery.com>
610 * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
611 immediate in br.n instruction.
613 2021-03-25 Jan Beulich <jbeulich@suse.com>
615 * i386-dis.c (XMGatherD, VexGatherD): New.
616 (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
617 (print_insn): Check masking for S/G insns.
618 (OP_E_memory): New local variable check_gather. Extend mandatory
619 SIB check. Check register conflicts for (EVEX-encoded) gathers.
620 Extend check for disallowed 16-bit addressing.
621 (OP_VEX): New local variables modrm_reg and sib_index. Convert
622 if()s to switch(). Check register conflicts for (VEX-encoded)
623 gathers. Drop no longer reachable cases.
624 * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
627 2021-03-25 Jan Beulich <jbeulich@suse.com>
629 * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
630 zeroing-masking without masking.
632 2021-03-25 Jan Beulich <jbeulich@suse.com>
634 * i386-opc.tbl (invlpgb): Fix multi-operand form.
635 (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
636 single-operand forms as deprecated.
637 * i386-tbl.h: Re-generate.
639 2021-03-25 Alan Modra <amodra@gmail.com>
642 * ppc-opc.c (XLOCB_MASK): Delete.
643 (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
645 (powerpc_opcodes): Accept a BH field on all extended forms of
646 bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
648 2021-03-24 Jan Beulich <jbeulich@suse.com>
650 * i386-gen.c (output_i386_opcode): Drop processing of
651 opcode_length. Calculate length from base_opcode. Adjust prefix
652 encoding determination.
653 (process_i386_opcodes): Drop output of fake opcode_length.
654 * i386-opc.h (struct insn_template): Drop opcode_length field.
655 * i386-opc.tbl: Drop opcode length field from all templates.
656 * i386-tbl.h: Re-generate.
658 2021-03-24 Jan Beulich <jbeulich@suse.com>
660 * i386-gen.c (process_i386_opcode_modifier): Return void. New
661 parameter "prefix". Drop local variable "regular_encoding".
662 Record prefix setting / check for consistency.
663 (output_i386_opcode): Parse opcode_length and base_opcode
664 earlier. Derive prefix encoding. Drop no longer applicable
665 consistency checking. Adjust process_i386_opcode_modifier()
667 (process_i386_opcodes): Adjust process_i386_opcode_modifier()
669 * i386-tbl.h: Re-generate.
671 2021-03-24 Jan Beulich <jbeulich@suse.com>
673 * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
675 * i386-opc.h (Prefix_*): Move #define-s.
676 * i386-opc.tbl: Move pseudo prefix enumerator values to
677 extension opcode field. Introduce pseudopfx template.
678 * i386-tbl.h: Re-generate.
680 2021-03-23 Jan Beulich <jbeulich@suse.com>
682 * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
684 * i386-tbl.h: Re-generate.
686 2021-03-23 Jan Beulich <jbeulich@suse.com>
688 * i386-opc.h (struct insn_template): Move cpu_flags field past
690 * i386-tbl.h: Re-generate.
692 2021-03-23 Jan Beulich <jbeulich@suse.com>
694 * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
695 * i386-opc.h (OpcodeSpace): New enumerator.
696 (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
697 (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
698 SPACE_XOP09, SPACE_XOP0A): ... respectively.
699 (struct i386_opcode_modifier): New field opcodespace. Shrink
701 i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
702 SpaceXOP09, SpaceXOP0A): Define. Use them to replace
704 * i386-tbl.h: Re-generate.
706 2021-03-22 Martin Liska <mliska@suse.cz>
708 * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
709 * arc-dis.c (parse_option): Likewise.
710 * arm-dis.c (parse_arm_disassembler_options): Likewise.
711 * cris-dis.c (print_with_operands): Likewise.
712 * h8300-dis.c (bfd_h8_disassemble): Likewise.
713 * i386-dis.c (print_insn): Likewise.
714 * ia64-gen.c (fetch_insn_class): Likewise.
715 (parse_resource_users): Likewise.
716 (in_iclass): Likewise.
717 (lookup_specifier): Likewise.
718 (insert_opcode_dependencies): Likewise.
719 * mips-dis.c (parse_mips_ase_option): Likewise.
720 (parse_mips_dis_option): Likewise.
721 * s390-dis.c (disassemble_init_s390): Likewise.
722 * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
724 2021-03-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
726 * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
728 2021-03-12 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
730 * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
731 icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
733 2021-03-12 Alan Modra <amodra@gmail.com>
735 * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
737 2021-03-11 Jan Beulich <jbeulich@suse.com>
739 * i386-dis.c (OP_XMM): Re-order checks.
741 2021-03-11 Jan Beulich <jbeulich@suse.com>
743 * i386-dis.c (putop): Drop need_vex check when also checking
745 (intel_operand_size, OP_E_memory): Drop vex.evex check when also
748 2021-03-11 Jan Beulich <jbeulich@suse.com>
750 * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
751 checks. Move case label past broadcast check.
753 2021-03-10 Jan Beulich <jbeulich@suse.com>
755 * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
756 vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
757 REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
758 EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
759 EVEX_W_0F38C7_M_0_L_2): Delete.
760 (REG_EVEX_0F38C7_M_0_L_2): New.
761 (intel_operand_size): Handle VEX and EVEX the same for
762 vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
763 vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
764 (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
765 vex_vsib_q_w_d_mode uses.
766 * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
767 0F38A1, and 0F38A3 entries.
768 * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
770 * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
771 * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
774 2021-03-10 Jan Beulich <jbeulich@suse.com>
776 * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
777 REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
778 MOD_VEX_0FXOP_09_12): Rename to ...
779 (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
780 REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
781 (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
782 RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
783 X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
784 X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
785 (reg_table): Adjust comments.
786 (x86_64_table): Move X86_64_0F24, X86_64_0F26,
787 X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
788 X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
789 (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
790 (vex_len_table): Adjust opcode 0A_12 entry.
791 (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
792 MOD_C5_32BIT, and MOD_XOP_09_12 entries.
793 (rm_table): Move hreset entry.
795 2021-03-10 Jan Beulich <jbeulich@suse.com>
797 * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
798 EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
799 EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
800 EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
801 EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
802 (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
803 (get_valid_dis386): Also handle 512-bit vector length when
804 vectoring into vex_len_table[].
805 * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
806 0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
808 * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
809 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
810 * i386-dis-evex-prefix.h: Adjust 0F7E entry.
811 * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
814 2021-03-10 Jan Beulich <jbeulich@suse.com>
816 * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
817 Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
818 EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
819 * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
821 * i386-dis-evex-len.h (evex_len_table): Likewise.
822 * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
824 2021-03-10 Jan Beulich <jbeulich@suse.com>
826 * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
827 MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
828 MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
829 MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
830 MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
831 MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
832 MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
833 MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
834 EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
835 EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
836 EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
837 EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
838 EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
839 EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
840 EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
841 EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
842 EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
843 EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
844 EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
845 EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
846 EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
847 EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
848 EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
849 EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
850 EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
851 EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
852 EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
853 EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
854 EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
855 EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
856 EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
857 EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
858 REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
859 REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
860 MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
861 MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
862 EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
863 EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
864 EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
865 EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
866 EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
867 EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
868 EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
869 EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
870 EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
871 EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
872 EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
873 EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
874 EVEX_W_0F3A43_L_n): New.
875 * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
876 0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
877 0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
878 * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
879 for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
880 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
881 0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
882 * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
883 0F385B, 0F38C6, and 0F38C7 entries.
884 * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
886 * i386-dis-evex-w.h: No longer link to evex_len_table[] for
887 opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
888 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
889 evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
891 2021-03-10 Jan Beulich <jbeulich@suse.com>
893 * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
894 MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
895 MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
896 MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
897 MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
898 MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
899 MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
900 MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
901 MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
902 MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
903 MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
904 MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
905 MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
906 MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
907 MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
908 MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
909 MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
910 MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
911 MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
912 MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
913 MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
914 MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
915 MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
916 MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
917 MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
918 PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
919 PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
920 PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
921 PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
922 PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
923 VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
924 VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
925 VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
926 VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
927 VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
928 VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
929 VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
930 VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
931 VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
932 VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
933 VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
934 VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
935 VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
936 VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
937 VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
938 VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
939 VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
940 VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
941 VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
942 VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
943 VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
944 VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
945 VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
946 VEX_W_0F99_P_2_LEN_0): Delete.
947 MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
948 MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
949 MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
950 MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
951 MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
952 PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
953 PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
954 PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
955 PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
956 PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
957 PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
958 PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
959 PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
960 PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
961 PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
962 PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
963 PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
964 PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
965 PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
966 VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
967 VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
968 VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
969 VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
970 VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
971 VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
972 VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
973 VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
974 (prefix_table): No longer link to vex_len_table[] for opcodes
975 0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
976 0F92, 0F93, 0F98, and 0F99.
977 (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
978 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
980 (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
981 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
983 (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
984 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
986 (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
987 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
990 2021-03-10 Jan Beulich <jbeulich@suse.com>
992 * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
993 Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
994 REG_VEX_0F73_M_0 respectively.
995 (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
996 MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
997 MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
998 MOD_VEX_0F73_REG_7): Delete.
999 (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
1000 (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
1001 PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
1002 PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
1003 PREFIX_VEX_0F3AF0_L_0 respectively.
1004 (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
1005 VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
1006 VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
1007 VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
1008 (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
1009 VEX_LEN_0F38F7): New.
1010 (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
1011 (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
1012 0F72, and 0F73. No longer link to vex_len_table[] for opcode
1014 (prefix_table): No longer link to vex_len_table[] for opcodes
1015 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
1016 (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
1017 0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
1018 0F38F6, 0F38F7, and 0F3AF0.
1019 (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
1020 prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
1021 (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
1024 2021-03-10 Jan Beulich <jbeulich@suse.com>
1026 * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
1027 REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
1028 (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
1029 MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
1030 MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
1031 (MOD_0F71, MOD_0F72, MOD_0F73): New.
1032 (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
1034 (reg_table): No longer link to mod_table[] for opcodes 0F71,
1036 (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
1039 2021-03-10 Jan Beulich <jbeulich@suse.com>
1041 * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
1042 MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
1043 (reg_table): Don't link to mod_table[] where not needed. Add
1044 PREFIX_IGNORED to nop entries.
1045 (prefix_table): Replace PREFIX_OPCODE in nop entries.
1046 (mod_table): Add nop entries next to prefetch ones. Drop
1047 MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
1048 MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
1049 (rm_table): Add PREFIX_IGNORED to nop entries. Drop
1050 PREFIX_OPCODE from endbr* entries.
1051 (get_valid_dis386): Also consider entry's name when zapping
1053 (print_insn): Handle PREFIX_IGNORED.
1055 2021-03-09 Jan Beulich <jbeulich@suse.com>
1057 * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
1058 IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
1060 * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
1061 HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
1062 (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
1063 PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
1064 (struct i386_opcode_modifier): Delete notrackprefixok,
1065 islockable, hleprefixok, and repprefixok fields. Add prefixok
1067 * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
1068 HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
1069 (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
1070 not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
1071 Replace HLEPrefixOk.
1072 * opcodes/i386-tbl.h: Re-generate.
1074 2021-03-09 Jan Beulich <jbeulich@suse.com>
1076 * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
1077 * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
1079 * opcodes/i386-tbl.h: Re-generate.
1081 2021-03-03 Jan Beulich <jbeulich@suse.com>
1083 * i386-gen.c (output_i386_opcode): Don't get operand count. Look
1084 for {} instead of {0}. Don't look for '0'.
1085 * i386-opc.tbl: Drop operand count field. Drop redundant operand
1088 2021-02-19 Nelson Chu <nelson.chu@sifive.com>
1091 * riscv-dis.c (print_insn_args): Updated encoding macros.
1092 * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
1093 (match_c_addi16sp): Updated encoding macros.
1094 (match_c_lui): Likewise.
1095 (match_c_lui_with_hint): Likewise.
1096 (match_c_addi4spn): Likewise.
1097 (match_c_slli): Likewise.
1098 (match_slli_as_c_slli): Likewise.
1099 (match_c_slli64): Likewise.
1100 (match_srxi_as_c_srxi): Likewise.
1101 (riscv_insn_types): Added .insn css/cl/cs.
1103 2021-02-18 Nelson Chu <nelson.chu@sifive.com>
1105 * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
1106 (default_priv_spec): Updated type to riscv_spec_class.
1107 (parse_riscv_dis_option): Updated.
1108 * riscv-opc.c: Moved stuff and make the file tidy.
1110 2021-02-17 Alan Modra <amodra@gmail.com>
1112 * wasm32-dis.c: Include limits.h.
1113 (CHAR_BIT): Provide backup define.
1114 (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
1115 Correct signed overflow checking.
1117 2021-02-16 Jan Beulich <jbeulich@suse.com>
1119 * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
1120 * i386-tbl.h: Re-generate.
1122 2021-02-16 Jan Beulich <jbeulich@suse.com>
1124 * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
1126 * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
1128 2021-02-15 Andreas Krebbel <krebbel@linux.ibm.com>
1130 * s390-mkopc.c (main): Accept arch14 as cpu string.
1131 * s390-opc.txt: Add new arch14 instructions.
1133 2021-02-04 Nick Alcock <nick.alcock@oracle.com>
1135 * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
1137 * configure: Regenerated.
1139 2021-02-08 Mike Frysinger <vapier@gentoo.org>
1141 * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
1142 * tic54x-opc.c (regs): Rename to ...
1143 (tic54x_regs): ... this.
1144 (mmregs): Rename to ...
1145 (tic54x_mmregs): ... this.
1146 (condition_codes): Rename to ...
1147 (tic54x_condition_codes): ... this.
1148 (cc2_codes): Rename to ...
1149 (tic54x_cc2_codes): ... this.
1150 (cc3_codes): Rename to ...
1151 (tic54x_cc3_codes): ... this.
1152 (status_bits): Rename to ...
1153 (tic54x_status_bits): ... this.
1154 (misc_symbols): Rename to ...
1155 (tic54x_misc_symbols): ... this.
1157 2021-02-04 Nelson Chu <nelson.chu@sifive.com>
1159 * riscv-opc.c (MASK_RVB_IMM): Removed.
1160 (riscv_opcodes): Removed zb* instructions.
1161 (riscv_ext_version_table): Removed versions for zb*.
1163 2021-01-26 Alan Modra <amodra@gmail.com>
1165 * i386-gen.c (parse_template): Ensure entire template_instance
1168 2021-01-15 Nelson Chu <nelson.chu@sifive.com>
1170 * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
1171 (riscv_fpr_names_abi): Likewise.
1172 (riscv_opcodes): Likewise.
1173 (riscv_insn_types): Likewise.
1175 2021-01-15 Nelson Chu <nelson.chu@sifive.com>
1177 * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
1179 2021-01-15 Nelson Chu <nelson.chu@sifive.com>
1181 * riscv-dis.c: Comments tidy and improvement.
1182 * riscv-opc.c: Likewise.
1184 2021-01-13 Alan Modra <amodra@gmail.com>
1186 * Makefile.in: Regenerate.
1188 2021-01-12 H.J. Lu <hongjiu.lu@intel.com>
1191 * configure.ac: Use GNU_MAKE_JOBSERVER.
1192 * aclocal.m4: Regenerated.
1193 * configure: Likewise.
1195 2021-01-12 Nick Clifton <nickc@redhat.com>
1197 * po/sr.po: Updated Serbian translation.
1199 2021-01-11 H.J. Lu <hongjiu.lu@intel.com>
1202 * configure: Regenerated.
1204 2021-01-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
1206 * aarch64-asm-2.c: Regenerate.
1207 * aarch64-dis-2.c: Likewise.
1208 * aarch64-opc-2.c: Likewise.
1209 * aarch64-opc.c (aarch64_print_operand):
1210 Delete handling of AARCH64_OPND_CSRE_CSR.
1211 * aarch64-tbl.h (aarch64_feature_csre): Delete.
1213 (_CSRE_INSN): Likewise.
1214 (aarch64_opcode_table): Delete csr.
1216 2021-01-11 Nick Clifton <nickc@redhat.com>
1218 * po/de.po: Updated German translation.
1219 * po/fr.po: Updated French translation.
1220 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1221 * po/sv.po: Updated Swedish translation.
1222 * po/uk.po: Updated Ukranian translation.
1224 2021-01-09 H.J. Lu <hongjiu.lu@intel.com>
1226 * configure: Regenerated.
1228 2021-01-09 Nick Clifton <nickc@redhat.com>
1230 * configure: Regenerate.
1231 * po/opcodes.pot: Regenerate.
1233 2021-01-09 Nick Clifton <nickc@redhat.com>
1235 * 2.36 release branch crated.
1237 2021-01-08 Peter Bergner <bergner@linux.ibm.com>
1239 * ppc-opc.c (insert_dw, (extract_dw): New functions.
1240 (DW, (XRC_MASK): Define.
1241 (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
1243 2021-01-09 Alan Modra <amodra@gmail.com>
1245 * configure: Regenerate.
1247 2021-01-08 Nick Clifton <nickc@redhat.com>
1249 * po/sv.po: Updated Swedish translation.
1251 2021-01-08 Nick Clifton <nickc@redhat.com>
1254 * aarch64-dis.c (determine_disassembling_preference): Move call to
1255 aarch64_match_operands_constraint outside of the assertion.
1256 * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
1257 Replace with a return of FALSE.
1260 * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
1261 core system register.
1263 2021-01-07 Samuel Thibault <samuel.thibault@gnu.org>
1265 * configure: Regenerate.
1267 2021-01-07 Nick Clifton <nickc@redhat.com>
1269 * po/fr.po: Updated French translation.
1271 2021-01-07 Fredrik Noring <noring@nocrew.org>
1273 * m68k-opc.c (chkl): Change minimum architecture requirement to
1276 2021-01-07 Philipp Tomsich <prt@gnu.org>
1278 * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
1280 2021-01-07 Claire Xenia Wolf <claire@symbioticeda.com>
1281 Jim Wilson <jimw@sifive.com>
1282 Andrew Waterman <andrew@sifive.com>
1283 Maxim Blinov <maxim.blinov@embecosm.com>
1284 Kito Cheng <kito.cheng@sifive.com>
1285 Nelson Chu <nelson.chu@sifive.com>
1287 * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
1288 (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
1290 2021-01-01 Alan Modra <amodra@gmail.com>
1292 Update year range in copyright notice of all files.
1294 For older changes see ChangeLog-2020
1296 Copyright (C) 2021-2022 Free Software Foundation, Inc.
1298 Copying and distribution of this file, with or without modification,
1299 are permitted in any medium without royalty provided the copyright
1300 notice and this notice are preserved.
1306 version-control: never