opcodes/ChangeLog

   1 2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
   2
   3         * crx-opc.c (crx_optab): Mark all rbase_disps* operands as signed.
   4         (no_op_insn): Initialize array with instructions that have no
   5         operands.
   6         * crx-dis.c (make_instruction): Get rid of COP_BRANCH_INS operand swapping.
   7
   8 2004-11-29  Richard Earnshaw  <rearnsha@arm.com>
   9
  10         * arm-dis.c: Correct top-level comment.
  11
  12 2004-11-27  Richard Earnshaw  <rearnsha@arm.com>
  13
  14         * arm-opc.h (arm_opcode, thumb_opcode): Add extra field for the
  15         architecuture defining the insn.
  16         (arm_opcodes, thumb_opcodes): Delete.  Move to ...
  17         * arm-dis.c (arm_opcodes, thumb_opcodes): Here.  Add architecutre
  18         field.
  19         Also include opcode/arm.h.
  20         * Makefile.am (arm-dis.lo): Update dependency list.
  21         * Makefile.in: Regenerate.
  22
  23 2004-11-22  Ravi Ramaseshan  <ravi.ramaseshan@codito.com>
  24
  25         * opcode/arc-opc.c (insert_base): Modify ls_operand[LS_OFFSET] to
  26         reflect the change to the short immediate syntax.
  27
  28 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
  29
  30         * or32-opc.c (debug): Warning fix.
  31         * po/POTFILES.in: Regenerate.
  32
  33         * maxq-dis.c: Formatting.
  34         (print_insn): Warning fix.
  35
  36 2004-11-17  Daniel Jacobowitz  <dan@codesourcery.com>
  37
  38         * arm-dis.c (WORD_ADDRESS): Define.
  39         (print_insn): Use it.  Correct big-endian end-of-section handling.
  40
  41 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
  42             Vineet Sharma      <vineets@noida.hcltech.com>
  43
  44         * maxq-dis.c: New file.
  45         * disassemble.c (ARCH_maxq): Define.
  46         (disassembler): Add 'print_insn_maxq_little' for handling maxq
  47         instructions..
  48         * configure.in: Add case for bfd_maxq_arch.
  49         * configure: Regenerate.
  50         * Makefile.am: Add support for maxq-dis.c
  51         * Makefile.in: Regenerate.
  52         * aclocal.m4: Regenerate.
  53
  54 2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
  55
  56         * crx-opc.c (crx_optab): Rename 'arg_icr' to 'arg_idxr' for Index register
  57         mode.
  58         * crx-dis.c: Likewise.
  59
  60 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
  61
  62         Generally, handle CRISv32.
  63         * cris-dis.c (TRACE_CASE): Define as (disdata->trace_case).
  64         (struct cris_disasm_data): New type.
  65         (format_reg, format_hex, cris_constraint, print_flags)
  66         (get_opcode_entry): Add struct cris_disasm_data * parameter.  All
  67         callers changed.
  68         (format_sup_reg, print_insn_crisv32_with_register_prefix)
  69         (print_insn_crisv32_without_register_prefix)
  70         (print_insn_crisv10_v32_with_register_prefix)
  71         (print_insn_crisv10_v32_without_register_prefix)
  72         (cris_parse_disassembler_options): New functions.
  73         (bytes_to_skip, cris_spec_reg): Add enum cris_disass_family
  74         parameter.  All callers changed.
  75         (get_opcode_entry): Call malloc, not xmalloc.  Return NULL on
  76         failure.
  77         (cris_constraint) <case 'Y', 'U'>: New cases.
  78         (bytes_to_skip): Handle 'Y' and 'N' as 's'.  Skip size is 4 bytes
  79         for constraint 'n'.
  80         (print_with_operands) <case 'Y'>: New case.
  81         (print_with_operands) <case 'T', 'A', '[', ']', 'd', 'n', 'u'>
  82         <case 'N', 'Y', 'Q'>: New cases.
  83         (print_insn_cris_generic): Emit "bcc ." for zero and CRISv32.
  84         (print_insn_cris_with_register_prefix)
  85         (print_insn_cris_without_register_prefix): Call
  86         cris_parse_disassembler_options.
  87         * cris-opc.c (cris_spec_regs): Mention that this table isn't used
  88         for CRISv32 and the size of immediate operands.  New v32-only
  89         entries for bz, pid, srs, wz, exs, eda, dz, ebp, erp, nrp, ccs and
  90         spc.  Add v32-only 4-byte entries for p2, p3, p5 and p6.  Change
  91         ccr, ibr, irp to be v0..v10.  Change bar, dccr to be v8..v10.
  92         Change brp to be v3..v10.
  93         (cris_support_regs): New vector.
  94         (cris_opcodes): Update head comment.  New format characters '[',
  95         ']', space, 'A', 'd', 'N', 'n', 'Q', 'T', 'u', 'U', 'Y'.
  96         Add new opcodes for v32 and adjust existing opcodes to accommodate
  97         differences to earlier variants.
  98         (cris_cond15s): New vector.
  99
 100 2004-11-04 Jan Beulich <jbeulich@novell.com>
 101
 102         * i386-dis.c (Eq, Edqw, indirEp, Gdq, I1): Define.
 103         (indirEb): Remove.
 104         (Mp): Use f_mode rather than none at all.
 105         (t_mode, dq_mode, dqw_mode, f_mode, const_1_mode): Define. t_mode
 106         replaces what previously was x_mode; x_mode now means 128-bit SSE
 107         operands.
 108         (dis386): Make far jumps and calls have an 'l' prefix only in AT&T
 109         mode. movmskpX's, pextrw's, and pmovmskb's first operands are Gdq.
 110         pinsrw's second operand is Edqw.
 111         (grps): 1-bit shifts' and rotates' second operands are I1. cmpxchg8b's
 112         operand is Eq. movntq's and movntdq's first operands are EM. s[gi]dt,
 113         fldenv, frstor, fsave, fstenv all should also have suffixes in Intel
 114         mode when an operand size override is present or always suffixing.
 115         More instructions will need to be added to this group.
 116         (putop): Handle new macro chars 'C' (short/long suffix selector),
 117         'I' (Intel mode override for following macro char), and 'J' (for
 118         adding the 'l' prefix to far branches in AT&T mode). When an
 119         alternative was specified in the template, honor macro character when
 120         specified for Intel mode.
 121         (OP_E): Handle new *_mode values. Correct pointer specifications for
 122         memory operands. Consolidate output of index register.
 123         (OP_G): Handle new *_mode values.
 124         (OP_I): Handle const_1_mode.
 125         (OP_ESreg, OP_DSreg): Generate pointer specifications. Indicate
 126         respective opcode prefix bits have been consumed.
 127         (OP_EM, OP_EX): Provide some default handling for generating pointer
 128         specifications.
 129
 130 2004-10-28  Tomer Levi  <Tomer.Levi@nsc.com>
 131
 132         * crx-opc.c (REV_COP_INST): New macro, reverse operand order of
 133         COP_INST macro.
 134
 135 2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
 136
 137         * crx-dis.c (enum REG_ARG_TYPE): New, replacing COP_ARG_TYPE.
 138         (getregliststring): Support HI/LO and user registers.
 139         * crx-opc.c (crx_instruction): Update data structure according to the
 140         rearrangement done in CRX opcode header file.
 141         (crx_regtab):  Likewise.
 142         (crx_optab):  Likewise.
 143         (crx_instruction): Reorder load/stor instructions, remove unsupported
 144         formats.
 145         support new Co-Processor instruction 'cpi'.
 146
 147 2004-10-27  Nick Clifton  <nickc@redhat.com>
 148
 149         * opcodes/iq2000-asm.c: Regenerate.
 150         * opcodes/iq2000-desc.c: Regenerate.
 151         * opcodes/iq2000-desc.h: Regenerate.
 152         * opcodes/iq2000-dis.c: Regenerate.
 153         * opcodes/iq2000-ibld.c: Regenerate.
 154         * opcodes/iq2000-opc.c: Regenerate.
 155         * opcodes/iq2000-opc.h: Regenerate.
 156
 157 2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
 158
 159         * crx-opc.c (crx_instruction): Replace i3, i4, i5 with us3,
 160         us4, us5 (respectively).
 161         Remove unsupported 'popa' instruction.
 162         Reverse operands order in store co-processor instructions.
 163
 164 2004-10-15  Alan Modra  <amodra@bigpond.net.au>
 165
 166         * Makefile.am: Run "make dep-am"
 167         * Makefile.in: Regenerate.
 168
 169 2004-10-12  Bob Wilson  <bob.wilson@acm.org>
 170
 171         * xtensa-dis.c: Use ISO C90 formatting.
 172
 173 2004-10-09  Alan Modra  <amodra@bigpond.net.au>
 174
 175         * ppc-opc.c: Revert 2004-09-09 change.
 176
 177 2004-10-07  Bob Wilson  <bob.wilson@acm.org>
 178
 179         * xtensa-dis.c (state_names): Delete.
 180         (fetch_data): Use xtensa_isa_maxlength.
 181         (print_xtensa_operand): Replace operand parameter with opcode/operand
 182         pair.  Remove print_sr_name parameter.  Use new xtensa-isa.h functions.
 183         (print_insn_xtensa): Use new xtensa-isa.h functions.  Handle multislot
 184         instruction bundles.  Use xmalloc instead of malloc.
 185
 186 2004-10-07  David Gibson  <david@gibson.dropbear.id.au>
 187
 188         * ppc-opc.c: Replace literal "0"s with NULLs in pointer
 189         initializers.
 190
 191 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
 192
 193         * crx-opc.c (crx_instruction): Support Co-processor insns.
 194         * crx-dis.c (COP_ARG_TYPE): New enum for CO-Processor arguments.
 195         (getregliststring): Change function to use the above enum.
 196         (print_arg): Handle CO-Processor insns.
 197         (crx_cinvs): Add 'b' option to invalidate the branch-target
 198         cache.
 199
 200 2004-10-06  Aldy Hernandez  <aldyh@redhat.com>
 201
 202         * ppc-opc.c (powerpc_opcodes): Add efscfd, efdabs, efdnabs,
 203         efdneg, efdadd, efdsub, efdmul, efddiv, efdcmpgt, efdcmplt,
 204         efdcmpeq, efdtstgt, efdtstlt, efdtsteq, efdcfsi, efdcfsid,
 205         efdcfui, efdcfuid, efdcfsf, efdcfuf, efdctsi, efdctsidz, efdctsiz,
 206         efdctui, efdctuidz, efdctuiz, efdctsf, efdctuf, efdctuf, efdcfs.
 207
 208 2004-10-01  Bill Farmer  <Bill@the-farmers.freeserve.co.uk>
 209
 210         * pdp11-dis.c (print_insn_pdp11): Subtract the SOB's displacement
 211         rather than add it.
 212
 213 2004-09-30  Paul Brook  <paul@codesourcery.com>
 214
 215         * arm-dis.c (print_insn_arm): Handle 'e' for SMI instruction.
 216         * arm-opc.h: Document %e.  Add ARMv6ZK instructions.
 217
 218 2004-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 219
 220         * Makefile.am (AUTOMAKE_OPTIONS): Require 1.9.
 221         (CONFIG_STATUS_DEPENDENCIES): New.
 222         (Makefile): Removed.
 223         (config.status): Likewise.
 224         * Makefile.in: Regenerated.
 225
 226 2004-09-17  Alan Modra  <amodra@bigpond.net.au>
 227
 228         * Makefile.am: Run "make dep-am".
 229         * Makefile.in: Regenerate.
 230         * aclocal.m4: Regenerate.
 231         * configure: Regenerate.
 232         * po/POTFILES.in: Regenerate.
 233         * po/opcodes.pot: Regenerate.
 234
 235 2004-09-11  Andreas Schwab  <schwab@suse.de>
 236
 237         * configure: Rebuild.
 238
 239 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
 240
 241         * ppc-opc.c (L): Make this field not optional.
 242
 243 2004-09-03  Tomer Levi  <Tomer.Levi@nsc.com>
 244
 245         * opc-crx.c: Rename 'popma' to 'popa', remove 'pushma'.
 246         Fix parameter to 'm[t|f]csr' insns.
 247
 248 2004-08-30  Nathanael Nerode  <neroden@gcc.gnu.org>
 249
 250         * configure.in: Autoupdate to autoconf 2.59.
 251         * aclocal.m4: Rebuild with aclocal 1.4p6.
 252         * configure: Rebuild with autoconf 2.59.
 253         * Makefile.in: Rebuild with automake 1.4p6 (picking up
 254         bfd changes for autoconf 2.59 on the way).
 255         * config.in: Rebuild with autoheader 2.59.
 256
 257 2004-08-27  Richard Sandiford  <rsandifo@redhat.com>
 258
 259         * frv-desc.[ch], frv-opc.[ch]: Regenerated.
 260
 261 2004-07-30  Michal Ludvig  <mludvig@suse.cz>
 262
 263         * i386-dis.c (GRPPADLCK): Renamed to GRPPADLCK1
 264         (GRPPADLCK2): New define.
 265         (twobyte_has_modrm): True for 0xA6.
 266         (grps): GRPPADLCK2 for opcode 0xA6.
 267
 268 2004-07-29  Alexandre Oliva  <aoliva@redhat.com>
 269
 270         Introduce SH2a support.
 271         * sh-opc.h (arch_sh2a_base): Renumber.
 272         (arch_sh2a_nofpu_base): Remove.
 273         (arch_sh_base_mask): Adjust.
 274         (arch_opann_mask): New.
 275         (arch_sh2a, arch_sh2a_nofpu): Adjust.
 276         (arch_sh2a_up, arch_sh2a_nofpu_up): Likewise.
 277         (sh_table): Adjust whitespace.
 278         2004-02-24  Corinna Vinschen  <vinschen@redhat.com>
 279         * sh-opc.h (arch_sh2a_nofpu_up): New.  Use instead of arch_sh2a_up in
 280         instruction list throughout.
 281         (arch_sh2a_up): Redefine to include fpu instruction set.  Use instead
 282         of arch_sh2a in instruction list throughout.
 283         (arch_sh2e_up): Accomodate above changes.
 284         (arch_sh2_up): Ditto.
 285         2004-02-20  Corinna Vinschen  <vinschen@redhat.com>
 286         * sh-opc.h: Add arch_sh2a_nofpu to arch_sh2_up.
 287         2004-02-18  Corinna Vinschen  <vinschen@redhat.com>
 288         * sh-dis.c (print_insn_sh): Add bfd_mach_sh2a_nofpu handling.
 289         * sh-opc.h (arch_sh2a_nofpu): New.
 290         (arch_sh2a_up): New, defines sh2a and sh2a_nofpu.
 291         (sh_table): Change all arch_sh2a to arch_sh2a_up unless FPU
 292         instruction.
 293         2004-01-20  DJ Delorie  <dj@redhat.com>
 294         * sh-dis.c (print_insn_sh): SH2A does not have 'X' fp regs.
 295         2003-12-29  DJ Delorie  <dj@redhat.com>
 296         * sh-opc.c (sh_nibble_type, sh_arg_type, arch_2a, arch_2e_up,
 297         sh_opcode_info, sh_table): Add sh2a support.
 298         (arch_op32): New, to tag 32-bit opcodes.
 299         * sh-dis.c (print_insn_sh): Support sh2a opcodes.
 300         2003-12-02  Michael Snyder  <msnyder@redhat.com>
 301         * sh-opc.h (arch_sh2a): Add.
 302         * sh-dis.c (arch_sh2a): Handle.
 303         * sh-opc.h (arch_sh2_up): Fix up to include arch_sh2a.
 304
 305 2004-07-27  Tomer Levi  <Tomer.Levi@nsc.com>
 306
 307         * crx-opc.c: Add popx,pushx insns. Indent code, fix comments.
 308
 309 2004-07-22  Nick Clifton  <nickc@redhat.com>
 310
 311         PR/280
 312         * h8300-dis.c (bfd_h8_disassemble): Do not dump raw bytes for the
 313         insns - this is done by objdump itself.
 314         * h8500-dis.c (print_insn_h8500): Likewise.
 315
 316 2004-07-21  Jan Beulich <jbeulich@novell.com>
 317
 318         * i386-dis.c (OP_E): Show rip-relative addressing in 64-bit mode
 319         regardless of address size prefix in effect.
 320         (ptr_reg): Size or address registers does not depend on rex64, but
 321         on the presence of an address size override.
 322         (OP_MMX): Use rex.x only for xmm registers.
 323         (OP_EM): Use rex.z only for xmm registers.
 324
 325 2004-07-20  Maciej W. Rozycki  <macro@linux-mips.org>
 326
 327         * mips-opc.c (mips_builtin_opcodes): Move coprocessor 2
 328         move/branch operations to the bottom so that VR5400 multimedia
 329         instructions take precedence in disassembly.
 330
 331 2004-07-20  Maciej W. Rozycki  <macro@linux-mips.org>
 332
 333         * mips-opc.c (mips_builtin_opcodes): Remove the MIPS32
 334         ISA-specific "break" encoding.
 335
 336 2004-07-13  Elvis Chiang  <elvisfb@gmail.com>
 337
 338         * arm-opc.h: Fix typo in comment.
 339
 340 2004-07-11  Andreas Schwab  <schwab@suse.de>
 341
 342         * m68k-dis.c (m68k_valid_ea): Fix typos in last change.
 343
 344 2004-07-09  Andreas Schwab  <schwab@suse.de>
 345
 346         * m68k-dis.c (m68k_valid_ea): Check validity of all codes.
 347
 348 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
 349
 350         * Makefile.am (CFILES): Add crx-dis.c, crx-opc.c.
 351         (ALL_MACHINES): Add crx-dis.lo, crx-opc.lo.
 352         (crx-dis.lo): New target.
 353         (crx-opc.lo): Likewise.
 354         * Makefile.in: Regenerate.
 355         * configure.in: Handle bfd_crx_arch.
 356         * configure: Regenerate.
 357         * crx-dis.c: New file.
 358         * crx-opc.c: New file.
 359         * disassemble.c (ARCH_crx): Define.
 360         (disassembler): Handle ARCH_crx.
 361
 362 2004-06-29  James E Wilson  <wilson@specifixinc.com>
 363
 364         * ia64-opc-a.c (ia64_opcodes_a): Delete mov immediate pseudo for adds.
 365         * ia64-asmtab.c: Regnerate.
 366
 367 2004-06-28  Alan Modra  <amodra@bigpond.net.au>
 368
 369         * ppc-opc.c (insert_fxm): Handle mfocrf and mtocrf.
 370         (extract_fxm): Don't test dialect.
 371         (XFXFXM_MASK): Include the power4 bit.
 372         (XFXM): Add p4 param.
 373         (powerpc_opcodes): Add mfocrf and mtocrf.  Adjust mtcr.
 374
 375 2004-06-27  Alexandre Oliva  <aoliva@redhat.com>
 376
 377         2003-07-21  Richard Sandiford  <rsandifo@redhat.com>
 378         * disassemble.c (disassembler): Handle bfd_mach_h8300sxn.
 379
 380 2004-06-26  Alan Modra  <amodra@bigpond.net.au>
 381
 382         * ppc-opc.c (BH, XLBH_MASK): Define.
 383         (powerpc_opcodes): Allow BH field on bclr, bclrl, bcctr, bcctrl.
 384
 385 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
 386
 387         * i386-dis.c (x_mode): Comment.
 388         (two_source_ops): File scope.
 389         (float_mem): Correct fisttpll and fistpll.
 390         (float_mem_mode): New table.
 391         (dofloat): Use it.
 392         (OP_E): Correct intel mode PTR output.
 393         (ptr_reg): Use open_char and close_char.
 394         (PNI_Fixup): Handle possible suffix on sidt.  Use op1out etc. for
 395         operands.  Set two_source_ops.
 396
 397 2004-06-15  Alan Modra  <amodra@bigpond.net.au>
 398
 399         * arc-ext.c (build_ARC_extmap): Use bfd_get_section_size
 400         instead of _raw_size.
 401
 402 2004-06-08  Jakub Jelinek  <jakub@redhat.com>
 403
 404         * ia64-gen.c (in_iclass): Handle more postinc st
 405         and ld variants.
 406         * ia64-asmtab.c: Rebuilt.
 407
 408 2004-06-01  Martin Schwidefsky  <schwidefsky@de.ibm.com>
 409
 410         * s390-opc.txt: Correct architecture mask for some opcodes.
 411         lrv, lrvh, strv, ml, dl, alc, slb rll and mvclu are available
 412         in the esa mode as well.
 413
 414 2004-05-28  Andrew Stubbs <andrew.stubbs@superh.com>
 415
 416         * sh-dis.c (target_arch): Make unsigned.
 417         (print_insn_sh): Replace (most of) switch with a call to
 418         sh_get_arch_from_bfd_mach(). Also use new architecture flags system.
 419         * sh-opc.h: Redefine architecture flags values.
 420         Add sh3-nommu architecture.
 421         Reorganise <arch>_up macros so they make more visual sense.
 422         (SH_MERGE_ARCH_SET): Define new macro.
 423         (SH_VALID_BASE_ARCH_SET): Likewise.
 424         (SH_VALID_MMU_ARCH_SET): Likewise.
 425         (SH_VALID_CO_ARCH_SET): Likewise.
 426         (SH_VALID_ARCH_SET): Likewise.
 427         (SH_MERGE_ARCH_SET_VALID): Likewise.
 428         (SH_ARCH_SET_HAS_FPU): Likewise.
 429         (SH_ARCH_SET_HAS_DSP): Likewise.
 430         (SH_ARCH_UNKNOWN_ARCH): Likewise.
 431         (sh_get_arch_from_bfd_mach): Add prototype.
 432         (sh_get_arch_up_from_bfd_mach): Likewise.
 433         (sh_get_bfd_mach_from_arch_set): Likewise.
 434         (sh_merge_bfd_arc): Likewise.
 435
 436 2004-05-24  Peter Barada  <peter@the-baradas.com>
 437
 438         * m68k-dis.c(print_insn_m68k): Strip body of diassembly out
 439         into new match_insn_m68k function.  Loop over canidate
 440         matches and select first that completely matches.
 441         * m68k-dis.c(print_insn_arg): Fix 'g' case to only extract 1 bit.
 442         * m68k-dis.c(print_insn_arg): Call new function m68k_valid_ea
 443         to verify addressing for MAC/EMAC.
 444         * m68k-dis.c(print_insn_arg): Use reg_half_names for MAC/EMAC
 445         reigster halves since 'fpu' and 'spl' look misleading.
 446         * m68k-dis.c(fetch_arg): Fix 'G', 'H', 'I', 'f', 'M', 'N' cases.
 447         * m68k-opc.c: Rearragne mac/emac cases to use longest for
 448         first, tighten up match masks.
 449         * m68k-opc.c: Add 'size' field to struct m68k_opcode.  Produce
 450         'size' from special case code in print_insn_m68k to
 451         determine decode size of insns.
 452
 453 2004-05-19  Alan Modra  <amodra@bigpond.net.au>
 454
 455         * ppc-opc.c (insert_fxm): Enable two operand mfcr when -many as
 456         well as when -mpower4.
 457
 458 2004-05-13  Nick Clifton  <nickc@redhat.com>
 459
 460         * po/fr.po: Updated French translation.
 461
 462 2004-05-05  Peter Barada  <peter@the-baradas.com>
 463
 464         * m68k-dis.c(print_insn_m68k): Add new chips, use core
 465         variants in arch_mask.  Only set m68881/68851 for 68k chips.
 466         * m68k-op.c: Switch from ColdFire chips to core variants.
 467
 468 2004-05-05  Alan Modra  <amodra@bigpond.net.au>
 469
 470         PR 147.
 471         * ppc-opc.c (PPCVEC): Remove PPC_OPCODE_PPC.
 472
 473 2004-04-29  Ben Elliston  <bje@au.ibm.com>
 474
 475         * ppc-opc.c (XCMPL): Renmame to XOPL. Update users.
 476         (powerpc_opcodes): Add "dbczl" instruction for PPC970.
 477
 478 2004-04-22  Kaz Kojima  <kkojima@rr.iij4u.or.jp>
 479
 480         * sh-dis.c (print_insn_sh): Print the value in constant pool
 481         as a symbol if it looks like a symbol.
 482
 483 2004-04-22  Peter Barada <peter@the-baradas.com>
 484
 485         * m68k-dis.c(print_insn_m68k): Set mfcmac/mcfemac on
 486         appropriate ColdFire architectures.
 487         (print_insn_m68k): Handle EMAC, MAC/EMAC scalefactor, and MAC/EMAC
 488         mask addressing.
 489         Add EMAC instructions, fix MAC instructions. Remove
 490         macmw/macml/msacmw/msacml instructions since mask addressing now
 491         supported.
 492
 493 2004-04-20  Jakub Jelinek  <jakub@redhat.com>
 494
 495         * sparc-opc.c (fmoviccx, fmovfccx, fmovccx): Define.
 496         (fmovicc, fmovfcc, fmovcc): Remove fpsize argument, change opcode to
 497         suffix.  Use fmov*x macros, create all 3 fpsize variants in one
 498         macro.  Adjust all users.
 499
 500 2004-04-15  Anil Paranjpe  <anilp1@kpitcummins.com>
 501
 502         * h8300-dis.c (bfd_h8_disassemble) : Treat "adds" & "subs"
 503         separately.
 504
 505 2004-03-30  Kazuhiro Inaoka  <inaoka.kazuhiro@renesas.com>
 506
 507         * m32r-asm.c: Regenerate.
 508
 509 2004-03-29  Stan Shebs  <shebs@apple.com>
 510
 511         * mpw-config.in, mpw-make.sed: Remove MPW support files, no longer
 512         used.
 513
 514 2004-03-19  Alan Modra  <amodra@bigpond.net.au>
 515
 516         * aclocal.m4: Regenerate.
 517         * config.in: Regenerate.
 518         * configure: Regenerate.
 519         * po/POTFILES.in: Regenerate.
 520         * po/opcodes.pot: Regenerate.
 521
 522 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
 523
 524         * ppc-dis.c (print_insn_powerpc): Don't print tabs.  Handle
 525         PPC_OPERANDS_GPR_0.
 526         * ppc-opc.c (RA0): Define.
 527         (RAQ, RAL, RAM, RAS, RSQ, RTQ, RSO): Use PPC_OPERAND_GPR_0.
 528         (RAOPT): Rename from RAO.  Update all uses.
 529         (powerpc_opcodes): Use RA0 as appropriate.
 530
 531 2004-03-15  Aldy Hernandez  <aldyh@redhat.com>
 532
 533         * ppc-opc.c (powerpc_opcodes): Add BOOKE versions of mfsprg.
 534
 535 2004-03-15  Alan Modra  <amodra@bigpond.net.au>
 536
 537         * sparc-dis.c (print_insn_sparc): Update getword prototype.
 538
 539 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 540
 541         * i386-dis.c (GRPPLOCK): Delete.
 542         (grps): Delete GRPPLOCK entry.
 543
 544 2004-03-12  Alan Modra  <amodra@bigpond.net.au>
 545
 546         * i386-dis.c (OP_M, OP_0f0e, OP_0fae, NOP_Fixup): New functions.
 547         (M, Mp): Use OP_M.
 548         (None, PADLOCK_SPECIAL, PADLOCK_0): Delete.
 549         (GRPPADLCK): Define.
 550         (dis386): Use NOP_Fixup on "nop".
 551         (dis386_twobyte): Use GRPPADLCK on opcode 0xa7.
 552         (twobyte_has_modrm): Set for 0xa7.
 553         (padlock_table): Delete.  Move to..
 554         (grps): ..here, using OP_0f07.  Use OP_Ofae on lfence, mfence
 555         and clflush.
 556         (print_insn): Revert PADLOCK_SPECIAL code.
 557         (OP_E): Delete sfence, lfence, mfence checks.
 558
 559 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
 560
 561         * i386-dis.c (grps): Use INVLPG_Fixup instead of OP_E for invlpg.
 562         (INVLPG_Fixup): New function.
 563         (PNI_Fixup): Remove ATTRIBUTE_UNUSED from sizeflag.
 564
 565 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 566
 567         * i386-dis.c (PADLOCK_SPECIAL, PADLOCK_0): New defines.
 568         (dis386_twobyte): Opcode 0xa7 is PADLOCK_0.
 569         (padlock_table): New struct with PadLock instructions.
 570         (print_insn): Handle PADLOCK_SPECIAL.
 571
 572 2004-03-12  Alan Modra  <amodra@bigpond.net.au>
 573
 574         * i386-dis.c (grps): Use clflush by default for 0x0fae/7.
 575         (OP_E): Twiddle clflush to sfence here.
 576
 577 2004-03-08  Nick Clifton  <nickc@redhat.com>
 578
 579         * po/de.po: Updated German translation.
 580
 581 2003-03-03  Andrew Stubbs  <andrew.stubbs@superh.com>
 582
 583         * sh-dis.c (print_insn_sh): Don't disassemble fp instructions in
 584         nofpu mode.  Add BFD type bfd_mach_sh4_nommu_nofpu.
 585         * sh-opc.h: Add sh4_nommu_nofpu architecture and adjust instructions
 586         accordingly.
 587
 588 2004-03-01  Richard Sandiford  <rsandifo@redhat.com>
 589
 590         * frv-asm.c: Regenerate.
 591         * frv-desc.c: Regenerate.
 592         * frv-desc.h: Regenerate.
 593         * frv-dis.c: Regenerate.
 594         * frv-ibld.c: Regenerate.
 595         * frv-opc.c: Regenerate.
 596         * frv-opc.h: Regenerate.
 597
 598 2004-03-01  Richard Sandiford  <rsandifo@redhat.com>
 599
 600         * frv-desc.c, frv-opc.c: Regenerate.
 601
 602 2004-03-01  Richard Sandiford  <rsandifo@redhat.com>
 603
 604         * frv-desc.c, frv-opc.c, frv-opc.h: Regenerate.
 605
 606 2004-02-26  Andrew Stubbs  <andrew.stubbs@superh.com>
 607
 608         * sh-opc.h: Move fsca and fsrra instructions from sh4a to sh4.
 609         Also correct mistake in the comment.
 610
 611 2004-02-26  Andrew Stubbs <andrew.stubbs@superh.com>
 612
 613         * sh-dis.c (print_insn_sh): Add REG_N_D nibble type to
 614         ensure that double registers have even numbers.
 615         Add REG_N_B01 for nn01 (binary 01) nibble to ensure
 616         that reserved instruction 0xfffd does not decode the same
 617         as 0xfdfd (ftrv).
 618         * sh-opc.h: Add REG_N_D nibble type and use it whereever
 619         REG_N refers to a double register.
 620         Add REG_N_B01 nibble type and use it instead of REG_NM
 621         in ftrv.
 622         Adjust the bit patterns in a few comments.
 623
 624 2004-02-25  Aldy Hernandez  <aldyh@redhat.com>
 625
 626         * ppc-opc.c (powerpc_opcodes): Change mask for dcbt and dcbtst.
 627
 628 2004-02-20  Aldy Hernandez  <aldyh@redhat.com>
 629
 630         * ppc-opc.c (powerpc_opcodes): Move mfmcsrr0 before mfdc_dat.
 631
 632 2004-02-20  Aldy Hernandez  <aldyh@redhat.com>
 633
 634         * ppc-opc.c (powerpc_opcodes): Add m*ivor35.
 635
 636 2004-02-20  Aldy Hernandez  <aldyh@redhat.com>
 637
 638         * ppc-opc.c (powerpc_opcodes): Add mfivor32, mfivor33, mfivor34,
 639         mtivor32, mtivor33, mtivor34.
 640
 641 2004-02-19  Aldy Hernandez  <aldyh@redhat.com>
 642
 643         * ppc-opc.c (powerpc_opcodes): Add mfmcar.
 644
 645 2004-02-10  Petko Manolov  <petkan@nucleusys.com>
 646
 647         * arm-opc.h Maverick accumulator register opcode fixes.
 648
 649 2004-02-13  Ben Elliston  <bje@wasabisystems.com>
 650
 651         * m32r-dis.c: Regenerate.
 652
 653 2004-01-27  Michael Snyder  <msnyder@redhat.com>
 654
 655         * sh-opc.h (sh_table): "fsrra", not "fssra".
 656
 657 2004-01-23  Andrew Over <andrew.over@cs.anu.edu.au>
 658
 659         * sparc-opc.c (fdtox, fstox, fqtox, fxtod, fxtos, fxtoq): Tighten
 660         contraints.
 661
 662 2004-01-19  Andrew Over  <andrew.over@cs.anu.edu.au>
 663
 664         * sparc-opc.c (sparc_opcodes) <f[dsq]tox, fxto[dsq]>: Fix args.
 665
 666 2004-01-19  Alan Modra  <amodra@bigpond.net.au>
 667
 668         * i386-dis.c (OP_E): Print scale factor on intel mode sib when not
 669         1.  Don't print scale factor on AT&T mode when index missing.
 670
 671 2004-01-16  Alexandre Oliva  <aoliva@redhat.com>
 672
 673         * m10300-opc.c (mov): 8- and 24-bit immediates are zero-extended
 674         when loaded into XR registers.
 675
 676 2004-01-14  Richard Sandiford  <rsandifo@redhat.com>
 677
 678         * frv-desc.h: Regenerate.
 679         * frv-desc.c: Regenerate.
 680         * frv-opc.c: Regenerate.
 681
 682 2004-01-13  Michael Snyder  <msnyder@redhat.com>
 683
 684         * sh-dis.c (print_insn_sh): Allocate 4 bytes for insn.
 685
 686 2004-01-09  Paul Brook  <paul@codesourcery.com>
 687
 688         * arm-opc.h (arm_opcodes): Move generic mcrr after known
 689         specific opcodes.
 690
 691 2004-01-07  Daniel Jacobowitz  <drow@mvista.com>
 692
 693         * Makefile.am (libopcodes_la_DEPENDENCIES)
 694         (libopcodes_la_LIBADD): Revert 2003-05-17 change.  Add explanatory
 695         comment about the problem.
 696         * Makefile.in: Regenerate.
 697
 698 2004-01-06  Alexandre Oliva  <aoliva@redhat.com>
 699
 700         2003-12-19  Alexandre Oliva  <aoliva@redhat.com>
 701         * frv-asm.c (parse_ulo16, parse_uhi16, parse_d12): Fix some
 702         cut&paste errors in shifting/truncating numerical operands.
 703         2003-08-04  Alexandre Oliva  <aoliva@redhat.com>
 704         * frv-asm.c (parse_ulo16): Parse gotofflo and gotofffuncdesclo.
 705         (parse_uslo16): Likewise.
 706         (parse_uhi16): Parse gotoffhi and gotofffuncdeschi.
 707         (parse_d12): Parse gotoff12 and gotofffuncdesc12.
 708         (parse_s12): Likewise.
 709         2003-08-04  Alexandre Oliva  <aoliva@redhat.com>
 710         * frv-asm.c (parse_ulo16): Parse gotlo and gotfuncdesclo.
 711         (parse_uslo16): Likewise.
 712         (parse_uhi16): Parse gothi and gotfuncdeschi.
 713         (parse_d12): Parse got12 and gotfuncdesc12.
 714         (parse_s12): Likewise.
 715
 716 2004-01-02  Albert Bartoszko  <albar@nt.kegel.com.pl>
 717
 718         * msp430-dis.c (msp430_doubleoperand): Check for an 'add'
 719         instruction which looks similar to an 'rla' instruction.
 720
 721 For older changes see ChangeLog-0203
 722 \f
 723 Local Variables:
 724 mode: change-log
 725 left-margin: 8
 726 fill-column: 74
 727 version-control: never
 728 End: