opcodes/ChangeLog

   1 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
   2
   3         * Makefile.am (mips-opc.lo, micromips-opc.lo, mips16-opc.lo): Remove
   4         special rules.
   5         * Makefile.in: Regenerate.
   6         * mips-opc.c, micromips-opc.c, mips16-opc.c: Explicitly initialize
   7         all fields.  Reformat.
   8
   9 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
  10
  11         * mips16-opc.c: Include mips-formats.h.
  12         (reg_0_map, reg_29_map, reg_31_map, reg_m16_map, reg32r_map): New
  13         static arrays.
  14         (decode_mips16_operand): New function.
  15         * mips-dis.c (mips16_to_32_reg_map, mips16_reg_names): Delete.
  16         (print_insn_arg): Handle OP_ENTRY_EXIT list.
  17         Abort for OP_SAVE_RESTORE_LIST.
  18         (print_mips16_insn_arg): Change interface.  Use mips_operand
  19         structures.  Delete GET_OP_S.  Move GET_OP definition to...
  20         (print_insn_mips16): ...here.  Call init_print_arg_state.
  21         Update the call to print_mips16_insn_arg.
  22
  23 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
  24
  25         * mips-formats.h: New file.
  26         * mips-opc.c: Include mips-formats.h.
  27         (reg_0_map): New static array.
  28         (decode_mips_operand): New function.
  29         * micromips-opc.c: Remove <stdio.h> include.  Include mips-formats.h.
  30         (reg_0_map, reg_28_map, reg_29_map, reg_31_map, reg_m16_map)
  31         (reg_mn_map, reg_q_map, reg_h_map1, reg_h_map2, int_b_map)
  32         (int_c_map): New static arrays.
  33         (decode_micromips_operand): New function.
  34         * mips-dis.c (micromips_to_32_reg_b_map, micromips_to_32_reg_c_map)
  35         (micromips_to_32_reg_d_map, micromips_to_32_reg_e_map)
  36         (micromips_to_32_reg_f_map, micromips_to_32_reg_g_map)
  37         (micromips_to_32_reg_h_map1, micromips_to_32_reg_h_map2)
  38         (micromips_to_32_reg_l_map, micromips_to_32_reg_m_map)
  39         (micromips_to_32_reg_n_map, micromips_to_32_reg_q_map)
  40         (micromips_imm_b_map, micromips_imm_c_map): Delete.
  41         (print_reg): New function.
  42         (mips_print_arg_state): New structure.
  43         (init_print_arg_state, print_insn_arg): New functions.
  44         (print_insn_args): Change interface and use mips_operand structures.
  45         Delete GET_OP_S.  Move GET_OP definition to...
  46         (print_insn_mips): ...here.  Update the call to print_insn_args.
  47         (print_insn_micromips): Use print_insn_args.
  48
  49 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
  50
  51         * mips16-opc.c (mips16_opcodes): Use "I" for immediate operands
  52         in macros.
  53
  54 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
  55
  56         * mips-opc.c (mips_builtin_opcodes): Use "S,T" rather than "V,T" for
  57         ADDA.S, MULA.S and SUBA.S.
  58
  59 2013-07-08  H.J. Lu  <hongjiu.lu@intel.com>
  60
  61         PR gas/13572
  62         * i386-opc.tbl: Replace Xmmword with Qword on cvttps2pi.
  63         * i386-tbl.h: Regenerated.
  64
  65 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
  66
  67         * mips-opc.c (mips_builtin_opcodes): Remove o(b) macros.  Move LD
  68         and SD A(B) macros up.
  69         * micromips-opc.c (micromips_opcodes): Likewise.
  70
  71 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
  72
  73         * mips16-opc.c: Add entries for argumentless "entry" and "exit"
  74         instructions.
  75
  76 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
  77
  78         * mips-opc.c (mips_builtin_opcodes): Use "Q" for the INSN_5400
  79         MDMX-like instructions.
  80         * mips-dis.c (print_insn_arg): Use "$f" rather than "$v" when
  81         printing "Q" operands for INSN_5400 instructions.
  82
  83 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
  84
  85         * mips-opc.c (mips_builtin_opcodes): Use "+s" for "cins32" and
  86         "+S" for "cins".
  87         * mips-dis.c (print_mips_arg): Update "+s" and "+S" comments.
  88         Combine cases.
  89
  90 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
  91
  92         * mips-opc.c (mips_builtin_opcodes): Use "+i" rather than "a" for
  93         "jalx".
  94         * mips16-opc.c (mips16_opcodes): Likewise.
  95         * micromips-opc.c (micromips_opcodes): Likewise.
  96         * mips-dis.c (print_insn_args, print_mips16_insn_arg)
  97         (print_insn_mips16): Handle "+i".
  98         (print_insn_micromips): Likewise.  Conditionally preserve the
  99         ISA bit for "a" but not for "+i".
 100
 101 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 102
 103         * micromips-opc.c (WR_mhi): Rename to..
 104         (WR_mh): ...this.
 105         (micromips_opcodes): Update "movep" entry accordingly.  Replace
 106         "mh,mi" with "mh".
 107         * mips-dis.c (micromips_to_32_reg_h_map): Rename to...
 108         (micromips_to_32_reg_h_map1): ...this.
 109         (micromips_to_32_reg_i_map): Rename to...
 110         (micromips_to_32_reg_h_map2): ...this.
 111         (print_micromips_insn): Remove "mi" case.  Print both registers
 112         in the pair for "mh".
 113
 114 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 115
 116         * mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries.
 117         * micromips-opc.c (micromips_opcodes): Likewise.
 118         * mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D"
 119         and "+T" handling.  Check for a "0" suffix when deciding whether to
 120         use coprocessor 0 names.  In that case, also check for ",H" selectors.
 121
 122 2013-07-05  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 123
 124         * s390-opc.c (J12_12, J24_24): New macros.
 125         (INSTR_MII_UPI): Rename to INSTR_MII_UPP.
 126         (MASK_MII_UPI): Rename to MASK_MII_UPP.
 127         * s390-opc.txt: Rename MII_UPI to MII_UPP for bprp instruction.
 128
 129 2013-07-04  Alan Modra  <amodra@gmail.com>
 130
 131         * ppc-opc.c (powerpc_opcodes): Add tdui, twui, tdu, twu, tui, tu.
 132
 133 2013-06-26  Nick Clifton  <nickc@redhat.com>
 134
 135         * rx-decode.opc (rx_decode_opcode): Check sd field as well as ss
 136         field when checking for type 2 nop.
 137         * rx-decode.c: Regenerate.
 138
 139 2013-06-25  Maciej W. Rozycki  <macro@codesourcery.com>
 140
 141         * micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc"
 142         and "movep" macros.
 143
 144 2013-06-24  Maciej W. Rozycki  <macro@codesourcery.com>
 145
 146         * mips-dis.c (is_mips16_plt_tail): New function.
 147         (print_insn_mips16): Handle MIPS16 PLT entry's GOT slot address
 148         word.
 149         (is_compressed_mode_p): Handle MIPS16/microMIPS PLT entries.
 150
 151 2013-06-21  DJ Delorie  <dj@redhat.com>
 152
 153         * msp430-decode.opc: New.
 154         * msp430-decode.c: New/generated.
 155         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add msp430-decode.c.
 156         (MAINTAINER_CLEANFILES): Likewise.
 157         Add rule to build msp430-decode.c frommsp430decode.opc
 158         using the opc2c program.
 159         * Makefile.in: Regenerate.
 160         * configure.in: Add msp430-decode.lo to msp430 architecture files.
 161         * configure: Regenerate.
 162
 163 2013-06-20  Yufeng Zhang  <yufeng.zhang@arm.com>
 164
 165         * aarch64-dis.c (EMBEDDED_ENV): Remove the check on it.
 166         (SYMTAB_AVAILABLE): Removed.
 167         (#include "elf/aarch64.h): Ditto.
 168
 169 2013-06-17  Catherine Moore  <clm@codesourcery.com>
 170             Maciej W. Rozycki  <macro@codesourcery.com>
 171             Chao-Ying Fu  <fu@mips.com>
 172
 173         * micromips-opc.c (EVA): Define.
 174         (TLBINV): Define.
 175         (micromips_opcodes): Add EVA opcodes.
 176         * mips-dis.c (mips_arch_choices): Update for ASE_EVA.
 177         (print_insn_args): Handle EVA offsets.
 178         (print_insn_micromips): Likewise.
 179         * mips-opc.c (EVA): Define.
 180         (TLBINV): Define.
 181         (mips_builtin_opcodes): Add EVA opcodes.
 182
 183 2013-06-17  Alan Modra  <amodra@gmail.com>
 184
 185         * Makefile.am (mips-opc.lo): Add rules to create automatic
 186         dependency files.  Pass archdefs.
 187         (micromips-opc.lo, mips16-opc.lo): Likewise.
 188         * Makefile.in: Regenerate.
 189
 190 2013-06-14  DJ Delorie  <dj@redhat.com>
 191
 192         * rx-decode.opc (rx_decode_opcode): Bit operations on
 193         registers are 32-bit operations, not 8-bit operations.
 194         * rx-decode.c: Regenerate.
 195
 196 2013-06-13  Chao-ying Fu  <Chao-ying.Fu@imgtec.com>
 197
 198         * micromips-opc.c (IVIRT): New define.
 199         (IVIRT64): New define.
 200         (micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
 201         tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions.
 202
 203         * mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0,
 204         dmtgc0 to print cp0 names.
 205
 206 2013-06-09  Sandra Loosemore  <sandra@codesourcery.com>
 207
 208         * nios2-opc.c (nios2_builtin_opcodes): Give "trap" a type-"b"
 209         argument.
 210
 211 2013-06-08  Catherine Moore  <clm@codesourcery.com>
 212             Richard Sandiford  <rdsandiford@googlemail.com>
 213
 214         * micromips-opc.c (D32, D33, MC): Update definitions.
 215         (micromips_opcodes):  Initialize ase field.
 216         * mips-dis.c (mips_arch_choice): Add ase field.
 217         (mips_arch_choices): Initialize ase field.
 218         (set_default_mips_dis_options): Declare and setup mips_ase.
 219         * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
 220         MT32, MC): Update definitions.
 221         (mips_builtin_opcodes): Initialize ase field.
 222
 223 2013-05-24  Richard Sandiford  <rsandifo@linux.vnet.ibm.com>
 224
 225         * s390-opc.txt (flogr): Require a register pair destination.
 226
 227 2013-05-23  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 228
 229         * s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU
 230         instruction format.
 231
 232 2013-05-22  Jürgen Urban  <JuergenUrban@gmx.de>
 233
 234         * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
 235
 236 2013-05-20  Peter Bergner <bergner@vnet.ibm.com>
 237
 238         * ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
 239         * ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
 240         XLS_MASK, PPCVSX2): New defines.
 241         (powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
 242         fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
 243         mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
 244         mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
 245         mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
 246         vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
 247         vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
 248         vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
 249         vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
 250         vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
 251         vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
 252         vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
 253         vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
 254         vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
 255         xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
 256         xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
 257         xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
 258         xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
 259         <lxvx, stxvx>: New extended mnemonics.
 260
 261 2013-05-17  Alan Modra  <amodra@gmail.com>
 262
 263         * ia64-raw.tbl: Replace non-ASCII char.
 264         * ia64-waw.tbl: Likewise.
 265         * ia64-asmtab.c: Regenerate.
 266
 267 2013-05-15  Saravanan Ekanathan <saravanan.ekanathan@amd.com>
 268
 269         * i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
 270         * i386-init.h: Regenerated.
 271
 272 2013-05-13  Yufeng Zhang  <yufeng.zhang@arm.com>
 273
 274         * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
 275         * aarch64-opc.c (operand_general_constraint_met_p): Relax the range
 276         check from [0, 255] to [-128, 255].
 277
 278 2013-05-09  Andrew Pinski  <apinski@cavium.com>
 279
 280         * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
 281         Add INSN_VIRT and INSN_VIRT64 to mips64r2.
 282         (parse_mips_dis_option): Handle the virt option.
 283         (print_insn_args): Handle "+J".
 284         (print_mips_disassembler_options): Print out message about virt64.
 285         * mips-opc.c (IVIRT): New define.
 286         (IVIRT64): New define.
 287         (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
 288         tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
 289         Move rfe to the bottom as it conflicts with tlbgp.
 290
 291 2013-05-09  Alan Modra  <amodra@gmail.com>
 292
 293         * ppc-opc.c (extract_vlesi): Properly sign extend.
 294         (extract_vlensi): Likewise.  Comment reason for setting invalid.
 295
 296 2013-05-02  Nick Clifton  <nickc@redhat.com>
 297
 298         * msp430-dis.c: Add support for MSP430X instructions.
 299
 300 2013-04-24  Sandra Loosemore  <sandra@codesourcery.com>
 301
 302         * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
 303         to "eccinj".
 304
 305 2013-04-17  Wei-chen Wang  <cole945@gmail.com>
 306
 307         PR binutils/15369
 308         * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
 309         of CGEN_CPU_ENDIAN.
 310         (hash_insns_list): Likewise.
 311
 312 2013-04-10  Jan Kratochvil  <jan.kratochvil@redhat.com>
 313
 314         * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
 315         warning workaround.
 316
 317 2013-04-08  Jan Beulich <jbeulich@suse.com>
 318
 319         * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
 320         * i386-tbl.h: Re-generate.
 321
 322 2013-04-06  David S. Miller  <davem@davemloft.net>
 323
 324         * sparc-dis.c (compare_opcodes): When encountering multiple aliases
 325         of an opcode, prefer the one with F_PREFERRED set.
 326         * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
 327         lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
 328         ops.  Make 64-bit VIS logical ops have "d" suffix in their names,
 329         mark existing mnenomics as aliases.  Add "cc" suffix to edge
 330         instructions generating condition codes, mark existing mnenomics
 331         as aliases.  Add "fp" prefix to VIS compare instructions, mark
 332         existing mnenomics as aliases.
 333
 334 2013-04-03  Nick Clifton  <nickc@redhat.com>
 335
 336         * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
 337         destination address by subtracting the operand from the current
 338         address.
 339         * v850-opc.c (insert_u16_loop): Disallow negative offsets.  Store
 340         a positive value in the insn.
 341         (extract_u16_loop): Do not negate the returned value.
 342         (D16_LOOP): Add V850_INVERSE_PCREL flag.
 343
 344         (ceilf.sw): Remove duplicate entry.
 345         (cvtf.hs): New entry.
 346         (cvtf.sh): Likewise.
 347         (fmaf.s): Likewise.
 348         (fmsf.s): Likewise.
 349         (fnmaf.s): Likewise.
 350         (fnmsf.s): Likewise.
 351         (maddf.s): Restrict to E3V5 architectures.
 352         (msubf.s): Likewise.
 353         (nmaddf.s): Likewise.
 354         (nmsubf.s): Likewise.
 355
 356 2013-03-27  H.J. Lu  <hongjiu.lu@intel.com>
 357
 358         * i386-dis.c (get_sib): Add the sizeflag argument.  Properly
 359         check address mode.
 360         (print_insn): Pass sizeflag to get_sib.
 361
 362 2013-03-27  Alexis Deruelle  <alexis.deruelle@gmail.com>
 363
 364         PR binutils/15068
 365         * tic6x-dis.c: Add support for displaying 16-bit insns.
 366
 367 2013-03-20  Alexis Deruelle  <alexis.deruelle@gmail.com>
 368
 369         PR gas/15095
 370         * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
 371         individual msb and lsb halves in src1 & src2 fields.  Discard the
 372         src1 (lsb) value and only use src2 (msb), discarding bit 0, to
 373         follow what Ti SDK does in that case as any value in the src1
 374         field yields the same output with SDK disassembler.
 375
 376 2013-03-12  Michael Eager <eager@eagercon.com>
 377
 378         * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
 379
 380 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
 381
 382         * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
 383
 384 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
 385
 386         * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
 387
 388 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
 389
 390         * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
 391
 392 2013-03-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 393
 394         * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
 395         (thumb32_opcodes): Likewise.
 396         (print_insn_thumb32): Handle 'S' control char.
 397
 398 2013-03-08  Yann Sionneau  <yann.sionneau@gmail.com>
 399
 400         * lm32-desc.c: Regenerate.
 401
 402 2013-03-01  H.J. Lu  <hongjiu.lu@intel.com>
 403
 404         * i386-reg.tbl (riz): Add RegRex64.
 405         * i386-tbl.h: Regenerated.
 406
 407 2013-02-28  Yufeng Zhang  <yufeng.zhang@arm.com>
 408
 409         * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
 410         (aarch64_feature_crc): New static.
 411         (CRC): New macro.
 412         (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
 413         crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
 414         * aarch64-asm-2.c: Re-generate.
 415         * aarch64-dis-2.c: Ditto.
 416         * aarch64-opc-2.c: Ditto.
 417
 418 2013-02-27  Alan Modra  <amodra@gmail.com>
 419
 420         * rl78-decode.opc (rl78_decode_opcode): Fix typo.
 421         * rl78-decode.c: Regenerate.
 422
 423 2013-02-25  Kaushik Phatak  <Kaushik.Phatak@kpitcummins.com>
 424
 425         * rl78-decode.opc: Fix encoding of DIVWU insn.
 426         * rl78-decode.c: Regenerate.
 427
 428 2013-02-19  H.J. Lu  <hongjiu.lu@intel.com>
 429
 430         PR gas/15159
 431         * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
 432
 433         * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
 434         (cpu_flags): Add CpuSMAP.
 435
 436         * i386-opc.h (CpuSMAP): New.
 437         (i386_cpu_flags): Add cpusmap.
 438
 439         * i386-opc.tbl: Add clac and stac.
 440
 441         * i386-init.h: Regenerated.
 442         * i386-tbl.h: Likewise.
 443
 444 2013-02-15  Markos Chandras  <markos.chandras@imgtec.com>
 445
 446         * metag-dis.c: Initialize outf->bytes_per_chunk to 4
 447         which also makes the disassembler output be in little
 448         endian like it should be.
 449
 450 2013-02-14  Yufeng Zhang  <yufeng.zhang@arm.com>
 451
 452         * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
 453         fields to NULL.
 454         (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
 455
 456 2013-02-13  Maciej W. Rozycki  <macro@codesourcery.com>
 457
 458         * mips-dis.c (is_compressed_mode_p): Only match symbols from the
 459         section disassembled.
 460
 461 2013-02-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 462
 463         * arm-dis.c: Update strht pattern.
 464
 465 2013-02-09  Jürgen Urban  <JuergenUrban@gmx.de>
 466
 467         * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
 468         single-float.  Disable ll, lld, sc and scd for EE.  Disable the
 469         trunc.w.s macro for EE.
 470
 471 2013-02-06  Sandra Loosemore  <sandra@codesourcery.com>
 472             Andrew Jenner <andrew@codesourcery.com>
 473
 474         Based on patches from Altera Corporation.
 475
 476         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
 477         nios2-opc.c.
 478         * Makefile.in: Regenerated.
 479         * configure.in: Add case for bfd_nios2_arch.
 480         * configure: Regenerated.
 481         * disassemble.c (ARCH_nios2): Define.
 482         (disassembler): Add case for bfd_arch_nios2.
 483         * nios2-dis.c: New file.
 484         * nios2-opc.c: New file.
 485
 486 2013-02-04  Alan Modra  <amodra@gmail.com>
 487
 488         * po/POTFILES.in: Regenerate.
 489         * rl78-decode.c: Regenerate.
 490         * rx-decode.c: Regenerate.
 491
 492 2013-01-30  Yufeng Zhang  <yufeng.zhang@arm.com>
 493
 494         * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
 495         ushll2 with F_HAS_ALIAS.  Add entries for sxtl, sxtl2, uxtl and uxtl2.
 496         * aarch64-asm.c (convert_xtl_to_shll): New function.
 497         (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
 498         calling convert_xtl_to_shll.
 499         * aarch64-dis.c (convert_shll_to_xtl): New function.
 500         (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
 501         calling convert_shll_to_xtl.
 502         * aarch64-gen.c: Update copyright year.
 503         * aarch64-asm-2.c: Re-generate.
 504         * aarch64-dis-2.c: Re-generate.
 505         * aarch64-opc-2.c: Re-generate.
 506
 507 2013-01-24  Nick Clifton  <nickc@redhat.com>
 508
 509         * v850-dis.c: Add support for e3v5 architecture.
 510         * v850-opc.c: Likewise.
 511
 512 2013-01-17  Yufeng Zhang  <yufeng.zhang@arm.com>
 513
 514         * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
 515         * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
 516         * aarch64-opc.c (operand_general_constraint_met_p): For
 517         AARCH64_MOD_LSL, move the range check on the shift amount before the
 518         alignment check; change to call set_sft_amount_out_of_range_error
 519         instead of set_imm_out_of_range_error.
 520         * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
 521         (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
 522         8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
 523         SIMD_IMM_SFT.
 524
 525 2013-01-16  H.J. Lu  <hongjiu.lu@intel.com>
 526
 527         * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
 528
 529         * i386-init.h: Regenerated.
 530         * i386-tbl.h: Likewise.
 531
 532 2013-01-15  Nick Clifton  <nickc@redhat.com>
 533
 534         * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
 535         values.
 536         * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
 537
 538 2013-01-14  Will Newton <will.newton@imgtec.com>
 539
 540         * metag-dis.c (REG_WIDTH): Increase to 64.
 541
 542 2013-01-10  Peter Bergner <bergner@vnet.ibm.com>
 543
 544         * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
 545         * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
 546         XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
 547         (SH6): Update.
 548         <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
 549         "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
 550         "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
 551         <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
 552
 553 2013-01-10  Will Newton <will.newton@imgtec.com>
 554
 555         * Makefile.am: Add Meta.
 556         * configure.in: Add Meta.
 557         * disassemble.c: Add Meta support.
 558         * metag-dis.c: New file.
 559         * Makefile.in: Regenerate.
 560         * configure: Regenerate.
 561
 562 2013-01-07  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
 563
 564         * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
 565         (match_opcode): Rename to cr16_match_opcode.
 566
 567 2013-01-04  Juergen Urban <JuergenUrban@gmx.de>
 568
 569         * mips-dis.c: Add names for CP0 registers of r5900.
 570         * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
 571         instructions sq and lq.
 572         Add support for MIPS r5900 CPU.
 573         Add support for 128 bit MMI (Multimedia Instructions).
 574         Add support for EE instructions (Emotion Engine).
 575         Disable unsupported floating point instructions (64 bit and
 576         undefined compare operations).
 577         Enable instructions of MIPS ISA IV which are supported by r5900.
 578         Disable 64 bit co processor instructions.
 579         Disable 64 bit multiplication and division instructions.
 580         Disable instructions for co-processor 2 and 3, because these are
 581         not supported (preparation for later VU0 support (Vector Unit)).
 582         Disable cvt.w.s because this behaves like trunc.w.s and the
 583         correct execution can't be ensured on r5900.
 584         Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
 585         will confuse less developers and compilers.
 586
 587 2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>
 588
 589         * aarch64-opc.c (aarch64_print_operand): Change to print
 590         AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
 591         in comment.
 592         * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
 593         from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
 594         OP_MOV_IMM_WIDE.
 595
 596 2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>
 597
 598         * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
 599         PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
 600
 601 2013-01-02  H.J. Lu  <hongjiu.lu@intel.com>
 602
 603         * i386-gen.c (process_copyright): Update copyright year to 2013.
 604
 605 2013-01-02  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
 606
 607         * cr16-dis.c (match_opcode,make_instruction): Remove static
 608         declaration.
 609         (dwordU,wordU): Moved typedefs to opcode/cr16.h
 610         (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
 611
 612 For older changes see ChangeLog-2012
 613 \f
 614 Copyright (C) 2013 Free Software Foundation, Inc.
 615
 616 Copying and distribution of this file, with or without modification,
 617 are permitted in any medium without royalty provided the copyright
 618 notice and this notice are preserved.
 619
 620 Local Variables:
 621 mode: change-log
 622 left-margin: 8
 623 fill-column: 74
 624 version-control: never
 625 End: