opcodes/ChangeLog

   1 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
   2
   3         * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
   4         and VMSR with the new operands.
   5
   6 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
   7
   8         * arm-dis.c (enum mve_instructions): New enum
   9         for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
  10         and cneg.
  11         (mve_opcodes): New instructions as above.
  12         (is_mve_encoding_conflict): Add cases for csinc, csinv,
  13         csneg and csel.
  14         (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
  15
  16 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
  17
  18         * arm-dis.c (emun mve_instructions): Updated for new instructions.
  19         (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
  20         sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
  21         uqshl, urshrl and urshr.
  22         (is_mve_okay_in_it): Add new instructions to TRUE list.
  23         (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
  24         (print_insn_mve): Updated to accept new %j,
  25         %<bitfield>m and %<bitfield>n patterns.
  26
  27 2019-05-21  Faraz Shahbazker  <fshahbazker@wavecomp.com>
  28
  29         * mips-opc.c (mips_builtin_opcodes): Change source register
  30         constraint for DAUI.
  31
  32 2019-05-20  Nick Clifton  <nickc@redhat.com>
  33
  34         * po/fr.po: Updated French translation.
  35
  36 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  37             Michael Collison <michael.collison@arm.com>
  38
  39         * arm-dis.c (thumb32_opcodes): Add new instructions.
  40         (enum mve_instructions): Likewise.
  41         (enum mve_undefined): Add new reasons.
  42         (is_mve_encoding_conflict): Handle new instructions.
  43         (is_mve_undefined): Likewise.
  44         (is_mve_unpredictable): Likewise.
  45         (print_mve_undefined): Likewise.
  46         (print_mve_size): Likewise.
  47
  48 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  49             Michael Collison <michael.collison@arm.com>
  50
  51         * arm-dis.c (thumb32_opcodes): Add new instructions.
  52         (enum mve_instructions): Likewise.
  53         (is_mve_encoding_conflict): Handle new instructions.
  54         (is_mve_undefined): Likewise.
  55         (is_mve_unpredictable): Likewise.
  56         (print_mve_size): Likewise.
  57
  58 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  59             Michael Collison <michael.collison@arm.com>
  60
  61         * arm-dis.c (thumb32_opcodes): Add new instructions.
  62         (enum mve_instructions): Likewise.
  63         (is_mve_encoding_conflict): Likewise.
  64         (is_mve_unpredictable): Likewise.
  65         (print_mve_size): Likewise.
  66
  67 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  68             Michael Collison <michael.collison@arm.com>
  69
  70         * arm-dis.c (thumb32_opcodes): Add new instructions.
  71         (enum mve_instructions): Likewise.
  72         (is_mve_encoding_conflict): Handle new instructions.
  73         (is_mve_undefined): Likewise.
  74         (is_mve_unpredictable): Likewise.
  75         (print_mve_size): Likewise.
  76
  77 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  78             Michael Collison <michael.collison@arm.com>
  79
  80         * arm-dis.c (thumb32_opcodes): Add new instructions.
  81         (enum mve_instructions): Likewise.
  82         (is_mve_encoding_conflict): Handle new instructions.
  83         (is_mve_undefined): Likewise.
  84         (is_mve_unpredictable): Likewise.
  85         (print_mve_size): Likewise.
  86         (print_insn_mve): Likewise.
  87
  88 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  89             Michael Collison <michael.collison@arm.com>
  90
  91         * arm-dis.c (thumb32_opcodes): Add new instructions.
  92         (print_insn_thumb32): Handle new instructions.
  93
  94 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  95             Michael Collison <michael.collison@arm.com>
  96
  97         * arm-dis.c (enum mve_instructions): Add new instructions.
  98         (enum mve_undefined): Add new reasons.
  99         (is_mve_encoding_conflict): Handle new instructions.
 100         (is_mve_undefined): Likewise.
 101         (is_mve_unpredictable): Likewise.
 102         (print_mve_undefined): Likewise.
 103         (print_mve_size): Likewise.
 104         (print_mve_shift_n): Likewise.
 105         (print_insn_mve): Likewise.
 106
 107 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 108             Michael Collison <michael.collison@arm.com>
 109
 110         * arm-dis.c (enum mve_instructions): Add new instructions.
 111         (is_mve_encoding_conflict): Handle new instructions.
 112         (is_mve_unpredictable): Likewise.
 113         (print_mve_rotate): Likewise.
 114         (print_mve_size): Likewise.
 115         (print_insn_mve): Likewise.
 116
 117 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 118             Michael Collison <michael.collison@arm.com>
 119
 120         * arm-dis.c (enum mve_instructions): Add new instructions.
 121         (is_mve_encoding_conflict): Handle new instructions.
 122         (is_mve_unpredictable): Likewise.
 123         (print_mve_size): Likewise.
 124         (print_insn_mve): Likewise.
 125
 126 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 127             Michael Collison <michael.collison@arm.com>
 128
 129         * arm-dis.c (enum mve_instructions): Add new instructions.
 130         (enum mve_undefined): Add new reasons.
 131         (is_mve_encoding_conflict): Handle new instructions.
 132         (is_mve_undefined): Likewise.
 133         (is_mve_unpredictable): Likewise.
 134         (print_mve_undefined): Likewise.
 135         (print_mve_size): Likewise.
 136         (print_insn_mve): Likewise.
 137
 138 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 139             Michael Collison <michael.collison@arm.com>
 140
 141         * arm-dis.c (enum mve_instructions): Add new instructions.
 142         (is_mve_encoding_conflict): Handle new instructions.
 143         (is_mve_undefined): Likewise.
 144         (is_mve_unpredictable): Likewise.
 145         (print_mve_size): Likewise.
 146         (print_insn_mve): Likewise.
 147
 148 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 149             Michael Collison <michael.collison@arm.com>
 150
 151         * arm-dis.c (enum mve_instructions): Add new instructions.
 152         (enum mve_unpredictable): Add new reasons.
 153         (enum mve_undefined): Likewise.
 154         (is_mve_okay_in_it): Handle new isntructions.
 155         (is_mve_encoding_conflict): Likewise.
 156         (is_mve_undefined): Likewise.
 157         (is_mve_unpredictable): Likewise.
 158         (print_mve_vmov_index): Likewise.
 159         (print_simd_imm8): Likewise.
 160         (print_mve_undefined): Likewise.
 161         (print_mve_unpredictable): Likewise.
 162         (print_mve_size): Likewise.
 163         (print_insn_mve): Likewise.
 164
 165 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 166             Michael Collison <michael.collison@arm.com>
 167
 168         * arm-dis.c (enum mve_instructions): Add new instructions.
 169         (enum mve_unpredictable): Add new reasons.
 170         (enum mve_undefined): Likewise.
 171         (is_mve_encoding_conflict): Handle new instructions.
 172         (is_mve_undefined): Likewise.
 173         (is_mve_unpredictable): Likewise.
 174         (print_mve_undefined): Likewise.
 175         (print_mve_unpredictable): Likewise.
 176         (print_mve_rounding_mode): Likewise.
 177         (print_mve_vcvt_size): Likewise.
 178         (print_mve_size): Likewise.
 179         (print_insn_mve): Likewise.
 180
 181 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 182             Michael Collison <michael.collison@arm.com>
 183
 184         * arm-dis.c (enum mve_instructions): Add new instructions.
 185         (enum mve_unpredictable): Add new reasons.
 186         (enum mve_undefined): Likewise.
 187         (is_mve_undefined): Handle new instructions.
 188         (is_mve_unpredictable): Likewise.
 189         (print_mve_undefined): Likewise.
 190         (print_mve_unpredictable): Likewise.
 191         (print_mve_size): Likewise.
 192         (print_insn_mve): Likewise.
 193
 194 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 195             Michael Collison <michael.collison@arm.com>
 196
 197         * arm-dis.c (enum mve_instructions): Add new instructions.
 198         (enum mve_undefined): Add new reasons.
 199         (insns): Add new instructions.
 200         (is_mve_encoding_conflict):
 201         (print_mve_vld_str_addr): New print function.
 202         (is_mve_undefined): Handle new instructions.
 203         (is_mve_unpredictable): Likewise.
 204         (print_mve_undefined): Likewise.
 205         (print_mve_size): Likewise.
 206         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
 207         (print_insn_mve):  Handle new operands.
 208
 209 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 210             Michael Collison <michael.collison@arm.com>
 211
 212         * arm-dis.c (enum mve_instructions): Add new instructions.
 213         (enum mve_unpredictable): Add new reasons.
 214         (is_mve_encoding_conflict): Handle new instructions.
 215         (is_mve_unpredictable): Likewise.
 216         (mve_opcodes): Add new instructions.
 217         (print_mve_unpredictable): Handle new reasons.
 218         (print_mve_register_blocks): New print function.
 219         (print_mve_size): Handle new instructions.
 220         (print_insn_mve): Likewise.
 221
 222 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 223             Michael Collison <michael.collison@arm.com>
 224
 225         * arm-dis.c (enum mve_instructions): Add new instructions.
 226         (enum mve_unpredictable): Add new reasons.
 227         (enum mve_undefined): Likewise.
 228         (is_mve_encoding_conflict): Handle new instructions.
 229         (is_mve_undefined): Likewise.
 230         (is_mve_unpredictable): Likewise.
 231         (coprocessor_opcodes): Move NEON VDUP from here...
 232         (neon_opcodes): ... to here.
 233         (mve_opcodes): Add new instructions.
 234         (print_mve_undefined):  Handle new reasons.
 235         (print_mve_unpredictable): Likewise.
 236         (print_mve_size): Handle new instructions.
 237         (print_insn_neon): Handle vdup.
 238         (print_insn_mve): Handle new operands.
 239
 240 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 241             Michael Collison <michael.collison@arm.com>
 242
 243         * arm-dis.c (enum mve_instructions): Add new instructions.
 244         (enum mve_unpredictable): Add new values.
 245         (mve_opcodes): Add new instructions.
 246         (vec_condnames): New array with vector conditions.
 247         (mve_predicatenames): New array with predicate suffixes.
 248         (mve_vec_sizename): New array with vector sizes.
 249         (enum vpt_pred_state): New enum with vector predication states.
 250         (struct vpt_block): New struct type for vpt blocks.
 251         (vpt_block_state): Global struct to keep track of state.
 252         (mve_extract_pred_mask): New helper function.
 253         (num_instructions_vpt_block): Likewise.
 254         (mark_outside_vpt_block): Likewise.
 255         (mark_inside_vpt_block): Likewise.
 256         (invert_next_predicate_state): Likewise.
 257         (update_next_predicate_state): Likewise.
 258         (update_vpt_block_state): Likewise.
 259         (is_vpt_instruction): Likewise.
 260         (is_mve_encoding_conflict): Add entries for new instructions.
 261         (is_mve_unpredictable): Likewise.
 262         (print_mve_unpredictable): Handle new cases.
 263         (print_instruction_predicate): Likewise.
 264         (print_mve_size): New function.
 265         (print_vec_condition): New function.
 266         (print_insn_mve): Handle vpt blocks and new print operands.
 267
 268 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 269
 270         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
 271         8, 14 and 15 for Armv8.1-M Mainline.
 272
 273 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 274             Michael Collison <michael.collison@arm.com>
 275
 276         * arm-dis.c (enum mve_instructions): New enum.
 277         (enum mve_unpredictable): Likewise.
 278         (enum mve_undefined): Likewise.
 279         (struct mopcode32): New struct.
 280         (is_mve_okay_in_it): New function.
 281         (is_mve_architecture): Likewise.
 282         (arm_decode_field): Likewise.
 283         (arm_decode_field_multiple): Likewise.
 284         (is_mve_encoding_conflict): Likewise.
 285         (is_mve_undefined): Likewise.
 286         (is_mve_unpredictable): Likewise.
 287         (print_mve_undefined): Likewise.
 288         (print_mve_unpredictable): Likewise.
 289         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
 290         (print_insn_mve): New function.
 291         (print_insn_thumb32): Handle MVE architecture.
 292         (select_arm_features): Force thumb for Armv8.1-m Mainline.
 293
 294 2019-05-10  Nick Clifton  <nickc@redhat.com>
 295
 296         PR 24538
 297         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
 298         end of the table prematurely.
 299
 300 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 301
 302         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
 303         macros for R6.
 304
 305 2019-05-11  Alan Modra  <amodra@gmail.com>
 306
 307         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
 308         when -Mraw is in effect.
 309
 310 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 311
 312         * aarch64-dis-2.c: Regenerate.
 313         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
 314         (OP_SVE_BBB): New variant set.
 315         (OP_SVE_DDDD): New variant set.
 316         (OP_SVE_HHH): New variant set.
 317         (OP_SVE_HHHU): New variant set.
 318         (OP_SVE_SSS): New variant set.
 319         (OP_SVE_SSSU): New variant set.
 320         (OP_SVE_SHH): New variant set.
 321         (OP_SVE_SBBU): New variant set.
 322         (OP_SVE_DSS): New variant set.
 323         (OP_SVE_DHHU): New variant set.
 324         (OP_SVE_VMV_HSD_BHS): New variant set.
 325         (OP_SVE_VVU_HSD_BHS): New variant set.
 326         (OP_SVE_VVVU_SD_BH): New variant set.
 327         (OP_SVE_VVVU_BHSD): New variant set.
 328         (OP_SVE_VVV_QHD_DBS): New variant set.
 329         (OP_SVE_VVV_HSD_BHS): New variant set.
 330         (OP_SVE_VVV_HSD_BHS2): New variant set.
 331         (OP_SVE_VVV_BHS_HSD): New variant set.
 332         (OP_SVE_VV_BHS_HSD): New variant set.
 333         (OP_SVE_VVV_SD): New variant set.
 334         (OP_SVE_VVU_BHS_HSD): New variant set.
 335         (OP_SVE_VZVV_SD): New variant set.
 336         (OP_SVE_VZVV_BH): New variant set.
 337         (OP_SVE_VZV_SD): New variant set.
 338         (aarch64_opcode_table): Add sve2 instructions.
 339
 340 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 341
 342         * aarch64-asm-2.c: Regenerated.
 343         * aarch64-dis-2.c: Regenerated.
 344         * aarch64-opc-2.c: Regenerated.
 345         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 346         for SVE_SHLIMM_UNPRED_22.
 347         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
 348         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
 349         operand.
 350
 351 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 352
 353         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 354         sve_size_tsz_bhs iclass encode.
 355         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 356         sve_size_tsz_bhs iclass decode.
 357
 358 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 359
 360         * aarch64-asm-2.c: Regenerated.
 361         * aarch64-dis-2.c: Regenerated.
 362         * aarch64-opc-2.c: Regenerated.
 363         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 364         for SVE_Zm4_11_INDEX.
 365         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
 366         (fields): Handle SVE_i2h field.
 367         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
 368         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
 369
 370 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 371
 372         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 373         sve_shift_tsz_bhsd iclass encode.
 374         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 375         sve_shift_tsz_bhsd iclass decode.
 376
 377 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 378
 379         * aarch64-asm-2.c: Regenerated.
 380         * aarch64-dis-2.c: Regenerated.
 381         * aarch64-opc-2.c: Regenerated.
 382         * aarch64-asm.c (aarch64_ins_sve_shrimm):
 383         (aarch64_encode_variant_using_iclass): Handle
 384         sve_shift_tsz_hsd iclass encode.
 385         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 386         sve_shift_tsz_hsd iclass decode.
 387         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 388         for SVE_SHRIMM_UNPRED_22.
 389         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
 390         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
 391         operand.
 392
 393 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 394
 395         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 396         sve_size_013 iclass encode.
 397         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 398         sve_size_013 iclass decode.
 399
 400 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 401
 402         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 403         sve_size_bh iclass encode.
 404         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 405         sve_size_bh iclass decode.
 406
 407 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 408
 409         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 410         sve_size_sd2 iclass encode.
 411         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 412         sve_size_sd2 iclass decode.
 413         * aarch64-opc.c (fields): Handle SVE_sz2 field.
 414         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
 415
 416 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 417
 418         * aarch64-asm-2.c: Regenerated.
 419         * aarch64-dis-2.c: Regenerated.
 420         * aarch64-opc-2.c: Regenerated.
 421         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 422         for SVE_ADDR_ZX.
 423         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
 424         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
 425
 426 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 427
 428         * aarch64-asm-2.c: Regenerated.
 429         * aarch64-dis-2.c: Regenerated.
 430         * aarch64-opc-2.c: Regenerated.
 431         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 432         for SVE_Zm3_11_INDEX.
 433         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
 434         (fields): Handle SVE_i3l and SVE_i3h2 fields.
 435         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
 436         fields.
 437         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
 438
 439 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 440
 441         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 442         sve_size_hsd2 iclass encode.
 443         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 444         sve_size_hsd2 iclass decode.
 445         * aarch64-opc.c (fields): Handle SVE_size field.
 446         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
 447
 448 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 449
 450         * aarch64-asm-2.c: Regenerated.
 451         * aarch64-dis-2.c: Regenerated.
 452         * aarch64-opc-2.c: Regenerated.
 453         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 454         for SVE_IMM_ROT3.
 455         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
 456         (fields): Handle SVE_rot3 field.
 457         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
 458         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
 459
 460 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 461
 462         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
 463         instructions.
 464
 465 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 466
 467         * aarch64-tbl.h
 468         (aarch64_feature_sve2, aarch64_feature_sve2aes,
 469         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
 470         aarch64_feature_sve2bitperm): New feature sets.
 471         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
 472         for feature set addresses.
 473         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
 474         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
 475
 476 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
 477             Faraz Shahbazker  <fshahbazker@wavecomp.com>
 478
 479         * mips-dis.c (mips_calculate_combination_ases): Add ISA
 480         argument and set ASE_EVA_R6 appropriately.
 481         (set_default_mips_dis_options): Pass ISA to above.
 482         (parse_mips_dis_option): Likewise.
 483         * mips-opc.c (EVAR6): New macro.
 484         (mips_builtin_opcodes): Add llwpe, scwpe.
 485
 486 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
 487
 488         * aarch64-asm-2.c: Regenerated.
 489         * aarch64-dis-2.c: Regenerated.
 490         * aarch64-opc-2.c: Regenerated.
 491         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
 492         AARCH64_OPND_TME_UIMM16.
 493         (aarch64_print_operand): Likewise.
 494         * aarch64-tbl.h (QL_IMM_NIL): New.
 495         (TME): New.
 496         (_TME_INSN): New.
 497         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
 498
 499 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
 500
 501         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
 502
 503 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
 504             Faraz Shahbazker  <fshahbazker@wavecomp.com>
 505
 506         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
 507
 508 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
 509
 510         * s12z-opc.h: Add extern "C" bracketing to help
 511         users who wish to use this interface in c++ code.
 512
 513 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
 514
 515         * s12z-opc.c (bm_decode): Handle bit map operations with the
 516         "reserved0" mode.
 517
 518 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 519
 520         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
 521         specifier.  Add entries for VLDR and VSTR of system registers.
 522         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
 523         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
 524         of %J and %K format specifier.
 525
 526 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 527
 528         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
 529         Add new entries for VSCCLRM instruction.
 530         (print_insn_coprocessor): Handle new %C format control code.
 531
 532 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 533
 534         * arm-dis.c (enum isa): New enum.
 535         (struct sopcode32): New structure.
 536         (coprocessor_opcodes): change type of entries to struct sopcode32 and
 537         set isa field of all current entries to ANY.
 538         (print_insn_coprocessor): Change type of insn to struct sopcode32.
 539         Only match an entry if its isa field allows the current mode.
 540
 541 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 542
 543         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
 544         CLRM.
 545         (print_insn_thumb32): Add logic to print %n CLRM register list.
 546
 547 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 548
 549         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
 550         and %Q patterns.
 551
 552 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 553
 554         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
 555         (print_insn_thumb32): Edit the switch case for %Z.
 556
 557 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 558
 559         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
 560
 561 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 562
 563         * arm-dis.c (thumb32_opcodes): New instruction bfl.
 564
 565 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 566
 567         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
 568
 569 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 570
 571         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
 572         Arm register with r13 and r15 unpredictable.
 573         (thumb32_opcodes): New instructions for bfx and bflx.
 574
 575 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 576
 577         * arm-dis.c (thumb32_opcodes): New instructions for bf.
 578
 579 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 580
 581         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
 582
 583 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 584
 585         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
 586
 587 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 588
 589         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
 590
 591 2019-04-12  John Darrington <john@darrington.wattle.id.au>
 592
 593         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
 594         "optr". ("operator" is a reserved word in c++).
 595
 596 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
 597
 598         * aarch64-opc.c (aarch64_print_operand): Add case for
 599         AARCH64_OPND_Rt_SP.
 600         (verify_constraints): Likewise.
 601         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
 602         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
 603         to accept Rt|SP as first operand.
 604         (AARCH64_OPERANDS): Add new Rt_SP.
 605         * aarch64-asm-2.c: Regenerated.
 606         * aarch64-dis-2.c: Regenerated.
 607         * aarch64-opc-2.c: Regenerated.
 608
 609 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
 610
 611         * aarch64-asm-2.c: Regenerated.
 612         * aarch64-dis-2.c: Likewise.
 613         * aarch64-opc-2.c: Likewise.
 614         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
 615
 616 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
 617
 618         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
 619
 620 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
 621
 622         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
 623         * i386-init.h: Regenerated.
 624
 625 2019-04-07  Alan Modra  <amodra@gmail.com>
 626
 627         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
 628         op_separator to control printing of spaces, comma and parens
 629         rather than need_comma, need_paren and spaces vars.
 630
 631 2019-04-07  Alan Modra  <amodra@gmail.com>
 632
 633         PR 24421
 634         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
 635         (print_insn_neon, print_insn_arm): Likewise.
 636
 637 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
 638
 639         * i386-dis-evex.h (evex_table): Updated to support BF16
 640         instructions.
 641         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
 642         and EVEX_W_0F3872_P_3.
 643         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
 644         (cpu_flags): Add bitfield for CpuAVX512_BF16.
 645         * i386-opc.h (enum): Add CpuAVX512_BF16.
 646         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
 647         * i386-opc.tbl: Add AVX512 BF16 instructions.
 648         * i386-init.h: Regenerated.
 649         * i386-tbl.h: Likewise.
 650
 651 2019-04-05  Alan Modra  <amodra@gmail.com>
 652
 653         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
 654         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
 655         to favour printing of "-" branch hint when using the "y" bit.
 656         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
 657
 658 2019-04-05  Alan Modra  <amodra@gmail.com>
 659
 660         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
 661         opcode until first operand is output.
 662
 663 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
 664
 665         PR gas/24349
 666         * ppc-opc.c (valid_bo_pre_v2): Add comments.
 667         (valid_bo_post_v2): Add support for 'at' branch hints.
 668         (insert_bo): Only error on branch on ctr.
 669         (get_bo_hint_mask): New function.
 670         (insert_boe): Add new 'branch_taken' formal argument.  Add support
 671         for inserting 'at' branch hints.
 672         (extract_boe): Add new 'branch_taken' formal argument.  Add support
 673         for extracting 'at' branch hints.
 674         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
 675         (BOE): Delete operand.
 676         (BOM, BOP): New operands.
 677         (RM): Update value.
 678         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
 679         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
 680         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
 681         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
 682         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
 683         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
 684         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
 685         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
 686         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
 687         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
 688         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
 689         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
 690         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
 691         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
 692         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
 693         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
 694         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
 695         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
 696         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
 697         bttarl+>: New extended mnemonics.
 698
 699 2019-03-28  Alan Modra  <amodra@gmail.com>
 700
 701         PR 24390
 702         * ppc-opc.c (BTF): Define.
 703         (powerpc_opcodes): Use for mtfsb*.
 704         * ppc-dis.c (print_insn_powerpc): Print fields with both
 705         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
 706
 707 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 708
 709         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
 710         (mapping_symbol_for_insn): Implement new algorithm.
 711         (print_insn): Remove duplicate code.
 712
 713 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 714
 715         * aarch64-dis.c (print_insn_aarch64):
 716         Implement override.
 717
 718 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 719
 720         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
 721         order.
 722
 723 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 724
 725         * aarch64-dis.c (last_stop_offset): New.
 726         (print_insn_aarch64): Use stop_offset.
 727
 728 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
 729
 730         PR gas/24359
 731         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
 732         CPU_ANY_AVX2_FLAGS.
 733         * i386-init.h: Regenerated.
 734
 735 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
 736
 737         PR gas/24348
 738         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
 739         vmovdqu16, vmovdqu32 and vmovdqu64.
 740         * i386-tbl.h: Regenerated.
 741
 742 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
 743
 744         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
 745         from vstrszb, vstrszh, and vstrszf.
 746
 747 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
 748
 749         * s390-opc.txt: Add instruction descriptions.
 750
 751 2019-02-08  Jim Wilson  <jimw@sifive.com>
 752
 753         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
 754         <bne>: Likewise.
 755
 756 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
 757
 758         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
 759
 760 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
 761
 762         PR binutils/23212
 763         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
 764         * aarch64-opc.c (verify_elem_sd): New.
 765         (fields): Add FLD_sz entr.
 766         * aarch64-tbl.h (_SIMD_INSN): New.
 767         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
 768         fmulx scalar and vector by element isns.
 769
 770 2019-02-07  Nick Clifton  <nickc@redhat.com>
 771
 772         * po/sv.po: Updated Swedish translation.
 773
 774 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
 775
 776         * s390-mkopc.c (main): Accept arch13 as cpu string.
 777         * s390-opc.c: Add new instruction formats and instruction opcode
 778         masks.
 779         * s390-opc.txt: Add new arch13 instructions.
 780
 781 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 782
 783         * aarch64-tbl.h (QL_LDST_AT): Update macro.
 784         (aarch64_opcode): Change encoding for stg, stzg
 785         st2g and st2zg.
 786         * aarch64-asm-2.c: Regenerated.
 787         * aarch64-dis-2.c: Regenerated.
 788         * aarch64-opc-2.c: Regenerated.
 789
 790 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 791
 792         * aarch64-asm-2.c: Regenerated.
 793         * aarch64-dis-2.c: Likewise.
 794         * aarch64-opc-2.c: Likewise.
 795         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
 796
 797 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 798             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
 799
 800         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
 801         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
 802         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
 803         * aarch64-dis.h (ext_addr_simple_2): Likewise.
 804         * aarch64-opc.c (operand_general_constraint_met_p): Remove
 805         case for ldstgv_indexed.
 806         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
 807         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
 808         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
 809         * aarch64-asm-2.c: Regenerated.
 810         * aarch64-dis-2.c: Regenerated.
 811         * aarch64-opc-2.c: Regenerated.
 812
 813 2019-01-23  Nick Clifton  <nickc@redhat.com>
 814
 815         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 816
 817 2019-01-21  Nick Clifton  <nickc@redhat.com>
 818
 819         * po/de.po: Updated German translation.
 820         * po/uk.po: Updated Ukranian translation.
 821
 822 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
 823         * mips-dis.c (mips_arch_choices): Fix typo in
 824         gs464, gs464e and gs264e descriptors.
 825
 826 2019-01-19  Nick Clifton  <nickc@redhat.com>
 827
 828         * configure: Regenerate.
 829         * po/opcodes.pot: Regenerate.
 830
 831 2018-06-24  Nick Clifton  <nickc@redhat.com>
 832
 833         2.32 branch created.
 834
 835 2019-01-09  John Darrington <john@darrington.wattle.id.au>
 836
 837         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
 838         if it is null.
 839         -dis.c (opr_emit_disassembly): Do not omit an index if it is
 840         zero.
 841
 842 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
 843
 844         * configure: Regenerate.
 845
 846 2019-01-07  Alan Modra  <amodra@gmail.com>
 847
 848         * configure: Regenerate.
 849         * po/POTFILES.in: Regenerate.
 850
 851 2019-01-03  John Darrington <john@darrington.wattle.id.au>
 852
 853         * s12z-opc.c: New file.
 854         * s12z-opc.h: New file.
 855         * s12z-dis.c: Removed all code not directly related to display
 856         of instructions.  Used the interface provided by the new files
 857         instead.
 858         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
 859         * Makefile.in: Regenerate.
 860         * configure.ac (bfd_s12z_arch): Correct the dependencies.
 861         * configure: Regenerate.
 862
 863 2019-01-01  Alan Modra  <amodra@gmail.com>
 864
 865         Update year range in copyright notice of all files.
 866
 867 For older changes see ChangeLog-2018
 868 \f
 869 Copyright (C) 2019 Free Software Foundation, Inc.
 870
 871 Copying and distribution of this file, with or without modification,
 872 are permitted in any medium without royalty provided the copyright
 873 notice and this notice are preserved.
 874
 875 Local Variables:
 876 mode: change-log
 877 left-margin: 8
 878 fill-column: 74
 879 version-control: never
 880 End: