1 2020-06-03 Nick Clifton <nickc@redhat.com>
3 * po/sr.po: Updated Serbian translation.
5 2020-06-03 Nelson Chu <nelson.chu@sifive.com>
7 * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
8 (riscv_get_priv_spec_class): Likewise.
10 2020-06-01 Alan Modra <amodra@gmail.com>
12 * bpf-desc.c: Regenerate.
14 2020-05-28 Jose E. Marchesi <jose.marchesi@oracle.com>
15 David Faust <david.faust@oracle.com>
17 * bpf-desc.c: Regenerate.
18 * bpf-opc.h: Likewise.
19 * bpf-opc.c: Likewise.
20 * bpf-dis.c: Likewise.
22 2020-05-28 Alan Modra <amodra@gmail.com>
24 * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
27 2020-05-28 Alan Modra <amodra@gmail.com>
29 * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
31 (print_insn_ns32k): Revert last change.
33 2020-05-28 Nick Clifton <nickc@redhat.com>
35 * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
38 2020-05-26 Sandra Loosemore <sandra@codesourcery.com>
40 Fix extraction of signed constants in nios2 disassembler (again).
42 * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
43 extractions of signed fields.
45 2020-05-26 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
47 * s390-opc.txt: Relocate vector load/store instructions with
48 additional alignment parameter and change architecture level
49 constraint from z14 to z13.
51 2020-05-21 Alan Modra <amodra@gmail.com>
53 * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
54 * sparc-dis.c: Likewise.
55 * tic4x-dis.c: Likewise.
56 * xtensa-dis.c: Likewise.
57 * bpf-desc.c: Regenerate.
58 * epiphany-desc.c: Regenerate.
59 * fr30-desc.c: Regenerate.
60 * frv-desc.c: Regenerate.
61 * ip2k-desc.c: Regenerate.
62 * iq2000-desc.c: Regenerate.
63 * lm32-desc.c: Regenerate.
64 * m32c-desc.c: Regenerate.
65 * m32r-desc.c: Regenerate.
66 * mep-asm.c: Regenerate.
67 * mep-desc.c: Regenerate.
68 * mt-desc.c: Regenerate.
69 * or1k-desc.c: Regenerate.
70 * xc16x-desc.c: Regenerate.
71 * xstormy16-desc.c: Regenerate.
73 2020-05-20 Nelson Chu <nelson.chu@sifive.com>
75 * riscv-opc.c (riscv_ext_version_table): The table used to store
76 all information about the supported spec and the corresponding ISA
77 versions. Currently, only Zicsr is supported to verify the
78 correctness of Z sub extension settings. Others will be supported
79 in the future patches.
80 (struct isa_spec_t, isa_specs): List for all supported ISA spec
81 classes and the corresponding strings.
82 (riscv_get_isa_spec_class): New function. Get the corresponding ISA
83 spec class by giving a ISA spec string.
84 * riscv-opc.c (struct priv_spec_t): New structure.
85 (struct priv_spec_t priv_specs): List for all supported privilege spec
86 classes and the corresponding strings.
87 (riscv_get_priv_spec_class): New function. Get the corresponding
88 privilege spec class by giving a spec string.
89 (riscv_get_priv_spec_name): New function. Get the corresponding
90 privilege spec string by giving a CSR version class.
91 * riscv-dis.c: Updated since DECLARE_CSR is changed.
92 * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
93 according to the chosen version. Build a hash table riscv_csr_hash to
94 store the valid CSR for the chosen pirv verison. Dump the direct
95 CSR address rather than it's name if it is invalid.
96 (parse_riscv_dis_option_without_args): New function. Parse the options
98 (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
99 parse the options without arguments first, and then handle the options
100 with arguments. Add the new option -Mpriv-spec, which has argument.
101 * riscv-dis.c (print_riscv_disassembler_options): Add description
102 about the new OBJDUMP option.
104 2020-05-19 Peter Bergner <bergner@linux.ibm.com>
106 * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
107 WC values on POWER10 sync, dcbf and wait instructions.
108 (insert_pl, extract_pl): New functions.
109 (L2OPT, LS, WC): Use insert_ls and extract_ls.
110 (LS3): New , 3-bit L for sync.
111 (LS3, L3OPT): New, 3-bit L for sync and dcbf.
112 (SC2, PL): New, 2-bit SC and PL for sync and wait.
113 (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
114 (XOPL3, XWCPL, XSYNCLS): New opcode macros.
115 (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
116 plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
117 <wait>: Enable PL operand on POWER10.
118 <dcbf>: Enable L3OPT operand on POWER10.
119 <sync>: Enable SC2 operand on POWER10.
121 2020-05-19 Stafford Horne <shorne@gmail.com>
124 * or1k-asm.c: Regenerate.
125 * or1k-desc.c: Regenerate.
126 * or1k-desc.h: Regenerate.
127 * or1k-dis.c: Regenerate.
128 * or1k-ibld.c: Regenerate.
129 * or1k-opc.c: Regenerate.
130 * or1k-opc.h: Regenerate.
131 * or1k-opinst.c: Regenerate.
133 2020-05-11 Alan Modra <amodra@gmail.com>
135 * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
138 2020-05-11 Alan Modra <amodra@gmail.com>
140 * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
141 stxvrbx, stxvrhx, stxvrwx, stxvrdx.
143 2020-05-11 Alan Modra <amodra@gmail.com>
145 * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
147 2020-05-11 Alan Modra <amodra@gmail.com>
149 * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
150 vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
152 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
154 * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
157 2020-05-11 Alan Modra <amodra@gmail.com>
159 * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
160 (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
161 vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
162 (prefix_opcodes): Add xxeval.
164 2020-05-11 Alan Modra <amodra@gmail.com>
166 * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
167 xxgenpcvwm, xxgenpcvdm.
169 2020-05-11 Alan Modra <amodra@gmail.com>
171 * ppc-opc.c (MP, VXVAM_MASK): Define.
172 (VXVAPS_MASK): Use VXVA_MASK.
173 (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
174 vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
175 vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
176 vcntmbb, vcntmbh, vcntmbw, vcntmbd.
178 2020-05-11 Alan Modra <amodra@gmail.com>
179 Peter Bergner <bergner@linux.ibm.com>
181 * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
183 (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
184 YMSK2, XA6a, XA6ap, XB6a entries.
185 (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
186 (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
188 (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
189 xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
190 xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
191 xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
192 xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
193 xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
194 xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
195 (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
196 pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
197 pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
198 pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
199 pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
200 pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
201 pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
203 2020-05-11 Alan Modra <amodra@gmail.com>
205 * ppc-opc.c (insert_imm32, extract_imm32): New functions.
206 (insert_xts, extract_xts): New functions.
207 (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
208 (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
209 (VXRC_MASK, VXSH_MASK): Define.
210 (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
211 vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
212 vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
213 vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
214 vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
215 (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
216 xxblendvh, xxblendvw, xxblendvd, xxpermx.
218 2020-05-11 Alan Modra <amodra@gmail.com>
220 * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
221 vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
222 vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
223 vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
224 xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
226 2020-05-11 Alan Modra <amodra@gmail.com>
228 * ppc-opc.c (insert_xtp, extract_xtp): New functions.
229 (XTP, DQXP, DQXP_MASK): Define.
230 (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
231 (prefix_opcodes): Add plxvp and pstxvp.
233 2020-05-11 Alan Modra <amodra@gmail.com>
235 * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
236 vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
237 vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
239 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
241 * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
243 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
245 * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
247 (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
249 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
251 * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
253 2020-05-11 Alan Modra <amodra@gmail.com>
255 * ppc-dis.c (powerpc_init_dialect): Default to "power10".
257 2020-05-11 Alan Modra <amodra@gmail.com>
259 * ppc-dis.c (ppc_opts): Add "power10" entry.
260 (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
261 * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
263 2020-05-11 Nick Clifton <nickc@redhat.com>
265 * po/fr.po: Updated French translation.
267 2020-04-30 Alex Coplan <alex.coplan@arm.com>
269 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
270 * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
271 (operand_general_constraint_met_p): validate
272 AARCH64_OPND_UNDEFINED.
273 * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
275 * aarch64-asm-2.c: Regenerated.
276 * aarch64-dis-2.c: Regenerated.
277 * aarch64-opc-2.c: Regenerated.
279 2020-04-29 Nick Clifton <nickc@redhat.com>
282 * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
285 2020-04-29 Nick Clifton <nickc@redhat.com>
287 * po/sv.po: Updated Swedish translation.
289 2020-04-29 Nick Clifton <nickc@redhat.com>
292 * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
293 IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
294 * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
297 2020-04-21 Andreas Schwab <schwab@linux-m68k.org>
300 * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
301 cmpi only on m68020up and cpu32.
303 2020-04-20 Sudakshina Das <sudi.das@arm.com>
305 * aarch64-asm.c (aarch64_ins_none): New.
306 * aarch64-asm.h (ins_none): New declaration.
307 * aarch64-dis.c (aarch64_ext_none): New.
308 * aarch64-dis.h (ext_none): New declaration.
309 * aarch64-opc.c (aarch64_print_operand): Update case for
310 AARCH64_OPND_BARRIER_PSB.
311 * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
312 (AARCH64_OPERANDS): Update inserter/extracter for
313 AARCH64_OPND_BARRIER_PSB to use new dummy functions.
314 * aarch64-asm-2.c: Regenerated.
315 * aarch64-dis-2.c: Regenerated.
316 * aarch64-opc-2.c: Regenerated.
318 2020-04-20 Sudakshina Das <sudi.das@arm.com>
320 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
321 (aarch64_feature_ras, RAS): Likewise.
322 (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
323 (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
324 autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
325 autiaz, autiasp, autibz, autibsp to be CORE_INSN.
326 * aarch64-asm-2.c: Regenerated.
327 * aarch64-dis-2.c: Regenerated.
328 * aarch64-opc-2.c: Regenerated.
330 2020-04-17 Fredrik Strupe <fredrik@strupe.net>
332 * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
333 (print_insn_neon): Support disassembly of conditional
336 2020-02-16 David Faust <david.faust@oracle.com>
338 * bpf-desc.c: Regenerate.
339 * bpf-desc.h: Likewise.
340 * bpf-opc.c: Regenerate.
341 * bpf-opc.h: Likewise.
343 2020-04-07 Lili Cui <lili.cui@intel.com>
345 * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
346 (prefix_table): New instructions (see prefixes above).
348 * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
349 CPU_ANY_TSXLDTRK_FLAGS.
350 (cpu_flags): Add CpuTSXLDTRK.
351 * i386-opc.h (enum): Add CpuTSXLDTRK.
352 (i386_cpu_flags): Add cputsxldtrk.
353 * i386-opc.tbl: Add XSUSPLDTRK insns.
354 * i386-init.h: Regenerate.
355 * i386-tbl.h: Likewise.
357 2020-04-02 Lili Cui <lili.cui@intel.com>
359 * i386-dis.c (prefix_table): New instructions serialize.
360 * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
361 CPU_ANY_SERIALIZE_FLAGS.
362 (cpu_flags): Add CpuSERIALIZE.
363 * i386-opc.h (enum): Add CpuSERIALIZE.
364 (i386_cpu_flags): Add cpuserialize.
365 * i386-opc.tbl: Add SERIALIZE insns.
366 * i386-init.h: Regenerate.
367 * i386-tbl.h: Likewise.
369 2020-03-26 Alan Modra <amodra@gmail.com>
371 * disassemble.h (opcodes_assert): Declare.
372 (OPCODES_ASSERT): Define.
373 * disassemble.c: Don't include assert.h. Include opintl.h.
374 (opcodes_assert): New function.
375 * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
376 (bfd_h8_disassemble): Reduce size of data array. Correctly
377 calculate maxlen. Omit insn decoding when insn length exceeds
378 maxlen. Exit from nibble loop when looking for E, before
379 accessing next data byte. Move processing of E outside loop.
380 Replace tests of maxlen in loop with assertions.
382 2020-03-26 Alan Modra <amodra@gmail.com>
384 * arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
386 2020-03-25 Alan Modra <amodra@gmail.com>
388 * z80-dis.c (suffix): Init mybuf.
390 2020-03-22 Alan Modra <amodra@gmail.com>
392 * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
393 successflly read from section.
395 2020-03-22 Alan Modra <amodra@gmail.com>
397 * arc-dis.c (find_format): Use ISO C string concatenation rather
398 than line continuation within a string. Don't access needs_limm
399 before testing opcode != NULL.
401 2020-03-22 Alan Modra <amodra@gmail.com>
403 * ns32k-dis.c (print_insn_arg): Update comment.
404 (print_insn_ns32k): Reduce size of index_offset array, and
405 initialize, passing -1 to print_insn_arg for args that are not
406 an index. Don't exit arg loop early. Abort on bad arg number.
408 2020-03-22 Alan Modra <amodra@gmail.com>
410 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
411 * s12z-opc.c: Formatting.
412 (operands_f): Return an int.
413 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
414 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
415 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
416 (exg_sex_discrim): Likewise.
417 (create_immediate_operand, create_bitfield_operand),
418 (create_register_operand_with_size, create_register_all_operand),
419 (create_register_all16_operand, create_simple_memory_operand),
420 (create_memory_operand, create_memory_auto_operand): Don't
421 segfault on malloc failure.
422 (z_ext24_decode): Return an int status, negative on fail, zero
424 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
425 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
426 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
427 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
428 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
429 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
430 (loop_primitive_decode, shift_decode, psh_pul_decode),
431 (bit_field_decode): Similarly.
432 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
433 to return value, update callers.
434 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
435 Don't segfault on NULL operand.
436 (decode_operation): Return OP_INVALID on first fail.
437 (decode_s12z): Check all reads, returning -1 on fail.
439 2020-03-20 Alan Modra <amodra@gmail.com>
441 * metag-dis.c (print_insn_metag): Don't ignore status from
444 2020-03-20 Alan Modra <amodra@gmail.com>
446 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
447 Initialize parts of buffer not written when handling a possible
448 2-byte insn at end of section. Don't attempt decoding of such
449 an insn by the 4-byte machinery.
451 2020-03-20 Alan Modra <amodra@gmail.com>
453 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
454 partially filled buffer. Prevent lookup of 4-byte insns when
455 only VLE 2-byte insns are possible due to section size. Print
456 ".word" rather than ".long" for 2-byte leftovers.
458 2020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
461 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
463 2020-03-13 Jan Beulich <jbeulich@suse.com>
465 * i386-dis.c (X86_64_0D): Rename to ...
466 (X86_64_0E): ... this.
468 2020-03-09 H.J. Lu <hongjiu.lu@intel.com>
470 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
471 * Makefile.in: Regenerated.
473 2020-03-09 Jan Beulich <jbeulich@suse.com>
475 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
477 * i386-tbl.h: Re-generate.
479 2020-03-09 Jan Beulich <jbeulich@suse.com>
481 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
482 vprot*, vpsha*, and vpshl*.
483 * i386-tbl.h: Re-generate.
485 2020-03-09 Jan Beulich <jbeulich@suse.com>
487 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
488 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
489 * i386-tbl.h: Re-generate.
491 2020-03-09 Jan Beulich <jbeulich@suse.com>
493 * i386-gen.c (set_bitfield): Ignore zero-length field names.
494 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
495 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
496 * i386-tbl.h: Re-generate.
498 2020-03-09 Jan Beulich <jbeulich@suse.com>
500 * i386-gen.c (struct template_arg, struct template_instance,
501 struct template_param, struct template, templates,
502 parse_template, expand_templates): New.
503 (process_i386_opcodes): Various local variables moved to
504 expand_templates. Call parse_template and expand_templates.
505 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
506 * i386-tbl.h: Re-generate.
508 2020-03-06 Jan Beulich <jbeulich@suse.com>
510 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
511 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
512 register and memory source templates. Replace VexW= by VexW*
514 * i386-tbl.h: Re-generate.
516 2020-03-06 Jan Beulich <jbeulich@suse.com>
518 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
519 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
520 * i386-tbl.h: Re-generate.
522 2020-03-06 Jan Beulich <jbeulich@suse.com>
524 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
525 * i386-tbl.h: Re-generate.
527 2020-03-06 Jan Beulich <jbeulich@suse.com>
529 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
530 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
531 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
532 VexW0 on SSE2AVX variants.
533 (vmovq): Drop NoRex64 from XMM/XMM variants.
534 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
535 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
536 applicable use VexW0.
537 * i386-tbl.h: Re-generate.
539 2020-03-06 Jan Beulich <jbeulich@suse.com>
541 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
542 * i386-opc.h (Rex64): Delete.
543 (struct i386_opcode_modifier): Remove rex64 field.
544 * i386-opc.tbl (crc32): Drop Rex64.
545 Replace Rex64 with Size64 everywhere else.
546 * i386-tbl.h: Re-generate.
548 2020-03-06 Jan Beulich <jbeulich@suse.com>
550 * i386-dis.c (OP_E_memory): Exclude recording of used address
551 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
552 addressed memory operands for MPX insns.
554 2020-03-06 Jan Beulich <jbeulich@suse.com>
556 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
557 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
558 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
559 (ptwrite): Split into non-64-bit and 64-bit forms.
560 * i386-tbl.h: Re-generate.
562 2020-03-06 Jan Beulich <jbeulich@suse.com>
564 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
566 * i386-tbl.h: Re-generate.
568 2020-03-04 Jan Beulich <jbeulich@suse.com>
570 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
571 (prefix_table): Move vmmcall here. Add vmgexit.
572 (rm_table): Replace vmmcall entry by prefix_table[] escape.
573 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
574 (cpu_flags): Add CpuSEV_ES entry.
575 * i386-opc.h (CpuSEV_ES): New.
576 (union i386_cpu_flags): Add cpusev_es field.
577 * i386-opc.tbl (vmgexit): New.
578 * i386-init.h, i386-tbl.h: Re-generate.
580 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
582 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
584 * i386-opc.h (IGNORESIZE): New.
585 (DEFAULTSIZE): Likewise.
586 (IgnoreSize): Removed.
587 (DefaultSize): Likewise.
589 (i386_opcode_modifier): Replace ignoresize/defaultsize with
591 * i386-opc.tbl (IgnoreSize): New.
592 (DefaultSize): Likewise.
593 * i386-tbl.h: Regenerated.
595 2020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
598 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
601 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
604 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
605 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
606 * i386-tbl.h: Regenerated.
608 2020-02-26 Alan Modra <amodra@gmail.com>
610 * aarch64-asm.c: Indent labels correctly.
611 * aarch64-dis.c: Likewise.
612 * aarch64-gen.c: Likewise.
613 * aarch64-opc.c: Likewise.
614 * alpha-dis.c: Likewise.
615 * i386-dis.c: Likewise.
616 * nds32-asm.c: Likewise.
617 * nfp-dis.c: Likewise.
618 * visium-dis.c: Likewise.
620 2020-02-25 Claudiu Zissulescu <claziss@gmail.com>
622 * arc-regs.h (int_vector_base): Make it available for all ARC
625 2020-02-20 Nelson Chu <nelson.chu@sifive.com>
627 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
630 2020-02-19 Nelson Chu <nelson.chu@sifive.com>
632 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
633 c.mv/c.li if rs1 is zero.
635 2020-02-17 H.J. Lu <hongjiu.lu@intel.com>
637 * i386-gen.c (cpu_flag_init): Replace CpuABM with
638 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
640 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
641 * i386-opc.h (CpuABM): Removed.
643 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
644 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
645 popcnt. Remove CpuABM from lzcnt.
646 * i386-init.h: Regenerated.
647 * i386-tbl.h: Likewise.
649 2020-02-17 Jan Beulich <jbeulich@suse.com>
651 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
652 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
653 VexW1 instead of open-coding them.
654 * i386-tbl.h: Re-generate.
656 2020-02-17 Jan Beulich <jbeulich@suse.com>
658 * i386-opc.tbl (AddrPrefixOpReg): Define.
659 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
660 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
661 templates. Drop NoRex64.
662 * i386-tbl.h: Re-generate.
664 2020-02-17 Jan Beulich <jbeulich@suse.com>
667 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
668 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
669 into Intel syntax instance (with Unpsecified) and AT&T one
671 (vcvtneps2bf16): Likewise, along with folding the two so far
673 * i386-tbl.h: Re-generate.
675 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
677 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
680 2020-02-17 Alan Modra <amodra@gmail.com>
682 * i386-gen.c (cpu_flag_init): Correct last change.
684 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
686 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
689 2020-02-14 H.J. Lu <hongjiu.lu@intel.com>
691 * i386-opc.tbl (movsx): Remove Intel syntax comments.
694 2020-02-14 Jan Beulich <jbeulich@suse.com>
697 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
698 destination for Cpu64-only variant.
699 (movzx): Fold patterns.
700 * i386-tbl.h: Re-generate.
702 2020-02-13 Jan Beulich <jbeulich@suse.com>
704 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
705 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
706 CPU_ANY_SSE4_FLAGS entry.
707 * i386-init.h: Re-generate.
709 2020-02-12 Jan Beulich <jbeulich@suse.com>
711 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
712 with Unspecified, making the present one AT&T syntax only.
713 * i386-tbl.h: Re-generate.
715 2020-02-12 Jan Beulich <jbeulich@suse.com>
717 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
718 * i386-tbl.h: Re-generate.
720 2020-02-12 Jan Beulich <jbeulich@suse.com>
723 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
724 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
725 Amd64 and Intel64 templates.
726 (call, jmp): Likewise for far indirect variants. Dro
728 * i386-tbl.h: Re-generate.
730 2020-02-11 Jan Beulich <jbeulich@suse.com>
732 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
733 * i386-opc.h (ShortForm): Delete.
734 (struct i386_opcode_modifier): Remove shortform field.
735 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
736 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
737 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
738 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
740 * i386-tbl.h: Re-generate.
742 2020-02-11 Jan Beulich <jbeulich@suse.com>
744 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
745 fucompi): Drop ShortForm from operand-less templates.
746 * i386-tbl.h: Re-generate.
748 2020-02-11 Alan Modra <amodra@gmail.com>
750 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
751 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
752 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
753 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
754 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
756 2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
758 * arm-dis.c (print_insn_cde): Define 'V' parse character.
759 (cde_opcodes): Add VCX* instructions.
761 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
762 Matthew Malcomson <matthew.malcomson@arm.com>
764 * arm-dis.c (struct cdeopcode32): New.
765 (CDE_OPCODE): New macro.
766 (cde_opcodes): New disassembly table.
767 (regnames): New option to table.
768 (cde_coprocs): New global variable.
769 (print_insn_cde): New
770 (print_insn_thumb32): Use print_insn_cde.
771 (parse_arm_disassembler_options): Parse coprocN args.
773 2020-02-10 H.J. Lu <hongjiu.lu@intel.com>
776 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
778 * i386-opc.h (AMD64): Removed.
782 (INTEL64ONLY): Likewise.
783 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
784 * i386-opc.tbl (Amd64): New.
786 (Intel64Only): Likewise.
787 Replace AMD64 with Amd64. Update sysenter/sysenter with
788 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
789 * i386-tbl.h: Regenerated.
791 2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
794 * z80-dis.c: Add support for GBZ80 opcodes.
796 2020-02-04 Alan Modra <amodra@gmail.com>
798 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
800 2020-02-03 Alan Modra <amodra@gmail.com>
802 * m32c-ibld.c: Regenerate.
804 2020-02-01 Alan Modra <amodra@gmail.com>
806 * frv-ibld.c: Regenerate.
808 2020-01-31 Jan Beulich <jbeulich@suse.com>
810 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
811 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
812 (OP_E_memory): Replace xmm_mdq_mode case label by
813 vex_scalar_w_dq_mode one.
814 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
816 2020-01-31 Jan Beulich <jbeulich@suse.com>
818 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
819 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
820 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
821 (intel_operand_size): Drop vex_w_dq_mode case label.
823 2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
825 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
826 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
828 2020-01-30 Alan Modra <amodra@gmail.com>
830 * m32c-ibld.c: Regenerate.
832 2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
834 * bpf-opc.c: Regenerate.
836 2020-01-30 Jan Beulich <jbeulich@suse.com>
838 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
839 (dis386): Use them to replace C2/C3 table entries.
840 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
841 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
842 ones. Use Size64 instead of DefaultSize on Intel64 ones.
843 * i386-tbl.h: Re-generate.
845 2020-01-30 Jan Beulich <jbeulich@suse.com>
847 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
849 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
851 * i386-tbl.h: Re-generate.
853 2020-01-30 Alan Modra <amodra@gmail.com>
855 * tic4x-dis.c (tic4x_dp): Make unsigned.
857 2020-01-27 H.J. Lu <hongjiu.lu@intel.com>
858 Jan Beulich <jbeulich@suse.com>
861 * i386-dis.c (MOVSXD_Fixup): New function.
862 (movsxd_mode): New enum.
863 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
864 (intel_operand_size): Handle movsxd_mode.
865 (OP_E_register): Likewise.
867 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
868 register on movsxd. Add movsxd with 16-bit destination register
869 for AMD64 and Intel64 ISAs.
870 * i386-tbl.h: Regenerated.
872 2020-01-27 Tamar Christina <tamar.christina@arm.com>
875 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
876 * aarch64-asm-2.c: Regenerate
877 * aarch64-dis-2.c: Likewise.
878 * aarch64-opc-2.c: Likewise.
880 2020-01-21 Jan Beulich <jbeulich@suse.com>
882 * i386-opc.tbl (sysret): Drop DefaultSize.
883 * i386-tbl.h: Re-generate.
885 2020-01-21 Jan Beulich <jbeulich@suse.com>
887 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
889 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
890 * i386-tbl.h: Re-generate.
892 2020-01-20 Nick Clifton <nickc@redhat.com>
894 * po/de.po: Updated German translation.
895 * po/pt_BR.po: Updated Brazilian Portuguese translation.
896 * po/uk.po: Updated Ukranian translation.
898 2020-01-20 Alan Modra <amodra@gmail.com>
900 * hppa-dis.c (fput_const): Remove useless cast.
902 2020-01-20 Alan Modra <amodra@gmail.com>
904 * arm-dis.c (print_insn_arm): Wrap 'T' value.
906 2020-01-18 Nick Clifton <nickc@redhat.com>
908 * configure: Regenerate.
909 * po/opcodes.pot: Regenerate.
911 2020-01-18 Nick Clifton <nickc@redhat.com>
913 Binutils 2.34 branch created.
915 2020-01-17 Christian Biesinger <cbiesinger@google.com>
917 * opintl.h: Fix spelling error (seperate).
919 2020-01-17 H.J. Lu <hongjiu.lu@intel.com>
921 * i386-opc.tbl: Add {vex} pseudo prefix.
922 * i386-tbl.h: Regenerated.
924 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
927 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
928 (neon_opcodes): Likewise.
929 (select_arm_features): Make sure we enable MVE bits when selecting
930 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
933 2020-01-16 Jan Beulich <jbeulich@suse.com>
935 * i386-opc.tbl: Drop stale comment from XOP section.
937 2020-01-16 Jan Beulich <jbeulich@suse.com>
939 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
940 (extractps): Add VexWIG to SSE2AVX forms.
941 * i386-tbl.h: Re-generate.
943 2020-01-16 Jan Beulich <jbeulich@suse.com>
945 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
946 Size64 from and use VexW1 on SSE2AVX forms.
947 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
948 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
949 * i386-tbl.h: Re-generate.
951 2020-01-15 Alan Modra <amodra@gmail.com>
953 * tic4x-dis.c (tic4x_version): Make unsigned long.
954 (optab, optab_special, registernames): New file scope vars.
955 (tic4x_print_register): Set up registernames rather than
956 malloc'd registertable.
957 (tic4x_disassemble): Delete optable and optable_special. Use
958 optab and optab_special instead. Throw away old optab,
959 optab_special and registernames when info->mach changes.
961 2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
964 * z80-dis.c (suffix): Use .db instruction to generate double
967 2020-01-14 Alan Modra <amodra@gmail.com>
969 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
970 values to unsigned before shifting.
972 2020-01-13 Thomas Troeger <tstroege@gmx.de>
974 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
976 (print_insn_thumb16, print_insn_thumb32): Likewise.
977 (print_insn): Initialize the insn info.
978 * i386-dis.c (print_insn): Initialize the insn info fields, and
981 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
983 * arc-opc.c (C_NE): Make it required.
985 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
987 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
988 reserved register name.
990 2020-01-13 Alan Modra <amodra@gmail.com>
992 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
993 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
995 2020-01-13 Alan Modra <amodra@gmail.com>
997 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
998 result of wasm_read_leb128 in a uint64_t and check that bits
999 are not lost when copying to other locals. Use uint32_t for
1000 most locals. Use PRId64 when printing int64_t.
1002 2020-01-13 Alan Modra <amodra@gmail.com>
1004 * score-dis.c: Formatting.
1005 * score7-dis.c: Formatting.
1007 2020-01-13 Alan Modra <amodra@gmail.com>
1009 * score-dis.c (print_insn_score48): Use unsigned variables for
1010 unsigned values. Don't left shift negative values.
1011 (print_insn_score32): Likewise.
1012 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
1014 2020-01-13 Alan Modra <amodra@gmail.com>
1016 * tic4x-dis.c (tic4x_print_register): Remove dead code.
1018 2020-01-13 Alan Modra <amodra@gmail.com>
1020 * fr30-ibld.c: Regenerate.
1022 2020-01-13 Alan Modra <amodra@gmail.com>
1024 * xgate-dis.c (print_insn): Don't left shift signed value.
1025 (ripBits): Formatting, use 1u.
1027 2020-01-10 Alan Modra <amodra@gmail.com>
1029 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
1030 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
1032 2020-01-10 Alan Modra <amodra@gmail.com>
1034 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
1035 and XRREG value earlier to avoid a shift with negative exponent.
1036 * m10200-dis.c (disassemble): Similarly.
1038 2020-01-09 Nick Clifton <nickc@redhat.com>
1041 * z80-dis.c (ld_ii_ii): Use correct cast.
1043 2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
1046 * z80-dis.c (ld_ii_ii): Use character constant when checking
1049 2020-01-09 Jan Beulich <jbeulich@suse.com>
1051 * i386-dis.c (SEP_Fixup): New.
1053 (dis386_twobyte): Use it for sysenter/sysexit.
1054 (enum x86_64_isa): Change amd64 enumerator to value 1.
1055 (OP_J): Compare isa64 against intel64 instead of amd64.
1056 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
1058 * i386-tbl.h: Re-generate.
1060 2020-01-08 Alan Modra <amodra@gmail.com>
1062 * z8k-dis.c: Include libiberty.h
1063 (instr_data_s): Make max_fetched unsigned.
1064 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
1065 Don't exceed byte_info bounds.
1066 (output_instr): Make num_bytes unsigned.
1067 (unpack_instr): Likewise for nibl_count and loop.
1068 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
1070 * z8k-opc.h: Regenerate.
1072 2020-01-07 Shahab Vahedi <shahab@synopsys.com>
1074 * arc-tbl.h (llock): Use 'LLOCK' as class.
1076 (scond): Use 'SCOND' as class.
1078 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
1081 2020-01-06 Alan Modra <amodra@gmail.com>
1083 * m32c-ibld.c: Regenerate.
1085 2020-01-06 Alan Modra <amodra@gmail.com>
1088 * z80-dis.c (suffix): Don't use a local struct buffer copy.
1089 Peek at next byte to prevent recursion on repeated prefix bytes.
1090 Ensure uninitialised "mybuf" is not accessed.
1091 (print_insn_z80): Don't zero n_fetch and n_used here,..
1092 (print_insn_z80_buf): ..do it here instead.
1094 2020-01-04 Alan Modra <amodra@gmail.com>
1096 * m32r-ibld.c: Regenerate.
1098 2020-01-04 Alan Modra <amodra@gmail.com>
1100 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
1102 2020-01-04 Alan Modra <amodra@gmail.com>
1104 * crx-dis.c (match_opcode): Avoid shift left of signed value.
1106 2020-01-04 Alan Modra <amodra@gmail.com>
1108 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
1110 2020-01-03 Jan Beulich <jbeulich@suse.com>
1112 * aarch64-tbl.h (aarch64_opcode_table): Use
1113 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
1115 2020-01-03 Jan Beulich <jbeulich@suse.com>
1117 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
1118 forms of SUDOT and USDOT.
1120 2020-01-03 Jan Beulich <jbeulich@suse.com>
1122 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
1124 * opcodes/aarch64-dis-2.c: Re-generate.
1126 2020-01-03 Jan Beulich <jbeulich@suse.com>
1128 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
1130 * opcodes/aarch64-dis-2.c: Re-generate.
1132 2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
1134 * z80-dis.c: Add support for eZ80 and Z80 instructions.
1136 2020-01-01 Alan Modra <amodra@gmail.com>
1138 Update year range in copyright notice of all files.
1140 For older changes see ChangeLog-2019
1142 Copyright (C) 2020 Free Software Foundation, Inc.
1144 Copying and distribution of this file, with or without modification,
1145 are permitted in any medium without royalty provided the copyright
1146 notice and this notice are preserved.
1152 version-control: never