opcodes/ChangeLog

   1 2021-06-03  Alan Modra  <amodra@gmail.com>
   2
   3         PR 1202
   4         * mcore-dis.c (print_insn_mcore): Correct loopt disassembly.
   5         Use unsigned int for inst.
   6
   7 2021-06-02  Shahab Vahedi  <shahab@synopsys.com>
   8
   9         * arc-dis.c (arc_option_arg_t): New enumeration.
  10         (arc_options): New variable.
  11         (disassembler_options_arc): New function.
  12         (print_arc_disassembler_options): Reimplement in terms of
  13         "disassembler_options_arc".
  14
  15 2021-05-29  Alan Modra  <amodra@gmail.com>
  16
  17         * ppc-dis.c (lookup_powerpc): Test deprecated field when -Many.
  18         Don't special case PPC_OPCODE_RAW.
  19         (lookup_prefix): Likewise.
  20         (lookup_vle, lookup_spe2): Similarly.  Add dialect parameter and..
  21         (print_insn_powerpc): ..update caller.
  22         * ppc-opc.c (EXT): Define.
  23         (powerpc_opcodes): Mark extended mnemonics with EXT.
  24         (prefix_opcodes, vle_opcodes): Likewise.
  25         (XISEL, XISEL_MASK): Add cr field and simplify.
  26         (powerpc_opcodes): Use XISEL with extended isel mnemonics and sort
  27         all isel variants to where the base mnemonic belongs.  Sort dstt,
  28         dststt and dssall.
  29
  30 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
  31
  32         * mips-opc.c (mips_builtin_opcodes): Reorder legacy COP0, COP2,
  33         COP3 opcode instructions.
  34
  35 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
  36
  37         * mips-opc.c (mips_builtin_opcodes): Update exclusion list for
  38         "ldc2", "ldc3", "lwc0", "lwc2", "lwc3", "sdc2", "sdc3", "swc0",
  39         "swc2", "swc3", "cfc0", "ctc0", "bc2f", "bc2fl", "bc2t",
  40         "bc2tl", "cfc2", "ctc2", "dmfc2", "dmtc2", "mfc2", "mtc2",
  41         "bc3f", "bc3fl", "bc3t", "bc3tl", "cfc3", "ctc3", "mfc3",
  42         "mtc3", "bc0f", "bc0fl", "bc0t", "bc0tl", "rfe", "c2", "c3",
  43         "cop2", and "cop3" entries.
  44
  45 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
  46
  47         * mips-opc.c (mips_builtin_opcodes): Remove "dmfc3" and "dmtc3"
  48         entries and associated comments.
  49
  50 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
  51
  52         * mips-opc.c (mips_builtin_opcodes): Move the "rfe" entry ahead
  53         of "c0".
  54
  55 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
  56
  57         * mips-dis.c (mips_cp1_names_mips): New variable.
  58         (mips_arch_choices): Use it rather than `mips_cp1_names_numeric'
  59         for "r3000", "r4000", "r4010", "vr4100", "vr4111", "vr4120",
  60         "r4300", "r4400", "r4600", "r4650", "r5000", "vr5400", "vr5500",
  61         "r5900", "r6000", "rm7000", "rm9000", "r8000", "r10000",
  62         "r12000", "r14000", "r16000", "mips5", "loongson2e", and
  63         "loongson2f".
  64
  65 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
  66
  67         * mips-dis.c (print_reg) <OP_REG_COPRO>: Move control register
  68         handling code over to...
  69         <OP_REG_CONTROL>: ... this new case.
  70         * mips-opc.c (decode_mips_operand) <'g', 'y'>: New cases.
  71         (mips_builtin_opcodes): Update "cfc1", "ctc1", "cttc1", "cttc2",
  72         "cfc0", "ctc0", "cfc2", "ctc2", "cfc3", and "ctc3" entries
  73         replacing the `G' operand code with `g'.  Update "cftc1" and
  74         "cftc2" entries replacing the `E' operand code with `y'.
  75         * micromips-opc.c (decode_micromips_operand) <'g'>: New case.
  76         (micromips_opcodes): Update "cfc1", "cfc2", "ctc1", and "ctc2"
  77         entries replacing the `G' operand code with `g'.
  78
  79 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
  80
  81         * mips-dis.c (mips_cp0_names_r3900): New variable.
  82         (mips_arch_choices): Use it rather than `mips_cp0_names_numeric'
  83         for "r3900".
  84
  85 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
  86
  87         * mips-opc.c (mips_builtin_opcodes): Switch "cttc2", "mttc2",
  88         and "mtthc2" to using the `G' rather than `g' operand code for
  89         the coprocessor control register referred.
  90
  91 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
  92
  93         * micromips-opc.c (micromips_opcodes): Swap the two "dmtc1"
  94         entries with each other.
  95
  96 2021-05-27  Peter Bergner  <bergner@linux.ibm.com>
  97
  98         * ppc-opc.c (powerpc_opcodes) <xxmr, xxlnot>: New extended mnemonics.
  99
 100 2021-05-25  Alan Modra  <amodra@gmail.com>
 101
 102         * cris-desc.c: Regenerate.
 103         * cris-desc.h: Regenerate.
 104         * cris-opc.h: Regenerate.
 105         * po/POTFILES.in: Regenerate.
 106
 107 2021-05-24  Mike Frysinger  <vapier@gentoo.org>
 108
 109         * Makefile.am (HFILES): Add cris-desc.h & cris-opc.h.
 110         (TARGET_LIBOPCODES_CFILES): Add cris-desc.c.
 111         (CGEN_CPUS): Add cris.
 112         (CRIS_DEPS): Define.
 113         (stamp-cris): New rule.
 114         * cgen.sh: Handle desc action.
 115         * configure.ac (bfd_cris_arch): Add cris-desc.lo.
 116         * Makefile.in, configure: Regenerate.
 117
 118 2021-05-18  Job Noorman  <mtvec@pm.me>
 119
 120         PR 27814
 121         * riscv-dis.c (riscv_get_disassembler): Get elf attributes only for
 122         the elf objects.
 123
 124 2021-05-17  Alex Coplan  <alex.coplan@arm.com>
 125
 126         * arm-dis.c (mve_opcodes): Fix disassembly of
 127         MVE_VMOV2_GP_TO_VEC_LANE when idx == 1.
 128         (is_mve_encoding_conflict): MVE vector loads should not match
 129         when P = W = 0.
 130         (is_mve_unpredictable): It's not unpredictable to use the same
 131         source register twice (for MVE_VMOV2_GP_TO_VEC_LANE).
 132
 133 2021-05-11  Nick Clifton  <nickc@redhat.com>
 134
 135         PR 27840
 136         * tic30-dis.c (print_insn_tic30): Prevent attempts to read beyond
 137         the end of the code buffer.
 138
 139 2021-05-06  Stafford Horne  <shorne@gmail.com>
 140
 141         PR 21464
 142         * or1k-asm.c: Regenerate.
 143
 144 2021-05-01  Max Filippov  <jcmvbkbc@gmail.com>
 145
 146         * xtensa-dis.c (print_insn_xtensa): Fill in info->insn_type and
 147         info->insn_info_valid.
 148
 149 2021-04-26  Jan Beulich  <jbeulich@suse.com>
 150
 151         * i386-opc.tbl (lea): Add Optimize.
 152         * opcodes/i386-tbl.h: Re-generate.
 153
 154 2020-04-23  Max Filippov  <jcmvbkbc@gmail.com>
 155
 156         * xtensa-dis.c (print_xtensa_operand): For PC-relative operand
 157         of l32r fetch and display referenced literal value.
 158
 159 2021-04-23  Max Filippov  <jcmvbkbc@gmail.com>
 160
 161         * xtensa-dis.c (print_insn_xtensa): Set info->bytes_per_chunk
 162         to 4 for literal disassembly.
 163
 164 2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 165
 166         * aarch64-opc.c: Add new registers (RPAOS, RPALOS, PAALLOS, PAALL) support
 167         for TLBI instruction.
 168
 169 2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 170
 171         * aarch64-opc.c: Add new register (CIPAPA, CIGDPAPA) support for
 172         DC instruction.
 173
 174 2021-04-19  Jan Beulich  <jbeulich@suse.com>
 175
 176         * aarch64-asm.c (encode_asimd_fcvt): Add initializer for
 177         "qualifier".
 178         (convert_mov_to_movewide): Add initializer for "value".
 179
 180 2021-04-16  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 181
 182         * aarch64-opc.c: Add RME system registers.
 183
 184 2021-04-16  Lifang Xia <lifang_xia@c-sky.com>
 185
 186         * riscv-opc.c (riscv_opcodes): New insn alias for addi. Compress
 187         "addi d,CV,z" to "c.mv d,CV".
 188
 189 2021-04-12  Alan Modra  <amodra@gmail.com>
 190
 191         * configure.ac (--enable-checking): Add support.
 192         * config.in: Regenerate.
 193         * configure: Regenerate.
 194
 195 2021-04-09  Tejas Belagod  <tejas.belagod@arm.com>
 196
 197         * aarch64-tbl.h (struct aarch64_opcode aarch64_opcode_table): Reclassify
 198         LD64/ST64 instructions to lse_atomic instead of ldstexcl.
 199
 200 2021-04-09  Alan Modra  <amodra@gmail.com>
 201
 202         * ppc-dis.c (struct dis_private): Add "special".
 203         (POWERPC_DIALECT): Delete.  Replace uses with..
 204         (private_data): ..this.  New inline function.
 205         (disassemble_init_powerpc): Init "special" names.
 206         (skip_optional_operands): Add is_pcrel arg, set when detecting R
 207         field of prefix instructions.
 208         (bsearch_reloc, print_got_plt): New functions.
 209         (print_insn_powerpc): For pcrel instructions, print target address
 210         and symbol if known, and decode plt and got loads too.
 211
 212 2021-04-08  Alan Modra  <amodra@gmail.com>
 213
 214         PR 27684
 215         * ppc-opc.c (powerpc_opcodes): Correct usprg typos, add mfpir.
 216
 217 2021-04-08  Alan Modra  <amodra@gmail.com>
 218
 219         PR 27676
 220         * ppc-opc.c (DCBT_EO): Move earlier.
 221         (insert_thct, extract_thct, insert_thds, extract_thds): New functions.
 222         (powerpc_operands): Add THCT and THDS entries.
 223         (powerpc_opcodes): Add dcbtstct, dcbtstds, dcbna, dcbtct, dcbtds.
 224
 225 2021-04-06  Alan Modra  <amodra@gmail.com>
 226
 227         * dis-buf.c (generic_symbol_at_address): Return symbol* NULL.
 228         * s12z-dis.c (decode_possible_symbol): Use symbol returned from
 229         symbol_at_address_func.
 230
 231 2021-04-05  Alan Modra  <amodra@gmail.com>
 232
 233         * configure.ac: Don't check for limits.h, string.h, strings.h or
 234         stdlib.h.
 235         (AC_ISC_POSIX): Don't invoke.
 236         * sysdep.h: Include stdlib.h and string.h unconditionally.
 237         * i386-opc.h: Include limits.h unconditionally.
 238         * wasm32-dis.c: Likewise.
 239         * cgen-opc.c: Don't include alloca-conf.h.
 240         * config.in: Regenerate.
 241         * configure: Regenerate.
 242
 243 2021-04-01  Martin Liska  <mliska@suse.cz>
 244
 245         * arm-dis.c (strneq): Remove strneq and use startswith.
 246         * cr16-dis.c (print_insn_cr16): Likewise.
 247         * score-dis.c (streq): Likewise.
 248         (strneq): Likewise.
 249         * score7-dis.c (strneq): Likewise.
 250
 251 2021-04-01  Alan Modra  <amodra@gmail.com>
 252
 253         PR 27675
 254         * ppc-opc.c (powerpc_opcodes): Add mfummcr2 and mfmmcr2.
 255
 256 2021-03-31  Alan Modra  <amodra@gmail.com>
 257
 258         * sysdep.h (POISON_BFD_BOOLEAN): Define.
 259         * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h,
 260         * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h,
 261         * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c,
 262         * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c,
 263         * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c,
 264         * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c,
 265         * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c,
 266         * microblaze-dis.h, * micromips-opc.c, * mips-dis.c,
 267         * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c,
 268         * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c,
 269         * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c,
 270         * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c,
 271         * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false,
 272         and TRUE with true throughout.
 273
 274 2021-03-31  Alan Modra  <amodra@gmail.com>
 275
 276         * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h.
 277         * aarch64-dis.h: Likewise.
 278         * aarch64-opc.c: Likewise.
 279         * avr-dis.c: Likewise.
 280         * csky-dis.c: Likewise.
 281         * nds32-asm.c: Likewise.
 282         * nds32-dis.c: Likewise.
 283         * nfp-dis.c: Likewise.
 284         * riscv-dis.c: Likewise.
 285         * s12z-dis.c: Likewise.
 286         * wasm32-dis.c: Likewise.
 287
 288 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 289
 290         * i386-opc.c (cs, ds, ss, es, fs, gs): Delete.
 291         (i386_seg_prefixes): New.
 292         * i386-opc.h (cs, ds, ss, es, fs, gs): Delete.
 293         (i386_seg_prefixes): Declare.
 294
 295 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 296
 297         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Delete.
 298
 299 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 300
 301         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Adjust values.
 302         * i386-reg.tbl (st): Move down.
 303         (st(0)): Delete. Extend comment.
 304         * i386-tbl.h: Re-generate.
 305
 306 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 307
 308         * i386-opc.tbl (movq, movabs): Move next to mov counterparts.
 309         (cmpsd): Move next to cmps.
 310         (movsd): Move next to movs.
 311         (cmpxchg16b): Move to separate section.
 312         (fisttp, fisttpll): Likewise.
 313         (monitor, mwait): Likewise.
 314         * i386-tbl.h: Re-generate.
 315
 316 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 317
 318         * i386-opc.tbl (psadbw): Add <sse2:comm>.
 319         (vpsadbw): Add C.
 320         * i386-tbl.h: Re-generate.
 321
 322 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 323
 324         * i386-opc.tbl (mmx, sse, sse2, sse3, ssse3, sse41, sse42, aes,
 325         pclmul, gfni): New templates. Use them wherever possible. Move
 326         SSE4.1 pextrw into respective section.
 327         * i386-tbl.h: Re-generate.
 328
 329 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 330
 331         * i386-gen.c (output_i386_opcode): Widen type of "opcode". Use
 332         strtoull(). Bump upper loop bound. Widen masks. Sanity check
 333         "length".
 334         * i386-opc.tbl (Prefix_0X66, Prefix_0XF2, Prefix_0XF3): Delete.
 335         Convert all of their uses to representation in opcode.
 336
 337 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 338
 339         * i386-opc.h (struct insn_template): Shrink base_opcode to 16
 340         bits. Shrink extension_opcode to 9 bits. Make it signed. Change
 341         value of None. Shrink operands to 3 bits.
 342
 343 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 344
 345         * i386-gen.c (process_i386_opcode_modifier): New parameter
 346         "space".
 347         (output_i386_opcode): New local variable "space". Adjust
 348         process_i386_opcode_modifier() invocation.
 349         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 350         invocation.
 351         * i386-tbl.h: Re-generate.
 352
 353 2021-03-29  Alan Modra  <amodra@gmail.com>
 354
 355         * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
 356         (fp_qualifier_p, get_data_pattern): Likewise.
 357         (aarch64_get_operand_modifier_from_value): Likewise.
 358         (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
 359         (operand_variant_qualifier_p): Likewise.
 360         (qualifier_value_in_range_constraint_p): Likewise.
 361         (aarch64_get_qualifier_esize): Likewise.
 362         (aarch64_get_qualifier_nelem): Likewise.
 363         (aarch64_get_qualifier_standard_value): Likewise.
 364         (get_lower_bound, get_upper_bound): Likewise.
 365         (aarch64_find_best_match, match_operands_qualifier): Likewise.
 366         (aarch64_print_operand): Likewise.
 367         * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
 368         (operand_need_sign_extension, operand_need_shift_by_two): Likewise.
 369         (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
 370         * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
 371         * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
 372         (print_insn_tic6x): Likewise.
 373
 374 2021-03-29  Alan Modra  <amodra@gmail.com>
 375
 376         * arc-dis.c (extract_operand_value): Correct NULL cast.
 377         * frv-opc.h: Regenerate.
 378
 379 2021-03-26  Jan Beulich  <jbeulich@suse.com>
 380
 381         * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to
 382         MMX form.
 383         * i386-tbl.h: Re-generate.
 384
 385 2021-03-25  Abid Qadeer  <abidh@codesourcery.com>
 386
 387         * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
 388         immediate in br.n instruction.
 389
 390 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 391
 392         * i386-dis.c (XMGatherD, VexGatherD): New.
 393         (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
 394         (print_insn): Check masking for S/G insns.
 395         (OP_E_memory): New local variable check_gather. Extend mandatory
 396         SIB check. Check register conflicts for (EVEX-encoded) gathers.
 397         Extend check for disallowed 16-bit addressing.
 398         (OP_VEX): New local variables modrm_reg and sib_index. Convert
 399         if()s to switch(). Check register conflicts for (VEX-encoded)
 400         gathers. Drop no longer reachable cases.
 401         * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
 402         vgatherdp*.
 403
 404 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 405
 406         * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
 407         zeroing-masking without masking.
 408
 409 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 410
 411         * i386-opc.tbl (invlpgb): Fix multi-operand form.
 412         (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
 413         single-operand forms as deprecated.
 414         * i386-tbl.h: Re-generate.
 415
 416 2021-03-25  Alan Modra  <amodra@gmail.com>
 417
 418         PR 27647
 419         * ppc-opc.c (XLOCB_MASK): Delete.
 420         (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
 421         XLBH_MASK.
 422         (powerpc_opcodes): Accept a BH field on all extended forms of
 423         bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
 424
 425 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 426
 427         * i386-gen.c (output_i386_opcode): Drop processing of
 428         opcode_length. Calculate length from base_opcode. Adjust prefix
 429         encoding determination.
 430         (process_i386_opcodes): Drop output of fake opcode_length.
 431         * i386-opc.h (struct insn_template): Drop opcode_length field.
 432         * i386-opc.tbl: Drop opcode length field from all templates.
 433         * i386-tbl.h: Re-generate.
 434
 435 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 436
 437         * i386-gen.c (process_i386_opcode_modifier): Return void. New
 438         parameter "prefix". Drop local variable "regular_encoding".
 439         Record prefix setting / check for consistency.
 440         (output_i386_opcode): Parse opcode_length and base_opcode
 441         earlier. Derive prefix encoding. Drop no longer applicable
 442         consistency checking. Adjust process_i386_opcode_modifier()
 443         invocation.
 444         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 445         invocation.
 446         * i386-tbl.h: Re-generate.
 447
 448 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 449
 450         * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
 451         check.
 452         * i386-opc.h (Prefix_*): Move #define-s.
 453         * i386-opc.tbl: Move pseudo prefix enumerator values to
 454         extension opcode field. Introduce pseudopfx template.
 455         * i386-tbl.h: Re-generate.
 456
 457 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 458
 459         * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
 460         comment.
 461         * i386-tbl.h: Re-generate.
 462
 463 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 464
 465         * i386-opc.h (struct insn_template): Move cpu_flags field past
 466         opcode_modifier one.
 467         * i386-tbl.h: Re-generate.
 468
 469 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 470
 471         * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
 472         * i386-opc.h (OpcodeSpace): New enumerator.
 473         (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
 474         (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
 475         SPACE_XOP09, SPACE_XOP0A): ... respectively.
 476         (struct i386_opcode_modifier): New field opcodespace. Shrink
 477         opcodeprefix field.
 478         i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
 479         SpaceXOP09, SpaceXOP0A): Define. Use them to replace
 480         OpcodePrefix uses.
 481         * i386-tbl.h: Re-generate.
 482
 483 2021-03-22  Martin Liska  <mliska@suse.cz>
 484
 485         * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
 486         * arc-dis.c (parse_option): Likewise.
 487         * arm-dis.c (parse_arm_disassembler_options): Likewise.
 488         * cris-dis.c (print_with_operands): Likewise.
 489         * h8300-dis.c (bfd_h8_disassemble): Likewise.
 490         * i386-dis.c (print_insn): Likewise.
 491         * ia64-gen.c (fetch_insn_class): Likewise.
 492         (parse_resource_users): Likewise.
 493         (in_iclass): Likewise.
 494         (lookup_specifier): Likewise.
 495         (insert_opcode_dependencies): Likewise.
 496         * mips-dis.c (parse_mips_ase_option): Likewise.
 497         (parse_mips_dis_option): Likewise.
 498         * s390-dis.c (disassemble_init_s390): Likewise.
 499         * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
 500
 501 2021-03-16  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
 502
 503         * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
 504
 505 2021-03-12  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 506
 507         * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
 508         icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
 509
 510 2021-03-12  Alan Modra  <amodra@gmail.com>
 511
 512         * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
 513
 514 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 515
 516         * i386-dis.c (OP_XMM): Re-order checks.
 517
 518 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 519
 520         * i386-dis.c (putop): Drop need_vex check when also checking
 521         vex.evex.
 522         (intel_operand_size, OP_E_memory): Drop vex.evex check when also
 523         checking vex.b.
 524
 525 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 526
 527         * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
 528         checks. Move case label past broadcast check.
 529
 530 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 531
 532         * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
 533         vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
 534         REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
 535         EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
 536         EVEX_W_0F38C7_M_0_L_2): Delete.
 537         (REG_EVEX_0F38C7_M_0_L_2): New.
 538         (intel_operand_size): Handle VEX and EVEX the same for
 539         vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
 540         vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
 541         (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
 542         vex_vsib_q_w_d_mode uses.
 543         * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
 544         0F38A1, and 0F38A3 entries.
 545         * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
 546         entry.
 547         * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
 548         * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
 549         0F38A3 entries.
 550
 551 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 552
 553         * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
 554         REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
 555         MOD_VEX_0FXOP_09_12): Rename to ...
 556         (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
 557         REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
 558         (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
 559         RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
 560         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 561         X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
 562         (reg_table): Adjust comments.
 563         (x86_64_table): Move X86_64_0F24, X86_64_0F26,
 564         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 565         X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
 566         (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
 567         (vex_len_table): Adjust opcode 0A_12 entry.
 568         (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
 569         MOD_C5_32BIT, and MOD_XOP_09_12 entries.
 570         (rm_table): Move hreset entry.
 571
 572 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 573
 574         * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
 575         EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
 576         EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
 577         EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
 578         EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
 579         (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
 580         (get_valid_dis386): Also handle 512-bit vector length when
 581         vectoring into vex_len_table[].
 582         * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
 583         0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
 584         entries.
 585         * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
 586         0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
 587         * i386-dis-evex-prefix.h: Adjust 0F7E entry.
 588         * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
 589         entries.
 590
 591 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 592
 593         * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
 594         Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
 595         EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
 596         * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
 597         entries.
 598         * i386-dis-evex-len.h (evex_len_table): Likewise.
 599         * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
 600
 601 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 602
 603         * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
 604         MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
 605         MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
 606         MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
 607         MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
 608         MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
 609         MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
 610         MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
 611         EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
 612         EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
 613         EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
 614         EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
 615         EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
 616         EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
 617         EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
 618         EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
 619         EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
 620         EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
 621         EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
 622         EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
 623         EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
 624         EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
 625         EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
 626         EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
 627         EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
 628         EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
 629         EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
 630         EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
 631         EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
 632         EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
 633         EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
 634         EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
 635         REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
 636         REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
 637         MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
 638         MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
 639         EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
 640         EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
 641         EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
 642         EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
 643         EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
 644         EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
 645         EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
 646         EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
 647         EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
 648         EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
 649         EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
 650         EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
 651         EVEX_W_0F3A43_L_n): New.
 652         * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
 653         0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
 654         0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
 655         * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
 656         for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
 657         0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
 658         0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
 659         * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
 660         0F385B, 0F38C6, and 0F38C7 entries.
 661         * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
 662         0F38C6 and 0F38C7.
 663         * i386-dis-evex-w.h: No longer link to evex_len_table[] for
 664         opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
 665         0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
 666         evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
 667
 668 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 669
 670         * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
 671         MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
 672         MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
 673         MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
 674         MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
 675         MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
 676         MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
 677         MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
 678         MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
 679         MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
 680         MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
 681         MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
 682         MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
 683         MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
 684         MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
 685         MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
 686         MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
 687         MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
 688         MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
 689         MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
 690         MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
 691         MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
 692         MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
 693         MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
 694         MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
 695         PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
 696         PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
 697         PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
 698         PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
 699         PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
 700         VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
 701         VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
 702         VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
 703         VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
 704         VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
 705         VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
 706         VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
 707         VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
 708         VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
 709         VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
 710         VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
 711         VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
 712         VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
 713         VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
 714         VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
 715         VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
 716         VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
 717         VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
 718         VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
 719         VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
 720         VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
 721         VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
 722         VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
 723         VEX_W_0F99_P_2_LEN_0): Delete.
 724         MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
 725         MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
 726         MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
 727         MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
 728         MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
 729         PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
 730         PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
 731         PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
 732         PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
 733         PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
 734         PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
 735         PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
 736         PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
 737         PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
 738         PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
 739         PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
 740         PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
 741         PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
 742         PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
 743         VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
 744         VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
 745         VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
 746         VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
 747         VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
 748         VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
 749         VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
 750         VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
 751         (prefix_table): No longer link to vex_len_table[] for opcodes
 752         0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
 753         0F92, 0F93, 0F98, and 0F99.
 754         (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
 755         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 756         0F98, and 0F99.
 757         (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
 758         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 759         0F98, and 0F99.
 760         (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
 761         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 762         0F98, and 0F99.
 763         (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
 764         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 765         0F98, and 0F99.
 766
 767 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 768
 769         * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
 770         Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
 771         REG_VEX_0F73_M_0 respectively.
 772         (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
 773         MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
 774         MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
 775         MOD_VEX_0F73_REG_7): Delete.
 776         (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
 777         (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
 778         PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
 779         PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
 780         PREFIX_VEX_0F3AF0_L_0 respectively.
 781         (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
 782         VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
 783         VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
 784         VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
 785         (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
 786         VEX_LEN_0F38F7): New.
 787         (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
 788         (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
 789         0F72, and 0F73. No longer link to vex_len_table[] for opcode
 790         0F38F3.
 791         (prefix_table): No longer link to vex_len_table[] for opcodes
 792         0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 793         (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
 794         0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
 795         0F38F6, 0F38F7, and 0F3AF0.
 796         (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
 797         prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 798         (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
 799         0F73.
 800
 801 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 802
 803         * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
 804         REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
 805         (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
 806         MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
 807         MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
 808         (MOD_0F71, MOD_0F72, MOD_0F73): New.
 809         (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
 810         73.
 811         (reg_table): No longer link to mod_table[] for opcodes 0F71,
 812         0F72, and 0F73.
 813         (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
 814         0F73.
 815
 816 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 817
 818         * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
 819         MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
 820         (reg_table): Don't link to mod_table[] where not needed. Add
 821         PREFIX_IGNORED to nop entries.
 822         (prefix_table): Replace PREFIX_OPCODE in nop entries.
 823         (mod_table): Add nop entries next to prefetch ones. Drop
 824         MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
 825         MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
 826         (rm_table): Add PREFIX_IGNORED to nop entries. Drop
 827         PREFIX_OPCODE from endbr* entries.
 828         (get_valid_dis386): Also consider entry's name when zapping
 829         vindex.
 830         (print_insn): Handle PREFIX_IGNORED.
 831
 832 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 833
 834         * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
 835         IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
 836         element.
 837         * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
 838         HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
 839         (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
 840         PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
 841         (struct i386_opcode_modifier): Delete notrackprefixok,
 842         islockable, hleprefixok, and repprefixok fields. Add prefixok
 843         field.
 844         * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
 845         HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
 846         (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
 847         not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
 848         Replace HLEPrefixOk.
 849         * opcodes/i386-tbl.h: Re-generate.
 850
 851 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 852
 853         * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
 854         * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
 855         64-bit form.
 856         * opcodes/i386-tbl.h: Re-generate.
 857
 858 2021-03-03  Jan Beulich  <jbeulich@suse.com>
 859
 860         * i386-gen.c (output_i386_opcode): Don't get operand count. Look
 861         for {} instead of {0}. Don't look for '0'.
 862         * i386-opc.tbl: Drop operand count field. Drop redundant operand
 863         size specifiers.
 864
 865 2021-02-19  Nelson Chu  <nelson.chu@sifive.com>
 866
 867         PR 27158
 868         * riscv-dis.c (print_insn_args): Updated encoding macros.
 869         * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
 870         (match_c_addi16sp): Updated encoding macros.
 871         (match_c_lui): Likewise.
 872         (match_c_lui_with_hint): Likewise.
 873         (match_c_addi4spn): Likewise.
 874         (match_c_slli): Likewise.
 875         (match_slli_as_c_slli): Likewise.
 876         (match_c_slli64): Likewise.
 877         (match_srxi_as_c_srxi): Likewise.
 878         (riscv_insn_types): Added .insn css/cl/cs.
 879
 880 2021-02-18  Nelson Chu  <nelson.chu@sifive.com>
 881
 882         * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
 883         (default_priv_spec): Updated type to riscv_spec_class.
 884         (parse_riscv_dis_option): Updated.
 885         * riscv-opc.c: Moved stuff and make the file tidy.
 886
 887 2021-02-17  Alan Modra  <amodra@gmail.com>
 888
 889         * wasm32-dis.c: Include limits.h.
 890         (CHAR_BIT): Provide backup define.
 891         (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
 892         Correct signed overflow checking.
 893
 894 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 895
 896         * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
 897         * i386-tbl.h: Re-generate.
 898
 899 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 900
 901         * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
 902         Oword.
 903         * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
 904
 905 2021-02-15  Andreas Krebbel  <krebbel@linux.ibm.com>
 906
 907         * s390-mkopc.c (main): Accept arch14 as cpu string.
 908         * s390-opc.txt: Add new arch14 instructions.
 909
 910 2021-02-04  Nick Alcock  <nick.alcock@oracle.com>
 911
 912         * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
 913         favour of LIBINTL.
 914         * configure: Regenerated.
 915
 916 2021-02-08  Mike Frysinger  <vapier@gentoo.org>
 917
 918         * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
 919         * tic54x-opc.c (regs): Rename to ...
 920         (tic54x_regs): ... this.
 921         (mmregs): Rename to ...
 922         (tic54x_mmregs): ... this.
 923         (condition_codes): Rename to ...
 924         (tic54x_condition_codes): ... this.
 925         (cc2_codes): Rename to ...
 926         (tic54x_cc2_codes): ... this.
 927         (cc3_codes): Rename to ...
 928         (tic54x_cc3_codes): ... this.
 929         (status_bits): Rename to ...
 930         (tic54x_status_bits): ... this.
 931         (misc_symbols): Rename to ...
 932         (tic54x_misc_symbols): ... this.
 933
 934 2021-02-04  Nelson Chu  <nelson.chu@sifive.com>
 935
 936         * riscv-opc.c (MASK_RVB_IMM): Removed.
 937         (riscv_opcodes): Removed zb* instructions.
 938         (riscv_ext_version_table): Removed versions for zb*.
 939
 940 2021-01-26  Alan Modra  <amodra@gmail.com>
 941
 942         * i386-gen.c (parse_template): Ensure entire template_instance
 943         is initialised.
 944
 945 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 946
 947         * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
 948         (riscv_fpr_names_abi): Likewise.
 949         (riscv_opcodes): Likewise.
 950         (riscv_insn_types): Likewise.
 951
 952 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 953
 954         * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
 955
 956 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 957
 958         * riscv-dis.c: Comments tidy and improvement.
 959         * riscv-opc.c: Likewise.
 960
 961 2021-01-13  Alan Modra  <amodra@gmail.com>
 962
 963         * Makefile.in: Regenerate.
 964
 965 2021-01-12  H.J. Lu  <hongjiu.lu@intel.com>
 966
 967         PR binutils/26792
 968         * configure.ac: Use GNU_MAKE_JOBSERVER.
 969         * aclocal.m4: Regenerated.
 970         * configure: Likewise.
 971
 972 2021-01-12  Nick Clifton  <nickc@redhat.com>
 973
 974         * po/sr.po: Updated Serbian translation.
 975
 976 2021-01-11  H.J. Lu  <hongjiu.lu@intel.com>
 977
 978         PR ld/27173
 979         * configure: Regenerated.
 980
 981 2021-01-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 982
 983         * aarch64-asm-2.c: Regenerate.
 984         * aarch64-dis-2.c: Likewise.
 985         * aarch64-opc-2.c: Likewise.
 986         * aarch64-opc.c (aarch64_print_operand):
 987         Delete handling of AARCH64_OPND_CSRE_CSR.
 988         * aarch64-tbl.h (aarch64_feature_csre): Delete.
 989         (CSRE): Likewise.
 990         (_CSRE_INSN): Likewise.
 991         (aarch64_opcode_table): Delete csr.
 992
 993 2021-01-11  Nick Clifton  <nickc@redhat.com>
 994
 995         * po/de.po: Updated German translation.
 996         * po/fr.po: Updated French translation.
 997         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 998         * po/sv.po: Updated Swedish translation.
 999         * po/uk.po: Updated Ukranian translation.
1000
1001 2021-01-09  H.J. Lu  <hongjiu.lu@intel.com>
1002
1003         * configure: Regenerated.
1004
1005 2021-01-09  Nick Clifton  <nickc@redhat.com>
1006
1007         * configure: Regenerate.
1008         * po/opcodes.pot: Regenerate.
1009
1010 2021-01-09  Nick Clifton  <nickc@redhat.com>
1011
1012         * 2.36 release branch crated.
1013
1014 2021-01-08  Peter Bergner  <bergner@linux.ibm.com>
1015
1016         * ppc-opc.c (insert_dw, (extract_dw): New functions.
1017         (DW, (XRC_MASK): Define.
1018         (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
1019
1020 2021-01-09  Alan Modra  <amodra@gmail.com>
1021
1022         * configure: Regenerate.
1023
1024 2021-01-08  Nick Clifton  <nickc@redhat.com>
1025
1026         * po/sv.po: Updated Swedish translation.
1027
1028 2021-01-08  Nick Clifton  <nickc@redhat.com>
1029
1030         PR 27129
1031         * aarch64-dis.c (determine_disassembling_preference): Move call to
1032         aarch64_match_operands_constraint outside of the assertion.
1033         * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
1034         Replace with a return of FALSE.
1035
1036         PR 27139
1037         * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
1038         core system register.
1039
1040 2021-01-07  Samuel Thibault  <samuel.thibault@gnu.org>
1041
1042         * configure: Regenerate.
1043
1044 2021-01-07  Nick Clifton  <nickc@redhat.com>
1045
1046         * po/fr.po: Updated French translation.
1047
1048 2021-01-07  Fredrik Noring  <noring@nocrew.org>
1049
1050         * m68k-opc.c (chkl): Change minimum architecture requirement to
1051         m68020.
1052
1053 2021-01-07  Philipp Tomsich  <prt@gnu.org>
1054
1055         * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
1056
1057 2021-01-07  Claire Xenia Wolf  <claire@symbioticeda.com>
1058             Jim Wilson  <jimw@sifive.com>
1059             Andrew Waterman  <andrew@sifive.com>
1060             Maxim Blinov  <maxim.blinov@embecosm.com>
1061             Kito Cheng  <kito.cheng@sifive.com>
1062             Nelson Chu  <nelson.chu@sifive.com>
1063
1064         * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
1065         (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
1066
1067 2021-01-01  Alan Modra  <amodra@gmail.com>
1068
1069         Update year range in copyright notice of all files.
1070
1071 For older changes see ChangeLog-2020
1072 \f
1073 Copyright (C) 2021 Free Software Foundation, Inc.
1074
1075 Copying and distribution of this file, with or without modification,
1076 are permitted in any medium without royalty provided the copyright
1077 notice and this notice are preserved.
1078
1079 Local Variables:
1080 mode: change-log
1081 left-margin: 8
1082 fill-column: 74
1083 version-control: never
1084 End: