opcodes/ChangeLog

   1 2013-10-08  Jan Beulich <jbeulich@suse.com>
   2
   3         * i386-opc.tbl (invlpg): Use Anysize instead of Unspecified.
   4         (clflush): Use Anysize instead of Byte|Unspecified.
   5         (prefetch*): Likewise.
   6         * i386-tbl.h: Re-generate.
   7
   8 2013-10-07  Chao-ying Fu  <Chao-ying.Fu@imgtec.com>
   9
  10         * micromips-opc.c (micromips_opcodes): Fix dmfgc0 and dmtgc0.
  11
  12 2013-09-30  H.J. Lu  <hongjiu.lu@intel.com>
  13
  14         * i386-opc.tbl: Add Size64 to movq/vmovq with Reg64 operand.
  15         * i386-init.h: Regenerated.
  16
  17 2013-09-30  Saravanan Ekanathan <saravanan.ekanathan@amd.com>
  18
  19         * i386-gen.c (cpu_flag_init): Add CPU_BDVER4_FLAGS.
  20         * i386-init.h: Regenerated.
  21
  22 2013-09-20  Alan Modra  <amodra@gmail.com>
  23
  24         * configure: Regenerate.
  25
  26 2013-09-17  Richard Sandiford  <rsandifo@linux.vnet.ibm.com>
  27
  28         * s390-opc.txt (clih): Make the immediate unsigned.
  29
  30 2013-09-04  Roland McGrath  <mcgrathr@google.com>
  31
  32         PR gas/15914
  33         * arm-dis.c (arm_opcodes): Add udf.
  34         (thumb_opcodes): Use "udf" mnemonic rather than UNDEFINED_INSTRUCTION.
  35         (thumb32_opcodes): Add udf.w.
  36         (print_insn_thumb32): Handle %H as the thumb32_opcodes comment says.
  37
  38 2013-09-02  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
  39
  40         * s390-opc.txt: Fix description for fiebra, fidbra, and fixbra.
  41         For the load fp integer instructions only the suppression flag was
  42         new with z196 version.
  43
  44 2013-08-28  Nick Clifton  <nickc@redhat.com>
  45
  46         * aarch64-opc.c (aarch64_logical_immediate_p): Return FALSE if the
  47         immediate is not suitable for the 32-bit ABI.
  48
  49 2013-08-23  Maciej W. Rozycki  <macro@codesourcery.com>
  50
  51         * micromips-opc.c (micromips_opcodes): Use RD_4 for "alnv.ps",
  52         replacing NODS.
  53
  54 2013-08-23  Yuri Chornoivan  <yurchor@ukr.net>
  55
  56         PR binutils/15834
  57         * aarch64-asm.c: Fix typos.
  58         * aarch64-dis.c: Likewise.
  59         * msp430-dis.c: Likewise.
  60
  61 2013-08-19  Richard Sandiford  <rdsandiford@googlemail.com>
  62
  63         * micromips-opc.c (micromips_opcodes): Replace "dext" and "dins"
  64         macro entries with "dextm", "dextu", "dinsm" and "dinsu" aliases.
  65         Use +H rather than +C for the real "dext".
  66         * mips-opc.c (mips_builtin_opcodes): Likewise.
  67
  68 2013-08-19  Richard Sandiford  <rdsandiford@googlemail.com>
  69
  70         * mips-formats.h (OPTIONAL_REG, OPTIONAL_MAPPED_REG): New macros.
  71         * micromips-opc.c (decode_micromips_operand): Use OPTIONAL_REG
  72         and OPTIONAL_MAPPED_REG.
  73         * mips-opc.c (decode_mips_operand): Likewise.
  74         * mips16-opc.c (decode_mips16_operand): Likewise.
  75         * mips-dis.c (print_insn_arg): Handle OP_OPTIONAL_REG.
  76
  77 2013-08-19  H.J. Lu  <hongjiu.lu@intel.com>
  78
  79         * i386-dis.c (PREFIX_EVEX_0F3A3E): Removed.
  80         (PREFIX_EVEX_0F3A3F): Likewise.
  81         * i386-dis-evex.h (evex_table): Updated.
  82
  83 2013-08-06  Jürgen Urban  <JuergenUrban@gmx.de>
  84
  85         * mips-opc.c (mips_builtin_opcodes): Add a suffixless version of
  86         VCLIPW.
  87
  88 2013-08-05  Eric Botcazou  <ebotcazou@adacore.com>
  89             Konrad Eisele  <konrad@gaisler.com>
  90
  91         * sparc-dis.c (compute_arch_mask): Set SPARC_OPCODE_ARCH_LEON bit for
  92         bfd_mach_sparc.
  93         * sparc-opc.c (MASK_LEON): Define.
  94         (v6, v6notlet, v7, v8, v6notv9): Add MASK_LEON.
  95         (letandleon): New macro.
  96         (v9andleon): Likewise.
  97         (sparc_opc): Add leon.
  98         (umac): Enable for letandleon.
  99         (smac): Likewise.
 100         (casa): Enable for v9andleon.
 101         (cas): Likewise.
 102         (casl): Likewise.
 103
 104 2013-08-04  Jürgen Urban  <JuergenUrban@gmx.de>
 105             Richard Sandiford  <rdsandiford@googlemail.com>
 106
 107         * mips-dis.c (print_reg): Handle OP_REG_VI, OP_REG_VF, OP_REG_R5900_I,
 108         OP_REG_R5900_Q, OP_REG_R5900_R and OP_REG_R5900_ACC.
 109         (print_vu0_channel): New function.
 110         (print_insn_arg): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX.
 111         (print_insn_args): Handle '#'.
 112         (print_insn_mips): Handle INSN2_VU0_CHANNEL_SUFFIX.
 113         * mips-opc.c (mips_vu0_channel_mask): New constant.
 114         (decode_mips_operand): Handle new VU0 operand types.
 115         (VU0, VU0CH): New macros.
 116         (mips_builtin_opcodes): Add VU0 opcodes.  Use "+7" rather than "E"
 117         for LQC2 and SQC2.  Use "+9" rather than "G" for EE CFC2 and CTC2.
 118         Use "+6" rather than "G" for QMFC2 and QMTC2.
 119
 120 2013-08-03  Richard Sandiford  <rdsandiford@googlemail.com>
 121
 122         * mips-formats.h (PCREL): Reorder parameters and update the definition
 123         to match new mips_pcrel_operand layout.
 124         (JUMP, JALX, BRANCH): Update accordingly.
 125         * mips16-opc.c (decode_mips16_operand): Likewise.
 126
 127 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 128
 129         * micromips-opc.c (WR_s): Delete.
 130
 131 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 132
 133         * mips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2, UDI):
 134         New macros.
 135         (WR_d, WR_t, WR_D, WR_T, WR_S, RD_s, RD_b, RD_t, RD_S, RD_T, RD_R)
 136         (WR_z, WR_Z, RD_z, RD_Z, RD_d): Delete.
 137         (mips_builtin_opcodes): Use the new position-based read-write flags
 138         instead of field-based ones.  Use UDI for "udi..." instructions.
 139         * mips16-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
 140         New macros.
 141         (WR_x, WR_y, WR_z, WR_Y, RD_x, RD_y, RD_Z, RD_X): Delete.
 142         (RD_T, WR_T, WR_31): Redefine using generic INSN_* flags.
 143         (WR_SP, RD_16): New macros.
 144         (RD_SP): Redefine as an INSN2_* flag.
 145         (MOD_SP): Redefine in terms of RD_SP and WR_SP.
 146         (mips16_opcodes): Use the new position-based read-write flags
 147         instead of field-based ones.  Use RD_16 for "nop".  Move RD_SP to
 148         pinfo2 field.
 149         * micromips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
 150         New macros.
 151         (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf, RD_mg, WR_mh, RD_mj)
 152         (WR_mj, RD_ml, RD_mmn, RD_mp, WR_mp, RD_mq, RD_gp, WR_d, WR_t, WR_D)
 153         (WR_T, WR_S, RD_s, RD_b, RD_t, RD_T, RD_S, RD_R, RD_D): Delete.
 154         (RD_sp, WR_sp): Redefine to INSN2_READ_SP and INSN2_WRITE_SP.
 155         (micromips_opcodes): Use the new position-based read-write flags
 156         instead of field-based ones.
 157         * mips-dis.c (print_insn_arg): Use mips_decode_reg_operand.
 158         (print_insn_mips, print_insn_micromips): Use INSN_WRITE_1 instead
 159         of field-based flags.
 160
 161 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 162
 163         * mips16-opc.c (UBR, CBR, RD_31, RD_PC): Redefine as INSN2_* flags.
 164         (WR_SP): Replace with...
 165         (MOD_SP): ...this.
 166         (mips16_opcodes): Update accordingly.
 167         * mips-dis.c (print_insn_mips16): Likewise.
 168
 169 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 170
 171         * mips16-opc.c (mips16_opcodes): Reformat.
 172
 173 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 174
 175         * mips-opc.c (mips_builtin_opcodes): Remove WR_* and RD_* flags
 176         for operands that are hard-coded to $0.
 177         * micromips-opc.c (micromips_opcodes): Likewise.
 178
 179 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 180
 181         * mips-opc.c (mips_builtin_opcodes): Use WR_31 rather than WR_d
 182         for the single-operand forms of JALR and JALR.HB.
 183         * micromips-opc.c (micromips_opcodes): Likewise JALR, JALRS, JALR.HB
 184         and JALRS.HB.
 185
 186 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 187
 188         * mips-opc.c (mips_builtin_opcodes): Add FP_D to VR5400 vector
 189         instructions.  Fix them to use WR_MACC instead of WR_CC and
 190         add missing RD_MACCs.
 191
 192 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 193
 194         * mips-dis.c (print_mips16_insn_arg): Include ISA bit in base address.
 195
 196 2013-07-29  Peter Bergner <bergner@vnet.ibm.com>
 197
 198         * ppc-dis.c (powerpc_init_dialect): Use ppc_parse_cpu() to set dialect.
 199
 200 2013-07-26  Sergey Guriev  <sergey.s.guriev@intel.com>
 201             Alexander Ivchenko  <alexander.ivchenko@intel.com>
 202             Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
 203             Sergey Lega  <sergey.s.lega@intel.com>
 204             Anna Tikhonova  <anna.tikhonova@intel.com>
 205             Ilya Tocar  <ilya.tocar@intel.com>
 206             Andrey Turetskiy  <andrey.turetskiy@intel.com>
 207             Ilya Verbin  <ilya.verbin@intel.com>
 208             Kirill Yukhin  <kirill.yukhin@intel.com>
 209             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 210
 211         * i386-dis-evex.h: New.
 212         * i386-dis.c (OP_Rounding): New.
 213         (VPCMP_Fixup): New.
 214         (OP_Mask): New.
 215         (Rdq): New.
 216         (XMxmmq): New.
 217         (EXdScalarS): New.
 218         (EXymm): New.
 219         (EXEvexHalfBcstXmmq): New.
 220         (EXxmm_mdq): New.
 221         (EXEvexXGscat): New.
 222         (EXEvexXNoBcst): New.
 223         (VPCMP): New.
 224         (EXxEVexR): New.
 225         (EXxEVexS): New.
 226         (XMask): New.
 227         (MaskG): New.
 228         (MaskE): New.
 229         (MaskR): New.
 230         (MaskVex): New.
 231         (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode,
 232         evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode,
 233         evex_rounding_mode, evex_sae_mode, mask_mode.
 234         (USE_EVEX_TABLE): New.
 235         (EVEX_TABLE): New.
 236         (EVEX enum): New.
 237         (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6,
 238         REG_EVEX_0F38C7.
 239         (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3,
 240         MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3,
 241         MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1,
 242         MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
 243         MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,  MOD_EVEX_0F38C7_REG_5,
 244         MOD_EVEX_0F38C7_REG_6.
 245         (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
 246         PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B,
 247         PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
 248         PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32,
 249         PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11,
 250         PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14,
 251         PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17,
 252         PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A,
 253         PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
 254         PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51,
 255         PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A,
 256         PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D,
 257         PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62,
 258         PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C,
 259         PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F,
 260         PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
 261         PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
 262         PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
 263         PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78,
 264         PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B,
 265         PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2,
 266         PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3,
 267         PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB,
 268         PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7,
 269         PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2,
 270         PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB,
 271         PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D,
 272         PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813,
 273         PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816,
 274         PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A,
 275         PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F,
 276         PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823,
 277         PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827,
 278         PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A,
 279         PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831,
 280         PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834,
 281         PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
 282         PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B,
 283         PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840,
 284         PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844,
 285         PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847,
 286         PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E,
 287         PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859,
 288         PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864,
 289         PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877,
 290         PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F,
 291         PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
 292         PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891,
 293         PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896,
 294         PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899,
 295         PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C,
 296         PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F,
 297         PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2,
 298         PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7,
 299         PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA,
 300         PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD,
 301         PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6,
 302         PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9,
 303         PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC,
 304         PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF,
 305         PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1,
 306         PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5,
 307         PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1,
 308         PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5,
 309         PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA,
 310         PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD,
 311         PREFIX_EVEX_0F3A00,  PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03,
 312         PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08,
 313         PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B,
 314         PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19,
 315         PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D,
 316         PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21,
 317         PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26,
 318         PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39,
 319         PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E,
 320         PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54,
 321         PREFIX_EVEX_0F3A55.
 322         (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0,
 323         VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0,
 324         VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0,
 325         VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0,
 326         VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1,
 327         VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1,
 328         VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1,
 329         VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0,
 330         VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0,
 331         VEX_W_0F3A32_P_2_LEN_0.
 332         (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0,
 333         EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0,
 334         EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0,
 335         EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0,
 336         EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1,
 337         EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
 338         EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0,
 339         EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1,
 340         EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
 341         EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2,
 342         EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
 343         EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2,
 344         EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3,
 345         EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3,
 346         EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3,
 347         EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3,
 348         EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0,
 349         EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0,
 350         EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0,
 351         EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0,
 352         EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2,
 353         EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2,
 354         EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2,
 355         EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2,
 356         EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0,
 357         EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1,
 358         EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1,
 359         EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2,
 360         EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2,
 361         EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1,
 362         EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2,
 363         EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2,
 364         EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2,
 365         EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1,
 366         EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1,
 367         EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2,
 368         EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
 369         EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1,
 370         EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2,
 371         EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1,
 372         EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1,
 373         EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1,
 374         EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1,
 375         EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2,
 376         EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2,
 377         EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
 378         EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2,
 379         EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
 380         EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
 381         EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2,
 382         EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
 383         EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2,
 384         EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2,
 385         EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2.
 386         (struct vex): Add fields evex, r, v, mask_register_specifier,
 387         zeroing, ll, b.
 388         (intel_names_xmm): Add upper 16 registers.
 389         (att_names_xmm): Ditto.
 390         (intel_names_ymm): Ditto.
 391         (att_names_ymm): Ditto.
 392         (names_zmm): New.
 393         (intel_names_zmm): Ditto.
 394         (att_names_zmm): Ditto.
 395         (names_mask): Ditto.
 396         (intel_names_mask): Ditto.
 397         (att_names_mask): Ditto.
 398         (names_rounding): Ditto.
 399         (names_broadcast): Ditto.
 400         (x86_64_table): Add escape to evex-table.
 401         (reg_table): Include reg_table evex-entries from
 402         i386-dis-evex.h.  Fix prefetchwt1 instruction.
 403         (prefix_table): Add entries for new instructions.
 404         (vex_table): Ditto.
 405         (vex_len_table): Ditto.
 406         (vex_w_table): Ditto.
 407         (mod_table): Ditto.
 408         (get_valid_dis386): Properly handle new instructions.
 409         (print_insn): Handle zmm and mask registers, print mask operand.
 410         (intel_operand_size): Support EVEX, new modes and sizes.
 411         (OP_E_register): Handle new modes.
 412         (OP_E_memory): Ditto.
 413         (OP_G): Ditto.
 414         (OP_XMM): Ditto.
 415         (OP_EX): Ditto.
 416         (OP_VEX): Ditto.
 417         * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and
 418         CPU_ANY_AVX_FLAGS.  Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS,
 419         CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
 420         (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER,
 421         CpuAVX512PF and CpuVREX.
 422         (operand_type_init): Add OPERAND_TYPE_REGZMM,
 423         OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8.
 424         (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast,
 425         StaticRounding, SAE, Disp8MemShift, NoDefMask.
 426         (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword.
 427         * i386-init.h: Regenerate.
 428         * i386-opc.h (CpuAVX512F): New.
 429         (CpuAVX512CD): New.
 430         (CpuAVX512ER): New.
 431         (CpuAVX512PF): New.
 432         (CpuVREX): New.
 433         (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er,
 434         cpuavx512pf and cpuvrex fields.
 435         (VecSIB): Add VecSIB512.
 436         (EVex): New.
 437         (Masking): New.
 438         (VecESize): New.
 439         (Broadcast): New.
 440         (StaticRounding): New.
 441         (SAE): New.
 442         (Disp8MemShift): New.
 443         (NoDefMask): New.
 444         (i386_opcode_modifier): Add evex, masking, vecesize, broadcast,
 445         staticrounding, sae, disp8memshift and nodefmask.
 446         (RegZMM): New.
 447         (Zmmword): Ditto.
 448         (Vec_Disp8): Ditto.
 449         (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8
 450         fields.
 451         (RegVRex): New.
 452         * i386-opc.tbl: Add AVX512 instructions.
 453         * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM
 454         registers, mask registers.
 455         * i386-tbl.h: Regenerate.
 456
 457 2013-07-25  Aaro Koskinen  <aaro.koskinen@iki.fi>
 458
 459         PR gas/15220
 460         * mips-opc.c (mips_builtin_opcodes): Fix wrong opcodes for
 461         Loongson 2F madd.ps, msub.ps, nmadd.ps and nmsub.ps.
 462
 463 2013-07-25  Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 464
 465         * i386-dis.c (PREFIX enum): Add PREFIX_0F38C8, PREFIX_0F38C9,
 466         PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC, PREFIX_0F38CD,
 467         PREFIX_0F3ACC.
 468         (prefix_table): Updated.
 469         (three_byte_table): Likewise.
 470         * i386-gen.c (cpu_flag_init): Add CPU_SHA_FLAGS.
 471         (cpu_flags): Add CpuSHA.
 472         (i386_cpu_flags): Add cpusha.
 473         * i386-init.h: Regenerate.
 474         * i386-opc.h (CpuSHA): New.
 475         (CpuUnused): Restored.
 476         (i386_cpu_flags): Add cpusha.
 477         * i386-opc.tbl: Add SHA instructions.
 478         * i386-tbl.h: Regenerate.
 479
 480 2013-07-24  Anna Tikhonova  <anna.tikhonova@intel.com>
 481             Kirill Yukhin  <kirill.yukhin@intel.com>
 482             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 483
 484         * i386-dis.c (BND_Fixup): New.
 485         (Ebnd): New.
 486         (Ev_bnd): New.
 487         (Gbnd): New.
 488         (BND): New.
 489         (v_bnd_mode): New.
 490         (bnd_mode): New.
 491         (MOD enum): Add MOD_0F1A_PREFIX_0, MOD_0F1B_PREFIX_0,
 492         MOD_0F1B_PREFIX_1.
 493         (PREFIX enum): Add PREFIX_0F1A, PREFIX_0F1B.
 494         (dis tables): Replace XX with BND for near branch and call
 495         instructions.
 496         (prefix_table): Add new entries.
 497         (mod_table): Likewise.
 498         (names_bnd): New.
 499         (intel_names_bnd): New.
 500         (att_names_bnd): New.
 501         (BND_PREFIX): New.
 502         (prefix_name): Handle BND_PREFIX.
 503         (print_insn): Initialize names_bnd.
 504         (intel_operand_size): Handle new modes.
 505         (OP_E_register): Likewise.
 506         (OP_E_memory): Likewise.
 507         (OP_G): Likewise.
 508         * i386-gen.c (cpu_flag_init): Add CpuMPX.
 509         (cpu_flags): Add CpuMPX.
 510         (operand_type_init): Add RegBND.
 511         (opcode_modifiers): Add BNDPrefixOk.
 512         (operand_types): Add RegBND.
 513         * i386-init.h: Regenerate.
 514         * i386-opc.h (CpuMPX): New.
 515         (CpuUnused): Comment out.
 516         (i386_cpu_flags): Add cpumpx.
 517         (BNDPrefixOk): New.
 518         (i386_opcode_modifier): Add bndprefixok.
 519         (RegBND): New.
 520         (i386_operand_type): Add regbnd.
 521         * i386-opc.tbl: Add BNDPrefixOk to near jumps, calls and rets.
 522         Add MPX instructions and bnd prefix.
 523         * i386-reg.tbl: Add bnd0-bnd3 registers.
 524         * i386-tbl.h: Regenerate.
 525
 526 2013-07-17  Richard Sandiford  <rdsandiford@googlemail.com>
 527
 528         * mips-formats.h (MAPPED_INT, MAPPED_REG, REG_PAIR): Add
 529         ATTRIBUTE_UNUSED.
 530
 531 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 532
 533         * Makefile.am (mips-opc.lo, micromips-opc.lo, mips16-opc.lo): Remove
 534         special rules.
 535         * Makefile.in: Regenerate.
 536         * mips-opc.c, micromips-opc.c, mips16-opc.c: Explicitly initialize
 537         all fields.  Reformat.
 538
 539 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 540
 541         * mips16-opc.c: Include mips-formats.h.
 542         (reg_0_map, reg_29_map, reg_31_map, reg_m16_map, reg32r_map): New
 543         static arrays.
 544         (decode_mips16_operand): New function.
 545         * mips-dis.c (mips16_to_32_reg_map, mips16_reg_names): Delete.
 546         (print_insn_arg): Handle OP_ENTRY_EXIT list.
 547         Abort for OP_SAVE_RESTORE_LIST.
 548         (print_mips16_insn_arg): Change interface.  Use mips_operand
 549         structures.  Delete GET_OP_S.  Move GET_OP definition to...
 550         (print_insn_mips16): ...here.  Call init_print_arg_state.
 551         Update the call to print_mips16_insn_arg.
 552
 553 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 554
 555         * mips-formats.h: New file.
 556         * mips-opc.c: Include mips-formats.h.
 557         (reg_0_map): New static array.
 558         (decode_mips_operand): New function.
 559         * micromips-opc.c: Remove <stdio.h> include.  Include mips-formats.h.
 560         (reg_0_map, reg_28_map, reg_29_map, reg_31_map, reg_m16_map)
 561         (reg_mn_map, reg_q_map, reg_h_map1, reg_h_map2, int_b_map)
 562         (int_c_map): New static arrays.
 563         (decode_micromips_operand): New function.
 564         * mips-dis.c (micromips_to_32_reg_b_map, micromips_to_32_reg_c_map)
 565         (micromips_to_32_reg_d_map, micromips_to_32_reg_e_map)
 566         (micromips_to_32_reg_f_map, micromips_to_32_reg_g_map)
 567         (micromips_to_32_reg_h_map1, micromips_to_32_reg_h_map2)
 568         (micromips_to_32_reg_l_map, micromips_to_32_reg_m_map)
 569         (micromips_to_32_reg_n_map, micromips_to_32_reg_q_map)
 570         (micromips_imm_b_map, micromips_imm_c_map): Delete.
 571         (print_reg): New function.
 572         (mips_print_arg_state): New structure.
 573         (init_print_arg_state, print_insn_arg): New functions.
 574         (print_insn_args): Change interface and use mips_operand structures.
 575         Delete GET_OP_S.  Move GET_OP definition to...
 576         (print_insn_mips): ...here.  Update the call to print_insn_args.
 577         (print_insn_micromips): Use print_insn_args.
 578
 579 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 580
 581         * mips16-opc.c (mips16_opcodes): Use "I" for immediate operands
 582         in macros.
 583
 584 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 585
 586         * mips-opc.c (mips_builtin_opcodes): Use "S,T" rather than "V,T" for
 587         ADDA.S, MULA.S and SUBA.S.
 588
 589 2013-07-08  H.J. Lu  <hongjiu.lu@intel.com>
 590
 591         PR gas/13572
 592         * i386-opc.tbl: Replace Xmmword with Qword on cvttps2pi.
 593         * i386-tbl.h: Regenerated.
 594
 595 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 596
 597         * mips-opc.c (mips_builtin_opcodes): Remove o(b) macros.  Move LD
 598         and SD A(B) macros up.
 599         * micromips-opc.c (micromips_opcodes): Likewise.
 600
 601 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 602
 603         * mips16-opc.c: Add entries for argumentless "entry" and "exit"
 604         instructions.
 605
 606 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 607
 608         * mips-opc.c (mips_builtin_opcodes): Use "Q" for the INSN_5400
 609         MDMX-like instructions.
 610         * mips-dis.c (print_insn_arg): Use "$f" rather than "$v" when
 611         printing "Q" operands for INSN_5400 instructions.
 612
 613 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 614
 615         * mips-opc.c (mips_builtin_opcodes): Use "+s" for "cins32" and
 616         "+S" for "cins".
 617         * mips-dis.c (print_mips_arg): Update "+s" and "+S" comments.
 618         Combine cases.
 619
 620 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 621
 622         * mips-opc.c (mips_builtin_opcodes): Use "+i" rather than "a" for
 623         "jalx".
 624         * mips16-opc.c (mips16_opcodes): Likewise.
 625         * micromips-opc.c (micromips_opcodes): Likewise.
 626         * mips-dis.c (print_insn_args, print_mips16_insn_arg)
 627         (print_insn_mips16): Handle "+i".
 628         (print_insn_micromips): Likewise.  Conditionally preserve the
 629         ISA bit for "a" but not for "+i".
 630
 631 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 632
 633         * micromips-opc.c (WR_mhi): Rename to..
 634         (WR_mh): ...this.
 635         (micromips_opcodes): Update "movep" entry accordingly.  Replace
 636         "mh,mi" with "mh".
 637         * mips-dis.c (micromips_to_32_reg_h_map): Rename to...
 638         (micromips_to_32_reg_h_map1): ...this.
 639         (micromips_to_32_reg_i_map): Rename to...
 640         (micromips_to_32_reg_h_map2): ...this.
 641         (print_micromips_insn): Remove "mi" case.  Print both registers
 642         in the pair for "mh".
 643
 644 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 645
 646         * mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries.
 647         * micromips-opc.c (micromips_opcodes): Likewise.
 648         * mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D"
 649         and "+T" handling.  Check for a "0" suffix when deciding whether to
 650         use coprocessor 0 names.  In that case, also check for ",H" selectors.
 651
 652 2013-07-05  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 653
 654         * s390-opc.c (J12_12, J24_24): New macros.
 655         (INSTR_MII_UPI): Rename to INSTR_MII_UPP.
 656         (MASK_MII_UPI): Rename to MASK_MII_UPP.
 657         * s390-opc.txt: Rename MII_UPI to MII_UPP for bprp instruction.
 658
 659 2013-07-04  Alan Modra  <amodra@gmail.com>
 660
 661         * ppc-opc.c (powerpc_opcodes): Add tdui, twui, tdu, twu, tui, tu.
 662
 663 2013-06-26  Nick Clifton  <nickc@redhat.com>
 664
 665         * rx-decode.opc (rx_decode_opcode): Check sd field as well as ss
 666         field when checking for type 2 nop.
 667         * rx-decode.c: Regenerate.
 668
 669 2013-06-25  Maciej W. Rozycki  <macro@codesourcery.com>
 670
 671         * micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc"
 672         and "movep" macros.
 673
 674 2013-06-24  Maciej W. Rozycki  <macro@codesourcery.com>
 675
 676         * mips-dis.c (is_mips16_plt_tail): New function.
 677         (print_insn_mips16): Handle MIPS16 PLT entry's GOT slot address
 678         word.
 679         (is_compressed_mode_p): Handle MIPS16/microMIPS PLT entries.
 680
 681 2013-06-21  DJ Delorie  <dj@redhat.com>
 682
 683         * msp430-decode.opc: New.
 684         * msp430-decode.c: New/generated.
 685         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add msp430-decode.c.
 686         (MAINTAINER_CLEANFILES): Likewise.
 687         Add rule to build msp430-decode.c frommsp430decode.opc
 688         using the opc2c program.
 689         * Makefile.in: Regenerate.
 690         * configure.in: Add msp430-decode.lo to msp430 architecture files.
 691         * configure: Regenerate.
 692
 693 2013-06-20  Yufeng Zhang  <yufeng.zhang@arm.com>
 694
 695         * aarch64-dis.c (EMBEDDED_ENV): Remove the check on it.
 696         (SYMTAB_AVAILABLE): Removed.
 697         (#include "elf/aarch64.h): Ditto.
 698
 699 2013-06-17  Catherine Moore  <clm@codesourcery.com>
 700             Maciej W. Rozycki  <macro@codesourcery.com>
 701             Chao-Ying Fu  <fu@mips.com>
 702
 703         * micromips-opc.c (EVA): Define.
 704         (TLBINV): Define.
 705         (micromips_opcodes): Add EVA opcodes.
 706         * mips-dis.c (mips_arch_choices): Update for ASE_EVA.
 707         (print_insn_args): Handle EVA offsets.
 708         (print_insn_micromips): Likewise.
 709         * mips-opc.c (EVA): Define.
 710         (TLBINV): Define.
 711         (mips_builtin_opcodes): Add EVA opcodes.
 712
 713 2013-06-17  Alan Modra  <amodra@gmail.com>
 714
 715         * Makefile.am (mips-opc.lo): Add rules to create automatic
 716         dependency files.  Pass archdefs.
 717         (micromips-opc.lo, mips16-opc.lo): Likewise.
 718         * Makefile.in: Regenerate.
 719
 720 2013-06-14  DJ Delorie  <dj@redhat.com>
 721
 722         * rx-decode.opc (rx_decode_opcode): Bit operations on
 723         registers are 32-bit operations, not 8-bit operations.
 724         * rx-decode.c: Regenerate.
 725
 726 2013-06-13  Chao-ying Fu  <Chao-ying.Fu@imgtec.com>
 727
 728         * micromips-opc.c (IVIRT): New define.
 729         (IVIRT64): New define.
 730         (micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
 731         tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions.
 732
 733         * mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0,
 734         dmtgc0 to print cp0 names.
 735
 736 2013-06-09  Sandra Loosemore  <sandra@codesourcery.com>
 737
 738         * nios2-opc.c (nios2_builtin_opcodes): Give "trap" a type-"b"
 739         argument.
 740
 741 2013-06-08  Catherine Moore  <clm@codesourcery.com>
 742             Richard Sandiford  <rdsandiford@googlemail.com>
 743
 744         * micromips-opc.c (D32, D33, MC): Update definitions.
 745         (micromips_opcodes):  Initialize ase field.
 746         * mips-dis.c (mips_arch_choice): Add ase field.
 747         (mips_arch_choices): Initialize ase field.
 748         (set_default_mips_dis_options): Declare and setup mips_ase.
 749         * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
 750         MT32, MC): Update definitions.
 751         (mips_builtin_opcodes): Initialize ase field.
 752
 753 2013-05-24  Richard Sandiford  <rsandifo@linux.vnet.ibm.com>
 754
 755         * s390-opc.txt (flogr): Require a register pair destination.
 756
 757 2013-05-23  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 758
 759         * s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU
 760         instruction format.
 761
 762 2013-05-22  Jürgen Urban  <JuergenUrban@gmx.de>
 763
 764         * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
 765
 766 2013-05-20  Peter Bergner <bergner@vnet.ibm.com>
 767
 768         * ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
 769         * ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
 770         XLS_MASK, PPCVSX2): New defines.
 771         (powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
 772         fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
 773         mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
 774         mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
 775         mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
 776         vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
 777         vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
 778         vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
 779         vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
 780         vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
 781         vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
 782         vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
 783         vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
 784         vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
 785         xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
 786         xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
 787         xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
 788         xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
 789         <lxvx, stxvx>: New extended mnemonics.
 790
 791 2013-05-17  Alan Modra  <amodra@gmail.com>
 792
 793         * ia64-raw.tbl: Replace non-ASCII char.
 794         * ia64-waw.tbl: Likewise.
 795         * ia64-asmtab.c: Regenerate.
 796
 797 2013-05-15  Saravanan Ekanathan <saravanan.ekanathan@amd.com>
 798
 799         * i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
 800         * i386-init.h: Regenerated.
 801
 802 2013-05-13  Yufeng Zhang  <yufeng.zhang@arm.com>
 803
 804         * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
 805         * aarch64-opc.c (operand_general_constraint_met_p): Relax the range
 806         check from [0, 255] to [-128, 255].
 807
 808 2013-05-09  Andrew Pinski  <apinski@cavium.com>
 809
 810         * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
 811         Add INSN_VIRT and INSN_VIRT64 to mips64r2.
 812         (parse_mips_dis_option): Handle the virt option.
 813         (print_insn_args): Handle "+J".
 814         (print_mips_disassembler_options): Print out message about virt64.
 815         * mips-opc.c (IVIRT): New define.
 816         (IVIRT64): New define.
 817         (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
 818         tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
 819         Move rfe to the bottom as it conflicts with tlbgp.
 820
 821 2013-05-09  Alan Modra  <amodra@gmail.com>
 822
 823         * ppc-opc.c (extract_vlesi): Properly sign extend.
 824         (extract_vlensi): Likewise.  Comment reason for setting invalid.
 825
 826 2013-05-02  Nick Clifton  <nickc@redhat.com>
 827
 828         * msp430-dis.c: Add support for MSP430X instructions.
 829
 830 2013-04-24  Sandra Loosemore  <sandra@codesourcery.com>
 831
 832         * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
 833         to "eccinj".
 834
 835 2013-04-17  Wei-chen Wang  <cole945@gmail.com>
 836
 837         PR binutils/15369
 838         * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
 839         of CGEN_CPU_ENDIAN.
 840         (hash_insns_list): Likewise.
 841
 842 2013-04-10  Jan Kratochvil  <jan.kratochvil@redhat.com>
 843
 844         * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
 845         warning workaround.
 846
 847 2013-04-08  Jan Beulich <jbeulich@suse.com>
 848
 849         * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
 850         * i386-tbl.h: Re-generate.
 851
 852 2013-04-06  David S. Miller  <davem@davemloft.net>
 853
 854         * sparc-dis.c (compare_opcodes): When encountering multiple aliases
 855         of an opcode, prefer the one with F_PREFERRED set.
 856         * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
 857         lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
 858         ops.  Make 64-bit VIS logical ops have "d" suffix in their names,
 859         mark existing mnenomics as aliases.  Add "cc" suffix to edge
 860         instructions generating condition codes, mark existing mnenomics
 861         as aliases.  Add "fp" prefix to VIS compare instructions, mark
 862         existing mnenomics as aliases.
 863
 864 2013-04-03  Nick Clifton  <nickc@redhat.com>
 865
 866         * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
 867         destination address by subtracting the operand from the current
 868         address.
 869         * v850-opc.c (insert_u16_loop): Disallow negative offsets.  Store
 870         a positive value in the insn.
 871         (extract_u16_loop): Do not negate the returned value.
 872         (D16_LOOP): Add V850_INVERSE_PCREL flag.
 873
 874         (ceilf.sw): Remove duplicate entry.
 875         (cvtf.hs): New entry.
 876         (cvtf.sh): Likewise.
 877         (fmaf.s): Likewise.
 878         (fmsf.s): Likewise.
 879         (fnmaf.s): Likewise.
 880         (fnmsf.s): Likewise.
 881         (maddf.s): Restrict to E3V5 architectures.
 882         (msubf.s): Likewise.
 883         (nmaddf.s): Likewise.
 884         (nmsubf.s): Likewise.
 885
 886 2013-03-27  H.J. Lu  <hongjiu.lu@intel.com>
 887
 888         * i386-dis.c (get_sib): Add the sizeflag argument.  Properly
 889         check address mode.
 890         (print_insn): Pass sizeflag to get_sib.
 891
 892 2013-03-27  Alexis Deruelle  <alexis.deruelle@gmail.com>
 893
 894         PR binutils/15068
 895         * tic6x-dis.c: Add support for displaying 16-bit insns.
 896
 897 2013-03-20  Alexis Deruelle  <alexis.deruelle@gmail.com>
 898
 899         PR gas/15095
 900         * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
 901         individual msb and lsb halves in src1 & src2 fields.  Discard the
 902         src1 (lsb) value and only use src2 (msb), discarding bit 0, to
 903         follow what Ti SDK does in that case as any value in the src1
 904         field yields the same output with SDK disassembler.
 905
 906 2013-03-12  Michael Eager <eager@eagercon.com>
 907
 908         * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
 909
 910 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
 911
 912         * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
 913
 914 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
 915
 916         * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
 917
 918 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
 919
 920         * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
 921
 922 2013-03-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 923
 924         * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
 925         (thumb32_opcodes): Likewise.
 926         (print_insn_thumb32): Handle 'S' control char.
 927
 928 2013-03-08  Yann Sionneau  <yann.sionneau@gmail.com>
 929
 930         * lm32-desc.c: Regenerate.
 931
 932 2013-03-01  H.J. Lu  <hongjiu.lu@intel.com>
 933
 934         * i386-reg.tbl (riz): Add RegRex64.
 935         * i386-tbl.h: Regenerated.
 936
 937 2013-02-28  Yufeng Zhang  <yufeng.zhang@arm.com>
 938
 939         * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
 940         (aarch64_feature_crc): New static.
 941         (CRC): New macro.
 942         (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
 943         crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
 944         * aarch64-asm-2.c: Re-generate.
 945         * aarch64-dis-2.c: Ditto.
 946         * aarch64-opc-2.c: Ditto.
 947
 948 2013-02-27  Alan Modra  <amodra@gmail.com>
 949
 950         * rl78-decode.opc (rl78_decode_opcode): Fix typo.
 951         * rl78-decode.c: Regenerate.
 952
 953 2013-02-25  Kaushik Phatak  <Kaushik.Phatak@kpitcummins.com>
 954
 955         * rl78-decode.opc: Fix encoding of DIVWU insn.
 956         * rl78-decode.c: Regenerate.
 957
 958 2013-02-19  H.J. Lu  <hongjiu.lu@intel.com>
 959
 960         PR gas/15159
 961         * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
 962
 963         * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
 964         (cpu_flags): Add CpuSMAP.
 965
 966         * i386-opc.h (CpuSMAP): New.
 967         (i386_cpu_flags): Add cpusmap.
 968
 969         * i386-opc.tbl: Add clac and stac.
 970
 971         * i386-init.h: Regenerated.
 972         * i386-tbl.h: Likewise.
 973
 974 2013-02-15  Markos Chandras  <markos.chandras@imgtec.com>
 975
 976         * metag-dis.c: Initialize outf->bytes_per_chunk to 4
 977         which also makes the disassembler output be in little
 978         endian like it should be.
 979
 980 2013-02-14  Yufeng Zhang  <yufeng.zhang@arm.com>
 981
 982         * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
 983         fields to NULL.
 984         (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
 985
 986 2013-02-13  Maciej W. Rozycki  <macro@codesourcery.com>
 987
 988         * mips-dis.c (is_compressed_mode_p): Only match symbols from the
 989         section disassembled.
 990
 991 2013-02-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 992
 993         * arm-dis.c: Update strht pattern.
 994
 995 2013-02-09  Jürgen Urban  <JuergenUrban@gmx.de>
 996
 997         * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
 998         single-float.  Disable ll, lld, sc and scd for EE.  Disable the
 999         trunc.w.s macro for EE.
1000
1001 2013-02-06  Sandra Loosemore  <sandra@codesourcery.com>
1002             Andrew Jenner <andrew@codesourcery.com>
1003
1004         Based on patches from Altera Corporation.
1005
1006         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
1007         nios2-opc.c.
1008         * Makefile.in: Regenerated.
1009         * configure.in: Add case for bfd_nios2_arch.
1010         * configure: Regenerated.
1011         * disassemble.c (ARCH_nios2): Define.
1012         (disassembler): Add case for bfd_arch_nios2.
1013         * nios2-dis.c: New file.
1014         * nios2-opc.c: New file.
1015
1016 2013-02-04  Alan Modra  <amodra@gmail.com>
1017
1018         * po/POTFILES.in: Regenerate.
1019         * rl78-decode.c: Regenerate.
1020         * rx-decode.c: Regenerate.
1021
1022 2013-01-30  Yufeng Zhang  <yufeng.zhang@arm.com>
1023
1024         * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
1025         ushll2 with F_HAS_ALIAS.  Add entries for sxtl, sxtl2, uxtl and uxtl2.
1026         * aarch64-asm.c (convert_xtl_to_shll): New function.
1027         (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
1028         calling convert_xtl_to_shll.
1029         * aarch64-dis.c (convert_shll_to_xtl): New function.
1030         (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
1031         calling convert_shll_to_xtl.
1032         * aarch64-gen.c: Update copyright year.
1033         * aarch64-asm-2.c: Re-generate.
1034         * aarch64-dis-2.c: Re-generate.
1035         * aarch64-opc-2.c: Re-generate.
1036
1037 2013-01-24  Nick Clifton  <nickc@redhat.com>
1038
1039         * v850-dis.c: Add support for e3v5 architecture.
1040         * v850-opc.c: Likewise.
1041
1042 2013-01-17  Yufeng Zhang  <yufeng.zhang@arm.com>
1043
1044         * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
1045         * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
1046         * aarch64-opc.c (operand_general_constraint_met_p): For
1047         AARCH64_MOD_LSL, move the range check on the shift amount before the
1048         alignment check; change to call set_sft_amount_out_of_range_error
1049         instead of set_imm_out_of_range_error.
1050         * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
1051         (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
1052         8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
1053         SIMD_IMM_SFT.
1054
1055 2013-01-16  H.J. Lu  <hongjiu.lu@intel.com>
1056
1057         * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
1058
1059         * i386-init.h: Regenerated.
1060         * i386-tbl.h: Likewise.
1061
1062 2013-01-15  Nick Clifton  <nickc@redhat.com>
1063
1064         * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
1065         values.
1066         * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
1067
1068 2013-01-14  Will Newton <will.newton@imgtec.com>
1069
1070         * metag-dis.c (REG_WIDTH): Increase to 64.
1071
1072 2013-01-10  Peter Bergner <bergner@vnet.ibm.com>
1073
1074         * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
1075         * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
1076         XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
1077         (SH6): Update.
1078         <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
1079         "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
1080         "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
1081         <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
1082
1083 2013-01-10  Will Newton <will.newton@imgtec.com>
1084
1085         * Makefile.am: Add Meta.
1086         * configure.in: Add Meta.
1087         * disassemble.c: Add Meta support.
1088         * metag-dis.c: New file.
1089         * Makefile.in: Regenerate.
1090         * configure: Regenerate.
1091
1092 2013-01-07  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
1093
1094         * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
1095         (match_opcode): Rename to cr16_match_opcode.
1096
1097 2013-01-04  Juergen Urban <JuergenUrban@gmx.de>
1098
1099         * mips-dis.c: Add names for CP0 registers of r5900.
1100         * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
1101         instructions sq and lq.
1102         Add support for MIPS r5900 CPU.
1103         Add support for 128 bit MMI (Multimedia Instructions).
1104         Add support for EE instructions (Emotion Engine).
1105         Disable unsupported floating point instructions (64 bit and
1106         undefined compare operations).
1107         Enable instructions of MIPS ISA IV which are supported by r5900.
1108         Disable 64 bit co processor instructions.
1109         Disable 64 bit multiplication and division instructions.
1110         Disable instructions for co-processor 2 and 3, because these are
1111         not supported (preparation for later VU0 support (Vector Unit)).
1112         Disable cvt.w.s because this behaves like trunc.w.s and the
1113         correct execution can't be ensured on r5900.
1114         Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
1115         will confuse less developers and compilers.
1116
1117 2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>
1118
1119         * aarch64-opc.c (aarch64_print_operand): Change to print
1120         AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
1121         in comment.
1122         * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
1123         from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
1124         OP_MOV_IMM_WIDE.
1125
1126 2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>
1127
1128         * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
1129         PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
1130
1131 2013-01-02  H.J. Lu  <hongjiu.lu@intel.com>
1132
1133         * i386-gen.c (process_copyright): Update copyright year to 2013.
1134
1135 2013-01-02  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
1136
1137         * cr16-dis.c (match_opcode,make_instruction): Remove static
1138         declaration.
1139         (dwordU,wordU): Moved typedefs to opcode/cr16.h
1140         (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
1141
1142 For older changes see ChangeLog-2012
1143 \f
1144 Copyright (C) 2013 Free Software Foundation, Inc.
1145
1146 Copying and distribution of this file, with or without modification,
1147 are permitted in any medium without royalty provided the copyright
1148 notice and this notice are preserved.
1149
1150 Local Variables:
1151 mode: change-log
1152 left-margin: 8
1153 fill-column: 74
1154 version-control: never
1155 End: