opcodes/ChangeLog

   1 2021-07-26  Chenghua Xu  <xuchenghua@loongson.cn>
   2
   3         * mips-dis.c (mips_arch_choices): Correct gs264e bfd_mach.
   4
   5 2021-06-07  Andreas Krebbel  <krebbel@linux.ibm.com>
   6
   7         * s390-opc.txt: Add qpaci.
   8
   9 2021-07-03  Nick Clifton  <nickc@redhat.com>
  10
  11         * configure: Regenerate.
  12         * po/opcodes.pot: Regenerate.
  13
  14 2021-07-03  Nick Clifton  <nickc@redhat.com>
  15
  16         * 2.37 release branch created.
  17
  18 2021-07-02  Alan Modra  <amodra@gmail.com>
  19
  20         * nds32-dis.c (nds32_find_reg_keyword): Constify arg and return.
  21         (nds32_parse_audio_ext, nds32_parse_opcode): Constify psys_reg.
  22         (nds32_field_table, nds32_opcode_table, nds32_keyword_table),
  23         (nds32_opcodes, nds32_operand_fields, nds32_keywords),
  24         (nds32_keyword_gpr): Move declarations to..
  25         * nds32-asm.h: ..here, constifying to match definitions.
  26
  27 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
  28
  29         * Makefile.am (GUILE): New variable.
  30         (CGEN): Use $(GUILE).
  31         * Makefile.in: Regenerate.
  32
  33 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
  34
  35         * mep-asm.c (macros): Mark static & const.
  36         (lookup_macro): Change return & m to const.
  37         (expand_macro): Change mac to const.
  38         (expand_string): Change pmacro to const.
  39
  40 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
  41
  42         * nds32-asm.c (operand_fields): Rename to ...
  43         (nds32_operand_fields): ... this.
  44         (keyword_gpr): Rename to ...
  45         (nds32_keyword_gpr): ... this.
  46         (keyword_usr, keyword_dxr, keyword_sr, keyword_cp, keyword_cpr,
  47         keyword_fsr, keyword_fdr, keyword_abdim, keyword_abm,
  48         keyword_dpref_st, keyword_cctl_lv, keyword_standby_st,
  49         keyword_msync_st, keyword_im5_i, keyword_im5_m, keyword_accumulator,
  50         keyword_aridx, keyword_aridx2, keyword_aridxi, keyword_aridxi_mx):
  51         Mark static.
  52         (keywords): Rename to ...
  53         (nds32_keywords): ... this.
  54         * nds32-dis.c: Rename operand_fields to nds32_operand_fields,
  55         keywords to nds32_keywords, and keyword_gpr to nds32_keyword_gpr.
  56
  57 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
  58
  59         * z80-dis.c (opc_ed): Make const.
  60         (pref_ed): Make p const.
  61
  62 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
  63
  64         * microblaze-dis.c (get_field_special): Make op const.
  65         (read_insn_microblaze): Make opr & op const.  Rename opcodes to
  66         microblaze_opcodes.
  67         (print_insn_microblaze): Make op & pop const.
  68         (get_insn_microblaze): Make op const.  Rename opcodes to
  69         microblaze_opcodes.
  70         (microblaze_get_target_address): Likewise.
  71         * microblaze-opc.h (struct op_code_struct): Make const.
  72         Rename opcodes to microblaze_opcodes.
  73
  74 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
  75
  76         * aarch64-gen.c (aarch64_opcode_table): Add const.
  77         * aarch64-tbl.h (aarch64_opcode_table): Likewise.
  78
  79 2021-06-22  Andrew Burgess  <andrew.burgess@embecosm.com>
  80
  81         * cgen-dis.c (count_decodable_bits): Use __builtin_popcount when
  82         available.
  83
  84 2021-06-22  Alan Modra  <amodra@gmail.com>
  85
  86         * pj-dis.c (print_insn_pj): Don't print trailing tab.  Do
  87         print separator for pcrel insns.
  88
  89 2021-06-19  Alan Modra  <amodra@gmail.com>
  90
  91         * vax-dis.c (print_insn_vax): Avoid pointer overflow.
  92
  93 2021-06-19  Alan Modra  <amodra@gmail.com>
  94
  95         * tic30-dis.c (get_register_operand): Don't ask strncpy to fill
  96         entire buffer.
  97
  98 2021-06-17  Alan Modra  <amodra@gmail.com>
  99
 100         * ppc-opc.c (powerpc_opcodes): Move cell db*cyc to proper location
 101         in table.
 102
 103 2021-06-03  Alan Modra  <amodra@gmail.com>
 104
 105         PR 1202
 106         * mcore-dis.c (print_insn_mcore): Correct loopt disassembly.
 107         Use unsigned int for inst.
 108
 109 2021-06-02  Shahab Vahedi  <shahab@synopsys.com>
 110
 111         * arc-dis.c (arc_option_arg_t): New enumeration.
 112         (arc_options): New variable.
 113         (disassembler_options_arc): New function.
 114         (print_arc_disassembler_options): Reimplement in terms of
 115         "disassembler_options_arc".
 116
 117 2021-05-29  Alan Modra  <amodra@gmail.com>
 118
 119         * ppc-dis.c (lookup_powerpc): Test deprecated field when -Many.
 120         Don't special case PPC_OPCODE_RAW.
 121         (lookup_prefix): Likewise.
 122         (lookup_vle, lookup_spe2): Similarly.  Add dialect parameter and..
 123         (print_insn_powerpc): ..update caller.
 124         * ppc-opc.c (EXT): Define.
 125         (powerpc_opcodes): Mark extended mnemonics with EXT.
 126         (prefix_opcodes, vle_opcodes): Likewise.
 127         (XISEL, XISEL_MASK): Add cr field and simplify.
 128         (powerpc_opcodes): Use XISEL with extended isel mnemonics and sort
 129         all isel variants to where the base mnemonic belongs.  Sort dstt,
 130         dststt and dssall.
 131
 132 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 133
 134         * mips-opc.c (mips_builtin_opcodes): Reorder legacy COP0, COP2,
 135         COP3 opcode instructions.
 136
 137 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 138
 139         * mips-opc.c (mips_builtin_opcodes): Update exclusion list for
 140         "ldc2", "ldc3", "lwc0", "lwc2", "lwc3", "sdc2", "sdc3", "swc0",
 141         "swc2", "swc3", "cfc0", "ctc0", "bc2f", "bc2fl", "bc2t",
 142         "bc2tl", "cfc2", "ctc2", "dmfc2", "dmtc2", "mfc2", "mtc2",
 143         "bc3f", "bc3fl", "bc3t", "bc3tl", "cfc3", "ctc3", "mfc3",
 144         "mtc3", "bc0f", "bc0fl", "bc0t", "bc0tl", "rfe", "c2", "c3",
 145         "cop2", and "cop3" entries.
 146
 147 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 148
 149         * mips-opc.c (mips_builtin_opcodes): Remove "dmfc3" and "dmtc3"
 150         entries and associated comments.
 151
 152 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 153
 154         * mips-opc.c (mips_builtin_opcodes): Move the "rfe" entry ahead
 155         of "c0".
 156
 157 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 158
 159         * mips-dis.c (mips_cp1_names_mips): New variable.
 160         (mips_arch_choices): Use it rather than `mips_cp1_names_numeric'
 161         for "r3000", "r4000", "r4010", "vr4100", "vr4111", "vr4120",
 162         "r4300", "r4400", "r4600", "r4650", "r5000", "vr5400", "vr5500",
 163         "r5900", "r6000", "rm7000", "rm9000", "r8000", "r10000",
 164         "r12000", "r14000", "r16000", "mips5", "loongson2e", and
 165         "loongson2f".
 166
 167 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 168
 169         * mips-dis.c (print_reg) <OP_REG_COPRO>: Move control register
 170         handling code over to...
 171         <OP_REG_CONTROL>: ... this new case.
 172         * mips-opc.c (decode_mips_operand) <'g', 'y'>: New cases.
 173         (mips_builtin_opcodes): Update "cfc1", "ctc1", "cttc1", "cttc2",
 174         "cfc0", "ctc0", "cfc2", "ctc2", "cfc3", and "ctc3" entries
 175         replacing the `G' operand code with `g'.  Update "cftc1" and
 176         "cftc2" entries replacing the `E' operand code with `y'.
 177         * micromips-opc.c (decode_micromips_operand) <'g'>: New case.
 178         (micromips_opcodes): Update "cfc1", "cfc2", "ctc1", and "ctc2"
 179         entries replacing the `G' operand code with `g'.
 180
 181 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 182
 183         * mips-dis.c (mips_cp0_names_r3900): New variable.
 184         (mips_arch_choices): Use it rather than `mips_cp0_names_numeric'
 185         for "r3900".
 186
 187 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 188
 189         * mips-opc.c (mips_builtin_opcodes): Switch "cttc2", "mttc2",
 190         and "mtthc2" to using the `G' rather than `g' operand code for
 191         the coprocessor control register referred.
 192
 193 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 194
 195         * micromips-opc.c (micromips_opcodes): Swap the two "dmtc1"
 196         entries with each other.
 197
 198 2021-05-27  Peter Bergner  <bergner@linux.ibm.com>
 199
 200         * ppc-opc.c (powerpc_opcodes) <xxmr, xxlnot>: New extended mnemonics.
 201
 202 2021-05-25  Alan Modra  <amodra@gmail.com>
 203
 204         * cris-desc.c: Regenerate.
 205         * cris-desc.h: Regenerate.
 206         * cris-opc.h: Regenerate.
 207         * po/POTFILES.in: Regenerate.
 208
 209 2021-05-24  Mike Frysinger  <vapier@gentoo.org>
 210
 211         * Makefile.am (HFILES): Add cris-desc.h & cris-opc.h.
 212         (TARGET_LIBOPCODES_CFILES): Add cris-desc.c.
 213         (CGEN_CPUS): Add cris.
 214         (CRIS_DEPS): Define.
 215         (stamp-cris): New rule.
 216         * cgen.sh: Handle desc action.
 217         * configure.ac (bfd_cris_arch): Add cris-desc.lo.
 218         * Makefile.in, configure: Regenerate.
 219
 220 2021-05-18  Job Noorman  <mtvec@pm.me>
 221
 222         PR 27814
 223         * riscv-dis.c (riscv_get_disassembler): Get elf attributes only for
 224         the elf objects.
 225
 226 2021-05-17  Alex Coplan  <alex.coplan@arm.com>
 227
 228         * arm-dis.c (mve_opcodes): Fix disassembly of
 229         MVE_VMOV2_GP_TO_VEC_LANE when idx == 1.
 230         (is_mve_encoding_conflict): MVE vector loads should not match
 231         when P = W = 0.
 232         (is_mve_unpredictable): It's not unpredictable to use the same
 233         source register twice (for MVE_VMOV2_GP_TO_VEC_LANE).
 234
 235 2021-05-11  Nick Clifton  <nickc@redhat.com>
 236
 237         PR 27840
 238         * tic30-dis.c (print_insn_tic30): Prevent attempts to read beyond
 239         the end of the code buffer.
 240
 241 2021-05-06  Stafford Horne  <shorne@gmail.com>
 242
 243         PR 21464
 244         * or1k-asm.c: Regenerate.
 245
 246 2021-05-01  Max Filippov  <jcmvbkbc@gmail.com>
 247
 248         * xtensa-dis.c (print_insn_xtensa): Fill in info->insn_type and
 249         info->insn_info_valid.
 250
 251 2021-04-26  Jan Beulich  <jbeulich@suse.com>
 252
 253         * i386-opc.tbl (lea): Add Optimize.
 254         * opcodes/i386-tbl.h: Re-generate.
 255
 256 2020-04-23  Max Filippov  <jcmvbkbc@gmail.com>
 257
 258         * xtensa-dis.c (print_xtensa_operand): For PC-relative operand
 259         of l32r fetch and display referenced literal value.
 260
 261 2021-04-23  Max Filippov  <jcmvbkbc@gmail.com>
 262
 263         * xtensa-dis.c (print_insn_xtensa): Set info->bytes_per_chunk
 264         to 4 for literal disassembly.
 265
 266 2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 267
 268         * aarch64-opc.c: Add new registers (RPAOS, RPALOS, PAALLOS, PAALL) support
 269         for TLBI instruction.
 270
 271 2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 272
 273         * aarch64-opc.c: Add new register (CIPAPA, CIGDPAPA) support for
 274         DC instruction.
 275
 276 2021-04-19  Jan Beulich  <jbeulich@suse.com>
 277
 278         * aarch64-asm.c (encode_asimd_fcvt): Add initializer for
 279         "qualifier".
 280         (convert_mov_to_movewide): Add initializer for "value".
 281
 282 2021-04-16  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 283
 284         * aarch64-opc.c: Add RME system registers.
 285
 286 2021-04-16  Lifang Xia <lifang_xia@c-sky.com>
 287
 288         * riscv-opc.c (riscv_opcodes): New insn alias for addi. Compress
 289         "addi d,CV,z" to "c.mv d,CV".
 290
 291 2021-04-12  Alan Modra  <amodra@gmail.com>
 292
 293         * configure.ac (--enable-checking): Add support.
 294         * config.in: Regenerate.
 295         * configure: Regenerate.
 296
 297 2021-04-09  Tejas Belagod  <tejas.belagod@arm.com>
 298
 299         * aarch64-tbl.h (struct aarch64_opcode aarch64_opcode_table): Reclassify
 300         LD64/ST64 instructions to lse_atomic instead of ldstexcl.
 301
 302 2021-04-09  Alan Modra  <amodra@gmail.com>
 303
 304         * ppc-dis.c (struct dis_private): Add "special".
 305         (POWERPC_DIALECT): Delete.  Replace uses with..
 306         (private_data): ..this.  New inline function.
 307         (disassemble_init_powerpc): Init "special" names.
 308         (skip_optional_operands): Add is_pcrel arg, set when detecting R
 309         field of prefix instructions.
 310         (bsearch_reloc, print_got_plt): New functions.
 311         (print_insn_powerpc): For pcrel instructions, print target address
 312         and symbol if known, and decode plt and got loads too.
 313
 314 2021-04-08  Alan Modra  <amodra@gmail.com>
 315
 316         PR 27684
 317         * ppc-opc.c (powerpc_opcodes): Correct usprg typos, add mfpir.
 318
 319 2021-04-08  Alan Modra  <amodra@gmail.com>
 320
 321         PR 27676
 322         * ppc-opc.c (DCBT_EO): Move earlier.
 323         (insert_thct, extract_thct, insert_thds, extract_thds): New functions.
 324         (powerpc_operands): Add THCT and THDS entries.
 325         (powerpc_opcodes): Add dcbtstct, dcbtstds, dcbna, dcbtct, dcbtds.
 326
 327 2021-04-06  Alan Modra  <amodra@gmail.com>
 328
 329         * dis-buf.c (generic_symbol_at_address): Return symbol* NULL.
 330         * s12z-dis.c (decode_possible_symbol): Use symbol returned from
 331         symbol_at_address_func.
 332
 333 2021-04-05  Alan Modra  <amodra@gmail.com>
 334
 335         * configure.ac: Don't check for limits.h, string.h, strings.h or
 336         stdlib.h.
 337         (AC_ISC_POSIX): Don't invoke.
 338         * sysdep.h: Include stdlib.h and string.h unconditionally.
 339         * i386-opc.h: Include limits.h unconditionally.
 340         * wasm32-dis.c: Likewise.
 341         * cgen-opc.c: Don't include alloca-conf.h.
 342         * config.in: Regenerate.
 343         * configure: Regenerate.
 344
 345 2021-04-01  Martin Liska  <mliska@suse.cz>
 346
 347         * arm-dis.c (strneq): Remove strneq and use startswith.
 348         * cr16-dis.c (print_insn_cr16): Likewise.
 349         * score-dis.c (streq): Likewise.
 350         (strneq): Likewise.
 351         * score7-dis.c (strneq): Likewise.
 352
 353 2021-04-01  Alan Modra  <amodra@gmail.com>
 354
 355         PR 27675
 356         * ppc-opc.c (powerpc_opcodes): Add mfummcr2 and mfmmcr2.
 357
 358 2021-03-31  Alan Modra  <amodra@gmail.com>
 359
 360         * sysdep.h (POISON_BFD_BOOLEAN): Define.
 361         * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h,
 362         * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h,
 363         * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c,
 364         * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c,
 365         * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c,
 366         * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c,
 367         * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c,
 368         * microblaze-dis.h, * micromips-opc.c, * mips-dis.c,
 369         * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c,
 370         * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c,
 371         * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c,
 372         * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c,
 373         * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false,
 374         and TRUE with true throughout.
 375
 376 2021-03-31  Alan Modra  <amodra@gmail.com>
 377
 378         * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h.
 379         * aarch64-dis.h: Likewise.
 380         * aarch64-opc.c: Likewise.
 381         * avr-dis.c: Likewise.
 382         * csky-dis.c: Likewise.
 383         * nds32-asm.c: Likewise.
 384         * nds32-dis.c: Likewise.
 385         * nfp-dis.c: Likewise.
 386         * riscv-dis.c: Likewise.
 387         * s12z-dis.c: Likewise.
 388         * wasm32-dis.c: Likewise.
 389
 390 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 391
 392         * i386-opc.c (cs, ds, ss, es, fs, gs): Delete.
 393         (i386_seg_prefixes): New.
 394         * i386-opc.h (cs, ds, ss, es, fs, gs): Delete.
 395         (i386_seg_prefixes): Declare.
 396
 397 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 398
 399         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Delete.
 400
 401 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 402
 403         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Adjust values.
 404         * i386-reg.tbl (st): Move down.
 405         (st(0)): Delete. Extend comment.
 406         * i386-tbl.h: Re-generate.
 407
 408 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 409
 410         * i386-opc.tbl (movq, movabs): Move next to mov counterparts.
 411         (cmpsd): Move next to cmps.
 412         (movsd): Move next to movs.
 413         (cmpxchg16b): Move to separate section.
 414         (fisttp, fisttpll): Likewise.
 415         (monitor, mwait): Likewise.
 416         * i386-tbl.h: Re-generate.
 417
 418 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 419
 420         * i386-opc.tbl (psadbw): Add <sse2:comm>.
 421         (vpsadbw): Add C.
 422         * i386-tbl.h: Re-generate.
 423
 424 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 425
 426         * i386-opc.tbl (mmx, sse, sse2, sse3, ssse3, sse41, sse42, aes,
 427         pclmul, gfni): New templates. Use them wherever possible. Move
 428         SSE4.1 pextrw into respective section.
 429         * i386-tbl.h: Re-generate.
 430
 431 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 432
 433         * i386-gen.c (output_i386_opcode): Widen type of "opcode". Use
 434         strtoull(). Bump upper loop bound. Widen masks. Sanity check
 435         "length".
 436         * i386-opc.tbl (Prefix_0X66, Prefix_0XF2, Prefix_0XF3): Delete.
 437         Convert all of their uses to representation in opcode.
 438
 439 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 440
 441         * i386-opc.h (struct insn_template): Shrink base_opcode to 16
 442         bits. Shrink extension_opcode to 9 bits. Make it signed. Change
 443         value of None. Shrink operands to 3 bits.
 444
 445 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 446
 447         * i386-gen.c (process_i386_opcode_modifier): New parameter
 448         "space".
 449         (output_i386_opcode): New local variable "space". Adjust
 450         process_i386_opcode_modifier() invocation.
 451         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 452         invocation.
 453         * i386-tbl.h: Re-generate.
 454
 455 2021-03-29  Alan Modra  <amodra@gmail.com>
 456
 457         * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
 458         (fp_qualifier_p, get_data_pattern): Likewise.
 459         (aarch64_get_operand_modifier_from_value): Likewise.
 460         (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
 461         (operand_variant_qualifier_p): Likewise.
 462         (qualifier_value_in_range_constraint_p): Likewise.
 463         (aarch64_get_qualifier_esize): Likewise.
 464         (aarch64_get_qualifier_nelem): Likewise.
 465         (aarch64_get_qualifier_standard_value): Likewise.
 466         (get_lower_bound, get_upper_bound): Likewise.
 467         (aarch64_find_best_match, match_operands_qualifier): Likewise.
 468         (aarch64_print_operand): Likewise.
 469         * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
 470         (operand_need_sign_extension, operand_need_shift_by_two): Likewise.
 471         (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
 472         * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
 473         * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
 474         (print_insn_tic6x): Likewise.
 475
 476 2021-03-29  Alan Modra  <amodra@gmail.com>
 477
 478         * arc-dis.c (extract_operand_value): Correct NULL cast.
 479         * frv-opc.h: Regenerate.
 480
 481 2021-03-26  Jan Beulich  <jbeulich@suse.com>
 482
 483         * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to
 484         MMX form.
 485         * i386-tbl.h: Re-generate.
 486
 487 2021-03-25  Abid Qadeer  <abidh@codesourcery.com>
 488
 489         * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
 490         immediate in br.n instruction.
 491
 492 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 493
 494         * i386-dis.c (XMGatherD, VexGatherD): New.
 495         (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
 496         (print_insn): Check masking for S/G insns.
 497         (OP_E_memory): New local variable check_gather. Extend mandatory
 498         SIB check. Check register conflicts for (EVEX-encoded) gathers.
 499         Extend check for disallowed 16-bit addressing.
 500         (OP_VEX): New local variables modrm_reg and sib_index. Convert
 501         if()s to switch(). Check register conflicts for (VEX-encoded)
 502         gathers. Drop no longer reachable cases.
 503         * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
 504         vgatherdp*.
 505
 506 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 507
 508         * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
 509         zeroing-masking without masking.
 510
 511 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 512
 513         * i386-opc.tbl (invlpgb): Fix multi-operand form.
 514         (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
 515         single-operand forms as deprecated.
 516         * i386-tbl.h: Re-generate.
 517
 518 2021-03-25  Alan Modra  <amodra@gmail.com>
 519
 520         PR 27647
 521         * ppc-opc.c (XLOCB_MASK): Delete.
 522         (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
 523         XLBH_MASK.
 524         (powerpc_opcodes): Accept a BH field on all extended forms of
 525         bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
 526
 527 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 528
 529         * i386-gen.c (output_i386_opcode): Drop processing of
 530         opcode_length. Calculate length from base_opcode. Adjust prefix
 531         encoding determination.
 532         (process_i386_opcodes): Drop output of fake opcode_length.
 533         * i386-opc.h (struct insn_template): Drop opcode_length field.
 534         * i386-opc.tbl: Drop opcode length field from all templates.
 535         * i386-tbl.h: Re-generate.
 536
 537 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 538
 539         * i386-gen.c (process_i386_opcode_modifier): Return void. New
 540         parameter "prefix". Drop local variable "regular_encoding".
 541         Record prefix setting / check for consistency.
 542         (output_i386_opcode): Parse opcode_length and base_opcode
 543         earlier. Derive prefix encoding. Drop no longer applicable
 544         consistency checking. Adjust process_i386_opcode_modifier()
 545         invocation.
 546         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 547         invocation.
 548         * i386-tbl.h: Re-generate.
 549
 550 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 551
 552         * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
 553         check.
 554         * i386-opc.h (Prefix_*): Move #define-s.
 555         * i386-opc.tbl: Move pseudo prefix enumerator values to
 556         extension opcode field. Introduce pseudopfx template.
 557         * i386-tbl.h: Re-generate.
 558
 559 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 560
 561         * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
 562         comment.
 563         * i386-tbl.h: Re-generate.
 564
 565 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 566
 567         * i386-opc.h (struct insn_template): Move cpu_flags field past
 568         opcode_modifier one.
 569         * i386-tbl.h: Re-generate.
 570
 571 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 572
 573         * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
 574         * i386-opc.h (OpcodeSpace): New enumerator.
 575         (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
 576         (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
 577         SPACE_XOP09, SPACE_XOP0A): ... respectively.
 578         (struct i386_opcode_modifier): New field opcodespace. Shrink
 579         opcodeprefix field.
 580         i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
 581         SpaceXOP09, SpaceXOP0A): Define. Use them to replace
 582         OpcodePrefix uses.
 583         * i386-tbl.h: Re-generate.
 584
 585 2021-03-22  Martin Liska  <mliska@suse.cz>
 586
 587         * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
 588         * arc-dis.c (parse_option): Likewise.
 589         * arm-dis.c (parse_arm_disassembler_options): Likewise.
 590         * cris-dis.c (print_with_operands): Likewise.
 591         * h8300-dis.c (bfd_h8_disassemble): Likewise.
 592         * i386-dis.c (print_insn): Likewise.
 593         * ia64-gen.c (fetch_insn_class): Likewise.
 594         (parse_resource_users): Likewise.
 595         (in_iclass): Likewise.
 596         (lookup_specifier): Likewise.
 597         (insert_opcode_dependencies): Likewise.
 598         * mips-dis.c (parse_mips_ase_option): Likewise.
 599         (parse_mips_dis_option): Likewise.
 600         * s390-dis.c (disassemble_init_s390): Likewise.
 601         * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
 602
 603 2021-03-16  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
 604
 605         * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
 606
 607 2021-03-12  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 608
 609         * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
 610         icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
 611
 612 2021-03-12  Alan Modra  <amodra@gmail.com>
 613
 614         * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
 615
 616 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 617
 618         * i386-dis.c (OP_XMM): Re-order checks.
 619
 620 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 621
 622         * i386-dis.c (putop): Drop need_vex check when also checking
 623         vex.evex.
 624         (intel_operand_size, OP_E_memory): Drop vex.evex check when also
 625         checking vex.b.
 626
 627 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 628
 629         * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
 630         checks. Move case label past broadcast check.
 631
 632 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 633
 634         * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
 635         vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
 636         REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
 637         EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
 638         EVEX_W_0F38C7_M_0_L_2): Delete.
 639         (REG_EVEX_0F38C7_M_0_L_2): New.
 640         (intel_operand_size): Handle VEX and EVEX the same for
 641         vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
 642         vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
 643         (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
 644         vex_vsib_q_w_d_mode uses.
 645         * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
 646         0F38A1, and 0F38A3 entries.
 647         * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
 648         entry.
 649         * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
 650         * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
 651         0F38A3 entries.
 652
 653 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 654
 655         * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
 656         REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
 657         MOD_VEX_0FXOP_09_12): Rename to ...
 658         (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
 659         REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
 660         (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
 661         RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
 662         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 663         X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
 664         (reg_table): Adjust comments.
 665         (x86_64_table): Move X86_64_0F24, X86_64_0F26,
 666         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 667         X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
 668         (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
 669         (vex_len_table): Adjust opcode 0A_12 entry.
 670         (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
 671         MOD_C5_32BIT, and MOD_XOP_09_12 entries.
 672         (rm_table): Move hreset entry.
 673
 674 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 675
 676         * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
 677         EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
 678         EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
 679         EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
 680         EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
 681         (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
 682         (get_valid_dis386): Also handle 512-bit vector length when
 683         vectoring into vex_len_table[].
 684         * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
 685         0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
 686         entries.
 687         * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
 688         0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
 689         * i386-dis-evex-prefix.h: Adjust 0F7E entry.
 690         * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
 691         entries.
 692
 693 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 694
 695         * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
 696         Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
 697         EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
 698         * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
 699         entries.
 700         * i386-dis-evex-len.h (evex_len_table): Likewise.
 701         * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
 702
 703 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 704
 705         * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
 706         MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
 707         MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
 708         MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
 709         MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
 710         MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
 711         MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
 712         MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
 713         EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
 714         EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
 715         EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
 716         EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
 717         EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
 718         EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
 719         EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
 720         EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
 721         EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
 722         EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
 723         EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
 724         EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
 725         EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
 726         EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
 727         EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
 728         EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
 729         EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
 730         EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
 731         EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
 732         EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
 733         EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
 734         EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
 735         EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
 736         EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
 737         REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
 738         REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
 739         MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
 740         MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
 741         EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
 742         EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
 743         EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
 744         EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
 745         EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
 746         EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
 747         EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
 748         EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
 749         EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
 750         EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
 751         EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
 752         EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
 753         EVEX_W_0F3A43_L_n): New.
 754         * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
 755         0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
 756         0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
 757         * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
 758         for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
 759         0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
 760         0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
 761         * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
 762         0F385B, 0F38C6, and 0F38C7 entries.
 763         * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
 764         0F38C6 and 0F38C7.
 765         * i386-dis-evex-w.h: No longer link to evex_len_table[] for
 766         opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
 767         0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
 768         evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
 769
 770 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 771
 772         * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
 773         MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
 774         MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
 775         MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
 776         MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
 777         MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
 778         MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
 779         MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
 780         MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
 781         MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
 782         MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
 783         MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
 784         MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
 785         MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
 786         MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
 787         MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
 788         MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
 789         MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
 790         MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
 791         MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
 792         MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
 793         MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
 794         MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
 795         MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
 796         MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
 797         PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
 798         PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
 799         PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
 800         PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
 801         PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
 802         VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
 803         VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
 804         VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
 805         VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
 806         VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
 807         VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
 808         VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
 809         VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
 810         VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
 811         VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
 812         VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
 813         VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
 814         VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
 815         VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
 816         VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
 817         VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
 818         VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
 819         VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
 820         VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
 821         VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
 822         VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
 823         VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
 824         VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
 825         VEX_W_0F99_P_2_LEN_0): Delete.
 826         MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
 827         MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
 828         MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
 829         MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
 830         MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
 831         PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
 832         PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
 833         PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
 834         PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
 835         PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
 836         PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
 837         PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
 838         PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
 839         PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
 840         PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
 841         PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
 842         PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
 843         PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
 844         PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
 845         VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
 846         VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
 847         VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
 848         VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
 849         VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
 850         VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
 851         VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
 852         VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
 853         (prefix_table): No longer link to vex_len_table[] for opcodes
 854         0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
 855         0F92, 0F93, 0F98, and 0F99.
 856         (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
 857         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 858         0F98, and 0F99.
 859         (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
 860         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 861         0F98, and 0F99.
 862         (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
 863         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 864         0F98, and 0F99.
 865         (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
 866         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 867         0F98, and 0F99.
 868
 869 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 870
 871         * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
 872         Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
 873         REG_VEX_0F73_M_0 respectively.
 874         (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
 875         MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
 876         MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
 877         MOD_VEX_0F73_REG_7): Delete.
 878         (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
 879         (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
 880         PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
 881         PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
 882         PREFIX_VEX_0F3AF0_L_0 respectively.
 883         (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
 884         VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
 885         VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
 886         VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
 887         (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
 888         VEX_LEN_0F38F7): New.
 889         (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
 890         (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
 891         0F72, and 0F73. No longer link to vex_len_table[] for opcode
 892         0F38F3.
 893         (prefix_table): No longer link to vex_len_table[] for opcodes
 894         0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 895         (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
 896         0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
 897         0F38F6, 0F38F7, and 0F3AF0.
 898         (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
 899         prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 900         (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
 901         0F73.
 902
 903 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 904
 905         * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
 906         REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
 907         (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
 908         MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
 909         MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
 910         (MOD_0F71, MOD_0F72, MOD_0F73): New.
 911         (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
 912         73.
 913         (reg_table): No longer link to mod_table[] for opcodes 0F71,
 914         0F72, and 0F73.
 915         (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
 916         0F73.
 917
 918 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 919
 920         * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
 921         MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
 922         (reg_table): Don't link to mod_table[] where not needed. Add
 923         PREFIX_IGNORED to nop entries.
 924         (prefix_table): Replace PREFIX_OPCODE in nop entries.
 925         (mod_table): Add nop entries next to prefetch ones. Drop
 926         MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
 927         MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
 928         (rm_table): Add PREFIX_IGNORED to nop entries. Drop
 929         PREFIX_OPCODE from endbr* entries.
 930         (get_valid_dis386): Also consider entry's name when zapping
 931         vindex.
 932         (print_insn): Handle PREFIX_IGNORED.
 933
 934 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 935
 936         * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
 937         IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
 938         element.
 939         * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
 940         HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
 941         (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
 942         PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
 943         (struct i386_opcode_modifier): Delete notrackprefixok,
 944         islockable, hleprefixok, and repprefixok fields. Add prefixok
 945         field.
 946         * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
 947         HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
 948         (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
 949         not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
 950         Replace HLEPrefixOk.
 951         * opcodes/i386-tbl.h: Re-generate.
 952
 953 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 954
 955         * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
 956         * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
 957         64-bit form.
 958         * opcodes/i386-tbl.h: Re-generate.
 959
 960 2021-03-03  Jan Beulich  <jbeulich@suse.com>
 961
 962         * i386-gen.c (output_i386_opcode): Don't get operand count. Look
 963         for {} instead of {0}. Don't look for '0'.
 964         * i386-opc.tbl: Drop operand count field. Drop redundant operand
 965         size specifiers.
 966
 967 2021-02-19  Nelson Chu  <nelson.chu@sifive.com>
 968
 969         PR 27158
 970         * riscv-dis.c (print_insn_args): Updated encoding macros.
 971         * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
 972         (match_c_addi16sp): Updated encoding macros.
 973         (match_c_lui): Likewise.
 974         (match_c_lui_with_hint): Likewise.
 975         (match_c_addi4spn): Likewise.
 976         (match_c_slli): Likewise.
 977         (match_slli_as_c_slli): Likewise.
 978         (match_c_slli64): Likewise.
 979         (match_srxi_as_c_srxi): Likewise.
 980         (riscv_insn_types): Added .insn css/cl/cs.
 981
 982 2021-02-18  Nelson Chu  <nelson.chu@sifive.com>
 983
 984         * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
 985         (default_priv_spec): Updated type to riscv_spec_class.
 986         (parse_riscv_dis_option): Updated.
 987         * riscv-opc.c: Moved stuff and make the file tidy.
 988
 989 2021-02-17  Alan Modra  <amodra@gmail.com>
 990
 991         * wasm32-dis.c: Include limits.h.
 992         (CHAR_BIT): Provide backup define.
 993         (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
 994         Correct signed overflow checking.
 995
 996 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 997
 998         * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
 999         * i386-tbl.h: Re-generate.
1000
1001 2021-02-16  Jan Beulich  <jbeulich@suse.com>
1002
1003         * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
1004         Oword.
1005         * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
1006
1007 2021-02-15  Andreas Krebbel  <krebbel@linux.ibm.com>
1008
1009         * s390-mkopc.c (main): Accept arch14 as cpu string.
1010         * s390-opc.txt: Add new arch14 instructions.
1011
1012 2021-02-04  Nick Alcock  <nick.alcock@oracle.com>
1013
1014         * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
1015         favour of LIBINTL.
1016         * configure: Regenerated.
1017
1018 2021-02-08  Mike Frysinger  <vapier@gentoo.org>
1019
1020         * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
1021         * tic54x-opc.c (regs): Rename to ...
1022         (tic54x_regs): ... this.
1023         (mmregs): Rename to ...
1024         (tic54x_mmregs): ... this.
1025         (condition_codes): Rename to ...
1026         (tic54x_condition_codes): ... this.
1027         (cc2_codes): Rename to ...
1028         (tic54x_cc2_codes): ... this.
1029         (cc3_codes): Rename to ...
1030         (tic54x_cc3_codes): ... this.
1031         (status_bits): Rename to ...
1032         (tic54x_status_bits): ... this.
1033         (misc_symbols): Rename to ...
1034         (tic54x_misc_symbols): ... this.
1035
1036 2021-02-04  Nelson Chu  <nelson.chu@sifive.com>
1037
1038         * riscv-opc.c (MASK_RVB_IMM): Removed.
1039         (riscv_opcodes): Removed zb* instructions.
1040         (riscv_ext_version_table): Removed versions for zb*.
1041
1042 2021-01-26  Alan Modra  <amodra@gmail.com>
1043
1044         * i386-gen.c (parse_template): Ensure entire template_instance
1045         is initialised.
1046
1047 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
1048
1049         * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
1050         (riscv_fpr_names_abi): Likewise.
1051         (riscv_opcodes): Likewise.
1052         (riscv_insn_types): Likewise.
1053
1054 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
1055
1056         * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
1057
1058 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
1059
1060         * riscv-dis.c: Comments tidy and improvement.
1061         * riscv-opc.c: Likewise.
1062
1063 2021-01-13  Alan Modra  <amodra@gmail.com>
1064
1065         * Makefile.in: Regenerate.
1066
1067 2021-01-12  H.J. Lu  <hongjiu.lu@intel.com>
1068
1069         PR binutils/26792
1070         * configure.ac: Use GNU_MAKE_JOBSERVER.
1071         * aclocal.m4: Regenerated.
1072         * configure: Likewise.
1073
1074 2021-01-12  Nick Clifton  <nickc@redhat.com>
1075
1076         * po/sr.po: Updated Serbian translation.
1077
1078 2021-01-11  H.J. Lu  <hongjiu.lu@intel.com>
1079
1080         PR ld/27173
1081         * configure: Regenerated.
1082
1083 2021-01-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
1084
1085         * aarch64-asm-2.c: Regenerate.
1086         * aarch64-dis-2.c: Likewise.
1087         * aarch64-opc-2.c: Likewise.
1088         * aarch64-opc.c (aarch64_print_operand):
1089         Delete handling of AARCH64_OPND_CSRE_CSR.
1090         * aarch64-tbl.h (aarch64_feature_csre): Delete.
1091         (CSRE): Likewise.
1092         (_CSRE_INSN): Likewise.
1093         (aarch64_opcode_table): Delete csr.
1094
1095 2021-01-11  Nick Clifton  <nickc@redhat.com>
1096
1097         * po/de.po: Updated German translation.
1098         * po/fr.po: Updated French translation.
1099         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1100         * po/sv.po: Updated Swedish translation.
1101         * po/uk.po: Updated Ukranian translation.
1102
1103 2021-01-09  H.J. Lu  <hongjiu.lu@intel.com>
1104
1105         * configure: Regenerated.
1106
1107 2021-01-09  Nick Clifton  <nickc@redhat.com>
1108
1109         * configure: Regenerate.
1110         * po/opcodes.pot: Regenerate.
1111
1112 2021-01-09  Nick Clifton  <nickc@redhat.com>
1113
1114         * 2.36 release branch crated.
1115
1116 2021-01-08  Peter Bergner  <bergner@linux.ibm.com>
1117
1118         * ppc-opc.c (insert_dw, (extract_dw): New functions.
1119         (DW, (XRC_MASK): Define.
1120         (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
1121
1122 2021-01-09  Alan Modra  <amodra@gmail.com>
1123
1124         * configure: Regenerate.
1125
1126 2021-01-08  Nick Clifton  <nickc@redhat.com>
1127
1128         * po/sv.po: Updated Swedish translation.
1129
1130 2021-01-08  Nick Clifton  <nickc@redhat.com>
1131
1132         PR 27129
1133         * aarch64-dis.c (determine_disassembling_preference): Move call to
1134         aarch64_match_operands_constraint outside of the assertion.
1135         * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
1136         Replace with a return of FALSE.
1137
1138         PR 27139
1139         * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
1140         core system register.
1141
1142 2021-01-07  Samuel Thibault  <samuel.thibault@gnu.org>
1143
1144         * configure: Regenerate.
1145
1146 2021-01-07  Nick Clifton  <nickc@redhat.com>
1147
1148         * po/fr.po: Updated French translation.
1149
1150 2021-01-07  Fredrik Noring  <noring@nocrew.org>
1151
1152         * m68k-opc.c (chkl): Change minimum architecture requirement to
1153         m68020.
1154
1155 2021-01-07  Philipp Tomsich  <prt@gnu.org>
1156
1157         * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
1158
1159 2021-01-07  Claire Xenia Wolf  <claire@symbioticeda.com>
1160             Jim Wilson  <jimw@sifive.com>
1161             Andrew Waterman  <andrew@sifive.com>
1162             Maxim Blinov  <maxim.blinov@embecosm.com>
1163             Kito Cheng  <kito.cheng@sifive.com>
1164             Nelson Chu  <nelson.chu@sifive.com>
1165
1166         * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
1167         (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
1168
1169 2021-01-01  Alan Modra  <amodra@gmail.com>
1170
1171         Update year range in copyright notice of all files.
1172
1173 For older changes see ChangeLog-2020
1174 \f
1175 Copyright (C) 2021 Free Software Foundation, Inc.
1176
1177 Copying and distribution of this file, with or without modification,
1178 are permitted in any medium without royalty provided the copyright
1179 notice and this notice are preserved.
1180
1181 Local Variables:
1182 mode: change-log
1183 left-margin: 8
1184 fill-column: 74
1185 version-control: never
1186 End: