opcodes/ChangeLog

   1 2017-06-30  Andrew Bennett  <andrew.bennett@imgtec.com>
   2             Maciej W. Rozycki  <macro@imgtec.com>
   3
   4         * micromips-opc.c (XPA, XPAVZ): New macros.
   5         (micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and
   6         "mthgc0".
   7
   8 2017-06-30  Andrew Bennett  <andrew.bennett@imgtec.com>
   9             Maciej W. Rozycki  <macro@imgtec.com>
  10
  11         * micromips-opc.c (I36): New macro.
  12         (micromips_opcodes): Add "eretnc".
  13
  14 2017-06-30  Maciej W. Rozycki  <macro@imgtec.com>
  15             Andrew Bennett  <andrew.bennett@imgtec.com>
  16
  17         * mips-dis.c (mips_calculate_combination_ases): Handle the
  18         ASE_XPA_VIRT flag.
  19         (parse_mips_ase_option): New function.
  20         (parse_mips_dis_option): Factor out ASE option handling to the
  21         new function.  Call `mips_calculate_combination_ases'.
  22         * mips-opc.c (XPAVZ): New macro.
  23         (mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0",
  24         "mfhgc0", "mthc0" and "mthgc0".
  25
  26 2017-06-29  Maciej W. Rozycki  <macro@imgtec.com>
  27
  28         * mips-dis.c (mips_calculate_combination_ases): New function.
  29         (mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT
  30         calculation to the new function.
  31         (set_default_mips_dis_options): Call the new function.
  32
  33 2017-06-29  Anton Kolesov  <Anton.Kolesov@synopsys.com>
  34
  35         * arc-dis.c (parse_disassembler_options): Use
  36         FOR_EACH_DISASSEMBLER_OPTION.
  37
  38 2017-06-29  Anton Kolesov  <Anton.Kolesov@synopsys.com>
  39
  40         * arc-dis.c (parse_option): Use disassembler_options_cmp to compare
  41         disassembler option strings.
  42         (parse_cpu_option): Likewise.
  43
  44 2017-06-28  Tamar Christina  <tamar.christina@arm.com>
  45
  46         * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod.
  47         * aarch64-dis.c (aarch64_ext_reglane): Likewise.
  48         * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New.
  49         (aarch64_feature_dotprod, DOT_INSN): New.
  50         (udot, sdot): New.
  51         * aarch64-dis-2.c: Regenerated.
  52
  53 2017-06-28  Jiong Wang  <jiong.wang@arm.com>
  54
  55         * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
  56
  57 2017-06-28  Maciej W. Rozycki  <macro@imgtec.com>
  58             Matthew Fortune  <matthew.fortune@imgtec.com>
  59             Andrew Bennett <andrew.bennett@imgtec.com>
  60
  61         * mips-formats.h (INT_BIAS): New macro.
  62         (INT_ADJ): Redefine in INT_BIAS terms.
  63         * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
  64         (mips_print_save_restore): New function.
  65         (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
  66         (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
  67         call.
  68         (print_insn_args): Handle OP_SAVE_RESTORE_LIST.
  69         (print_mips16_insn_arg): Call `mips_print_save_restore' for
  70         OP_SAVE_RESTORE_LIST handling, factored out from here.
  71         * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
  72         (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
  73         (mips_builtin_opcodes): Add "restore" and "save" entries.
  74         * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
  75         (IAMR2): New macro.
  76         (mips16_opcodes): Add "copyw" and "ucopyw" entries.
  77
  78 2017-06-23  Andrew Waterman  <andrew@sifive.com>
  79
  80         * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
  81         alias; do not mark SLTI instruction as an alias.
  82
  83 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
  84
  85         * i386-dis.c (RM_0FAE_REG_5): Removed.
  86         (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
  87         (PREFIX_MOD_3_0F01_REG_5_RM_0): New.
  88         (PREFIX_MOD_3_0FAE_REG_5): Likewise.
  89         (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1.  Add
  90         PREFIX_MOD_3_0F01_REG_5_RM_0.
  91         (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5.  Add
  92         PREFIX_MOD_3_0FAE_REG_5.
  93         (mod_table): Update MOD_0FAE_REG_5.
  94         (rm_table): Update RM_0F01_REG_5.  Remove RM_0FAE_REG_5.
  95         * i386-opc.tbl: Update incsspd, incsspq and setssbsy.
  96         * i386-tbl.h: Regenerated.
  97
  98 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
  99
 100         * i386-dis.c (prefix_table): Replace savessp with saveprevssp.
 101         * i386-opc.tbl: Likewise.
 102         * i386-tbl.h: Regenerated.
 103
 104 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 105
 106         * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"
 107         and "jmp{&|}".
 108         (NOTRACK_Fixup): Support memory indirect branch with NOTRACK
 109         prefix.
 110
 111 2017-06-19  Nick Clifton  <nickc@redhat.com>
 112
 113         PR binutils/21614
 114         * score-dis.c (score_opcodes): Add sentinel.
 115
 116 2017-06-16  Alan Modra  <amodra@gmail.com>
 117
 118         * rx-decode.c: Regenerate.
 119
 120 2017-06-15  H.J. Lu  <hongjiu.lu@intel.com>
 121
 122         PR binutils/21594
 123         * i386-dis.c (OP_E_register): Check valid bnd register.
 124         (OP_G): Likewise.
 125
 126 2017-06-15  Nick Clifton  <nickc@redhat.com>
 127
 128         PR binutils/21595
 129         * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
 130         range value.
 131
 132 2017-06-15  Nick Clifton  <nickc@redhat.com>
 133
 134         PR binutils/21588
 135         * rl78-decode.opc (OP_BUF_LEN): Define.
 136         (GETBYTE): Check for the index exceeding OP_BUF_LEN.
 137         (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
 138         array.
 139         * rl78-decode.c: Regenerate.
 140
 141 2017-06-15  Nick Clifton  <nickc@redhat.com>
 142
 143         PR binutils/21586
 144         * bfin-dis.c (gregs): Clip index to prevent overflow.
 145         (regs): Likewise.
 146         (regs_lo): Likewise.
 147         (regs_hi): Likewise.
 148
 149 2017-06-14  Nick Clifton  <nickc@redhat.com>
 150
 151         PR binutils/21576
 152         * score7-dis.c (score_opcodes): Add sentinel.
 153
 154 2017-06-14  Yao Qi  <yao.qi@linaro.org>
 155
 156         * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
 157         * arm-dis.c: Likewise.
 158         * ia64-dis.c: Likewise.
 159         * mips-dis.c: Likewise.
 160         * spu-dis.c: Likewise.
 161         * disassemble.h (print_insn_aarch64): New declaration, moved from
 162         include/dis-asm.h.
 163         (print_insn_big_arm, print_insn_big_mips): Likewise.
 164         (print_insn_i386, print_insn_ia64): Likewise.
 165         (print_insn_little_arm, print_insn_little_mips): Likewise.
 166
 167 2017-06-14  Nick Clifton  <nickc@redhat.com>
 168
 169         PR binutils/21587
 170         * rx-decode.opc: Include libiberty.h
 171         (GET_SCALE): New macro - validates access to SCALE array.
 172         (GET_PSCALE): New macro - validates access to PSCALE array.
 173         (DIs, SIs, S2Is, rx_disp): Use new macros.
 174         * rx-decode.c: Regenerate.
 175
 176 2017-07-14  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 177
 178         * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
 179
 180 2017-05-30  Anton Kolesov  <anton.kolesov@synopsys.com>
 181
 182         * arc-dis.c (enforced_isa_mask): Declare.
 183         (cpu_types): Likewise.
 184         (parse_cpu_option): New function.
 185         (parse_disassembler_options): Use it.
 186         (print_insn_arc): Use enforced_isa_mask.
 187         (print_arc_disassembler_options): Document new options.
 188
 189 2017-05-24  Yao Qi  <yao.qi@linaro.org>
 190
 191         * alpha-dis.c: Include disassemble.h, don't include
 192         dis-asm.h.
 193         * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
 194         * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
 195         * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
 196         * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
 197         * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
 198         * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
 199         * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
 200         * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
 201         * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
 202         * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
 203         * moxie-dis.c, msp430-dis.c, mt-dis.c:
 204         * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
 205         * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
 206         * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
 207         * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
 208         * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
 209         * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
 210         * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
 211         * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
 212         * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
 213         * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
 214         * z80-dis.c, z8k-dis.c: Likewise.
 215         * disassemble.h: New file.
 216
 217 2017-05-24  Yao Qi  <yao.qi@linaro.org>
 218
 219         * rl78-dis.c (rl78_get_disassembler): If parameter abfd
 220         is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
 221
 222 2017-05-24  Yao Qi  <yao.qi@linaro.org>
 223
 224         * disassemble.c (disassembler): Add arguments a, big and mach.
 225         Use them.
 226
 227 2017-05-22  H.J. Lu  <hongjiu.lu@intel.com>
 228
 229         * i386-dis.c (NOTRACK_Fixup): New.
 230         (NOTRACK): Likewise.
 231         (NOTRACK_PREFIX): Likewise.
 232         (last_active_prefix): Likewise.
 233         (reg_table): Use NOTRACK on indirect call and jmp.
 234         (ckprefix): Set last_active_prefix.
 235         (prefix_name): Return "notrack" for NOTRACK_PREFIX.
 236         * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
 237         * i386-opc.h (NoTrackPrefixOk): New.
 238         (i386_opcode_modifier): Add notrackprefixok.
 239         * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
 240         Add notrack.
 241         * i386-tbl.h: Regenerated.
 242
 243 2017-05-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
 244
 245         * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
 246         (X_IMM2): Define.
 247         (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
 248         bfd_mach_sparc_v9m8.
 249         (print_insn_sparc): Handle new operand types.
 250         * sparc-opc.c (MASK_M8): Define.
 251         (v6): Add MASK_M8.
 252         (v6notlet): Likewise.
 253         (v7): Likewise.
 254         (v8): Likewise.
 255         (v9): Likewise.
 256         (v9a): Likewise.
 257         (v9b): Likewise.
 258         (v9c): Likewise.
 259         (v9d): Likewise.
 260         (v9e): Likewise.
 261         (v9v): Likewise.
 262         (v9m): Likewise.
 263         (v9andleon): Likewise.
 264         (m8): Define.
 265         (HWS_VM8): Define.
 266         (HWS2_VM8): Likewise.
 267         (sparc_opcode_archs): Add entry for "m8".
 268         (sparc_opcodes): Add OSA2017 and M8 instructions
 269         dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
 270         fpx{ll,ra,rl}64x,
 271         ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
 272         ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
 273         revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
 274         stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
 275         (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
 276         ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
 277         ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
 278         ASI_CORE_SELECT_COMMIT_NHT.
 279
 280 2017-05-18  Alan Modra  <amodra@gmail.com>
 281
 282         * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
 283         * aarch64-dis.c: Likewise.
 284         * aarch64-gen.c: Likewise.
 285         * aarch64-opc.c: Likewise.
 286
 287 2017-05-15  Maciej W. Rozycki  <macro@imgtec.com>
 288             Matthew Fortune  <matthew.fortune@imgtec.com>
 289
 290         * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
 291         ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
 292         (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
 293         (print_insn_arg) <OP_REG28>: Add handler.
 294         (validate_insn_args) <OP_REG28>: Handle.
 295         (print_mips16_insn_arg): Handle MIPS16 instructions that require
 296         32-bit encoding and 9-bit immediates.
 297         (print_insn_mips16): Handle MIPS16 instructions that require
 298         32-bit encoding and MFC0/MTC0 operand decoding.
 299         * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
 300         <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
 301         (RD_C0, WR_C0, E2, E2MT): New macros.
 302         (mips16_opcodes): Add entries for MIPS16e2 instructions:
 303         GP-relative "addiu" and its "addu" spelling, "andi", "cache",
 304         "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
 305         "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
 306         "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
 307         "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
 308         instructions, "swl", "swr", "sync" and its "sync_acquire",
 309         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
 310         "xori", "dmt", "dvpe", "emt" and "evpe".  Add split
 311         regular/extended entries for original MIPS16 ISA revision
 312         instructions whose extended forms are subdecoded in the MIPS16e2
 313         ISA revision: "li", "sll" and "srl".
 314
 315 2017-05-15  Maciej W. Rozycki  <macro@imgtec.com>
 316
 317         * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
 318         reference in CP0 move operand decoding.
 319
 320 2017-05-12  Maciej W. Rozycki  <macro@imgtec.com>
 321
 322         * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
 323         type to hexadecimal.
 324         (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
 325
 326 2017-05-11  Maciej W. Rozycki  <macro@imgtec.com>
 327
 328         * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
 329         "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
 330         "sync_rmb" and "sync_wmb" as aliases.
 331         * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
 332         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
 333
 334 2017-05-10  Claudiu Zissulescu  <claziss@synopsys.com>
 335
 336         * arc-dis.c (parse_option): Update quarkse_em option..
 337         * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
 338         QUARKSE1.
 339         (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
 340
 341 2017-05-03  Kito Cheng  <kito.cheng@gmail.com>
 342
 343         * riscv-dis.c (print_insn_args): Handle 'Co' operands.
 344
 345 2017-05-01  Michael Clark  <michaeljclark@mac.com>
 346
 347         * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
 348         register.
 349
 350 2017-05-02  Maciej W. Rozycki  <macro@imgtec.com>
 351
 352         * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
 353         and branches and not synthetic data instructions.
 354
 355 2017-05-02  Bernd Edlinger   <bernd.edlinger@hotmail.de>
 356
 357         * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
 358
 359 2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>
 360
 361         * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
 362         * arc-opc.c (insert_r13el): New function.
 363         (R13_EL): Define.
 364         * arc-tbl.h: Add new enter/leave variants.
 365
 366 2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>
 367
 368         * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
 369
 370 2017-04-25  Maciej W. Rozycki  <macro@imgtec.com>
 371
 372         * mips-dis.c (print_mips_disassembler_options): Add
 373         `no-aliases'.
 374
 375 2017-04-25  Maciej W. Rozycki  <macro@imgtec.com>
 376
 377         * mips16-opc.c (AL): New macro.
 378         (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
 379         of "ld" and "lw" as aliases.
 380
 381 2017-04-24  Tamar Christina  <tamar.christina@arm.com>
 382
 383         * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
 384         arguments.
 385
 386 2017-04-22  Alexander Fedotov  <alfedotov@gmail.com>
 387             Alan Modra  <amodra@gmail.com>
 388
 389         * ppc-opc.c (ELEV): Define.
 390         (vle_opcodes): Add se_rfgi and e_sc.
 391         (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
 392         for E200Z4.
 393
 394 2017-04-21  Jose E. Marchesi  <jose.marchesi@oracle.com>
 395
 396         * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
 397
 398 2017-04-21  Nick Clifton  <nickc@redhat.com>
 399
 400         PR binutils/21380
 401         * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
 402         LD3R and LD4R.
 403
 404 2017-04-13  Alan Modra  <amodra@gmail.com>
 405
 406         * epiphany-desc.c: Regenerate.
 407         * fr30-desc.c: Regenerate.
 408         * frv-desc.c: Regenerate.
 409         * ip2k-desc.c: Regenerate.
 410         * iq2000-desc.c: Regenerate.
 411         * lm32-desc.c: Regenerate.
 412         * m32c-desc.c: Regenerate.
 413         * m32r-desc.c: Regenerate.
 414         * mep-desc.c: Regenerate.
 415         * mt-desc.c: Regenerate.
 416         * or1k-desc.c: Regenerate.
 417         * xc16x-desc.c: Regenerate.
 418         * xstormy16-desc.c: Regenerate.
 419
 420 2017-04-11  Alan Modra  <amodra@gmail.com>
 421
 422         * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
 423         PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm".  Formatting.  Set
 424         PPC_OPCODE_TMR for e6500.
 425         * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
 426         (PPCVEC3): Define as PPC_OPCODE_POWER9.
 427         (PPCVSX2): Define as PPC_OPCODE_POWER8.
 428         (PPCVSX3): Define as PPC_OPCODE_POWER9.
 429         (PPCHTM): Define as PPC_OPCODE_POWER8.
 430         (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
 431
 432 2017-04-10  Alan Modra  <amodra@gmail.com>
 433
 434         * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
 435         * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
 436         (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
 437         removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
 438
 439 2017-04-09  Pip Cet  <pipcet@gmail.com>
 440
 441         * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
 442         appropriate floating-point precision directly.
 443
 444 2017-04-07  Alan Modra  <amodra@gmail.com>
 445
 446         * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
 447         lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
 448         lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
 449         lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
 450         vector instructions with E6500 not PPCVEC2.
 451
 452 2017-04-06  Pip Cet  <pipcet@gmail.com>
 453
 454         * Makefile.am: Add wasm32-dis.c.
 455         * configure.ac: Add wasm32-dis.c to wasm32 target.
 456         * disassemble.c: Add wasm32 disassembler code.
 457         * wasm32-dis.c: New file.
 458         * Makefile.in: Regenerate.
 459         * configure: Regenerate.
 460         * po/POTFILES.in: Regenerate.
 461         * po/opcodes.pot: Regenerate.
 462
 463 2017-04-05  Pedro Alves  <palves@redhat.com>
 464
 465         * arc-dis.c (parse_option, parse_disassembler_options): Constify.
 466         * arm-dis.c (parse_arm_disassembler_options): Constify.
 467         * ppc-dis.c (powerpc_init_dialect): Constify local.
 468         * vax-dis.c (parse_disassembler_options): Constify.
 469
 470 2017-04-03  Palmer Dabbelt  <palmer@dabbelt.com>
 471
 472         * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
 473         RISCV_GP_SYMBOL.
 474
 475 2017-03-30  Pip Cet  <pipcet@gmail.com>
 476
 477         * configure.ac: Add (empty) bfd_wasm32_arch target.
 478         * configure: Regenerate
 479         * po/opcodes.pot: Regenerate.
 480
 481 2017-03-29  Sheldon Lobo  <sheldon.lobo@oracle.com>
 482
 483         Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
 484         OSA2015.
 485         * opcodes/sparc-opc.c (asi_table): New ASIs.
 486
 487 2017-03-29  Alan Modra  <amodra@gmail.com>
 488
 489         * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags.  Add
 490         "raw" option.
 491         (lookup_powerpc): Don't special case -1 dialect.  Handle
 492         PPC_OPCODE_RAW.
 493         (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
 494         lookup_powerpc call, pass it on second.
 495
 496 2017-03-27  Alan Modra  <amodra@gmail.com>
 497
 498         PR 21303
 499         * ppc-dis.c (struct ppc_mopt): Comment.
 500         (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
 501
 502 2017-03-27  Rinat Zelig  <rinat@mellanox.com>
 503
 504         * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
 505         * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
 506         F_NPS_M, F_NPS_CORE, F_NPS_ALL.
 507         (insert_nps_misc_imm_offset): New function.
 508         (extract_nps_misc imm_offset): New function.
 509         (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
 510         (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
 511
 512 2017-03-21  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 513
 514         * s390-mkopc.c (main): Remove vx2 check.
 515         * s390-opc.txt: Remove vx2 instruction flags.
 516
 517 2017-03-21  Rinat Zelig  <rinat@mellanox.com>
 518
 519         * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
 520         * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
 521         (insert_nps_imm_offset): New function.
 522         (extract_nps_imm_offset): New function.
 523         (insert_nps_imm_entry): New function.
 524         (extract_nps_imm_entry): New function.
 525
 526 2017-03-17  Alan Modra  <amodra@gmail.com>
 527
 528         PR 21248
 529         * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
 530         mtivor32, and mtivor33 for e6500.  Move mfibatl and mfibatu after
 531         those spr mnemonics they alias.  Similarly for mtibatl, mtibatu.
 532
 533 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
 534
 535         * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
 536         <c.andi>: Likewise.
 537         <c.addiw> Likewise.
 538
 539 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
 540
 541         * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
 542
 543 2017-03-13  Andrew Waterman  <andrew@sifive.com>
 544
 545         * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
 546         <srl> Likewise.
 547         <srai> Likewise.
 548         <sra> Likewise.
 549
 550 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 551
 552         * i386-gen.c (opcode_modifiers): Replace S with Load.
 553         * i386-opc.h (S): Removed.
 554         (Load): New.
 555         (i386_opcode_modifier): Replace s with load.
 556         * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
 557         and {evex}.  Replace S with Load.
 558         * i386-tbl.h: Regenerated.
 559
 560 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 561
 562         * i386-opc.tbl: Use CpuCET on rdsspq.
 563         * i386-tbl.h: Regenerated.
 564
 565 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
 566
 567         * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
 568         <vsx>: Do not use PPC_OPCODE_VSX3;
 569
 570 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
 571
 572         * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
 573
 574 2017-03-06  H.J. Lu  <hongjiu.lu@intel.com>
 575
 576         * i386-dis.c (REG_0F1E_MOD_3): New enum.
 577         (MOD_0F1E_PREFIX_1): Likewise.
 578         (MOD_0F38F5_PREFIX_2): Likewise.
 579         (MOD_0F38F6_PREFIX_0): Likewise.
 580         (RM_0F1E_MOD_3_REG_7): Likewise.
 581         (PREFIX_MOD_0_0F01_REG_5): Likewise.
 582         (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
 583         (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
 584         (PREFIX_0F1E): Likewise.
 585         (PREFIX_MOD_0_0FAE_REG_5): Likewise.
 586         (PREFIX_0F38F5): Likewise.
 587         (dis386_twobyte): Use PREFIX_0F1E.
 588         (reg_table): Add REG_0F1E_MOD_3.
 589         (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
 590         PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
 591         PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5.  Update
 592         PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
 593         (three_byte_table): Use PREFIX_0F38F5.
 594         (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
 595         Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
 596         (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
 597         RM_0F1E_MOD_3_REG_7.  Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
 598         PREFIX_MOD_3_0F01_REG_5_RM_2.
 599         * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
 600         (cpu_flags): Add CpuCET.
 601         * i386-opc.h (CpuCET): New enum.
 602         (CpuUnused): Commented out.
 603         (i386_cpu_flags): Add cpucet.
 604         * i386-opc.tbl: Add Intel CET instructions.
 605         * i386-init.h: Regenerated.
 606         * i386-tbl.h: Likewise.
 607
 608 2017-03-06  Alan Modra  <amodra@gmail.com>
 609
 610         PR 21124
 611         * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
 612         (extract_raq, extract_ras, extract_rbx): New functions.
 613         (powerpc_operands): Use opposite corresponding insert function.
 614         (Q_MASK): Define.
 615         (powerpc_opcodes): Apply Q_MASK to all quad insns with even
 616         register restriction.
 617
 618 2017-02-28  Peter Bergner  <bergner@vnet.ibm.com>
 619
 620         * disassemble.c Include "safe-ctype.h".
 621         (disassemble_init_for_target): Handle s390 init.
 622         (remove_whitespace_and_extra_commas): New function.
 623         (disassembler_options_cmp): Likewise.
 624         * arm-dis.c: Include "libiberty.h".
 625         (NUM_ELEM): Delete.
 626         (regnames): Use long disassembler style names.
 627         Add force-thumb and no-force-thumb options.
 628         (NUM_ARM_REGNAMES): Rename from this...
 629         (NUM_ARM_OPTIONS): ...to this.  Use ARRAY_SIZE.
 630         (get_arm_regname_num_options): Delete.
 631         (set_arm_regname_option): Likewise.
 632         (get_arm_regnames): Likewise.
 633         (parse_disassembler_options): Likewise.
 634         (parse_arm_disassembler_option): Rename from this...
 635         (parse_arm_disassembler_options): ...to this.  Make static.
 636         Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
 637         (print_insn): Use parse_arm_disassembler_options.
 638         (disassembler_options_arm): New function.
 639         (print_arm_disassembler_options): Handle updated regnames.
 640         * ppc-dis.c: Include "libiberty.h".
 641         (ppc_opts): Add "32" and "64" entries.
 642         (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
 643         (powerpc_init_dialect): Add break to switch statement.
 644         Use new FOR_EACH_DISASSEMBLER_OPTION macro.
 645         (disassembler_options_powerpc): New function.
 646         (print_ppc_disassembler_options): Use ARRAY_SIZE.
 647         Remove printing of "32" and "64".
 648         * s390-dis.c: Include "libiberty.h".
 649         (init_flag): Remove unneeded variable.
 650         (struct s390_options_t): New structure type.
 651         (options): New structure.
 652         (init_disasm): Rename from this...
 653         (disassemble_init_s390): ...to this.  Add initializations for
 654         current_arch_mask and option_use_insn_len_bits_p.  Remove init_flag.
 655         (print_insn_s390): Delete call to init_disasm.
 656         (disassembler_options_s390): New function.
 657         (print_s390_disassembler_options): Print using information from
 658         struct 'options'.
 659         * po/opcodes.pot: Regenerate.
 660
 661 2017-02-28  Jan Beulich  <jbeulich@suse.com>
 662
 663         * i386-dis.c (PCMPESTR_Fixup): New.
 664         (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
 665         (prefix_table): Use PCMPESTR_Fixup.
 666         (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
 667         PCMPESTR_Fixup.
 668         (vex_w_table): Delete VPCMPESTR{I,M} entries.
 669         * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
 670         Split 64-bit and non-64-bit variants.
 671         * opcodes/i386-tbl.h: Re-generate.
 672
 673 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
 674
 675         * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
 676         (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
 677         (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
 678         (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
 679         (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
 680         (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
 681         (OP_SVE_V_HSD): New macros.
 682         (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
 683         (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
 684         (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
 685         (aarch64_opcode_table): Add new SVE instructions.
 686         (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
 687         for rotation operands.  Add new SVE operands.
 688         * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
 689         (ins_sve_quad_index): Likewise.
 690         (ins_imm_rotate): Split into...
 691         (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
 692         * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
 693         (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
 694         functions.
 695         (aarch64_ins_sve_addr_ri_s4): New function.
 696         (aarch64_ins_sve_quad_index): Likewise.
 697         (do_misc_encoding): Handle "MOV Zn.Q, Qm".
 698         * aarch64-asm-2.c: Regenerate.
 699         * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
 700         (ext_sve_quad_index): Likewise.
 701         (ext_imm_rotate): Split into...
 702         (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
 703         * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
 704         (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
 705         functions.
 706         (aarch64_ext_sve_addr_ri_s4): New function.
 707         (aarch64_ext_sve_quad_index): Likewise.
 708         (aarch64_ext_sve_index): Allow quad indices.
 709         (do_misc_decoding): Likewise.
 710         * aarch64-dis-2.c: Regenerate.
 711         * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
 712         aarch64_field_kinds.
 713         (OPD_F_OD_MASK): Widen by one bit.
 714         (OPD_F_NO_ZR): Bump accordingly.
 715         (get_operand_field_width): New function.
 716         * aarch64-opc.c (fields): Add new SVE fields.
 717         (operand_general_constraint_met_p): Handle new SVE operands.
 718         (aarch64_print_operand): Likewise.
 719         * aarch64-opc-2.c: Regenerate.
 720
 721 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
 722
 723         * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
 724         (aarch64_feature_compnum): ...this.
 725         (SIMD_V8_3): Replace with...
 726         (COMPNUM): ...this.
 727         (CNUM_INSN): New macro.
 728         (aarch64_opcode_table): Use it for the complex number instructions.
 729
 730 2017-02-24  Jan Beulich  <jbeulich@suse.com>
 731
 732         * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
 733
 734 2017-02-23  Sheldon Lobo <sheldon.lobo@oracle.com>
 735
 736         Add support for associating SPARC ASIs with an architecture level.
 737         * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
 738         * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
 739         decoding of SPARC ASIs.
 740
 741 2017-02-23  Jan Beulich  <jbeulich@suse.com>
 742
 743         * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
 744         82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
 745
 746 2017-02-21  Jan Beulich  <jbeulich@suse.com>
 747
 748         * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
 749         1 (instead of to itself). Correct typo.
 750
 751 2017-02-14  Andrew Waterman  <andrew@sifive.com>
 752
 753         * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
 754         pseudoinstructions.
 755
 756 2017-02-15  Richard Sandiford  <richard.sandiford@arm.com>
 757
 758         * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
 759         (aarch64_sys_reg_supported_p): Handle them.
 760
 761 2017-02-15  Claudiu Zissulescu  <claziss@synopsys.com>
 762
 763         * arc-opc.c (UIMM6_20R): Define.
 764         (SIMM12_20): Use above.
 765         (SIMM12_20R): Define.
 766         (SIMM3_5_S): Use above.
 767         (UIMM7_A32_11R_S): Define.
 768         (UIMM7_9_S): Use above.
 769         (UIMM3_13R_S): Define.
 770         (SIMM11_A32_7_S): Use above.
 771         (SIMM9_8R): Define.
 772         (UIMM10_A32_8_S): Use above.
 773         (UIMM8_8R_S): Define.
 774         (W6): Use above.
 775         (arc_relax_opcodes): Use all above defines.
 776
 777 2017-02-15  Vineet Gupta <vgupta@synopsys.com>
 778
 779         * arc-regs.h: Distinguish some of the registers different on
 780         ARC700 and HS38 cpus.
 781
 782 2017-02-14  Alan Modra  <amodra@gmail.com>
 783
 784         PR 21118
 785         * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
 786         with PPC_OPERAND_SPR.  Flag PSQ and PSQM with PPC_OPERAND_GQR.
 787
 788 2017-02-11  Stafford Horne  <shorne@gmail.com>
 789             Alan Modra  <amodra@gmail.com>
 790
 791         * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
 792         Use insn_bytes_value and insn_int_value directly instead.  Don't
 793         free allocated memory until function exit.
 794
 795 2017-02-10  Nicholas Piggin  <npiggin@gmail.com>
 796
 797         * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
 798
 799 2017-02-03  Nick Clifton  <nickc@redhat.com>
 800
 801         PR 21096
 802         * aarch64-opc.c (print_register_list): Ensure that the register
 803         list index will fir into the tb buffer.
 804         (print_register_offset_address): Likewise.
 805         * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
 806
 807 2017-01-27  Alexis Deruell  <alexis.deruelle@gmail.com>
 808
 809         PR 21056
 810         * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
 811         instructions when the previous fetch packet ends with a 32-bit
 812         instruction.
 813
 814 2017-01-24  Dimitar Dimitrov  <dimitar@dinux.eu>
 815
 816         * pru-opc.c: Remove vague reference to a future GDB port.
 817
 818 2017-01-20  Nick Clifton  <nickc@redhat.com>
 819
 820         * po/ga.po: Updated Irish translation.
 821
 822 2017-01-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 823
 824         * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
 825
 826 2017-01-13  Yao Qi  <yao.qi@linaro.org>
 827
 828         * m68k-dis.c (match_insn_m68k): Extend comments.  Return -1
 829         if FETCH_DATA returns 0.
 830         (m68k_scan_mask): Likewise.
 831         (print_insn_m68k): Update code to handle -1 return value.
 832
 833 2017-01-13  Yao Qi  <yao.qi@linaro.org>
 834
 835         * m68k-dis.c (enum print_insn_arg_error): New.
 836         (NEXTBYTE): Replace -3 with
 837         PRINT_INSN_ARG_MEMORY_ERROR.
 838         (NEXTULONG): Likewise.
 839         (NEXTSINGLE): Likewise.
 840         (NEXTDOUBLE): Likewise.
 841         (NEXTDOUBLE): Likewise.
 842         (NEXTPACKED): Likewise.
 843         (FETCH_ARG): Likewise.
 844         (FETCH_DATA): Update comments.
 845         (print_insn_arg): Update comments. Replace magic numbers with
 846         enum.
 847         (match_insn_m68k): Likewise.
 848
 849 2017-01-12  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 850
 851         * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
 852         * i386-dis-evex.h (evex_table): Updated.
 853         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
 854         CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 855         (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
 856         * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
 857         (i386_cpu_flags): Add cpuavx512_vpopcntdq.
 858         * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
 859         * i386-init.h: Regenerate.
 860         * i386-tbl.h: Ditto.
 861
 862 2017-01-12  Yao Qi  <yao.qi@linaro.org>
 863
 864         * msp430-dis.c (msp430_singleoperand): Return -1 if
 865         msp430dis_opcode_signed returns false.
 866         (msp430_doubleoperand): Likewise.
 867         (msp430_branchinstr): Return -1 if
 868         msp430dis_opcode_unsigned returns false.
 869         (msp430x_calla_instr): Likewise.
 870         (print_insn_msp430): Likewise.
 871
 872 2017-01-05  Nick Clifton  <nickc@redhat.com>
 873
 874         PR 20946
 875         * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
 876         could not be matched.
 877         (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
 878         NULL.
 879
 880 2017-01-04  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 881
 882         * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
 883         (aarch64_opcode_table): Use RCPC_INSN.
 884
 885 2017-01-03  Kito Cheng  <kito.cheng@gmail.com>
 886
 887         * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
 888         extension.
 889         * riscv-opcodes/all-opcodes: Likewise.
 890
 891 2017-01-03  Dilyan Palauzov  <dilyan.palauzov@aegee.org>
 892
 893         * riscv-dis.c (print_insn_args): Add fall through comment.
 894
 895 2017-01-03  Nick Clifton  <nickc@redhat.com>
 896
 897         * po/sr.po: New Serbian translation.
 898         * configure.ac (ALL_LINGUAS): Add sr.
 899         * configure: Regenerate.
 900
 901 2017-01-02  Alan Modra  <amodra@gmail.com>
 902
 903         * epiphany-desc.h: Regenerate.
 904         * epiphany-opc.h: Regenerate.
 905         * fr30-desc.h: Regenerate.
 906         * fr30-opc.h: Regenerate.
 907         * frv-desc.h: Regenerate.
 908         * frv-opc.h: Regenerate.
 909         * ip2k-desc.h: Regenerate.
 910         * ip2k-opc.h: Regenerate.
 911         * iq2000-desc.h: Regenerate.
 912         * iq2000-opc.h: Regenerate.
 913         * lm32-desc.h: Regenerate.
 914         * lm32-opc.h: Regenerate.
 915         * m32c-desc.h: Regenerate.
 916         * m32c-opc.h: Regenerate.
 917         * m32r-desc.h: Regenerate.
 918         * m32r-opc.h: Regenerate.
 919         * mep-desc.h: Regenerate.
 920         * mep-opc.h: Regenerate.
 921         * mt-desc.h: Regenerate.
 922         * mt-opc.h: Regenerate.
 923         * or1k-desc.h: Regenerate.
 924         * or1k-opc.h: Regenerate.
 925         * xc16x-desc.h: Regenerate.
 926         * xc16x-opc.h: Regenerate.
 927         * xstormy16-desc.h: Regenerate.
 928         * xstormy16-opc.h: Regenerate.
 929
 930 2017-01-02  Alan Modra  <amodra@gmail.com>
 931
 932         Update year range in copyright notice of all files.
 933
 934 For older changes see ChangeLog-2016
 935 \f
 936 Copyright (C) 2017 Free Software Foundation, Inc.
 937
 938 Copying and distribution of this file, with or without modification,
 939 are permitted in any medium without royalty provided the copyright
 940 notice and this notice are preserved.
 941
 942 Local Variables:
 943 mode: change-log
 944 left-margin: 8
 945 fill-column: 74
 946 version-control: never
 947 End: