opcodes/ChangeLog

   1 2006-09-23  H.J. Lu  <hongjiu.lu@intel.com>
   2
   3         PR binutils/3235
   4         * i386-dis.c (OP_OFF64): Get 32bit offset if there is an
   5         address size prefix.
   6
   7 2006-09-17  Mei Ligang  <ligang@sunnorth.com.cn>
   8
   9         * score-dis.c: New file.
  10         * score-opc.h: New file.
  11         * Makefile.am: Add Score files.
  12         * Makefile.in: Regenerate.
  13         * configure.in: Add support for Score target.
  14         * configure: Regenerate.
  15         * disassemble.c: Add support for Score target.
  16
  17 2006-09-16  Nick Clifton  <nickc@redhat.com>
  18             Pedro Alves  <pedro_alves@portugalmail.pt>
  19
  20         * arm-dis.c: Make use of new STRING_COMMA_LEN and CONST_STRNEQ
  21         macros defined in bfd.h.
  22         * cris-dis.c: Likewise.
  23         * h8300-dis.c: Likewise.
  24         * i386-dis.c: Likewise.
  25         * ia64-gen.c: Likewise.
  26         * mips-dis: Likewise.
  27
  28 2006-09-04  Paul Brook  <paul@codesourcery.com>
  29
  30         * arm-dis.c (neon_opcode): Fix suffix on VMOVN.
  31
  32 2006-08-23  H.J. Lu  <hongjiu.lu@intel.com>
  33
  34         * i386-dis.c (three_byte_table): Expand to 256 elements.
  35
  36 2006-08-04  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
  37
  38         * i386-dis.c (MXC,EMC): Define.
  39         (OP_MXC): New function to handle cvt* (convert instructions) between
  40         %xmm and %mm register correctly.
  41         (OP_EMC): ditto.
  42         (prefix_user_table): Modified cvtpi2pd,cvtpd2pi and cvttpd2pi
  43         instruction operands in PREGRP2,PREGRP3,PREGRP4 appropriately
  44         with EMC/MXC.
  45
  46 2006-07-29  Richard Sandiford  <richard@codesourcery.com>
  47
  48         * m68k-opc.c (m68k_opcodes): Fix operand specificer in the Coldfire
  49         "fdaddl" entry.
  50
  51 2006-07-19  Paul Brook  <paul@codesourcery.com>
  52
  53         * armd-dis.c (arm_opcodes): Fix rbit opcode.
  54
  55 2006-07-18  H.J. Lu  <hongjiu.lu@intel.com>
  56
  57         * i386-dis.c (grps): Change "sldtQ", "strQ" and "smswQ" to
  58         "sldt", "str" and "smsw".
  59
  60 2006-07-15  H.J. Lu  <hongjiu.lu@intel.com>
  61
  62         PR binutils/2829
  63         * i386-dis.c (GRP11_C6): NEW.
  64         (GRP11_C7): Likewise.
  65         (GRP12): Updated.
  66         (GRP13): Likewise.
  67         (GRP14): Likewise.
  68         (GRP15): Likewise.
  69         (GRP16): Likewise.
  70         (GRPAMD): Likewise.
  71         (GRPPADLCK1): Likewise.
  72         (GRPPADLCK2): Likewise.
  73         (dis386): Use GRP11_C6 and GRP11_C7 for entres 0xc6 and 0xc7,
  74         respectively.
  75         (grps): Add entries for GRP11_C6 and GRP11_C7.
  76
  77 2006-07-10 Dwarakanath Rajagopal        <dwarak.rajagopal@amd.com>
  78            Michael Meissner             <michael.meissner@amd.com>
  79
  80         * i386-dis.c (dis386): Add support for 4 operand instructions. Add
  81         support for amdfam10 SSE4a/ABM instructions. Modify all
  82         initializer macros to have additional arguments. Disallow REP
  83         prefix for non-string instructions.
  84         (print_insn): Ditto.
  85
  86
  87 2006-07-05  Julian Brown  <julian@codesourcery.com>
  88
  89         * arm-dis.c (coprocessor): Alter fmsrr disassembly syntax.
  90
  91 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
  92
  93         * i386-dis.c (dis386_twobyte): Use "nopQ" for 0x1f.
  94         (twobyte_has_modrm): Set 1 for 0x1f.
  95
  96 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
  97
  98         * i386-dis.c (NOP_Fixup): Removed.
  99         (NOP_Fixup1): New.
 100         (NOP_Fixup2): Likewise.
 101         (dis386): Use NOP_Fixup1 and NOP_Fixup2 on 0x90.
 102
 103 2006-06-12  Julian Brown  <julian@codesourcery.com>
 104
 105         * arm-dis.c (print_insn_neon): Disassemble 32-bit immediates as signed
 106         on 64-bit hosts.
 107
 108 2006-06-10  H.J. Lu  <hongjiu.lu@intel.com>
 109
 110         * i386.c (GRP10): Renamed to ...
 111         (GRP12): This.
 112         (GRP11): Renamed to ...
 113         (GRP13): This.
 114         (GRP12): Renamed to ...
 115         (GRP14): This.
 116         (GRP13): Renamed to ...
 117         (GRP15): This.
 118         (GRP14): Renamed to ...
 119         (GRP16): This.
 120         (dis386_twobyte): Updated.
 121         (grps): Likewise.
 122
 123 2006-06-09  Nick Clifton  <nickc@redhat.com>
 124
 125         * po/fi.po: Updated Finnish translation.
 126
 127 2006-06-07  Joseph S. Myers  <joseph@codesourcery.com>
 128
 129         * po/Make-in (pdf, ps): New dummy targets.
 130
 131 2006-06-06  Paul Brook  <paul@codesourcery.com>
 132
 133         * arm-dis.c (coprocessor_opcodes): Add %c to unconditional arm
 134         instructions.
 135         (neon_opcodes): Add conditional execution specifiers.
 136         (thumb_opcodes): Ditto.
 137         (thumb32_opcodes): Ditto.
 138         (arm_conditional): Change 0xe to "al" and add "" to end.
 139         (ifthen_state, ifthen_next_state, ifthen_address): New.
 140         (IFTHEN_COND): Define.
 141         (print_insn_coprocessor, print_insn_neon): Print thumb conditions.
 142         (print_insn_arm): Change %c to use new values of arm_conditional.
 143         (print_insn_thumb16): Print thumb conditions.  Add %I.
 144         (print_insn_thumb32): Print thumb conditions.
 145         (find_ifthen_state): New function.
 146         (print_insn): Track IT block state.
 147
 148 2006-06-06  Ben Elliston  <bje@au.ibm.com>
 149             Anton Blanchard  <anton@samba.org>
 150             Peter Bergner  <bergner@vnet.ibm.com>
 151
 152         * ppc-dis.c (powerpc_dialect): Handle power6 option.
 153         (print_ppc_disassembler_options): Mention power6.
 154
 155 2006-06-06  Thiemo Seufer  <ths@mips.com>
 156             Chao-ying Fu  <fu@mips.com>
 157
 158         * mips-dis.c: Disassemble DSP64 instructions for MIPS64R2.
 159         * mips-opc.c: Add DSP64 instructions.
 160
 161 2006-06-06  Alan Modra  <amodra@bigpond.net.au>
 162
 163         * m68hc11-dis.c (print_insn): Warning fix.
 164
 165 2006-06-05  Daniel Jacobowitz  <dan@codesourcery.com>
 166
 167         * po/Make-in (top_builddir): Define.
 168
 169 2006-06-05  Alan Modra  <amodra@bigpond.net.au>
 170
 171         * Makefile.am: Run "make dep-am".
 172         * Makefile.in: Regenerate.
 173         * config.in: Regenerate.
 174
 175 2006-05-31  Daniel Jacobowitz  <dan@codesourcery.com>
 176
 177         * Makefile.am (INCLUDES): Use @INCINTL@.
 178         * acinclude.m4: Include new gettext macros.
 179         * configure.in: Use ZW_GNU_GETTEXT_SISTER_DIR and AM_PO_SUBDIRS.
 180         Remove local code for po/Makefile.
 181         * Makefile.in, aclocal.m4, configure: Regenerated.
 182
 183 2006-05-30  Nick Clifton  <nickc@redhat.com>
 184
 185         * po/es.po: Updated Spanish translation.
 186
 187 2006-05-25  Richard Sandiford  <richard@codesourcery.com>
 188
 189         * m68k-opc.c (m68k_opcodes): Fix the masks of the Coldfire fmovemd
 190         and fmovem entries.  Put register list entries before immediate
 191         mask entries.  Use "l" rather than "L" in the fmovem entries.
 192         * m68k-dis.c (match_insn_m68k): Remove the PRIV argument and work it
 193         out from INFO.
 194         (m68k_scan_mask): New function, split out from...
 195         (print_insn_m68k): ...here.  If no architecture has been set,
 196         first try printing an m680x0 instruction, then try a Coldfire one.
 197
 198 2006-05-24  Nick Clifton  <nickc@redhat.com>
 199
 200         * po/ga.po: Updated Irish translation.
 201
 202 2006-05-22  Nick Clifton  <nickc@redhat.com>
 203
 204         * crx-dis.c (EXTRACT): Make macro work on 64-bit hosts.
 205
 206 2006-05-22  Nick Clifton  <nickc@redhat.com>
 207
 208         * po/nl.po: Updated translation.
 209
 210 2006-05-18  Alan Modra  <amodra@bigpond.net.au>
 211
 212         * avr-dis.c: Formatting fix.
 213
 214 2006-05-14  Thiemo Seufer  <ths@mips.com>
 215
 216         * mips16-opc.c (I1, I32, I64): New shortcut defines.
 217         (mips16_opcodes): Change membership of instructions to their
 218         lowest baseline ISA.
 219
 220 2006-05-09  H.J. Lu  <hongjiu.lu@intel.com>
 221
 222         * i386-dis.c (grps): Update sgdt/sidt for 64bit.
 223
 224 2006-05-05  Julian Brown  <julian@codesourcery.com>
 225
 226         * arm-dis.c (coprocessor_opcodes): Don't interpret fldmx/fstmx as
 227         vldm/vstm.
 228
 229 2006-05-05  Thiemo Seufer  <ths@mips.com>
 230             David Ung  <davidu@mips.com>
 231
 232         * mips-opc.c: Add macro for cache instruction.
 233
 234 2006-05-04  Thiemo Seufer  <ths@mips.com>
 235             Nigel Stephens  <nigel@mips.com>
 236             David Ung  <davidu@mips.com>
 237
 238         * mips-dis.c (mips_arch_choices): Add smartmips instruction
 239         decoding to MIPS32 and MIPS32R2.  Limit DSP decoding to release
 240         2 ISAs.  Add MIPS3D decoding to MIPS32R2.  Add MT decoding to
 241         MIPS64R2.
 242         * mips-opc.c: fix random typos in comments.
 243         (INSN_SMARTMIPS): New defines.
 244         (mips_builtin_opcodes): Add paired single support for MIPS32R2.
 245         Move bc3f, bc3fl, bc3t, bc3tl downwards.  Move flushi, flushd,
 246         flushid, wb upwards.  Move cfc3, ctc3 downwards.  Rework the
 247         FP_S and FP_D flags to denote single and double register
 248         accesses separately.  Move dmfc3, dmtc3, mfc3, mtc3 downwards.
 249         Allow jr.hb and jalr.hb for release 1 ISAs.  Allow luxc1, suxc1
 250         for MIPS32R2.  Add SmartMIPS instructions.  Add two-argument
 251         variants of bc2f, bc2fl, bc2t, bc2tl.  Add mfhc2, mthc2 to
 252         release 2 ISAs.
 253         * mips16-opc.c (mips16_opcodes): Add sdbbp instruction.
 254
 255 2006-05-03  Thiemo Seufer  <ths@mips.com>
 256
 257         * mips-opc.c (mips_builtin_opcodes): Fix mftr argument order.
 258
 259 2006-05-02  Thiemo Seufer  <ths@mips.com>
 260             Nigel Stephens  <nigel@mips.com>
 261             David Ung  <davidu@mips.com>
 262
 263         * mips-dis.c (print_insn_args): Force mips16 to odd addresses.
 264         (print_mips16_insn_arg): Force mips16 to odd addresses.
 265
 266 2006-04-30  Thiemo Seufer  <ths@mips.com>
 267             David Ung  <davidu@mips.com>
 268
 269         * mips-opc.c (mips_builtin_opcodes): Add udi instructions
 270         "udi0" to "udi15".
 271         * mips-dis.c (print_insn_args): Adds udi argument handling.
 272
 273 2006-04-28  James E Wilson  <wilson@specifix.com>
 274
 275         * m68k-dis.c (match_insn_m68k): Restore fprintf_func before printing
 276         error message.
 277
 278 2006-04-28  Thiemo Seufer  <ths@mips.com>
 279             David Ung  <davidu@mips.com>
 280             Nigel Stephens  <nigel@mips.com>
 281
 282         * mips-dis.c (mips_cp0sel_names_mips3264r2): Add MT register
 283         names.
 284
 285 2006-04-28  Thiemo Seufer  <ths@mips.com>
 286             Nigel Stephens  <nigel@mips.com>
 287             David Ung  <davidu@mips.com>
 288
 289         * mips-dis.c (print_insn_args): Add mips_opcode argument.
 290         (print_insn_mips):  Adjust print_insn_args call.
 291
 292 2006-04-28  Thiemo Seufer  <ths@mips.com>
 293             Nigel Stephens  <nigel@mips.com>
 294
 295         * mips-dis.c (print_insn_args): Print $fcc only for FP
 296         instructions, use $cc elsewise.
 297
 298 2006-04-28  Thiemo Seufer  <ths@mips.com>
 299             Nigel Stephens  <nigel@mips.com>
 300
 301         * opcodes/mips-dis.c (mips16_to_32_reg_map, mips16_reg_names):
 302         Map MIPS16 registers to O32 names.
 303         (print_mips16_insn_arg): Use mips16_reg_names.
 304
 305 2006-04-26  Julian Brown  <julian@codesourcery.com>
 306
 307         * arm-dis.c (print_insn_neon): Disassemble floating-point constant
 308         VMOV.
 309
 310 2006-04-26  Nathan Sidwell  <nathan@codesourcery.com>
 311             Julian Brown  <julian@codesourcery.com>
 312
 313         * opcodes/arm-dis.c (coprocessor_opcodes): Add %A, %B, %k, convert
 314         %<code>[zy] into %[zy]<code>.  Expand meaning of %<bitfield>['`?].
 315         Add unified load/store instruction names.
 316         (neon_opcode_table): New.
 317         (arm_opcodes): Expand meaning of %<bitfield>['`?].
 318         (arm_decode_bitfield): New.
 319         (print_insn_coprocessor): Add pc argument. Add %A & %B specifiers.
 320         Use arm_decode_bitfield and adjust numeric specifiers. Adjust %z & %y.
 321         (print_insn_neon): New.
 322         (print_insn_arm): Adjust print_insn_coprocessor call. Call
 323         print_insn_neon. Use arm_decode_bitfield and adjust numeric specifiers.
 324         (print_insn_thumb32): Likewise.
 325
 326 2006-04-19  Alan Modra  <amodra@bigpond.net.au>
 327
 328         * Makefile.am: Run "make dep-am".
 329         * Makefile.in: Regenerate.
 330
 331 2006-04-19  Alan Modra  <amodra@bigpond.net.au>
 332
 333         * avr-dis.c (avr_operand): Warning fix.
 334
 335         * configure: Regenerate.
 336
 337 2006-04-16  Daniel Jacobowitz  <dan@codesourcery.com>
 338
 339         * po/POTFILES.in: Regenerated.
 340
 341 2006-04-12   Hochstein  <hochstein@algo.informatik.tu-darmstadt.de>
 342
 343         PR binutils/2454
 344         * avr-dis.c (avr_operand): Arrange for a comment to appear before
 345         the symolic form of an address, so that the output of objdump -d
 346         can be reassembled.
 347
 348 2006-04-10  DJ Delorie  <dj@redhat.com>
 349
 350         * m32c-asm.c: Regenerate.
 351
 352 2006-04-06  Carlos O'Donell  <carlos@codesourcery.com>
 353
 354         * Makefile.am: Add install-html target.
 355         * Makefile.in: Regenerate.
 356
 357 2006-04-06  Nick Clifton  <nickc@redhat.com>
 358
 359         * po/vi/po: Updated Vietnamese translation.
 360
 361 2006-03-31  Paul Koning  <ni1d@arrl.net>
 362
 363         * pdp11-opc.c (pdp11_opcodes): Fix opcode for SEC instruction.
 364
 365 2006-03-16  Bernd Schmidt  <bernd.schmidt@analog.com>
 366
 367         * bfin-dis.c (decode_dsp32shiftimm_0): Simplify and correct the
 368         logic to identify halfword shifts.
 369
 370 2006-03-16  Paul Brook  <paul@codesourcery.com>
 371
 372         * arm-dis.c (arm_opcodes): Rename swi to svc.
 373         (thumb_opcodes): Ditto.
 374
 375 2006-03-13  DJ Delorie  <dj@redhat.com>
 376
 377         * m32c-asm.c: Regenerate.
 378         * m32c-desc.c: Likewise.
 379         * m32c-desc.h: Likewise.
 380         * m32c-dis.c: Likewise.
 381         * m32c-ibld.c: Likewise.
 382         * m32c-opc.c: Likewise.
 383         * m32c-opc.h: Likewise.
 384
 385 2006-03-10  DJ Delorie  <dj@redhat.com>
 386
 387         * m32c-desc.c: Regenerate with mul.l, mulu.l.
 388         * m32c-opc.c: Likewise.
 389         * m32c-opc.h: Likewise.
 390
 391
 392 2006-03-09  Nick Clifton  <nickc@redhat.com>
 393
 394         * po/sv.po: Updated Swedish translation.
 395
 396 2006-03-07  H.J. Lu  <hongjiu.lu@intel.com>
 397
 398         PR binutils/2428
 399         * i386-dis.c (REP_Fixup): New function.
 400         (AL): Remove duplicate.
 401         (Xbr): New.
 402         (Xvr): Likewise.
 403         (Ybr): Likewise.
 404         (Yvr): Likewise.
 405         (indirDXr): Likewise.
 406         (ALr): Likewise.
 407         (eAXr): Likewise.
 408         (dis386): Updated entries of ins, outs, movs, lods and stos.
 409
 410 2006-03-05  Nick Clifton  <nickc@redhat.com>
 411
 412         * cgen-ibld.in (insert_normal): Cope with attempts to insert a
 413         signed 32-bit value into an unsigned 32-bit field when the host is
 414         a 64-bit machine.
 415         * fr30-ibld.c: Regenerate.
 416         * frv-ibld.c: Regenerate.
 417         * ip2k-ibld.c: Regenerate.
 418         * iq2000-asm.c: Regenerate.
 419         * iq2000-ibld.c: Regenerate.
 420         * m32c-ibld.c: Regenerate.
 421         * m32r-ibld.c: Regenerate.
 422         * openrisc-ibld.c: Regenerate.
 423         * xc16x-ibld.c: Regenerate.
 424         * xstormy16-ibld.c: Regenerate.
 425
 426 2006-03-03 Shrirang Khisti <shrirangk@kpitcummins.com)
 427
 428         * xc16x-asm.c: Regenerate.
 429         * xc16x-dis.c: Regenerate.
 430
 431 2006-02-27  Carlos O'Donell  <carlos@codesourcery.com>
 432
 433         * po/Make-in: Add html target.
 434
 435 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
 436
 437         * i386-dis.c (IS_3BYTE_OPCODE): New for 3-byte opcodes used by
 438         Intel Merom New Instructions.
 439         (THREE_BYTE_0): Likewise.
 440         (THREE_BYTE_1): Likewise.
 441         (three_byte_table): Likewise.
 442         (dis386_twobyte): Use THREE_BYTE_0 for entry 0x38. Use
 443         THREE_BYTE_1 for entry 0x3a.
 444         (twobyte_has_modrm): Updated.
 445         (twobyte_uses_SSE_prefix): Likewise.
 446         (print_insn): Handle 3-byte opcodes used by Intel Merom New
 447         Instructions.
 448
 449 2006-02-24  David S. Miller  <davem@sunset.davemloft.net>
 450
 451         * sparc-dis.c (v9_priv_reg_names): Add "gl" entry.
 452         (v9_hpriv_reg_names): New table.
 453         (print_insn_sparc): Allow values up to 16 for '?' and '!'.
 454         New cases '$' and '%' for read/write hyperprivileged register.
 455         * sparc-opc.c (sparc_opcodes): Add new entries for UA2005
 456         window handling and rdhpr/wrhpr instructions.
 457
 458 2006-02-24  DJ Delorie  <dj@redhat.com>
 459
 460         * m32c-desc.c: Regenerate with linker relaxation attributes.
 461         * m32c-desc.h: Likewise.
 462         * m32c-dis.c: Likewise.
 463         * m32c-opc.c: Likewise.
 464
 465 2006-02-24  Paul Brook  <paul@codesourcery.com>
 466
 467         * arm-dis.c (arm_opcodes): Add V7 instructions.
 468         (thumb32_opcodes): Ditto.  Handle V7M MSR/MRS variants.
 469         (print_arm_address): New function.
 470         (print_insn_arm): Use it.  Add 'P' and 'U' cases.
 471         (psr_name): New function.
 472         (print_insn_thumb32): Add 'U', 'C' and 'D' cases.
 473
 474 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
 475
 476         * ia64-opc-i.c (bXc): New.
 477         (mXc): Likewise.
 478         (OpX2TaTbYaXcC): Likewise.
 479         (TF). Likewise.
 480         (TFCM). Likewise.
 481         (ia64_opcodes_i): Add instructions for tf.
 482
 483         * ia64-opc.h (IMMU5b): New.
 484
 485         * ia64-asmtab.c: Regenerated.
 486
 487 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
 488
 489         * ia64-gen.c: Update copyright years.
 490         * ia64-opc-b.c: Likewise.
 491
 492 2006-02-22  H.J. Lu  <hongjiu.lu@intel.com>
 493
 494         * ia64-gen.c (lookup_regindex): Handle ".vm".
 495         (print_dependency_table): Handle '\"'.
 496
 497         * ia64-ic.tbl: Updated from SDM 2.2.
 498         * ia64-raw.tbl: Likewise.
 499         * ia64-waw.tbl: Likewise.
 500         * ia64-asmtab.c: Regenerated.
 501
 502         * ia64-opc-b.c (ia64_opcodes_b): Add vmsw.0 and vmsw.1.
 503
 504 2006-02-17  Shrirang Khisti  <shrirangk@kpitcummins.com>
 505             Anil Paranjape   <anilp1@kpitcummins.com>
 506             Shilin Shakti    <shilins@kpitcummins.com>
 507
 508         * xc16x-desc.h: New file
 509         * xc16x-desc.c: New file
 510         * xc16x-opc.h: New file
 511         * xc16x-opc.c: New file
 512         * xc16x-ibld.c: New file
 513         * xc16x-asm.c: New file
 514         * xc16x-dis.c: New file
 515         * Makefile.am: Entries for xc16x
 516         * Makefile.in: Regenerate
 517         * cofigure.in: Add xc16x target information.
 518         * configure: Regenerate.
 519         * disassemble.c: Add xc16x target information.
 520
 521 2006-02-11  H.J. Lu  <hongjiu.lu@intel.com>
 522
 523         * i386-dis.c (dis386_twobyte): Use "movZ" for debug register
 524         moves.
 525
 526 2006-02-11  H.J. Lu  <hongjiu.lu@intel.com>
 527
 528         * i386-dis.c ('Z'): Add a new macro.
 529         (dis386_twobyte): Use "movZ" for control register moves.
 530
 531 2006-02-10  Nick Clifton  <nickc@redhat.com>
 532
 533         * iq2000-asm.c: Regenerate.
 534
 535 2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
 536
 537         * m68k-dis.c (print_insn_m68k): Use bfd_m68k_mach_to_features.
 538
 539 2006-01-26  David Ung  <davidu@mips.com>
 540
 541         * mips-opc.c: Add I33 masks to these MIPS32R2 instructions: prefx,
 542         ceil.l.d, ceil.l.s, cvt.d.l, cvt.l.d, cvt.l.s, cvt.s.l, floor.l.d,
 543         floor.l.s, ldxc1, lwxc1, madd.d, madd.s, msub.d, msub.s, nmadd.d,
 544         nmadd.s, nmsub.d, nmsub.s, recip.d, recip.s, round.l.d, rsqrt.d,
 545         rsqrt.s, sdxc1, swxc1, trunc.l.d, trunc.l.s.
 546
 547 2006-01-18  Arnold Metselaar  <arnoldm@sourceware.org>
 548
 549         * z80-dis.c (struct buffer, prt_d, prt_d_n, arit_d, ld_r_d,
 550         ld_d_r, pref_xd_cb): Use signed char to hold data to be
 551         disassembled.
 552         * z80-dis.c (TXTSIZ): Increase buffer size to 24, this fixes
 553         buffer overflows when disassembling instructions like
 554         ld (ix+123),0x23
 555         * z80-dis.c (opc_ind, pref_xd_cb): Suppress '+' in an indexed
 556         operand, if the offset is negative.
 557
 558 2006-01-17  Arnold Metselaar  <arnoldm@sourceware.org>
 559
 560         * z80-dis.c (struct buffer, prt_d, prt_d_n, pref_xd_cb): Use
 561         unsigned char to hold data to be disassembled.
 562
 563 2006-01-17  Andreas Schwab  <schwab@suse.de>
 564
 565         PR binutils/1486
 566         * disassemble.c (disassemble_init_for_target): Set
 567         disassembler_needs_relocs for bfd_arch_arm.
 568
 569 2006-01-16  Paul Brook  <paul@codesourcery.com>
 570
 571         * m68k-opc.c (m68k_opcodes): Fix opcodes for ColdFire f?abss,
 572         f?add?, and f?sub? instructions.
 573
 574 2006-01-16  Nick Clifton  <nickc@redhat.com>
 575
 576         * po/zh_CN.po: New Chinese (simplified) translation.
 577         * configure.in (ALL_LINGUAS): Add "zh_CH".
 578         * configure: Regenerate.
 579
 580 2006-01-05  Paul Brook  <paul@codesourcery.com>
 581
 582         * m68k-opc.c (m68k_opcodes): Add missing ColdFire fdsqrtd entry.
 583
 584 2006-01-06  DJ Delorie  <dj@redhat.com>
 585
 586         * m32c-desc.c: Regenerate.
 587         * m32c-opc.c: Regenerate.
 588         * m32c-opc.h: Regenerate.
 589
 590 2006-01-03  DJ Delorie  <dj@redhat.com>
 591
 592         * cgen-ibld.in (extract_normal): Avoid memory range errors.
 593         * m32c-ibld.c: Regenerated.
 594
 595 For older changes see ChangeLog-2005
 596 \f
 597 Local Variables:
 598 mode: change-log
 599 left-margin: 8
 600 fill-column: 74
 601 version-control: never
 602 End: