opcodes/ChangeLog

   1 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
   2
   3         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
   4         sve_size_hsd2 iclass encode.
   5         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
   6         sve_size_hsd2 iclass decode.
   7         * aarch64-opc.c (fields): Handle SVE_size field.
   8         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
   9
  10 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
  11
  12         * aarch64-asm-2.c: Regenerated.
  13         * aarch64-dis-2.c: Regenerated.
  14         * aarch64-opc-2.c: Regenerated.
  15         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
  16         for SVE_IMM_ROT3.
  17         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
  18         (fields): Handle SVE_rot3 field.
  19         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
  20         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
  21
  22 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
  23
  24         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
  25         instructions.
  26
  27 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
  28
  29         * aarch64-tbl.h
  30         (aarch64_feature_sve2, aarch64_feature_sve2aes,
  31         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
  32         aarch64_feature_sve2bitperm): New feature sets.
  33         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
  34         for feature set addresses.
  35         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
  36         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
  37
  38 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
  39             Faraz Shahbazker  <fshahbazker@wavecomp.com>
  40
  41         * mips-dis.c (mips_calculate_combination_ases): Add ISA
  42         argument and set ASE_EVA_R6 appropriately.
  43         (set_default_mips_dis_options): Pass ISA to above.
  44         (parse_mips_dis_option): Likewise.
  45         * mips-opc.c (EVAR6): New macro.
  46         (mips_builtin_opcodes): Add llwpe, scwpe.
  47
  48 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
  49
  50         * aarch64-asm-2.c: Regenerated.
  51         * aarch64-dis-2.c: Regenerated.
  52         * aarch64-opc-2.c: Regenerated.
  53         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
  54         AARCH64_OPND_TME_UIMM16.
  55         (aarch64_print_operand): Likewise.
  56         * aarch64-tbl.h (QL_IMM_NIL): New.
  57         (TME): New.
  58         (_TME_INSN): New.
  59         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
  60
  61 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
  62
  63         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
  64
  65 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
  66             Faraz Shahbazker  <fshahbazker@wavecomp.com>
  67
  68         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
  69
  70 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
  71
  72         * s12z-opc.h: Add extern "C" bracketing to help
  73         users who wish to use this interface in c++ code.
  74
  75 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
  76
  77         * s12z-opc.c (bm_decode): Handle bit map operations with the
  78         "reserved0" mode.
  79
  80 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
  81
  82         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
  83         specifier.  Add entries for VLDR and VSTR of system registers.
  84         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
  85         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
  86         of %J and %K format specifier.
  87
  88 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
  89
  90         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
  91         Add new entries for VSCCLRM instruction.
  92         (print_insn_coprocessor): Handle new %C format control code.
  93
  94 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
  95
  96         * arm-dis.c (enum isa): New enum.
  97         (struct sopcode32): New structure.
  98         (coprocessor_opcodes): change type of entries to struct sopcode32 and
  99         set isa field of all current entries to ANY.
 100         (print_insn_coprocessor): Change type of insn to struct sopcode32.
 101         Only match an entry if its isa field allows the current mode.
 102
 103 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 104
 105         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
 106         CLRM.
 107         (print_insn_thumb32): Add logic to print %n CLRM register list.
 108
 109 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 110
 111         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
 112         and %Q patterns.
 113
 114 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 115
 116         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
 117         (print_insn_thumb32): Edit the switch case for %Z.
 118
 119 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 120
 121         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
 122
 123 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 124
 125         * arm-dis.c (thumb32_opcodes): New instruction bfl.
 126
 127 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 128
 129         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
 130
 131 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 132
 133         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
 134         Arm register with r13 and r15 unpredictable.
 135         (thumb32_opcodes): New instructions for bfx and bflx.
 136
 137 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 138
 139         * arm-dis.c (thumb32_opcodes): New instructions for bf.
 140
 141 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 142
 143         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
 144
 145 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 146
 147         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
 148
 149 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 150
 151         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
 152
 153 2019-04-12  John Darrington <john@darrington.wattle.id.au>
 154
 155         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
 156         "optr". ("operator" is a reserved word in c++).
 157
 158 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
 159
 160         * aarch64-opc.c (aarch64_print_operand): Add case for
 161         AARCH64_OPND_Rt_SP.
 162         (verify_constraints): Likewise.
 163         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
 164         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
 165         to accept Rt|SP as first operand.
 166         (AARCH64_OPERANDS): Add new Rt_SP.
 167         * aarch64-asm-2.c: Regenerated.
 168         * aarch64-dis-2.c: Regenerated.
 169         * aarch64-opc-2.c: Regenerated.
 170
 171 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
 172
 173         * aarch64-asm-2.c: Regenerated.
 174         * aarch64-dis-2.c: Likewise.
 175         * aarch64-opc-2.c: Likewise.
 176         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
 177
 178 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
 179
 180         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
 181
 182 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
 183
 184         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
 185         * i386-init.h: Regenerated.
 186
 187 2019-04-07  Alan Modra  <amodra@gmail.com>
 188
 189         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
 190         op_separator to control printing of spaces, comma and parens
 191         rather than need_comma, need_paren and spaces vars.
 192
 193 2019-04-07  Alan Modra  <amodra@gmail.com>
 194
 195         PR 24421
 196         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
 197         (print_insn_neon, print_insn_arm): Likewise.
 198
 199 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
 200
 201         * i386-dis-evex.h (evex_table): Updated to support BF16
 202         instructions.
 203         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
 204         and EVEX_W_0F3872_P_3.
 205         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
 206         (cpu_flags): Add bitfield for CpuAVX512_BF16.
 207         * i386-opc.h (enum): Add CpuAVX512_BF16.
 208         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
 209         * i386-opc.tbl: Add AVX512 BF16 instructions.
 210         * i386-init.h: Regenerated.
 211         * i386-tbl.h: Likewise.
 212
 213 2019-04-05  Alan Modra  <amodra@gmail.com>
 214
 215         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
 216         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
 217         to favour printing of "-" branch hint when using the "y" bit.
 218         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
 219
 220 2019-04-05  Alan Modra  <amodra@gmail.com>
 221
 222         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
 223         opcode until first operand is output.
 224
 225 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
 226
 227         PR gas/24349
 228         * ppc-opc.c (valid_bo_pre_v2): Add comments.
 229         (valid_bo_post_v2): Add support for 'at' branch hints.
 230         (insert_bo): Only error on branch on ctr.
 231         (get_bo_hint_mask): New function.
 232         (insert_boe): Add new 'branch_taken' formal argument.  Add support
 233         for inserting 'at' branch hints.
 234         (extract_boe): Add new 'branch_taken' formal argument.  Add support
 235         for extracting 'at' branch hints.
 236         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
 237         (BOE): Delete operand.
 238         (BOM, BOP): New operands.
 239         (RM): Update value.
 240         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
 241         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
 242         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
 243         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
 244         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
 245         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
 246         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
 247         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
 248         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
 249         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
 250         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
 251         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
 252         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
 253         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
 254         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
 255         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
 256         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
 257         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
 258         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
 259         bttarl+>: New extended mnemonics.
 260
 261 2019-03-28  Alan Modra  <amodra@gmail.com>
 262
 263         PR 24390
 264         * ppc-opc.c (BTF): Define.
 265         (powerpc_opcodes): Use for mtfsb*.
 266         * ppc-dis.c (print_insn_powerpc): Print fields with both
 267         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
 268
 269 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 270
 271         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
 272         (mapping_symbol_for_insn): Implement new algorithm.
 273         (print_insn): Remove duplicate code.
 274
 275 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 276
 277         * aarch64-dis.c (print_insn_aarch64):
 278         Implement override.
 279
 280 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 281
 282         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
 283         order.
 284
 285 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 286
 287         * aarch64-dis.c (last_stop_offset): New.
 288         (print_insn_aarch64): Use stop_offset.
 289
 290 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
 291
 292         PR gas/24359
 293         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
 294         CPU_ANY_AVX2_FLAGS.
 295         * i386-init.h: Regenerated.
 296
 297 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
 298
 299         PR gas/24348
 300         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
 301         vmovdqu16, vmovdqu32 and vmovdqu64.
 302         * i386-tbl.h: Regenerated.
 303
 304 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
 305
 306         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
 307         from vstrszb, vstrszh, and vstrszf.
 308
 309 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
 310
 311         * s390-opc.txt: Add instruction descriptions.
 312
 313 2019-02-08  Jim Wilson  <jimw@sifive.com>
 314
 315         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
 316         <bne>: Likewise.
 317
 318 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
 319
 320         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
 321
 322 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
 323
 324         PR binutils/23212
 325         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
 326         * aarch64-opc.c (verify_elem_sd): New.
 327         (fields): Add FLD_sz entr.
 328         * aarch64-tbl.h (_SIMD_INSN): New.
 329         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
 330         fmulx scalar and vector by element isns.
 331
 332 2019-02-07  Nick Clifton  <nickc@redhat.com>
 333
 334         * po/sv.po: Updated Swedish translation.
 335
 336 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
 337
 338         * s390-mkopc.c (main): Accept arch13 as cpu string.
 339         * s390-opc.c: Add new instruction formats and instruction opcode
 340         masks.
 341         * s390-opc.txt: Add new arch13 instructions.
 342
 343 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 344
 345         * aarch64-tbl.h (QL_LDST_AT): Update macro.
 346         (aarch64_opcode): Change encoding for stg, stzg
 347         st2g and st2zg.
 348         * aarch64-asm-2.c: Regenerated.
 349         * aarch64-dis-2.c: Regenerated.
 350         * aarch64-opc-2.c: Regenerated.
 351
 352 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 353
 354         * aarch64-asm-2.c: Regenerated.
 355         * aarch64-dis-2.c: Likewise.
 356         * aarch64-opc-2.c: Likewise.
 357         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
 358
 359 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 360             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
 361
 362         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
 363         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
 364         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
 365         * aarch64-dis.h (ext_addr_simple_2): Likewise.
 366         * aarch64-opc.c (operand_general_constraint_met_p): Remove
 367         case for ldstgv_indexed.
 368         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
 369         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
 370         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
 371         * aarch64-asm-2.c: Regenerated.
 372         * aarch64-dis-2.c: Regenerated.
 373         * aarch64-opc-2.c: Regenerated.
 374
 375 2019-01-23  Nick Clifton  <nickc@redhat.com>
 376
 377         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 378
 379 2019-01-21  Nick Clifton  <nickc@redhat.com>
 380
 381         * po/de.po: Updated German translation.
 382         * po/uk.po: Updated Ukranian translation.
 383
 384 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
 385         * mips-dis.c (mips_arch_choices): Fix typo in
 386         gs464, gs464e and gs264e descriptors.
 387
 388 2019-01-19  Nick Clifton  <nickc@redhat.com>
 389
 390         * configure: Regenerate.
 391         * po/opcodes.pot: Regenerate.
 392
 393 2018-06-24  Nick Clifton  <nickc@redhat.com>
 394
 395         2.32 branch created.
 396
 397 2019-01-09  John Darrington <john@darrington.wattle.id.au>
 398
 399         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
 400         if it is null.
 401         -dis.c (opr_emit_disassembly): Do not omit an index if it is
 402         zero.
 403
 404 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
 405
 406         * configure: Regenerate.
 407
 408 2019-01-07  Alan Modra  <amodra@gmail.com>
 409
 410         * configure: Regenerate.
 411         * po/POTFILES.in: Regenerate.
 412
 413 2019-01-03  John Darrington <john@darrington.wattle.id.au>
 414
 415         * s12z-opc.c: New file.
 416         * s12z-opc.h: New file.
 417         * s12z-dis.c: Removed all code not directly related to display
 418         of instructions.  Used the interface provided by the new files
 419         instead.
 420         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
 421         * Makefile.in: Regenerate.
 422         * configure.ac (bfd_s12z_arch): Correct the dependencies.
 423         * configure: Regenerate.
 424
 425 2019-01-01  Alan Modra  <amodra@gmail.com>
 426
 427         Update year range in copyright notice of all files.
 428
 429 For older changes see ChangeLog-2018
 430 \f
 431 Copyright (C) 2019 Free Software Foundation, Inc.
 432
 433 Copying and distribution of this file, with or without modification,
 434 are permitted in any medium without royalty provided the copyright
 435 notice and this notice are preserved.
 436
 437 Local Variables:
 438 mode: change-log
 439 left-margin: 8
 440 fill-column: 74
 441 version-control: never
 442 End: