opcodes/ChangeLog

   1 2020-02-17  Alan Modra  <amodra@gmail.com>
   2
   3         * i386-gen.c (cpu_flag_init): Correct last change.
   4
   5 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
   6
   7         * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS.  Remove
   8         CPU_ANY_SSE4_FLAGS.
   9
  10 2020-02-14  H.J. Lu  <hongjiu.lu@intel.com>
  11
  12         * i386-opc.tbl (movsx): Remove Intel syntax comments.
  13         (movzx): Likewise.
  14
  15 2020-02-14  Jan Beulich  <jbeulich@suse.com>
  16
  17         PR gas/25438
  18         * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
  19         destination for Cpu64-only variant.
  20         (movzx): Fold patterns.
  21         * i386-tbl.h: Re-generate.
  22
  23 2020-02-13  Jan Beulich  <jbeulich@suse.com>
  24
  25         * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
  26         CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
  27         CPU_ANY_SSE4_FLAGS entry.
  28         * i386-init.h: Re-generate.
  29
  30 2020-02-12  Jan Beulich  <jbeulich@suse.com>
  31
  32         * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
  33         with Unspecified, making the present one AT&T syntax only.
  34         * i386-tbl.h: Re-generate.
  35
  36 2020-02-12  Jan Beulich  <jbeulich@suse.com>
  37
  38         * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
  39         * i386-tbl.h: Re-generate.
  40
  41 2020-02-12  Jan Beulich  <jbeulich@suse.com>
  42
  43         PR gas/24546
  44         * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
  45         * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
  46         Amd64 and Intel64 templates.
  47         (call, jmp): Likewise for far indirect variants. Dro
  48         Unspecified.
  49         * i386-tbl.h: Re-generate.
  50
  51 2020-02-11  Jan Beulich  <jbeulich@suse.com>
  52
  53         * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
  54         * i386-opc.h (ShortForm): Delete.
  55         (struct i386_opcode_modifier): Remove shortform field.
  56         * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
  57         fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
  58         fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
  59         ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
  60         Drop ShortForm.
  61         * i386-tbl.h: Re-generate.
  62
  63 2020-02-11  Jan Beulich  <jbeulich@suse.com>
  64
  65         * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
  66         fucompi): Drop ShortForm from operand-less templates.
  67         * i386-tbl.h: Re-generate.
  68
  69 2020-02-11  Alan Modra  <amodra@gmail.com>
  70
  71         * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
  72         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
  73         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
  74         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
  75         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
  76
  77 2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
  78
  79         * arm-dis.c (print_insn_cde): Define 'V' parse character.
  80         (cde_opcodes): Add VCX* instructions.
  81
  82 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
  83             Matthew Malcomson  <matthew.malcomson@arm.com>
  84
  85         * arm-dis.c (struct cdeopcode32): New.
  86         (CDE_OPCODE): New macro.
  87         (cde_opcodes): New disassembly table.
  88         (regnames): New option to table.
  89         (cde_coprocs): New global variable.
  90         (print_insn_cde): New
  91         (print_insn_thumb32): Use print_insn_cde.
  92         (parse_arm_disassembler_options): Parse coprocN args.
  93
  94 2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
  95
  96         PR gas/25516
  97         * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
  98         with ISA64.
  99         * i386-opc.h (AMD64): Removed.
 100         (Intel64): Likewose.
 101         (AMD64): New.
 102         (INTEL64): Likewise.
 103         (INTEL64ONLY): Likewise.
 104         (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
 105         * i386-opc.tbl (Amd64): New.
 106         (Intel64): Likewise.
 107         (Intel64Only): Likewise.
 108         Replace AMD64 with Amd64.  Update sysenter/sysenter with
 109         Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
 110         * i386-tbl.h: Regenerated.
 111
 112 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
 113
 114         PR 25469
 115         * z80-dis.c: Add support for GBZ80 opcodes.
 116
 117 2020-02-04  Alan Modra  <amodra@gmail.com>
 118
 119         * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
 120
 121 2020-02-03  Alan Modra  <amodra@gmail.com>
 122
 123         * m32c-ibld.c: Regenerate.
 124
 125 2020-02-01  Alan Modra  <amodra@gmail.com>
 126
 127         * frv-ibld.c: Regenerate.
 128
 129 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 130
 131         * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
 132         (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
 133         (OP_E_memory): Replace xmm_mdq_mode case label by
 134         vex_scalar_w_dq_mode one.
 135         * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
 136
 137 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 138
 139         * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
 140         (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
 141         vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
 142         (intel_operand_size): Drop vex_w_dq_mode case label.
 143
 144 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
 145
 146         * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
 147         Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
 148
 149 2020-01-30  Alan Modra  <amodra@gmail.com>
 150
 151         * m32c-ibld.c: Regenerate.
 152
 153 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
 154
 155         * bpf-opc.c: Regenerate.
 156
 157 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 158
 159         * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
 160         (dis386): Use them to replace C2/C3 table entries.
 161         (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
 162         * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
 163         ones. Use Size64 instead of DefaultSize on Intel64 ones.
 164         * i386-tbl.h: Re-generate.
 165
 166 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 167
 168         * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
 169         forms.
 170         (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
 171         DefaultSize.
 172         * i386-tbl.h: Re-generate.
 173
 174 2020-01-30  Alan Modra  <amodra@gmail.com>
 175
 176         * tic4x-dis.c (tic4x_dp): Make unsigned.
 177
 178 2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
 179             Jan Beulich  <jbeulich@suse.com>
 180
 181         PR binutils/25445
 182         * i386-dis.c (MOVSXD_Fixup): New function.
 183         (movsxd_mode): New enum.
 184         (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
 185         (intel_operand_size): Handle movsxd_mode.
 186         (OP_E_register): Likewise.
 187         (OP_G): Likewise.
 188         * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
 189         register on movsxd.  Add movsxd with 16-bit destination register
 190         for AMD64 and Intel64 ISAs.
 191         * i386-tbl.h: Regenerated.
 192
 193 2020-01-27  Tamar Christina  <tamar.christina@arm.com>
 194
 195         PR 25403
 196         * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
 197         * aarch64-asm-2.c: Regenerate
 198         * aarch64-dis-2.c: Likewise.
 199         * aarch64-opc-2.c: Likewise.
 200
 201 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 202
 203         * i386-opc.tbl (sysret): Drop DefaultSize.
 204         * i386-tbl.h: Re-generate.
 205
 206 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 207
 208         * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
 209         Dword.
 210         (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
 211         * i386-tbl.h: Re-generate.
 212
 213 2020-01-20  Nick Clifton  <nickc@redhat.com>
 214
 215         * po/de.po: Updated German translation.
 216         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 217         * po/uk.po: Updated Ukranian translation.
 218
 219 2020-01-20  Alan Modra  <amodra@gmail.com>
 220
 221         * hppa-dis.c (fput_const): Remove useless cast.
 222
 223 2020-01-20  Alan Modra  <amodra@gmail.com>
 224
 225         * arm-dis.c (print_insn_arm): Wrap 'T' value.
 226
 227 2020-01-18  Nick Clifton  <nickc@redhat.com>
 228
 229         * configure: Regenerate.
 230         * po/opcodes.pot: Regenerate.
 231
 232 2020-01-18  Nick Clifton  <nickc@redhat.com>
 233
 234         Binutils 2.34 branch created.
 235
 236 2020-01-17  Christian Biesinger  <cbiesinger@google.com>
 237
 238         * opintl.h: Fix spelling error (seperate).
 239
 240 2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
 241
 242         * i386-opc.tbl: Add {vex} pseudo prefix.
 243         * i386-tbl.h: Regenerated.
 244
 245 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 246
 247         PR 25376
 248         * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
 249         (neon_opcodes): Likewise.
 250         (select_arm_features): Make sure we enable MVE bits when selecting
 251         armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
 252         any architecture.
 253
 254 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 255
 256         * i386-opc.tbl: Drop stale comment from XOP section.
 257
 258 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 259
 260         * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
 261         (extractps): Add VexWIG to SSE2AVX forms.
 262         * i386-tbl.h: Re-generate.
 263
 264 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 265
 266         * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
 267         Size64 from and use VexW1 on SSE2AVX forms.
 268         (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
 269         VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
 270         * i386-tbl.h: Re-generate.
 271
 272 2020-01-15  Alan Modra  <amodra@gmail.com>
 273
 274         * tic4x-dis.c (tic4x_version): Make unsigned long.
 275         (optab, optab_special, registernames): New file scope vars.
 276         (tic4x_print_register): Set up registernames rather than
 277         malloc'd registertable.
 278         (tic4x_disassemble): Delete optable and optable_special.  Use
 279         optab and optab_special instead.  Throw away old optab,
 280         optab_special and registernames when info->mach changes.
 281
 282 2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>
 283
 284         PR 25377
 285         * z80-dis.c (suffix): Use .db instruction to generate double
 286         prefix.
 287
 288 2020-01-14  Alan Modra  <amodra@gmail.com>
 289
 290         * z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
 291         values to unsigned before shifting.
 292
 293 2020-01-13  Thomas Troeger  <tstroege@gmx.de>
 294
 295         * arm-dis.c (print_insn_arm): Fill in insn info fields for control
 296         flow instructions.
 297         (print_insn_thumb16, print_insn_thumb32): Likewise.
 298         (print_insn): Initialize the insn info.
 299         * i386-dis.c (print_insn): Initialize the insn info fields, and
 300         detect jumps.
 301
 302 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 303
 304         * arc-opc.c (C_NE): Make it required.
 305
 306 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 307
 308         * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
 309         reserved register name.
 310
 311 2020-01-13  Alan Modra  <amodra@gmail.com>
 312
 313         * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
 314         (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
 315
 316 2020-01-13  Alan Modra  <amodra@gmail.com>
 317
 318         * wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
 319         result of wasm_read_leb128 in a uint64_t and check that bits
 320         are not lost when copying to other locals.  Use uint32_t for
 321         most locals.  Use PRId64 when printing int64_t.
 322
 323 2020-01-13  Alan Modra  <amodra@gmail.com>
 324
 325         * score-dis.c: Formatting.
 326         * score7-dis.c: Formatting.
 327
 328 2020-01-13  Alan Modra  <amodra@gmail.com>
 329
 330         * score-dis.c (print_insn_score48): Use unsigned variables for
 331         unsigned values.  Don't left shift negative values.
 332         (print_insn_score32): Likewise.
 333         * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
 334
 335 2020-01-13  Alan Modra  <amodra@gmail.com>
 336
 337         * tic4x-dis.c (tic4x_print_register): Remove dead code.
 338
 339 2020-01-13  Alan Modra  <amodra@gmail.com>
 340
 341         * fr30-ibld.c: Regenerate.
 342
 343 2020-01-13  Alan Modra  <amodra@gmail.com>
 344
 345         * xgate-dis.c (print_insn): Don't left shift signed value.
 346         (ripBits): Formatting, use 1u.
 347
 348 2020-01-10  Alan Modra  <amodra@gmail.com>
 349
 350         * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
 351         * tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
 352
 353 2020-01-10  Alan Modra  <amodra@gmail.com>
 354
 355         * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
 356         and XRREG value earlier to avoid a shift with negative exponent.
 357         * m10200-dis.c (disassemble): Similarly.
 358
 359 2020-01-09  Nick Clifton  <nickc@redhat.com>
 360
 361         PR 25224
 362         * z80-dis.c (ld_ii_ii): Use correct cast.
 363
 364 2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 365
 366         PR 25224
 367         * z80-dis.c (ld_ii_ii): Use character constant when checking
 368         opcode byte value.
 369
 370 2020-01-09  Jan Beulich  <jbeulich@suse.com>
 371
 372         * i386-dis.c (SEP_Fixup): New.
 373         (SEP): Define.
 374         (dis386_twobyte): Use it for sysenter/sysexit.
 375         (enum x86_64_isa): Change amd64 enumerator to value 1.
 376         (OP_J): Compare isa64 against intel64 instead of amd64.
 377         * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
 378         forms.
 379         * i386-tbl.h: Re-generate.
 380
 381 2020-01-08  Alan Modra  <amodra@gmail.com>
 382
 383         * z8k-dis.c: Include libiberty.h
 384         (instr_data_s): Make max_fetched unsigned.
 385         (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
 386         Don't exceed byte_info bounds.
 387         (output_instr): Make num_bytes unsigned.
 388         (unpack_instr): Likewise for nibl_count and loop.
 389         * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
 390         idx unsigned.
 391         * z8k-opc.h: Regenerate.
 392
 393 2020-01-07  Shahab Vahedi  <shahab@synopsys.com>
 394
 395         * arc-tbl.h (llock): Use 'LLOCK' as class.
 396         (llockd): Likewise.
 397         (scond): Use 'SCOND' as class.
 398         (scondd): Likewise.
 399         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
 400         (scondd): Likewise.
 401
 402 2020-01-06  Alan Modra  <amodra@gmail.com>
 403
 404         * m32c-ibld.c: Regenerate.
 405
 406 2020-01-06  Alan Modra  <amodra@gmail.com>
 407
 408         PR 25344
 409         * z80-dis.c (suffix): Don't use a local struct buffer copy.
 410         Peek at next byte to prevent recursion on repeated prefix bytes.
 411         Ensure uninitialised "mybuf" is not accessed.
 412         (print_insn_z80): Don't zero n_fetch and n_used here,..
 413         (print_insn_z80_buf): ..do it here instead.
 414
 415 2020-01-04  Alan Modra  <amodra@gmail.com>
 416
 417         * m32r-ibld.c: Regenerate.
 418
 419 2020-01-04  Alan Modra  <amodra@gmail.com>
 420
 421         * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
 422
 423 2020-01-04  Alan Modra  <amodra@gmail.com>
 424
 425         * crx-dis.c (match_opcode): Avoid shift left of signed value.
 426
 427 2020-01-04  Alan Modra  <amodra@gmail.com>
 428
 429         * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
 430
 431 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 432
 433         * aarch64-tbl.h (aarch64_opcode_table): Use
 434         SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
 435
 436 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 437
 438         * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
 439         forms of SUDOT and USDOT.
 440
 441 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 442
 443         * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
 444         uzip{1,2}.
 445         * opcodes/aarch64-dis-2.c: Re-generate.
 446
 447 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 448
 449         * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
 450         FMMLA encoding.
 451         * opcodes/aarch64-dis-2.c: Re-generate.
 452
 453 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
 454
 455         * z80-dis.c: Add support for eZ80 and Z80 instructions.
 456
 457 2020-01-01  Alan Modra  <amodra@gmail.com>
 458
 459         Update year range in copyright notice of all files.
 460
 461 For older changes see ChangeLog-2019
 462 \f
 463 Copyright (C) 2020 Free Software Foundation, Inc.
 464
 465 Copying and distribution of this file, with or without modification,
 466 are permitted in any medium without royalty provided the copyright
 467 notice and this notice are preserved.
 468
 469 Local Variables:
 470 mode: change-log
 471 left-margin: 8
 472 fill-column: 74
 473 version-control: never
 474 End: