opcodes/ChangeLog

   1 2006-12-11  H.J. Lu  <hongjiu.lu@intel.com>
   2
   3         * i386-dis.c (Eq): Replaced by ...
   4         (Mq): New. This.
   5         (Ma): Defined with OP_M instead of OP_E.
   6         (grps): Updated cmpxchg8b and vmptrst for Eq -> Mq.
   7         (OP_M): Added bound, cmpxchg8b and vmptrst to bad modrm list.
   8
   9 2006-12-11  Daniel Jacobowitz  <dan@codesourcery.com>
  10
  11         * po/Make-in (.po.gmo): Put gmo files in objdir.
  12
  13 2006-12-09  H.J. Lu  <hongjiu.lu@intel.com>
  14
  15         * i386-dis.c (X86_64_1): New.
  16         (X86_64_2): Likewise.
  17         (X86_64_3): Likewise.
  18         (dis386): Replace 0x60, 0x61 and 0x62 entries with x86-64
  19         tables.
  20         (x86_64_table): Add entries for 0x60, 0x61 and 0x62.
  21
  22 2006-12-09  H.J. Lu  <hongjiu.lu@intel.com>
  23
  24         * i386-dis.c: Adjust white spaces.
  25
  26 2006-12-04  Jan Beulich  <jbeulich@novell.com>
  27
  28         * i386-dis.c (OP_J): Update used_prefixes in v_mode.
  29
  30 2006-11-30  Jan Beulich  <jbeulich@novell.com>
  31
  32         * i386-dis.c (SEG_Fixup): Delete.
  33         (Sv): Use OP_SEG.
  34         (putop): New suffix character 'D'.
  35         (dis386): Use it.
  36         (grps): Likewise.
  37         (OP_SEG): Handle bytemode other than w_mode.
  38
  39 2006-11-30  Jan Beulich  <jbeulich@novell.com>
  40
  41         * i386-dis.c (zAX): New.
  42         (Xz): New.
  43         (Yzr): New.
  44         (z_mode): New.
  45         (z_mode_ax_reg): New.
  46         (putop): New suffix character 'G'.
  47         (dis386): Use it for in, out, ins, and outs.
  48         (intel_operand_size): Handle z_mode.
  49         (OP_REG): Delete unreachable case indir_dx_reg.
  50         (OP_IMREG): Fix Intel syntax output for case indir_dx_reg. Handle
  51         z_mode_ax_reg.
  52         (OP_ESreg): Fix Intel syntax operand size handling.
  53         (OP_DSreg): Likewise.
  54
  55 2006-11-30  Jan Beulich  <jbeulich@novell.com>
  56
  57         * i386-dis.c (dis386): Use 'R' and 'O' for cbw/cwd unconditionally.
  58         (putop): For 'O' suffix, print 'q' in Intel mode, and mark data prefix
  59         used. For 'R' and 'W' suffix, simplify and fix Intel mode.
  60
  61 2006-11-29  Paul Brook  <paul@codesourcery.com>
  62
  63         * arm-dis.c (coprocessor_opcodes): Fix bitfields for fconstd/fconstd.
  64
  65 2006-11-22  Daniel Jacobowitz  <dan@codesourcery.com>
  66
  67         * arm-dis.c (last_is_thumb): Delete.
  68         (enum map_type, last_type): New.
  69         (print_insn_data): New.
  70         (get_sym_code_type): Take MAP_TYPE argument.  Check the type of
  71         the right symbol.  Handle $d.
  72         (print_insn): Check for mapping symbols even without a normal
  73         symbol.  Adjust searching.  If $d is found see how much data
  74         to print.  Handle data.
  75
  76 2006-11-16  Nathan Sidwell  <nathan@codesourcery.com>
  77
  78         * m68k-opc.c (m68k_opcodes): Place trap instructions before set
  79         conditionals.  Add tpf coldfire instruction as alias for trapf.
  80
  81 2006-11-09  H.J. Lu  <hongjiu.lu@intel.com>
  82
  83         * i386-dis.c (print_insn): Check PREFIX_REPNZ before
  84         PREFIX_DATA when prefix user table is used.
  85
  86 2006-11-09  H.J. Lu  <hongjiu.lu@intel.com>
  87
  88         * i386-dis.c (twobyte_uses_SSE_prefix): Renamed to ...
  89         (twobyte_uses_DATA_prefix): This.
  90         (twobyte_uses_REPNZ_prefix): New.
  91         (twobyte_uses_REPZ_prefix): Likewise.
  92         (threebyte_0x38_uses_DATA_prefix): Likewise.
  93         (threebyte_0x38_uses_REPNZ_prefix): Likewise.
  94         (threebyte_0x38_uses_REPZ_prefix): Likewise.
  95         (threebyte_0x3a_uses_DATA_prefix): Likewise.
  96         (threebyte_0x3a_uses_REPNZ_prefix): Likewise.
  97         (threebyte_0x3a_uses_REPZ_prefix): Likewise.
  98         (print_insn): Updated checking usages of DATA/REPNZ/REPZ
  99         prefixes.
 100
 101 2006-11-06  Troy Rollo  <troy@corvu.com.au>
 102
 103         * ppc-opc.c: Restore COM to mfcr wrongly removed 2003-07-04.
 104
 105 2006-11-01  Mei Ligang  <ligang@sunnorth.com.cn>
 106
 107         * score-opc.h (score_opcodes): Delete modifier '0x'.
 108
 109 2006-10-30  Paul Brook  <paul@codesourcery.com>
 110
 111         * arm-dis.c (last_is_thumb, last_mapping_sym, last_mapping_addr): New.
 112         (get_sym_code_type): New function.
 113         (print_insn): Search for mapping symbols.
 114
 115 2006-10-31  Mei Ligang  <ligang@sunnorth.com.cn>
 116
 117         * score-dis.c (print_insn): Correct the error code to print
 118         correct PCE instruction disassembly.
 119
 120 2006-10-26  Ben Elliston  <bje@au.ibm.com>
 121             Anton Blanchard  <anton@samba.org>
 122             Peter Bergner  <bergner@vnet.ibm.com>
 123
 124         * ppc-opc.c (A_L, DCM, DGM, TE, RMC, R, SP, S, SH16, XRT_L, EH,
 125         AFRALFRC_MASK, Z, ZRC, Z_MASK, XLRT_MASK, XEH_MASK): Define.
 126         (POWER6): Define.
 127         (powerpc_opcodes): Extend "lwarx", "ldarx", "dcbf", "fres", "fres.",
 128         "frsqrtes", "frsqrtes." "fre", "fre.", "frsqrte" and "frsqrte.".
 129         Add "doze", "nap", "sleep", "rvwinkle", "dcbfl", "prtyw", "prtyd",
 130         "mfcfar", "cmpb", "lfdpx", "stfdpx", "mtcfar", "mffgpr", "mftgpr",
 131         "lwzcix", "lhzcix", "lbzcix", "ldcix", "lfiwax", "stwcix", "sthcix",
 132         "stbcix", "stdcix", "lfdp", "dadd", "dadd.", "dqua", "dqua.", "dmul",
 133         "dmul.", "drrnd", "drrnd.", "dscli", "dscli.", "dquai", "dquai.",
 134         "dscri", "dscri.", "drintx", "drintx.", "dcmpo", "dtstex", "dtstdc",
 135         "dtstdg", "dtstsf", "drintn", "drintn.", "dctdp", "dctdp.", "dctfix",
 136         "dctfix.", "ddedpd", "ddedpd.", "dxex", "dxex.", "dsub", "dsub.",
 137         "ddiv", "ddiv.", "dcmpu", "drsp", "drsp.", "dcffix", "dcffix.",
 138         "denbcd", "denbcd.", "diex", "diex.", "stfdp", "daddq", "daddq.",
 139         "dquaq", "dquaq.", "fcpsgn", "fcpsgn.", "dmulq", "dmulq.",
 140         "drrndq", "drrndq.", "dscliq", "dscliq.", "dquaiq", "dquaiq.",
 141         "dscriq", "dscriq.", "drintxq", "drintxq.", "dcmpoq", "dtstexq",
 142         "dtstdcq", "dtstdgq", "dtstsfq", "drintnq", "drintnq.",
 143         "dctqpq", "dctqpq.", "dctfixq", "dctfixq.", "ddedpdq", "ddedpdq.",
 144         "dxexq", "dxexq.", "dsubq", "dsubq.", "ddivq", "ddivq.", "dcmpuq",
 145         "drdpq", "drdpq.", "dcffixq", "dcffixq.", "denbcdq", "denbcdq.",
 146         "diexq" and "diexq." opcodes.
 147
 148 2006-10-26  Daniel Jacobowitz  <dan@codesourcery.com>
 149
 150         * h8300-dis.c (bfd_h8_disassemble): Add missing consts.
 151
 152 2006-10-25  Trevor Smigiel  <Trevor_Smigiel@playstation.sony.com>
 153             Yukishige Shibata  <shibata@rd.scei.sony.co.jp>
 154             Nobuhisa Fujinami  <fnami@rd.scei.sony.co.jp>
 155             Takeaki Fukuoka  <fukuoka@rd.scei.sony.co.jp>
 156             Alan Modra  <amodra@bigpond.net.au>
 157
 158         * spu-dis.c: New file.
 159         * spu-opc.c: New file.
 160         * configure.in: Add SPU support.
 161         * disassemble.c: Likewise.
 162         * Makefile.am: Likewise.  Run "make dep-am".
 163         * Makefile.in: Regenerate.
 164         * configure: Regenerate.
 165         * po/POTFILES.in: Regenerate.
 166
 167 2006-10-24  Andrew Pinski  <andrew_pinski@playstation.sony.com>
 168
 169         * ppc-opc.c (CELL): New define.
 170         (powerpc_opcodes): Enable hrfid for Cell.  Add ldbrx and stdbrx,
 171         cell specific instructions.  Add {st,l}x{r,l}{,l} cell specific
 172         VMX instructions.
 173         * ppc-dis.c (powerpc_dialect): Handle cell.
 174
 175 2006-10-23  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
 176
 177         * i386-dis.c (dis386): Add support for the change in POPCNT opcode in
 178         amdfam10 architecture.
 179         (PREGRP37): NEW.
 180         (print_insn): Disallow REP prefix for POPCNT.
 181
 182 2006-10-20  Andrew Stubbs  <andrew.stubbs@st.com>
 183
 184         * sh-dis.c (print_insn_sh): Remove 0x from output to prevent GDB
 185         duplicating it.
 186
 187 2006-10-18  Dave Brolley  <brolley@redhat.com>
 188
 189         * configure.in (BFD_MACHINES): Add cgen-bitset.lo for bfd_sh_arch.
 190         * configure: Regenerated.
 191
 192 2006-09-29  Alan Modra  <amodra@bigpond.net.au>
 193
 194         * po/POTFILES.in: Regenerate.
 195
 196 2006-09-26  Mark Shinwell  <shinwell@codesourcery.com>
 197             Joseph Myers  <joseph@codesourcery.com>
 198             Ian Lance Taylor  <ian@wasabisystems.com>
 199             Ben Elliston  <bje@wasabisystems.com>
 200
 201         * arm-dis.c (coprocessor_opcodes): The X-qualifier to WMADD may
 202         only be used with the default multiply-add operation, so if N is
 203         set, don't bother printing X.  Add new iwmmxt instructions.
 204         (IWMMXT_INSN_COUNT): Update.
 205         (iwmmxt_wwssnames): Qualify "wwss" names at index 2, 6, 10 and 14
 206         with a 'c' suffix.
 207         (print_insn_coprocessor): Check for iWMMXt2.  Handle format
 208         specifiers 'r', 'i'.
 209
 210 2006-09-24  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
 211
 212         PR binutils/3100
 213         * i386-dis.c (prefix_user_table): Fix the second operand of
 214         maskmovdqu instruction to allow only %xmm register instead of
 215         both %xmm register and memory.
 216
 217 2006-09-23  H.J. Lu  <hongjiu.lu@intel.com>
 218
 219         PR binutils/3235
 220         * i386-dis.c (OP_OFF64): Get 32bit offset if there is an
 221         address size prefix.
 222
 223 2006-09-17  Mei Ligang  <ligang@sunnorth.com.cn>
 224
 225         * score-dis.c: New file.
 226         * score-opc.h: New file.
 227         * Makefile.am: Add Score files.
 228         * Makefile.in: Regenerate.
 229         * configure.in: Add support for Score target.
 230         * configure: Regenerate.
 231         * disassemble.c: Add support for Score target.
 232
 233 2006-09-16  Nick Clifton  <nickc@redhat.com>
 234             Pedro Alves  <pedro_alves@portugalmail.pt>
 235
 236         * arm-dis.c: Make use of new STRING_COMMA_LEN and CONST_STRNEQ
 237         macros defined in bfd.h.
 238         * cris-dis.c: Likewise.
 239         * h8300-dis.c: Likewise.
 240         * i386-dis.c: Likewise.
 241         * ia64-gen.c: Likewise.
 242         * mips-dis: Likewise.
 243
 244 2006-09-04  Paul Brook  <paul@codesourcery.com>
 245
 246         * arm-dis.c (neon_opcode): Fix suffix on VMOVN.
 247
 248 2006-08-23  H.J. Lu  <hongjiu.lu@intel.com>
 249
 250         * i386-dis.c (three_byte_table): Expand to 256 elements.
 251
 252 2006-08-04  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
 253
 254         PR binutils/3000
 255         * i386-dis.c (MXC,EMC): Define.
 256         (OP_MXC): New function to handle cvt* (convert instructions) between
 257         %xmm and %mm register correctly.
 258         (OP_EMC): ditto.
 259         (prefix_user_table): Modified cvtpi2pd,cvtpd2pi and cvttpd2pi
 260         instruction operands in PREGRP2,PREGRP3,PREGRP4 appropriately
 261         with EMC/MXC.
 262
 263 2006-07-29  Richard Sandiford  <richard@codesourcery.com>
 264
 265         * m68k-opc.c (m68k_opcodes): Fix operand specificer in the Coldfire
 266         "fdaddl" entry.
 267
 268 2006-07-19  Paul Brook  <paul@codesourcery.com>
 269
 270         * armd-dis.c (arm_opcodes): Fix rbit opcode.
 271
 272 2006-07-18  H.J. Lu  <hongjiu.lu@intel.com>
 273
 274         * i386-dis.c (grps): Change "sldtQ", "strQ" and "smswQ" to
 275         "sldt", "str" and "smsw".
 276
 277 2006-07-15  H.J. Lu  <hongjiu.lu@intel.com>
 278
 279         PR binutils/2829
 280         * i386-dis.c (GRP11_C6): NEW.
 281         (GRP11_C7): Likewise.
 282         (GRP12): Updated.
 283         (GRP13): Likewise.
 284         (GRP14): Likewise.
 285         (GRP15): Likewise.
 286         (GRP16): Likewise.
 287         (GRPAMD): Likewise.
 288         (GRPPADLCK1): Likewise.
 289         (GRPPADLCK2): Likewise.
 290         (dis386): Use GRP11_C6 and GRP11_C7 for entres 0xc6 and 0xc7,
 291         respectively.
 292         (grps): Add entries for GRP11_C6 and GRP11_C7.
 293
 294 2006-07-10 Dwarakanath Rajagopal        <dwarak.rajagopal@amd.com>
 295            Michael Meissner             <michael.meissner@amd.com>
 296
 297         * i386-dis.c (dis386): Add support for 4 operand instructions. Add
 298         support for amdfam10 SSE4a/ABM instructions. Modify all
 299         initializer macros to have additional arguments. Disallow REP
 300         prefix for non-string instructions.
 301         (print_insn): Ditto.
 302
 303 2006-07-05  Julian Brown  <julian@codesourcery.com>
 304
 305         * arm-dis.c (coprocessor): Alter fmsrr disassembly syntax.
 306
 307 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 308
 309         * i386-dis.c (dis386_twobyte): Use "nopQ" for 0x1f.
 310         (twobyte_has_modrm): Set 1 for 0x1f.
 311
 312 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 313
 314         * i386-dis.c (NOP_Fixup): Removed.
 315         (NOP_Fixup1): New.
 316         (NOP_Fixup2): Likewise.
 317         (dis386): Use NOP_Fixup1 and NOP_Fixup2 on 0x90.
 318
 319 2006-06-12  Julian Brown  <julian@codesourcery.com>
 320
 321         * arm-dis.c (print_insn_neon): Disassemble 32-bit immediates as signed
 322         on 64-bit hosts.
 323
 324 2006-06-10  H.J. Lu  <hongjiu.lu@intel.com>
 325
 326         * i386.c (GRP10): Renamed to ...
 327         (GRP12): This.
 328         (GRP11): Renamed to ...
 329         (GRP13): This.
 330         (GRP12): Renamed to ...
 331         (GRP14): This.
 332         (GRP13): Renamed to ...
 333         (GRP15): This.
 334         (GRP14): Renamed to ...
 335         (GRP16): This.
 336         (dis386_twobyte): Updated.
 337         (grps): Likewise.
 338
 339 2006-06-09  Nick Clifton  <nickc@redhat.com>
 340
 341         * po/fi.po: Updated Finnish translation.
 342
 343 2006-06-07  Joseph S. Myers  <joseph@codesourcery.com>
 344
 345         * po/Make-in (pdf, ps): New dummy targets.
 346
 347 2006-06-06  Paul Brook  <paul@codesourcery.com>
 348
 349         * arm-dis.c (coprocessor_opcodes): Add %c to unconditional arm
 350         instructions.
 351         (neon_opcodes): Add conditional execution specifiers.
 352         (thumb_opcodes): Ditto.
 353         (thumb32_opcodes): Ditto.
 354         (arm_conditional): Change 0xe to "al" and add "" to end.
 355         (ifthen_state, ifthen_next_state, ifthen_address): New.
 356         (IFTHEN_COND): Define.
 357         (print_insn_coprocessor, print_insn_neon): Print thumb conditions.
 358         (print_insn_arm): Change %c to use new values of arm_conditional.
 359         (print_insn_thumb16): Print thumb conditions.  Add %I.
 360         (print_insn_thumb32): Print thumb conditions.
 361         (find_ifthen_state): New function.
 362         (print_insn): Track IT block state.
 363
 364 2006-06-06  Ben Elliston  <bje@au.ibm.com>
 365             Anton Blanchard  <anton@samba.org>
 366             Peter Bergner  <bergner@vnet.ibm.com>
 367
 368         * ppc-dis.c (powerpc_dialect): Handle power6 option.
 369         (print_ppc_disassembler_options): Mention power6.
 370
 371 2006-06-06  Thiemo Seufer  <ths@mips.com>
 372             Chao-ying Fu  <fu@mips.com>
 373
 374         * mips-dis.c: Disassemble DSP64 instructions for MIPS64R2.
 375         * mips-opc.c: Add DSP64 instructions.
 376
 377 2006-06-06  Alan Modra  <amodra@bigpond.net.au>
 378
 379         * m68hc11-dis.c (print_insn): Warning fix.
 380
 381 2006-06-05  Daniel Jacobowitz  <dan@codesourcery.com>
 382
 383         * po/Make-in (top_builddir): Define.
 384
 385 2006-06-05  Alan Modra  <amodra@bigpond.net.au>
 386
 387         * Makefile.am: Run "make dep-am".
 388         * Makefile.in: Regenerate.
 389         * config.in: Regenerate.
 390
 391 2006-05-31  Daniel Jacobowitz  <dan@codesourcery.com>
 392
 393         * Makefile.am (INCLUDES): Use @INCINTL@.
 394         * acinclude.m4: Include new gettext macros.
 395         * configure.in: Use ZW_GNU_GETTEXT_SISTER_DIR and AM_PO_SUBDIRS.
 396         Remove local code for po/Makefile.
 397         * Makefile.in, aclocal.m4, configure: Regenerated.
 398
 399 2006-05-30  Nick Clifton  <nickc@redhat.com>
 400
 401         * po/es.po: Updated Spanish translation.
 402
 403 2006-05-25  Richard Sandiford  <richard@codesourcery.com>
 404
 405         * m68k-opc.c (m68k_opcodes): Fix the masks of the Coldfire fmovemd
 406         and fmovem entries.  Put register list entries before immediate
 407         mask entries.  Use "l" rather than "L" in the fmovem entries.
 408         * m68k-dis.c (match_insn_m68k): Remove the PRIV argument and work it
 409         out from INFO.
 410         (m68k_scan_mask): New function, split out from...
 411         (print_insn_m68k): ...here.  If no architecture has been set,
 412         first try printing an m680x0 instruction, then try a Coldfire one.
 413
 414 2006-05-24  Nick Clifton  <nickc@redhat.com>
 415
 416         * po/ga.po: Updated Irish translation.
 417
 418 2006-05-22  Nick Clifton  <nickc@redhat.com>
 419
 420         * crx-dis.c (EXTRACT): Make macro work on 64-bit hosts.
 421
 422 2006-05-22  Nick Clifton  <nickc@redhat.com>
 423
 424         * po/nl.po: Updated translation.
 425
 426 2006-05-18  Alan Modra  <amodra@bigpond.net.au>
 427
 428         * avr-dis.c: Formatting fix.
 429
 430 2006-05-14  Thiemo Seufer  <ths@mips.com>
 431
 432         * mips16-opc.c (I1, I32, I64): New shortcut defines.
 433         (mips16_opcodes): Change membership of instructions to their
 434         lowest baseline ISA.
 435
 436 2006-05-09  H.J. Lu  <hongjiu.lu@intel.com>
 437
 438         * i386-dis.c (grps): Update sgdt/sidt for 64bit.
 439
 440 2006-05-05  Julian Brown  <julian@codesourcery.com>
 441
 442         * arm-dis.c (coprocessor_opcodes): Don't interpret fldmx/fstmx as
 443         vldm/vstm.
 444
 445 2006-05-05  Thiemo Seufer  <ths@mips.com>
 446             David Ung  <davidu@mips.com>
 447
 448         * mips-opc.c: Add macro for cache instruction.
 449
 450 2006-05-04  Thiemo Seufer  <ths@mips.com>
 451             Nigel Stephens  <nigel@mips.com>
 452             David Ung  <davidu@mips.com>
 453
 454         * mips-dis.c (mips_arch_choices): Add smartmips instruction
 455         decoding to MIPS32 and MIPS32R2.  Limit DSP decoding to release
 456         2 ISAs.  Add MIPS3D decoding to MIPS32R2.  Add MT decoding to
 457         MIPS64R2.
 458         * mips-opc.c: fix random typos in comments.
 459         (INSN_SMARTMIPS): New defines.
 460         (mips_builtin_opcodes): Add paired single support for MIPS32R2.
 461         Move bc3f, bc3fl, bc3t, bc3tl downwards.  Move flushi, flushd,
 462         flushid, wb upwards.  Move cfc3, ctc3 downwards.  Rework the
 463         FP_S and FP_D flags to denote single and double register
 464         accesses separately.  Move dmfc3, dmtc3, mfc3, mtc3 downwards.
 465         Allow jr.hb and jalr.hb for release 1 ISAs.  Allow luxc1, suxc1
 466         for MIPS32R2.  Add SmartMIPS instructions.  Add two-argument
 467         variants of bc2f, bc2fl, bc2t, bc2tl.  Add mfhc2, mthc2 to
 468         release 2 ISAs.
 469         * mips16-opc.c (mips16_opcodes): Add sdbbp instruction.
 470
 471 2006-05-03  Thiemo Seufer  <ths@mips.com>
 472
 473         * mips-opc.c (mips_builtin_opcodes): Fix mftr argument order.
 474
 475 2006-05-02  Thiemo Seufer  <ths@mips.com>
 476             Nigel Stephens  <nigel@mips.com>
 477             David Ung  <davidu@mips.com>
 478
 479         * mips-dis.c (print_insn_args): Force mips16 to odd addresses.
 480         (print_mips16_insn_arg): Force mips16 to odd addresses.
 481
 482 2006-04-30  Thiemo Seufer  <ths@mips.com>
 483             David Ung  <davidu@mips.com>
 484
 485         * mips-opc.c (mips_builtin_opcodes): Add udi instructions
 486         "udi0" to "udi15".
 487         * mips-dis.c (print_insn_args): Adds udi argument handling.
 488
 489 2006-04-28  James E Wilson  <wilson@specifix.com>
 490
 491         * m68k-dis.c (match_insn_m68k): Restore fprintf_func before printing
 492         error message.
 493
 494 2006-04-28  Thiemo Seufer  <ths@mips.com>
 495             David Ung  <davidu@mips.com>
 496             Nigel Stephens  <nigel@mips.com>
 497
 498         * mips-dis.c (mips_cp0sel_names_mips3264r2): Add MT register
 499         names.
 500
 501 2006-04-28  Thiemo Seufer  <ths@mips.com>
 502             Nigel Stephens  <nigel@mips.com>
 503             David Ung  <davidu@mips.com>
 504
 505         * mips-dis.c (print_insn_args): Add mips_opcode argument.
 506         (print_insn_mips):  Adjust print_insn_args call.
 507
 508 2006-04-28  Thiemo Seufer  <ths@mips.com>
 509             Nigel Stephens  <nigel@mips.com>
 510
 511         * mips-dis.c (print_insn_args): Print $fcc only for FP
 512         instructions, use $cc elsewise.
 513
 514 2006-04-28  Thiemo Seufer  <ths@mips.com>
 515             Nigel Stephens  <nigel@mips.com>
 516
 517         * opcodes/mips-dis.c (mips16_to_32_reg_map, mips16_reg_names):
 518         Map MIPS16 registers to O32 names.
 519         (print_mips16_insn_arg): Use mips16_reg_names.
 520
 521 2006-04-26  Julian Brown  <julian@codesourcery.com>
 522
 523         * arm-dis.c (print_insn_neon): Disassemble floating-point constant
 524         VMOV.
 525
 526 2006-04-26  Nathan Sidwell  <nathan@codesourcery.com>
 527             Julian Brown  <julian@codesourcery.com>
 528
 529         * opcodes/arm-dis.c (coprocessor_opcodes): Add %A, %B, %k, convert
 530         %<code>[zy] into %[zy]<code>.  Expand meaning of %<bitfield>['`?].
 531         Add unified load/store instruction names.
 532         (neon_opcode_table): New.
 533         (arm_opcodes): Expand meaning of %<bitfield>['`?].
 534         (arm_decode_bitfield): New.
 535         (print_insn_coprocessor): Add pc argument. Add %A & %B specifiers.
 536         Use arm_decode_bitfield and adjust numeric specifiers. Adjust %z & %y.
 537         (print_insn_neon): New.
 538         (print_insn_arm): Adjust print_insn_coprocessor call. Call
 539         print_insn_neon. Use arm_decode_bitfield and adjust numeric specifiers.
 540         (print_insn_thumb32): Likewise.
 541
 542 2006-04-19  Alan Modra  <amodra@bigpond.net.au>
 543
 544         * Makefile.am: Run "make dep-am".
 545         * Makefile.in: Regenerate.
 546
 547 2006-04-19  Alan Modra  <amodra@bigpond.net.au>
 548
 549         * avr-dis.c (avr_operand): Warning fix.
 550
 551         * configure: Regenerate.
 552
 553 2006-04-16  Daniel Jacobowitz  <dan@codesourcery.com>
 554
 555         * po/POTFILES.in: Regenerated.
 556
 557 2006-04-12   Hochstein  <hochstein@algo.informatik.tu-darmstadt.de>
 558
 559         PR binutils/2454
 560         * avr-dis.c (avr_operand): Arrange for a comment to appear before
 561         the symolic form of an address, so that the output of objdump -d
 562         can be reassembled.
 563
 564 2006-04-10  DJ Delorie  <dj@redhat.com>
 565
 566         * m32c-asm.c: Regenerate.
 567
 568 2006-04-06  Carlos O'Donell  <carlos@codesourcery.com>
 569
 570         * Makefile.am: Add install-html target.
 571         * Makefile.in: Regenerate.
 572
 573 2006-04-06  Nick Clifton  <nickc@redhat.com>
 574
 575         * po/vi/po: Updated Vietnamese translation.
 576
 577 2006-03-31  Paul Koning  <ni1d@arrl.net>
 578
 579         * pdp11-opc.c (pdp11_opcodes): Fix opcode for SEC instruction.
 580
 581 2006-03-16  Bernd Schmidt  <bernd.schmidt@analog.com>
 582
 583         * bfin-dis.c (decode_dsp32shiftimm_0): Simplify and correct the
 584         logic to identify halfword shifts.
 585
 586 2006-03-16  Paul Brook  <paul@codesourcery.com>
 587
 588         * arm-dis.c (arm_opcodes): Rename swi to svc.
 589         (thumb_opcodes): Ditto.
 590
 591 2006-03-13  DJ Delorie  <dj@redhat.com>
 592
 593         * m32c-asm.c: Regenerate.
 594         * m32c-desc.c: Likewise.
 595         * m32c-desc.h: Likewise.
 596         * m32c-dis.c: Likewise.
 597         * m32c-ibld.c: Likewise.
 598         * m32c-opc.c: Likewise.
 599         * m32c-opc.h: Likewise.
 600
 601 2006-03-10  DJ Delorie  <dj@redhat.com>
 602
 603         * m32c-desc.c: Regenerate with mul.l, mulu.l.
 604         * m32c-opc.c: Likewise.
 605         * m32c-opc.h: Likewise.
 606
 607
 608 2006-03-09  Nick Clifton  <nickc@redhat.com>
 609
 610         * po/sv.po: Updated Swedish translation.
 611
 612 2006-03-07  H.J. Lu  <hongjiu.lu@intel.com>
 613
 614         PR binutils/2428
 615         * i386-dis.c (REP_Fixup): New function.
 616         (AL): Remove duplicate.
 617         (Xbr): New.
 618         (Xvr): Likewise.
 619         (Ybr): Likewise.
 620         (Yvr): Likewise.
 621         (indirDXr): Likewise.
 622         (ALr): Likewise.
 623         (eAXr): Likewise.
 624         (dis386): Updated entries of ins, outs, movs, lods and stos.
 625
 626 2006-03-05  Nick Clifton  <nickc@redhat.com>
 627
 628         * cgen-ibld.in (insert_normal): Cope with attempts to insert a
 629         signed 32-bit value into an unsigned 32-bit field when the host is
 630         a 64-bit machine.
 631         * fr30-ibld.c: Regenerate.
 632         * frv-ibld.c: Regenerate.
 633         * ip2k-ibld.c: Regenerate.
 634         * iq2000-asm.c: Regenerate.
 635         * iq2000-ibld.c: Regenerate.
 636         * m32c-ibld.c: Regenerate.
 637         * m32r-ibld.c: Regenerate.
 638         * openrisc-ibld.c: Regenerate.
 639         * xc16x-ibld.c: Regenerate.
 640         * xstormy16-ibld.c: Regenerate.
 641
 642 2006-03-03 Shrirang Khisti <shrirangk@kpitcummins.com)
 643
 644         * xc16x-asm.c: Regenerate.
 645         * xc16x-dis.c: Regenerate.
 646
 647 2006-02-27  Carlos O'Donell  <carlos@codesourcery.com>
 648
 649         * po/Make-in: Add html target.
 650
 651 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
 652
 653         * i386-dis.c (IS_3BYTE_OPCODE): New for 3-byte opcodes used by
 654         Intel Merom New Instructions.
 655         (THREE_BYTE_0): Likewise.
 656         (THREE_BYTE_1): Likewise.
 657         (three_byte_table): Likewise.
 658         (dis386_twobyte): Use THREE_BYTE_0 for entry 0x38. Use
 659         THREE_BYTE_1 for entry 0x3a.
 660         (twobyte_has_modrm): Updated.
 661         (twobyte_uses_SSE_prefix): Likewise.
 662         (print_insn): Handle 3-byte opcodes used by Intel Merom New
 663         Instructions.
 664
 665 2006-02-24  David S. Miller  <davem@sunset.davemloft.net>
 666
 667         * sparc-dis.c (v9_priv_reg_names): Add "gl" entry.
 668         (v9_hpriv_reg_names): New table.
 669         (print_insn_sparc): Allow values up to 16 for '?' and '!'.
 670         New cases '$' and '%' for read/write hyperprivileged register.
 671         * sparc-opc.c (sparc_opcodes): Add new entries for UA2005
 672         window handling and rdhpr/wrhpr instructions.
 673
 674 2006-02-24  DJ Delorie  <dj@redhat.com>
 675
 676         * m32c-desc.c: Regenerate with linker relaxation attributes.
 677         * m32c-desc.h: Likewise.
 678         * m32c-dis.c: Likewise.
 679         * m32c-opc.c: Likewise.
 680
 681 2006-02-24  Paul Brook  <paul@codesourcery.com>
 682
 683         * arm-dis.c (arm_opcodes): Add V7 instructions.
 684         (thumb32_opcodes): Ditto.  Handle V7M MSR/MRS variants.
 685         (print_arm_address): New function.
 686         (print_insn_arm): Use it.  Add 'P' and 'U' cases.
 687         (psr_name): New function.
 688         (print_insn_thumb32): Add 'U', 'C' and 'D' cases.
 689
 690 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
 691
 692         * ia64-opc-i.c (bXc): New.
 693         (mXc): Likewise.
 694         (OpX2TaTbYaXcC): Likewise.
 695         (TF). Likewise.
 696         (TFCM). Likewise.
 697         (ia64_opcodes_i): Add instructions for tf.
 698
 699         * ia64-opc.h (IMMU5b): New.
 700
 701         * ia64-asmtab.c: Regenerated.
 702
 703 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
 704
 705         * ia64-gen.c: Update copyright years.
 706         * ia64-opc-b.c: Likewise.
 707
 708 2006-02-22  H.J. Lu  <hongjiu.lu@intel.com>
 709
 710         * ia64-gen.c (lookup_regindex): Handle ".vm".
 711         (print_dependency_table): Handle '\"'.
 712
 713         * ia64-ic.tbl: Updated from SDM 2.2.
 714         * ia64-raw.tbl: Likewise.
 715         * ia64-waw.tbl: Likewise.
 716         * ia64-asmtab.c: Regenerated.
 717
 718         * ia64-opc-b.c (ia64_opcodes_b): Add vmsw.0 and vmsw.1.
 719
 720 2006-02-17  Shrirang Khisti  <shrirangk@kpitcummins.com>
 721             Anil Paranjape   <anilp1@kpitcummins.com>
 722             Shilin Shakti    <shilins@kpitcummins.com>
 723
 724         * xc16x-desc.h: New file
 725         * xc16x-desc.c: New file
 726         * xc16x-opc.h: New file
 727         * xc16x-opc.c: New file
 728         * xc16x-ibld.c: New file
 729         * xc16x-asm.c: New file
 730         * xc16x-dis.c: New file
 731         * Makefile.am: Entries for xc16x
 732         * Makefile.in: Regenerate
 733         * cofigure.in: Add xc16x target information.
 734         * configure: Regenerate.
 735         * disassemble.c: Add xc16x target information.
 736
 737 2006-02-11  H.J. Lu  <hongjiu.lu@intel.com>
 738
 739         * i386-dis.c (dis386_twobyte): Use "movZ" for debug register
 740         moves.
 741
 742 2006-02-11  H.J. Lu  <hongjiu.lu@intel.com>
 743
 744         * i386-dis.c ('Z'): Add a new macro.
 745         (dis386_twobyte): Use "movZ" for control register moves.
 746
 747 2006-02-10  Nick Clifton  <nickc@redhat.com>
 748
 749         * iq2000-asm.c: Regenerate.
 750
 751 2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
 752
 753         * m68k-dis.c (print_insn_m68k): Use bfd_m68k_mach_to_features.
 754
 755 2006-01-26  David Ung  <davidu@mips.com>
 756
 757         * mips-opc.c: Add I33 masks to these MIPS32R2 instructions: prefx,
 758         ceil.l.d, ceil.l.s, cvt.d.l, cvt.l.d, cvt.l.s, cvt.s.l, floor.l.d,
 759         floor.l.s, ldxc1, lwxc1, madd.d, madd.s, msub.d, msub.s, nmadd.d,
 760         nmadd.s, nmsub.d, nmsub.s, recip.d, recip.s, round.l.d, rsqrt.d,
 761         rsqrt.s, sdxc1, swxc1, trunc.l.d, trunc.l.s.
 762
 763 2006-01-18  Arnold Metselaar  <arnoldm@sourceware.org>
 764
 765         * z80-dis.c (struct buffer, prt_d, prt_d_n, arit_d, ld_r_d,
 766         ld_d_r, pref_xd_cb): Use signed char to hold data to be
 767         disassembled.
 768         * z80-dis.c (TXTSIZ): Increase buffer size to 24, this fixes
 769         buffer overflows when disassembling instructions like
 770         ld (ix+123),0x23
 771         * z80-dis.c (opc_ind, pref_xd_cb): Suppress '+' in an indexed
 772         operand, if the offset is negative.
 773
 774 2006-01-17  Arnold Metselaar  <arnoldm@sourceware.org>
 775
 776         * z80-dis.c (struct buffer, prt_d, prt_d_n, pref_xd_cb): Use
 777         unsigned char to hold data to be disassembled.
 778
 779 2006-01-17  Andreas Schwab  <schwab@suse.de>
 780
 781         PR binutils/1486
 782         * disassemble.c (disassemble_init_for_target): Set
 783         disassembler_needs_relocs for bfd_arch_arm.
 784
 785 2006-01-16  Paul Brook  <paul@codesourcery.com>
 786
 787         * m68k-opc.c (m68k_opcodes): Fix opcodes for ColdFire f?abss,
 788         f?add?, and f?sub? instructions.
 789
 790 2006-01-16  Nick Clifton  <nickc@redhat.com>
 791
 792         * po/zh_CN.po: New Chinese (simplified) translation.
 793         * configure.in (ALL_LINGUAS): Add "zh_CH".
 794         * configure: Regenerate.
 795
 796 2006-01-05  Paul Brook  <paul@codesourcery.com>
 797
 798         * m68k-opc.c (m68k_opcodes): Add missing ColdFire fdsqrtd entry.
 799
 800 2006-01-06  DJ Delorie  <dj@redhat.com>
 801
 802         * m32c-desc.c: Regenerate.
 803         * m32c-opc.c: Regenerate.
 804         * m32c-opc.h: Regenerate.
 805
 806 2006-01-03  DJ Delorie  <dj@redhat.com>
 807
 808         * cgen-ibld.in (extract_normal): Avoid memory range errors.
 809         * m32c-ibld.c: Regenerated.
 810
 811 For older changes see ChangeLog-2005
 812 \f
 813 Local Variables:
 814 mode: change-log
 815 left-margin: 8
 816 fill-column: 74
 817 version-control: never
 818 End: