opcodes/ChangeLog

   1 2013-12-16  Andrew Bennett  <andrew.bennett@imgtec.com>
   2
   3         * mips-dis.c: Add mips_cp1_names pointer.
   4         (mips_cp1_names_numeric): New array.
   5         (mips_cp1_names_mips3264): New array.
   6         (mips_arch_choice): Add cp1_names.
   7         (mips_arch_choices): Add relevant cp1 register name array to each of
   8         the elements.
   9         (set_default_mips_dis_options): Add support for setting up the
  10         mips_cp1_names pointer.
  11         (parse_mips_dis_option): Add support for the cp1-names command line
  12         variable.  Also setup the mips_cp1_names pointer.
  13         (print_reg): Print out name of the cp1 register.
  14
  15 2013-12-16  Andrew Bennett  <andrew.bennett@imgtec.com>
  16
  17         * micromips-opc.c (decode_micromips_operand): Reduced range of +o, +u,
  18         +v and +w.
  19         (micromips_opcodes): Reduced element index range for sldi, splati,
  20         copy_s, copy_u, insert and insve instructions.
  21         * opcodes/mips-opc.c (decode_mips_operand): Reduced range of +o, +u,
  22         +v and +w.
  23         (mips_builtin_opcodes): Reduced element index range for sldi, splati,
  24         copy_s, copy_u, insert and insve instructions.
  25
  26 2013-12-13  Jan-Benedict Glaw  <jbglaw@lug-owl.de>
  27
  28         * nds32-dis.c (mnemonic_96): Fix typo.
  29
  30 2013-12-13  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
  31             Wei-Cheng Wang  <cole945@gmail.com>
  32
  33         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nds32-asm.c
  34         and nds32-dis.c.
  35         * Makefile.in: Regenerate.
  36         * configure.in: Add case for bfd_nds32_arch.
  37         * configure: Regenerate.
  38         * disassemble.c (ARCH_nds32): Define.
  39         * nds32-asm.c: New file for nds32.
  40         * nds32-asm.h: New file for nds32.
  41         * nds32-dis.c: New file for nds32.
  42         * nds32-opc.h: New file for nds32.
  43
  44 2013-12-05  Nick Clifton  <nickc@redhat.com>
  45
  46         * s390-mkopc.c (dumpTable): Provide a format string to printf so
  47         that compiling with -Werror=format-security does not produce an
  48         error.
  49
  50 2013-11-20  Yufeng Zhang  <yufeng.zhang@arm.com>
  51
  52         * aarch64-opc.c (aarch64_pstatefields): Update.
  53
  54 2013-11-19  Catherine Moore  <clm@codesourcery.com>
  55
  56         * micromips-opc.c (LM): Define.
  57         (micromips_opcodes): Add LM to load instructions.
  58         * mips-opc.c (prefe): Add LM attribute.
  59
  60 2013-11-18  Yufeng Zhang  <yufeng.zhang@arm.com>
  61
  62         Revert
  63
  64         2013-11-15  Yufeng Zhang  <yufeng.zhang@arm.com>
  65
  66         * aarch64-opc.c (CPENT): New define.
  67         (F_READONLY, F_WRITEONLY): Likewise.
  68         (aarch64_sys_regs): Add trace unit registers.
  69         (aarch64_sys_reg_readonly_p): New function.
  70         (aarch64_sys_reg_writeonly_p): Ditto.
  71
  72 2013-11-15  Yufeng Zhang  <yufeng.zhang@arm.com>
  73
  74         * aarch64-opc.c (CPENT): New define.
  75         (F_READONLY, F_WRITEONLY): Likewise.
  76         (aarch64_sys_regs): Add trace unit registers.
  77         (aarch64_sys_reg_readonly_p): New function.
  78         (aarch64_sys_reg_writeonly_p): Ditto.
  79
  80 2013-11-15  Maciej W. Rozycki  <macro@codesourcery.com>
  81
  82         * mips-opc.c (mips_builtin_opcodes): Add RD_2 to "mfcr" and
  83         "mtcr".
  84
  85 2013-11-11  Catherine Moore  <clm@codesourcery.com>
  86
  87         * mips-dis.c (print_insn_mips): Use
  88         INSN_LOAD_MEMORY instead of INSN_LOAD_MEMORY_DELAY.
  89         (print_insn_micromips): Likewise.
  90         * mips-opc.c (LDD): Remove.
  91         (CLD): Include INSN_LOAD_MEMORY.
  92         (LM): New.
  93         (mips_builtin_opcodes): Use LM instead of LDD.
  94         Add LM to load instructions.
  95
  96 2013-11-08  H.J. Lu  <hongjiu.lu@intel.com>
  97
  98         PR gas/16140
  99         * i386-gen.c (cpu_flag_init): Remove CpuNop from CPU_K6_2_FLAGS.
 100         * i386-init.h: Regenerated.
 101
 102 2013-11-05  Yufeng Zhang  <yufeng.zhang@arm.com>
 103
 104         * aarch64-opc.c (F_DEPRECATED): New macro.
 105         (aarch64_sys_regs): Update; flag "spsr_svc" and "spsr_hyp" with
 106         F_DEPRECATED.
 107         (aarch64_print_operand): Call aarch64_sys_reg_deprecated_p on
 108         AARCH64_OPND_SYSREG.
 109
 110 2013-11-05  Yufeng Zhang  <yufeng.zhang@arm.com>
 111
 112         * aarch64-dis.c (convert_ubfm_to_lsl): Check for cond != '111x'.
 113         (convert_from_csel): Likewise.
 114         * aarch64-opc.c (operand_general_constraint_met_p): Handle
 115         AARCH64_OPND_CLASS_COND and AARCH64_OPND_COND1.
 116         (aarch64_print_operand): Handle AARCH64_OPND_COND1.
 117         * aarch64-tbl.h (aarch64_opcode_table): Use COND1 instead of
 118         COND for cinc, cset, cinv, csetm and cneg.
 119         (AARCH64_OPERANDS): Add entry for AARCH64_OPND_COND1.
 120         * aarch64-asm-2.c: Re-generated.
 121         * aarch64-dis-2.c: Ditto.
 122         * aarch64-opc-2.c: Ditto.
 123
 124 2013-11-05  Yufeng Zhang  <yufeng.zhang@arm.com>
 125
 126         * aarch64-opc.c (set_syntax_error): New function.
 127         (operand_general_constraint_met_p): Replace set_other_error
 128         with set_syntax_error.
 129
 130 2013-10-30  Andreas Arnez  <arnez@linux.vnet.ibm.com>
 131
 132         * s390-dis.c (init_disasm): Default to full 'zarch' opcode
 133         availability even for 31-bit programs.
 134
 135 2013-10-15  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
 136
 137         * arm-dis.c (neon_opcodes): Adjust print string for vshll.
 138
 139 2013-10-14  Chao-ying Fu  <Chao-ying.Fu@imgtec.com>
 140
 141         * micromips-opc.c (decode_micromips_operand): Add +T, +U, +V, +W,
 142         +d, +e, +h, +k, +l, +n, +o, +u, +v, +w, +x,
 143         +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
 144         (MSA): New define.
 145         (MSA64): New define.
 146         (micromips_opcodes): Add MSA instructions.
 147         * mips-dis.c (msa_control_names): New array.
 148         (mips_abi_choice): Add ASE_MSA to mips32r2.
 149         Remove ASE_MDMX from mips64r2.
 150         Add ASE_MSA and ASE_MSA64 to mips64r2.
 151         (parse_mips_dis_option): Handle -Mmsa.
 152         (print_reg): Handle cases for OP_REG_MSA and OP_REG_MSA_CTRL.
 153         (print_insn_arg): Handle cases for OP_IMM_INDEX and OP_REG_INDEX.
 154         (print_mips_disassembler_options): Print -Mmsa.
 155         * mips-opc.c (decode_mips_operand): Add +T, +U, +V, +W, +d, +e, +h, +k,
 156         +l, +n, +o, +u, +v, +w, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
 157         (MSA): New define.
 158         (MSA64): New define.
 159         (mips_builtin_op): Add MSA instructions.
 160
 161 2013-10-13  Sandra Loosemore  <sandra@codesourcery.com>
 162
 163         * nios2-opc.c (nios2_builtin_reg): Use "sstatus" rather than "ba"
 164         as the primary name of r30.
 165
 166 2013-10-12  Jan Beulich <jbeulich@suse.com>
 167
 168         * i386-dis.c (intel_operand_size): Move v_bnd_mode alongside the
 169         default case.
 170         (OP_E_register): Move v_bnd_mode alongside m_mode.
 171         * i386-opc.tbl (bndcl, bndcu, bndcn): Split 32- and 64-bit variants.
 172         Drop Reg16 and Disp16. Add NoRex64.
 173         (bndmk, bndmov, bndldx, bndstx): Drop Disp16.
 174         * i386-tbl.h: Re-generate.
 175
 176 2013-10-10  Sean Keys <skeys@ipdatasys.com>
 177
 178         * xgate-opc.c (xgate_opcode): Remove short_hand field from opcode
 179         table.
 180         * xgate-dis.c (print_insn): Refactor to work with table change.
 181
 182 2013-10-10  Roland McGrath  <mcgrathr@google.com>
 183
 184         * i386-dis.c (oappend_maybe_intel): New function.
 185         (OP_ST, OP_STi, append_seg, OP_I, OP_I64, OP_sI, OP_ESreg): Use it.
 186         (OP_C, OP_T, CMP_Fixup, OP_EX_VexImmW): Likewise.
 187         (VCMP_Fixup, VPCMP_Fixup, PCLMUL_Fixup): Likewise.
 188
 189         * cr16-opc.c (REG): Cast NAME to 'reg' enum type to suppress
 190         possible compiler warnings when the union's initializer is
 191         actually meant for the 'preg' enum typed member.
 192         * crx-opc.c (REG): Likewise.
 193
 194         * v850-dis.c (v850_cacheop_codes, v850_prefop_codes):
 195         Remove duplicate const qualifier.
 196
 197 2013-10-08  Jan Beulich <jbeulich@suse.com>
 198
 199         * i386-opc.tbl (invlpg): Use Anysize instead of Unspecified.
 200         (clflush): Use Anysize instead of Byte|Unspecified.
 201         (prefetch*): Likewise.
 202         * i386-tbl.h: Re-generate.
 203
 204 2013-10-07  Chao-ying Fu  <Chao-ying.Fu@imgtec.com>
 205
 206         * micromips-opc.c (micromips_opcodes): Fix dmfgc0 and dmtgc0.
 207
 208 2013-09-30  H.J. Lu  <hongjiu.lu@intel.com>
 209
 210         * i386-opc.tbl: Add Size64 to movq/vmovq with Reg64 operand.
 211         * i386-init.h: Regenerated.
 212
 213 2013-09-30  Saravanan Ekanathan <saravanan.ekanathan@amd.com>
 214
 215         * i386-gen.c (cpu_flag_init): Add CPU_BDVER4_FLAGS.
 216         * i386-init.h: Regenerated.
 217
 218 2013-09-20  Alan Modra  <amodra@gmail.com>
 219
 220         * configure: Regenerate.
 221
 222 2013-09-17  Richard Sandiford  <rsandifo@linux.vnet.ibm.com>
 223
 224         * s390-opc.txt (clih): Make the immediate unsigned.
 225
 226 2013-09-04  Roland McGrath  <mcgrathr@google.com>
 227
 228         PR gas/15914
 229         * arm-dis.c (arm_opcodes): Add udf.
 230         (thumb_opcodes): Use "udf" mnemonic rather than UNDEFINED_INSTRUCTION.
 231         (thumb32_opcodes): Add udf.w.
 232         (print_insn_thumb32): Handle %H as the thumb32_opcodes comment says.
 233
 234 2013-09-02  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 235
 236         * s390-opc.txt: Fix description for fiebra, fidbra, and fixbra.
 237         For the load fp integer instructions only the suppression flag was
 238         new with z196 version.
 239
 240 2013-08-28  Nick Clifton  <nickc@redhat.com>
 241
 242         * aarch64-opc.c (aarch64_logical_immediate_p): Return FALSE if the
 243         immediate is not suitable for the 32-bit ABI.
 244
 245 2013-08-23  Maciej W. Rozycki  <macro@codesourcery.com>
 246
 247         * micromips-opc.c (micromips_opcodes): Use RD_4 for "alnv.ps",
 248         replacing NODS.
 249
 250 2013-08-23  Yuri Chornoivan  <yurchor@ukr.net>
 251
 252         PR binutils/15834
 253         * aarch64-asm.c: Fix typos.
 254         * aarch64-dis.c: Likewise.
 255         * msp430-dis.c: Likewise.
 256
 257 2013-08-19  Richard Sandiford  <rdsandiford@googlemail.com>
 258
 259         * micromips-opc.c (micromips_opcodes): Replace "dext" and "dins"
 260         macro entries with "dextm", "dextu", "dinsm" and "dinsu" aliases.
 261         Use +H rather than +C for the real "dext".
 262         * mips-opc.c (mips_builtin_opcodes): Likewise.
 263
 264 2013-08-19  Richard Sandiford  <rdsandiford@googlemail.com>
 265
 266         * mips-formats.h (OPTIONAL_REG, OPTIONAL_MAPPED_REG): New macros.
 267         * micromips-opc.c (decode_micromips_operand): Use OPTIONAL_REG
 268         and OPTIONAL_MAPPED_REG.
 269         * mips-opc.c (decode_mips_operand): Likewise.
 270         * mips16-opc.c (decode_mips16_operand): Likewise.
 271         * mips-dis.c (print_insn_arg): Handle OP_OPTIONAL_REG.
 272
 273 2013-08-19  H.J. Lu  <hongjiu.lu@intel.com>
 274
 275         * i386-dis.c (PREFIX_EVEX_0F3A3E): Removed.
 276         (PREFIX_EVEX_0F3A3F): Likewise.
 277         * i386-dis-evex.h (evex_table): Updated.
 278
 279 2013-08-06  Jürgen Urban  <JuergenUrban@gmx.de>
 280
 281         * mips-opc.c (mips_builtin_opcodes): Add a suffixless version of
 282         VCLIPW.
 283
 284 2013-08-05  Eric Botcazou  <ebotcazou@adacore.com>
 285             Konrad Eisele  <konrad@gaisler.com>
 286
 287         * sparc-dis.c (compute_arch_mask): Set SPARC_OPCODE_ARCH_LEON bit for
 288         bfd_mach_sparc.
 289         * sparc-opc.c (MASK_LEON): Define.
 290         (v6, v6notlet, v7, v8, v6notv9): Add MASK_LEON.
 291         (letandleon): New macro.
 292         (v9andleon): Likewise.
 293         (sparc_opc): Add leon.
 294         (umac): Enable for letandleon.
 295         (smac): Likewise.
 296         (casa): Enable for v9andleon.
 297         (cas): Likewise.
 298         (casl): Likewise.
 299
 300 2013-08-04  Jürgen Urban  <JuergenUrban@gmx.de>
 301             Richard Sandiford  <rdsandiford@googlemail.com>
 302
 303         * mips-dis.c (print_reg): Handle OP_REG_VI, OP_REG_VF, OP_REG_R5900_I,
 304         OP_REG_R5900_Q, OP_REG_R5900_R and OP_REG_R5900_ACC.
 305         (print_vu0_channel): New function.
 306         (print_insn_arg): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX.
 307         (print_insn_args): Handle '#'.
 308         (print_insn_mips): Handle INSN2_VU0_CHANNEL_SUFFIX.
 309         * mips-opc.c (mips_vu0_channel_mask): New constant.
 310         (decode_mips_operand): Handle new VU0 operand types.
 311         (VU0, VU0CH): New macros.
 312         (mips_builtin_opcodes): Add VU0 opcodes.  Use "+7" rather than "E"
 313         for LQC2 and SQC2.  Use "+9" rather than "G" for EE CFC2 and CTC2.
 314         Use "+6" rather than "G" for QMFC2 and QMTC2.
 315
 316 2013-08-03  Richard Sandiford  <rdsandiford@googlemail.com>
 317
 318         * mips-formats.h (PCREL): Reorder parameters and update the definition
 319         to match new mips_pcrel_operand layout.
 320         (JUMP, JALX, BRANCH): Update accordingly.
 321         * mips16-opc.c (decode_mips16_operand): Likewise.
 322
 323 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 324
 325         * micromips-opc.c (WR_s): Delete.
 326
 327 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 328
 329         * mips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2, UDI):
 330         New macros.
 331         (WR_d, WR_t, WR_D, WR_T, WR_S, RD_s, RD_b, RD_t, RD_S, RD_T, RD_R)
 332         (WR_z, WR_Z, RD_z, RD_Z, RD_d): Delete.
 333         (mips_builtin_opcodes): Use the new position-based read-write flags
 334         instead of field-based ones.  Use UDI for "udi..." instructions.
 335         * mips16-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
 336         New macros.
 337         (WR_x, WR_y, WR_z, WR_Y, RD_x, RD_y, RD_Z, RD_X): Delete.
 338         (RD_T, WR_T, WR_31): Redefine using generic INSN_* flags.
 339         (WR_SP, RD_16): New macros.
 340         (RD_SP): Redefine as an INSN2_* flag.
 341         (MOD_SP): Redefine in terms of RD_SP and WR_SP.
 342         (mips16_opcodes): Use the new position-based read-write flags
 343         instead of field-based ones.  Use RD_16 for "nop".  Move RD_SP to
 344         pinfo2 field.
 345         * micromips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
 346         New macros.
 347         (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf, RD_mg, WR_mh, RD_mj)
 348         (WR_mj, RD_ml, RD_mmn, RD_mp, WR_mp, RD_mq, RD_gp, WR_d, WR_t, WR_D)
 349         (WR_T, WR_S, RD_s, RD_b, RD_t, RD_T, RD_S, RD_R, RD_D): Delete.
 350         (RD_sp, WR_sp): Redefine to INSN2_READ_SP and INSN2_WRITE_SP.
 351         (micromips_opcodes): Use the new position-based read-write flags
 352         instead of field-based ones.
 353         * mips-dis.c (print_insn_arg): Use mips_decode_reg_operand.
 354         (print_insn_mips, print_insn_micromips): Use INSN_WRITE_1 instead
 355         of field-based flags.
 356
 357 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 358
 359         * mips16-opc.c (UBR, CBR, RD_31, RD_PC): Redefine as INSN2_* flags.
 360         (WR_SP): Replace with...
 361         (MOD_SP): ...this.
 362         (mips16_opcodes): Update accordingly.
 363         * mips-dis.c (print_insn_mips16): Likewise.
 364
 365 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 366
 367         * mips16-opc.c (mips16_opcodes): Reformat.
 368
 369 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 370
 371         * mips-opc.c (mips_builtin_opcodes): Remove WR_* and RD_* flags
 372         for operands that are hard-coded to $0.
 373         * micromips-opc.c (micromips_opcodes): Likewise.
 374
 375 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 376
 377         * mips-opc.c (mips_builtin_opcodes): Use WR_31 rather than WR_d
 378         for the single-operand forms of JALR and JALR.HB.
 379         * micromips-opc.c (micromips_opcodes): Likewise JALR, JALRS, JALR.HB
 380         and JALRS.HB.
 381
 382 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 383
 384         * mips-opc.c (mips_builtin_opcodes): Add FP_D to VR5400 vector
 385         instructions.  Fix them to use WR_MACC instead of WR_CC and
 386         add missing RD_MACCs.
 387
 388 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 389
 390         * mips-dis.c (print_mips16_insn_arg): Include ISA bit in base address.
 391
 392 2013-07-29  Peter Bergner <bergner@vnet.ibm.com>
 393
 394         * ppc-dis.c (powerpc_init_dialect): Use ppc_parse_cpu() to set dialect.
 395
 396 2013-07-26  Sergey Guriev  <sergey.s.guriev@intel.com>
 397             Alexander Ivchenko  <alexander.ivchenko@intel.com>
 398             Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
 399             Sergey Lega  <sergey.s.lega@intel.com>
 400             Anna Tikhonova  <anna.tikhonova@intel.com>
 401             Ilya Tocar  <ilya.tocar@intel.com>
 402             Andrey Turetskiy  <andrey.turetskiy@intel.com>
 403             Ilya Verbin  <ilya.verbin@intel.com>
 404             Kirill Yukhin  <kirill.yukhin@intel.com>
 405             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 406
 407         * i386-dis-evex.h: New.
 408         * i386-dis.c (OP_Rounding): New.
 409         (VPCMP_Fixup): New.
 410         (OP_Mask): New.
 411         (Rdq): New.
 412         (XMxmmq): New.
 413         (EXdScalarS): New.
 414         (EXymm): New.
 415         (EXEvexHalfBcstXmmq): New.
 416         (EXxmm_mdq): New.
 417         (EXEvexXGscat): New.
 418         (EXEvexXNoBcst): New.
 419         (VPCMP): New.
 420         (EXxEVexR): New.
 421         (EXxEVexS): New.
 422         (XMask): New.
 423         (MaskG): New.
 424         (MaskE): New.
 425         (MaskR): New.
 426         (MaskVex): New.
 427         (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode,
 428         evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode,
 429         evex_rounding_mode, evex_sae_mode, mask_mode.
 430         (USE_EVEX_TABLE): New.
 431         (EVEX_TABLE): New.
 432         (EVEX enum): New.
 433         (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6,
 434         REG_EVEX_0F38C7.
 435         (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3,
 436         MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3,
 437         MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1,
 438         MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
 439         MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,  MOD_EVEX_0F38C7_REG_5,
 440         MOD_EVEX_0F38C7_REG_6.
 441         (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
 442         PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B,
 443         PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
 444         PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32,
 445         PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11,
 446         PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14,
 447         PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17,
 448         PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A,
 449         PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
 450         PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51,
 451         PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A,
 452         PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D,
 453         PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62,
 454         PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C,
 455         PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F,
 456         PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
 457         PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
 458         PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
 459         PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78,
 460         PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B,
 461         PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2,
 462         PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3,
 463         PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB,
 464         PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7,
 465         PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2,
 466         PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB,
 467         PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D,
 468         PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813,
 469         PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816,
 470         PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A,
 471         PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F,
 472         PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823,
 473         PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827,
 474         PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A,
 475         PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831,
 476         PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834,
 477         PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
 478         PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B,
 479         PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840,
 480         PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844,
 481         PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847,
 482         PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E,
 483         PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859,
 484         PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864,
 485         PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877,
 486         PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F,
 487         PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
 488         PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891,
 489         PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896,
 490         PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899,
 491         PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C,
 492         PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F,
 493         PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2,
 494         PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7,
 495         PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA,
 496         PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD,
 497         PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6,
 498         PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9,
 499         PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC,
 500         PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF,
 501         PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1,
 502         PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5,
 503         PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1,
 504         PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5,
 505         PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA,
 506         PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD,
 507         PREFIX_EVEX_0F3A00,  PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03,
 508         PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08,
 509         PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B,
 510         PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19,
 511         PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D,
 512         PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21,
 513         PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26,
 514         PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39,
 515         PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E,
 516         PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54,
 517         PREFIX_EVEX_0F3A55.
 518         (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0,
 519         VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0,
 520         VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0,
 521         VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0,
 522         VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1,
 523         VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1,
 524         VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1,
 525         VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0,
 526         VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0,
 527         VEX_W_0F3A32_P_2_LEN_0.
 528         (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0,
 529         EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0,
 530         EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0,
 531         EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0,
 532         EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1,
 533         EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
 534         EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0,
 535         EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1,
 536         EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
 537         EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2,
 538         EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
 539         EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2,
 540         EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3,
 541         EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3,
 542         EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3,
 543         EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3,
 544         EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0,
 545         EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0,
 546         EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0,
 547         EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0,
 548         EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2,
 549         EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2,
 550         EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2,
 551         EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2,
 552         EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0,
 553         EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1,
 554         EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1,
 555         EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2,
 556         EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2,
 557         EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1,
 558         EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2,
 559         EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2,
 560         EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2,
 561         EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1,
 562         EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1,
 563         EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2,
 564         EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
 565         EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1,
 566         EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2,
 567         EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1,
 568         EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1,
 569         EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1,
 570         EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1,
 571         EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2,
 572         EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2,
 573         EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
 574         EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2,
 575         EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
 576         EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
 577         EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2,
 578         EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
 579         EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2,
 580         EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2,
 581         EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2.
 582         (struct vex): Add fields evex, r, v, mask_register_specifier,
 583         zeroing, ll, b.
 584         (intel_names_xmm): Add upper 16 registers.
 585         (att_names_xmm): Ditto.
 586         (intel_names_ymm): Ditto.
 587         (att_names_ymm): Ditto.
 588         (names_zmm): New.
 589         (intel_names_zmm): Ditto.
 590         (att_names_zmm): Ditto.
 591         (names_mask): Ditto.
 592         (intel_names_mask): Ditto.
 593         (att_names_mask): Ditto.
 594         (names_rounding): Ditto.
 595         (names_broadcast): Ditto.
 596         (x86_64_table): Add escape to evex-table.
 597         (reg_table): Include reg_table evex-entries from
 598         i386-dis-evex.h.  Fix prefetchwt1 instruction.
 599         (prefix_table): Add entries for new instructions.
 600         (vex_table): Ditto.
 601         (vex_len_table): Ditto.
 602         (vex_w_table): Ditto.
 603         (mod_table): Ditto.
 604         (get_valid_dis386): Properly handle new instructions.
 605         (print_insn): Handle zmm and mask registers, print mask operand.
 606         (intel_operand_size): Support EVEX, new modes and sizes.
 607         (OP_E_register): Handle new modes.
 608         (OP_E_memory): Ditto.
 609         (OP_G): Ditto.
 610         (OP_XMM): Ditto.
 611         (OP_EX): Ditto.
 612         (OP_VEX): Ditto.
 613         * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and
 614         CPU_ANY_AVX_FLAGS.  Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS,
 615         CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
 616         (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER,
 617         CpuAVX512PF and CpuVREX.
 618         (operand_type_init): Add OPERAND_TYPE_REGZMM,
 619         OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8.
 620         (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast,
 621         StaticRounding, SAE, Disp8MemShift, NoDefMask.
 622         (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword.
 623         * i386-init.h: Regenerate.
 624         * i386-opc.h (CpuAVX512F): New.
 625         (CpuAVX512CD): New.
 626         (CpuAVX512ER): New.
 627         (CpuAVX512PF): New.
 628         (CpuVREX): New.
 629         (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er,
 630         cpuavx512pf and cpuvrex fields.
 631         (VecSIB): Add VecSIB512.
 632         (EVex): New.
 633         (Masking): New.
 634         (VecESize): New.
 635         (Broadcast): New.
 636         (StaticRounding): New.
 637         (SAE): New.
 638         (Disp8MemShift): New.
 639         (NoDefMask): New.
 640         (i386_opcode_modifier): Add evex, masking, vecesize, broadcast,
 641         staticrounding, sae, disp8memshift and nodefmask.
 642         (RegZMM): New.
 643         (Zmmword): Ditto.
 644         (Vec_Disp8): Ditto.
 645         (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8
 646         fields.
 647         (RegVRex): New.
 648         * i386-opc.tbl: Add AVX512 instructions.
 649         * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM
 650         registers, mask registers.
 651         * i386-tbl.h: Regenerate.
 652
 653 2013-07-25  Aaro Koskinen  <aaro.koskinen@iki.fi>
 654
 655         PR gas/15220
 656         * mips-opc.c (mips_builtin_opcodes): Fix wrong opcodes for
 657         Loongson 2F madd.ps, msub.ps, nmadd.ps and nmsub.ps.
 658
 659 2013-07-25  Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 660
 661         * i386-dis.c (PREFIX enum): Add PREFIX_0F38C8, PREFIX_0F38C9,
 662         PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC, PREFIX_0F38CD,
 663         PREFIX_0F3ACC.
 664         (prefix_table): Updated.
 665         (three_byte_table): Likewise.
 666         * i386-gen.c (cpu_flag_init): Add CPU_SHA_FLAGS.
 667         (cpu_flags): Add CpuSHA.
 668         (i386_cpu_flags): Add cpusha.
 669         * i386-init.h: Regenerate.
 670         * i386-opc.h (CpuSHA): New.
 671         (CpuUnused): Restored.
 672         (i386_cpu_flags): Add cpusha.
 673         * i386-opc.tbl: Add SHA instructions.
 674         * i386-tbl.h: Regenerate.
 675
 676 2013-07-24  Anna Tikhonova  <anna.tikhonova@intel.com>
 677             Kirill Yukhin  <kirill.yukhin@intel.com>
 678             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 679
 680         * i386-dis.c (BND_Fixup): New.
 681         (Ebnd): New.
 682         (Ev_bnd): New.
 683         (Gbnd): New.
 684         (BND): New.
 685         (v_bnd_mode): New.
 686         (bnd_mode): New.
 687         (MOD enum): Add MOD_0F1A_PREFIX_0, MOD_0F1B_PREFIX_0,
 688         MOD_0F1B_PREFIX_1.
 689         (PREFIX enum): Add PREFIX_0F1A, PREFIX_0F1B.
 690         (dis tables): Replace XX with BND for near branch and call
 691         instructions.
 692         (prefix_table): Add new entries.
 693         (mod_table): Likewise.
 694         (names_bnd): New.
 695         (intel_names_bnd): New.
 696         (att_names_bnd): New.
 697         (BND_PREFIX): New.
 698         (prefix_name): Handle BND_PREFIX.
 699         (print_insn): Initialize names_bnd.
 700         (intel_operand_size): Handle new modes.
 701         (OP_E_register): Likewise.
 702         (OP_E_memory): Likewise.
 703         (OP_G): Likewise.
 704         * i386-gen.c (cpu_flag_init): Add CpuMPX.
 705         (cpu_flags): Add CpuMPX.
 706         (operand_type_init): Add RegBND.
 707         (opcode_modifiers): Add BNDPrefixOk.
 708         (operand_types): Add RegBND.
 709         * i386-init.h: Regenerate.
 710         * i386-opc.h (CpuMPX): New.
 711         (CpuUnused): Comment out.
 712         (i386_cpu_flags): Add cpumpx.
 713         (BNDPrefixOk): New.
 714         (i386_opcode_modifier): Add bndprefixok.
 715         (RegBND): New.
 716         (i386_operand_type): Add regbnd.
 717         * i386-opc.tbl: Add BNDPrefixOk to near jumps, calls and rets.
 718         Add MPX instructions and bnd prefix.
 719         * i386-reg.tbl: Add bnd0-bnd3 registers.
 720         * i386-tbl.h: Regenerate.
 721
 722 2013-07-17  Richard Sandiford  <rdsandiford@googlemail.com>
 723
 724         * mips-formats.h (MAPPED_INT, MAPPED_REG, REG_PAIR): Add
 725         ATTRIBUTE_UNUSED.
 726
 727 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 728
 729         * Makefile.am (mips-opc.lo, micromips-opc.lo, mips16-opc.lo): Remove
 730         special rules.
 731         * Makefile.in: Regenerate.
 732         * mips-opc.c, micromips-opc.c, mips16-opc.c: Explicitly initialize
 733         all fields.  Reformat.
 734
 735 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 736
 737         * mips16-opc.c: Include mips-formats.h.
 738         (reg_0_map, reg_29_map, reg_31_map, reg_m16_map, reg32r_map): New
 739         static arrays.
 740         (decode_mips16_operand): New function.
 741         * mips-dis.c (mips16_to_32_reg_map, mips16_reg_names): Delete.
 742         (print_insn_arg): Handle OP_ENTRY_EXIT list.
 743         Abort for OP_SAVE_RESTORE_LIST.
 744         (print_mips16_insn_arg): Change interface.  Use mips_operand
 745         structures.  Delete GET_OP_S.  Move GET_OP definition to...
 746         (print_insn_mips16): ...here.  Call init_print_arg_state.
 747         Update the call to print_mips16_insn_arg.
 748
 749 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 750
 751         * mips-formats.h: New file.
 752         * mips-opc.c: Include mips-formats.h.
 753         (reg_0_map): New static array.
 754         (decode_mips_operand): New function.
 755         * micromips-opc.c: Remove <stdio.h> include.  Include mips-formats.h.
 756         (reg_0_map, reg_28_map, reg_29_map, reg_31_map, reg_m16_map)
 757         (reg_mn_map, reg_q_map, reg_h_map1, reg_h_map2, int_b_map)
 758         (int_c_map): New static arrays.
 759         (decode_micromips_operand): New function.
 760         * mips-dis.c (micromips_to_32_reg_b_map, micromips_to_32_reg_c_map)
 761         (micromips_to_32_reg_d_map, micromips_to_32_reg_e_map)
 762         (micromips_to_32_reg_f_map, micromips_to_32_reg_g_map)
 763         (micromips_to_32_reg_h_map1, micromips_to_32_reg_h_map2)
 764         (micromips_to_32_reg_l_map, micromips_to_32_reg_m_map)
 765         (micromips_to_32_reg_n_map, micromips_to_32_reg_q_map)
 766         (micromips_imm_b_map, micromips_imm_c_map): Delete.
 767         (print_reg): New function.
 768         (mips_print_arg_state): New structure.
 769         (init_print_arg_state, print_insn_arg): New functions.
 770         (print_insn_args): Change interface and use mips_operand structures.
 771         Delete GET_OP_S.  Move GET_OP definition to...
 772         (print_insn_mips): ...here.  Update the call to print_insn_args.
 773         (print_insn_micromips): Use print_insn_args.
 774
 775 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 776
 777         * mips16-opc.c (mips16_opcodes): Use "I" for immediate operands
 778         in macros.
 779
 780 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 781
 782         * mips-opc.c (mips_builtin_opcodes): Use "S,T" rather than "V,T" for
 783         ADDA.S, MULA.S and SUBA.S.
 784
 785 2013-07-08  H.J. Lu  <hongjiu.lu@intel.com>
 786
 787         PR gas/13572
 788         * i386-opc.tbl: Replace Xmmword with Qword on cvttps2pi.
 789         * i386-tbl.h: Regenerated.
 790
 791 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 792
 793         * mips-opc.c (mips_builtin_opcodes): Remove o(b) macros.  Move LD
 794         and SD A(B) macros up.
 795         * micromips-opc.c (micromips_opcodes): Likewise.
 796
 797 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 798
 799         * mips16-opc.c: Add entries for argumentless "entry" and "exit"
 800         instructions.
 801
 802 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 803
 804         * mips-opc.c (mips_builtin_opcodes): Use "Q" for the INSN_5400
 805         MDMX-like instructions.
 806         * mips-dis.c (print_insn_arg): Use "$f" rather than "$v" when
 807         printing "Q" operands for INSN_5400 instructions.
 808
 809 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 810
 811         * mips-opc.c (mips_builtin_opcodes): Use "+s" for "cins32" and
 812         "+S" for "cins".
 813         * mips-dis.c (print_mips_arg): Update "+s" and "+S" comments.
 814         Combine cases.
 815
 816 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 817
 818         * mips-opc.c (mips_builtin_opcodes): Use "+i" rather than "a" for
 819         "jalx".
 820         * mips16-opc.c (mips16_opcodes): Likewise.
 821         * micromips-opc.c (micromips_opcodes): Likewise.
 822         * mips-dis.c (print_insn_args, print_mips16_insn_arg)
 823         (print_insn_mips16): Handle "+i".
 824         (print_insn_micromips): Likewise.  Conditionally preserve the
 825         ISA bit for "a" but not for "+i".
 826
 827 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 828
 829         * micromips-opc.c (WR_mhi): Rename to..
 830         (WR_mh): ...this.
 831         (micromips_opcodes): Update "movep" entry accordingly.  Replace
 832         "mh,mi" with "mh".
 833         * mips-dis.c (micromips_to_32_reg_h_map): Rename to...
 834         (micromips_to_32_reg_h_map1): ...this.
 835         (micromips_to_32_reg_i_map): Rename to...
 836         (micromips_to_32_reg_h_map2): ...this.
 837         (print_micromips_insn): Remove "mi" case.  Print both registers
 838         in the pair for "mh".
 839
 840 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 841
 842         * mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries.
 843         * micromips-opc.c (micromips_opcodes): Likewise.
 844         * mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D"
 845         and "+T" handling.  Check for a "0" suffix when deciding whether to
 846         use coprocessor 0 names.  In that case, also check for ",H" selectors.
 847
 848 2013-07-05  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 849
 850         * s390-opc.c (J12_12, J24_24): New macros.
 851         (INSTR_MII_UPI): Rename to INSTR_MII_UPP.
 852         (MASK_MII_UPI): Rename to MASK_MII_UPP.
 853         * s390-opc.txt: Rename MII_UPI to MII_UPP for bprp instruction.
 854
 855 2013-07-04  Alan Modra  <amodra@gmail.com>
 856
 857         * ppc-opc.c (powerpc_opcodes): Add tdui, twui, tdu, twu, tui, tu.
 858
 859 2013-06-26  Nick Clifton  <nickc@redhat.com>
 860
 861         * rx-decode.opc (rx_decode_opcode): Check sd field as well as ss
 862         field when checking for type 2 nop.
 863         * rx-decode.c: Regenerate.
 864
 865 2013-06-25  Maciej W. Rozycki  <macro@codesourcery.com>
 866
 867         * micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc"
 868         and "movep" macros.
 869
 870 2013-06-24  Maciej W. Rozycki  <macro@codesourcery.com>
 871
 872         * mips-dis.c (is_mips16_plt_tail): New function.
 873         (print_insn_mips16): Handle MIPS16 PLT entry's GOT slot address
 874         word.
 875         (is_compressed_mode_p): Handle MIPS16/microMIPS PLT entries.
 876
 877 2013-06-21  DJ Delorie  <dj@redhat.com>
 878
 879         * msp430-decode.opc: New.
 880         * msp430-decode.c: New/generated.
 881         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add msp430-decode.c.
 882         (MAINTAINER_CLEANFILES): Likewise.
 883         Add rule to build msp430-decode.c frommsp430decode.opc
 884         using the opc2c program.
 885         * Makefile.in: Regenerate.
 886         * configure.in: Add msp430-decode.lo to msp430 architecture files.
 887         * configure: Regenerate.
 888
 889 2013-06-20  Yufeng Zhang  <yufeng.zhang@arm.com>
 890
 891         * aarch64-dis.c (EMBEDDED_ENV): Remove the check on it.
 892         (SYMTAB_AVAILABLE): Removed.
 893         (#include "elf/aarch64.h): Ditto.
 894
 895 2013-06-17  Catherine Moore  <clm@codesourcery.com>
 896             Maciej W. Rozycki  <macro@codesourcery.com>
 897             Chao-Ying Fu  <fu@mips.com>
 898
 899         * micromips-opc.c (EVA): Define.
 900         (TLBINV): Define.
 901         (micromips_opcodes): Add EVA opcodes.
 902         * mips-dis.c (mips_arch_choices): Update for ASE_EVA.
 903         (print_insn_args): Handle EVA offsets.
 904         (print_insn_micromips): Likewise.
 905         * mips-opc.c (EVA): Define.
 906         (TLBINV): Define.
 907         (mips_builtin_opcodes): Add EVA opcodes.
 908
 909 2013-06-17  Alan Modra  <amodra@gmail.com>
 910
 911         * Makefile.am (mips-opc.lo): Add rules to create automatic
 912         dependency files.  Pass archdefs.
 913         (micromips-opc.lo, mips16-opc.lo): Likewise.
 914         * Makefile.in: Regenerate.
 915
 916 2013-06-14  DJ Delorie  <dj@redhat.com>
 917
 918         * rx-decode.opc (rx_decode_opcode): Bit operations on
 919         registers are 32-bit operations, not 8-bit operations.
 920         * rx-decode.c: Regenerate.
 921
 922 2013-06-13  Chao-ying Fu  <Chao-ying.Fu@imgtec.com>
 923
 924         * micromips-opc.c (IVIRT): New define.
 925         (IVIRT64): New define.
 926         (micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
 927         tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions.
 928
 929         * mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0,
 930         dmtgc0 to print cp0 names.
 931
 932 2013-06-09  Sandra Loosemore  <sandra@codesourcery.com>
 933
 934         * nios2-opc.c (nios2_builtin_opcodes): Give "trap" a type-"b"
 935         argument.
 936
 937 2013-06-08  Catherine Moore  <clm@codesourcery.com>
 938             Richard Sandiford  <rdsandiford@googlemail.com>
 939
 940         * micromips-opc.c (D32, D33, MC): Update definitions.
 941         (micromips_opcodes):  Initialize ase field.
 942         * mips-dis.c (mips_arch_choice): Add ase field.
 943         (mips_arch_choices): Initialize ase field.
 944         (set_default_mips_dis_options): Declare and setup mips_ase.
 945         * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
 946         MT32, MC): Update definitions.
 947         (mips_builtin_opcodes): Initialize ase field.
 948
 949 2013-05-24  Richard Sandiford  <rsandifo@linux.vnet.ibm.com>
 950
 951         * s390-opc.txt (flogr): Require a register pair destination.
 952
 953 2013-05-23  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 954
 955         * s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU
 956         instruction format.
 957
 958 2013-05-22  Jürgen Urban  <JuergenUrban@gmx.de>
 959
 960         * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
 961
 962 2013-05-20  Peter Bergner <bergner@vnet.ibm.com>
 963
 964         * ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
 965         * ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
 966         XLS_MASK, PPCVSX2): New defines.
 967         (powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
 968         fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
 969         mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
 970         mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
 971         mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
 972         vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
 973         vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
 974         vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
 975         vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
 976         vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
 977         vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
 978         vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
 979         vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
 980         vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
 981         xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
 982         xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
 983         xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
 984         xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
 985         <lxvx, stxvx>: New extended mnemonics.
 986
 987 2013-05-17  Alan Modra  <amodra@gmail.com>
 988
 989         * ia64-raw.tbl: Replace non-ASCII char.
 990         * ia64-waw.tbl: Likewise.
 991         * ia64-asmtab.c: Regenerate.
 992
 993 2013-05-15  Saravanan Ekanathan <saravanan.ekanathan@amd.com>
 994
 995         * i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
 996         * i386-init.h: Regenerated.
 997
 998 2013-05-13  Yufeng Zhang  <yufeng.zhang@arm.com>
 999
1000         * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
1001         * aarch64-opc.c (operand_general_constraint_met_p): Relax the range
1002         check from [0, 255] to [-128, 255].
1003
1004 2013-05-09  Andrew Pinski  <apinski@cavium.com>
1005
1006         * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
1007         Add INSN_VIRT and INSN_VIRT64 to mips64r2.
1008         (parse_mips_dis_option): Handle the virt option.
1009         (print_insn_args): Handle "+J".
1010         (print_mips_disassembler_options): Print out message about virt64.
1011         * mips-opc.c (IVIRT): New define.
1012         (IVIRT64): New define.
1013         (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
1014         tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
1015         Move rfe to the bottom as it conflicts with tlbgp.
1016
1017 2013-05-09  Alan Modra  <amodra@gmail.com>
1018
1019         * ppc-opc.c (extract_vlesi): Properly sign extend.
1020         (extract_vlensi): Likewise.  Comment reason for setting invalid.
1021
1022 2013-05-02  Nick Clifton  <nickc@redhat.com>
1023
1024         * msp430-dis.c: Add support for MSP430X instructions.
1025
1026 2013-04-24  Sandra Loosemore  <sandra@codesourcery.com>
1027
1028         * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
1029         to "eccinj".
1030
1031 2013-04-17  Wei-chen Wang  <cole945@gmail.com>
1032
1033         PR binutils/15369
1034         * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
1035         of CGEN_CPU_ENDIAN.
1036         (hash_insns_list): Likewise.
1037
1038 2013-04-10  Jan Kratochvil  <jan.kratochvil@redhat.com>
1039
1040         * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
1041         warning workaround.
1042
1043 2013-04-08  Jan Beulich <jbeulich@suse.com>
1044
1045         * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
1046         * i386-tbl.h: Re-generate.
1047
1048 2013-04-06  David S. Miller  <davem@davemloft.net>
1049
1050         * sparc-dis.c (compare_opcodes): When encountering multiple aliases
1051         of an opcode, prefer the one with F_PREFERRED set.
1052         * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
1053         lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
1054         ops.  Make 64-bit VIS logical ops have "d" suffix in their names,
1055         mark existing mnenomics as aliases.  Add "cc" suffix to edge
1056         instructions generating condition codes, mark existing mnenomics
1057         as aliases.  Add "fp" prefix to VIS compare instructions, mark
1058         existing mnenomics as aliases.
1059
1060 2013-04-03  Nick Clifton  <nickc@redhat.com>
1061
1062         * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
1063         destination address by subtracting the operand from the current
1064         address.
1065         * v850-opc.c (insert_u16_loop): Disallow negative offsets.  Store
1066         a positive value in the insn.
1067         (extract_u16_loop): Do not negate the returned value.
1068         (D16_LOOP): Add V850_INVERSE_PCREL flag.
1069
1070         (ceilf.sw): Remove duplicate entry.
1071         (cvtf.hs): New entry.
1072         (cvtf.sh): Likewise.
1073         (fmaf.s): Likewise.
1074         (fmsf.s): Likewise.
1075         (fnmaf.s): Likewise.
1076         (fnmsf.s): Likewise.
1077         (maddf.s): Restrict to E3V5 architectures.
1078         (msubf.s): Likewise.
1079         (nmaddf.s): Likewise.
1080         (nmsubf.s): Likewise.
1081
1082 2013-03-27  H.J. Lu  <hongjiu.lu@intel.com>
1083
1084         * i386-dis.c (get_sib): Add the sizeflag argument.  Properly
1085         check address mode.
1086         (print_insn): Pass sizeflag to get_sib.
1087
1088 2013-03-27  Alexis Deruelle  <alexis.deruelle@gmail.com>
1089
1090         PR binutils/15068
1091         * tic6x-dis.c: Add support for displaying 16-bit insns.
1092
1093 2013-03-20  Alexis Deruelle  <alexis.deruelle@gmail.com>
1094
1095         PR gas/15095
1096         * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
1097         individual msb and lsb halves in src1 & src2 fields.  Discard the
1098         src1 (lsb) value and only use src2 (msb), discarding bit 0, to
1099         follow what Ti SDK does in that case as any value in the src1
1100         field yields the same output with SDK disassembler.
1101
1102 2013-03-12  Michael Eager <eager@eagercon.com>
1103
1104         * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
1105
1106 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
1107
1108         * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
1109
1110 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
1111
1112         * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
1113
1114 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
1115
1116         * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
1117
1118 2013-03-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
1119
1120         * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
1121         (thumb32_opcodes): Likewise.
1122         (print_insn_thumb32): Handle 'S' control char.
1123
1124 2013-03-08  Yann Sionneau  <yann.sionneau@gmail.com>
1125
1126         * lm32-desc.c: Regenerate.
1127
1128 2013-03-01  H.J. Lu  <hongjiu.lu@intel.com>
1129
1130         * i386-reg.tbl (riz): Add RegRex64.
1131         * i386-tbl.h: Regenerated.
1132
1133 2013-02-28  Yufeng Zhang  <yufeng.zhang@arm.com>
1134
1135         * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
1136         (aarch64_feature_crc): New static.
1137         (CRC): New macro.
1138         (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
1139         crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
1140         * aarch64-asm-2.c: Re-generate.
1141         * aarch64-dis-2.c: Ditto.
1142         * aarch64-opc-2.c: Ditto.
1143
1144 2013-02-27  Alan Modra  <amodra@gmail.com>
1145
1146         * rl78-decode.opc (rl78_decode_opcode): Fix typo.
1147         * rl78-decode.c: Regenerate.
1148
1149 2013-02-25  Kaushik Phatak  <Kaushik.Phatak@kpitcummins.com>
1150
1151         * rl78-decode.opc: Fix encoding of DIVWU insn.
1152         * rl78-decode.c: Regenerate.
1153
1154 2013-02-19  H.J. Lu  <hongjiu.lu@intel.com>
1155
1156         PR gas/15159
1157         * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
1158
1159         * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
1160         (cpu_flags): Add CpuSMAP.
1161
1162         * i386-opc.h (CpuSMAP): New.
1163         (i386_cpu_flags): Add cpusmap.
1164
1165         * i386-opc.tbl: Add clac and stac.
1166
1167         * i386-init.h: Regenerated.
1168         * i386-tbl.h: Likewise.
1169
1170 2013-02-15  Markos Chandras  <markos.chandras@imgtec.com>
1171
1172         * metag-dis.c: Initialize outf->bytes_per_chunk to 4
1173         which also makes the disassembler output be in little
1174         endian like it should be.
1175
1176 2013-02-14  Yufeng Zhang  <yufeng.zhang@arm.com>
1177
1178         * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
1179         fields to NULL.
1180         (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
1181
1182 2013-02-13  Maciej W. Rozycki  <macro@codesourcery.com>
1183
1184         * mips-dis.c (is_compressed_mode_p): Only match symbols from the
1185         section disassembled.
1186
1187 2013-02-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
1188
1189         * arm-dis.c: Update strht pattern.
1190
1191 2013-02-09  Jürgen Urban  <JuergenUrban@gmx.de>
1192
1193         * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
1194         single-float.  Disable ll, lld, sc and scd for EE.  Disable the
1195         trunc.w.s macro for EE.
1196
1197 2013-02-06  Sandra Loosemore  <sandra@codesourcery.com>
1198             Andrew Jenner <andrew@codesourcery.com>
1199
1200         Based on patches from Altera Corporation.
1201
1202         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
1203         nios2-opc.c.
1204         * Makefile.in: Regenerated.
1205         * configure.in: Add case for bfd_nios2_arch.
1206         * configure: Regenerated.
1207         * disassemble.c (ARCH_nios2): Define.
1208         (disassembler): Add case for bfd_arch_nios2.
1209         * nios2-dis.c: New file.
1210         * nios2-opc.c: New file.
1211
1212 2013-02-04  Alan Modra  <amodra@gmail.com>
1213
1214         * po/POTFILES.in: Regenerate.
1215         * rl78-decode.c: Regenerate.
1216         * rx-decode.c: Regenerate.
1217
1218 2013-01-30  Yufeng Zhang  <yufeng.zhang@arm.com>
1219
1220         * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
1221         ushll2 with F_HAS_ALIAS.  Add entries for sxtl, sxtl2, uxtl and uxtl2.
1222         * aarch64-asm.c (convert_xtl_to_shll): New function.
1223         (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
1224         calling convert_xtl_to_shll.
1225         * aarch64-dis.c (convert_shll_to_xtl): New function.
1226         (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
1227         calling convert_shll_to_xtl.
1228         * aarch64-gen.c: Update copyright year.
1229         * aarch64-asm-2.c: Re-generate.
1230         * aarch64-dis-2.c: Re-generate.
1231         * aarch64-opc-2.c: Re-generate.
1232
1233 2013-01-24  Nick Clifton  <nickc@redhat.com>
1234
1235         * v850-dis.c: Add support for e3v5 architecture.
1236         * v850-opc.c: Likewise.
1237
1238 2013-01-17  Yufeng Zhang  <yufeng.zhang@arm.com>
1239
1240         * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
1241         * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
1242         * aarch64-opc.c (operand_general_constraint_met_p): For
1243         AARCH64_MOD_LSL, move the range check on the shift amount before the
1244         alignment check; change to call set_sft_amount_out_of_range_error
1245         instead of set_imm_out_of_range_error.
1246         * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
1247         (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
1248         8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
1249         SIMD_IMM_SFT.
1250
1251 2013-01-16  H.J. Lu  <hongjiu.lu@intel.com>
1252
1253         * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
1254
1255         * i386-init.h: Regenerated.
1256         * i386-tbl.h: Likewise.
1257
1258 2013-01-15  Nick Clifton  <nickc@redhat.com>
1259
1260         * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
1261         values.
1262         * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
1263
1264 2013-01-14  Will Newton <will.newton@imgtec.com>
1265
1266         * metag-dis.c (REG_WIDTH): Increase to 64.
1267
1268 2013-01-10  Peter Bergner <bergner@vnet.ibm.com>
1269
1270         * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
1271         * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
1272         XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
1273         (SH6): Update.
1274         <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
1275         "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
1276         "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
1277         <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
1278
1279 2013-01-10  Will Newton <will.newton@imgtec.com>
1280
1281         * Makefile.am: Add Meta.
1282         * configure.in: Add Meta.
1283         * disassemble.c: Add Meta support.
1284         * metag-dis.c: New file.
1285         * Makefile.in: Regenerate.
1286         * configure: Regenerate.
1287
1288 2013-01-07  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
1289
1290         * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
1291         (match_opcode): Rename to cr16_match_opcode.
1292
1293 2013-01-04  Juergen Urban <JuergenUrban@gmx.de>
1294
1295         * mips-dis.c: Add names for CP0 registers of r5900.
1296         * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
1297         instructions sq and lq.
1298         Add support for MIPS r5900 CPU.
1299         Add support for 128 bit MMI (Multimedia Instructions).
1300         Add support for EE instructions (Emotion Engine).
1301         Disable unsupported floating point instructions (64 bit and
1302         undefined compare operations).
1303         Enable instructions of MIPS ISA IV which are supported by r5900.
1304         Disable 64 bit co processor instructions.
1305         Disable 64 bit multiplication and division instructions.
1306         Disable instructions for co-processor 2 and 3, because these are
1307         not supported (preparation for later VU0 support (Vector Unit)).
1308         Disable cvt.w.s because this behaves like trunc.w.s and the
1309         correct execution can't be ensured on r5900.
1310         Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
1311         will confuse less developers and compilers.
1312
1313 2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>
1314
1315         * aarch64-opc.c (aarch64_print_operand): Change to print
1316         AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
1317         in comment.
1318         * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
1319         from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
1320         OP_MOV_IMM_WIDE.
1321
1322 2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>
1323
1324         * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
1325         PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
1326
1327 2013-01-02  H.J. Lu  <hongjiu.lu@intel.com>
1328
1329         * i386-gen.c (process_copyright): Update copyright year to 2013.
1330
1331 2013-01-02  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
1332
1333         * cr16-dis.c (match_opcode,make_instruction): Remove static
1334         declaration.
1335         (dwordU,wordU): Moved typedefs to opcode/cr16.h
1336         (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
1337
1338 For older changes see ChangeLog-2012
1339 \f
1340 Copyright (C) 2013 Free Software Foundation, Inc.
1341
1342 Copying and distribution of this file, with or without modification,
1343 are permitted in any medium without royalty provided the copyright
1344 notice and this notice are preserved.
1345
1346 Local Variables:
1347 mode: change-log
1348 left-margin: 8
1349 fill-column: 74
1350 version-control: never
1351 End: