opcodes/ChangeLog

   1 2014-10-15  Tristan Gingold  <gingold@adacore.com>
   2
   3         * configure: Regenerate.
   4
   5 2014-10-09  Jose E. Marchesi  &lt;jose.marchesi@oracle.com&gt;
   6
   7         * sparc-opc.c (sparc-opcodes): Remove instructions `chkpt',
   8         `commit', `random', `wr r,r,%cps', `wr r,i,%cps' and `rd %cps,r'.
   9         Annotate table with HWCAP2 bits.
  10         Add instructions xmontmul, xmontsqr, xmpmul.
  11         (sparc-opcodes): Add the `mwait',  `wr r,r,%mwait', `wr
  12         r,i,%mwait' and `rd %mwait,r' instructions.
  13         Add rd/wr instructions for accessing the %mcdper ancillary state
  14         register.
  15         (sparc-opcodes): Add sparc5/vis4.0 instructions:
  16         subxc, subxccc, fpadd8, fpadds8, fpaddus8, fpaddus16, fpcmple8,
  17         fpcmpgt8, fpcmpule16, fpcmpugt16, fpcmpule32, fpcmpugt32, fpmax8,
  18         fpmax16, fpmax32, fpmaxu8, fpmaxu16, fpmaxu32, fpmin8, fpmin16,
  19         fpmin32, fpminu8, fpminu16, fpminu32, fpsub8, fpsubs8, fpsubus8,
  20         fpsubus16, and faligndatai.
  21         * sparc-dis.c (v9a_asr_reg_names): Add the %mwait (%asr28)
  22         ancillary state register to the table.
  23         (print_insn_sparc): Handle the %mcdper ancillary state register.
  24         (print_insn_sparc): Handle new operand type '}'.
  25
  26 2014-09-22  H.J. Lu  <hongjiu.lu@intel.com>
  27
  28         * i386-dis.c (MOD_0F20): Removed.
  29         (MOD_0F21): Likewise.
  30         (MOD_0F22): Likewise.
  31         (MOD_0F23): Likewise.
  32         (dis386_twobyte): Replace MOD_0F20, MOD_0F21, MOD_0F22 and
  33         MOD_0F23 with "movZ".
  34         (mod_table): Remove MOD_0F20, MOD_0F21, MOD_0F22 and MOD_0F23.
  35         (OP_R): Check mod/rm byte and call OP_E_register.
  36
  37 2014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
  38
  39         * nds32-asm.c (nds32_opcodes, operand_fields, keyword_im5_i,
  40         keyword_im5_m, keyword_accumulator, keyword_aridx, keyword_aridx2,
  41         keyword_aridxi): Add audio ISA extension.
  42         (keyword_gpr, keyword_usr, keyword_sr, keyword_cp, keyword_cpr,
  43         keyword_fsr, keyword_fdr, keyword_abdim, keyword_abm, keyword_dpref_st,
  44         keyword_cctl_lv, keyword_standby_st, keyword_msync_st): Adjust scrope
  45         for nds32-dis.c using.
  46         (build_opcode_syntax): Remove dead code.
  47         (parse_re, parse_a30b20, parse_rt21, parse_rte_start, parse_rte_end,
  48         parse_rte69_start, parse_rte69_end, parse_im5_ip, parse_im5_mr,
  49         parse_im6_ip, parse_im6_iq, parse_im6_mr, parse_im6_ms): Add audio ISA
  50         operand parser.
  51         * nds32-asm.h: Declare.
  52         * nds32-dis.c: Use array nds32_opcodes to disassemble instead of
  53         decoding by switch.
  54
  55 2014-09-15  Andrew Bennett  <andrew.bennett@imgtec.com>
  56             Matthew Fortune  <matthew.fortune@imgtec.com>
  57
  58         * mips-dis.c (mips_arch_choices): Add entries for mips32r6 and
  59         mips64r6.
  60         (parse_mips_dis_option): Allow MSA and virtualization support for
  61         mips64r6.
  62         (mips_print_arg_state): Add fields dest_regno and seen_dest.
  63         (mips_seen_register): New function.
  64         (print_insn_arg): Refactored code to use mips_seen_register
  65         function.  Add support for OP_SAME_RS_RT, OP_CHECK_PREV and
  66         OP_NON_ZERO_REG.  Changed OP_REPEAT_DEST_REG case to print out
  67         the register rather than aborting.
  68         (print_insn_args): Add length argument.  Add code to correctly
  69         calculate the instruction address for pc relative instructions.
  70         (validate_insn_args): New static function.
  71         (print_insn_mips): Prevent jalx disassembling for r6.  Use
  72         validate_insn_args.
  73         (print_insn_micromips): Use validate_insn_args.
  74         all the arguments are valid.
  75         * mips-formats.h (PREV_CHECK): New define.
  76         * mips-opc.c (decode_mips_operand): Add support for -a, -b, -d, -s,
  77         -t, -u, -v, -w, -x, -y, -A, -B, +I, +O, +R, +:, +\, +", +;
  78         (RD_pc): New define.
  79         (FS): New define.
  80         (I37): New define.
  81         (I69): New define.
  82         (mips_builtin_opcodes): Add MIPS R6 instructions.  Exclude recoded
  83         MIPS R6 instructions from MIPS R2 instructions.
  84
  85 2014-09-10  H.J. Lu  <hongjiu.lu@intel.com>
  86
  87         * i386-dis.c (dis386): Replace "P" with "%LP" for iret and sysret.
  88         (putop): Handle "%LP".
  89
  90 2014-09-03  Jiong Wang  <jiong.wang@arm.com>
  91
  92         * aarch64-tbl.h (aarch64_opcode_table): Update encoding for mrs/msr.
  93         * aarch64-dis-2.c: Update auto-generated file.
  94
  95 2014-09-03  Jiong Wang  <jiong.wang@arm.com>
  96
  97         * aarch64-tbl.h (QL_R4NIL): New qualifiers.
  98         (aarch64_feature_lse): New feature added.
  99         (LSE): New Added.
 100         (aarch64_opcode_table): New LSE instructions added.  Improve
 101         descriptions for ldarb/ldarh/ldar.
 102         (aarch64_opcode_table): Describe PAIRREG.
 103         * aarch64-opc.h (aarch64_field_kind): Add FLD_lse_sz.
 104         * aarch64-opc.c (fields): Add entry for F_LSE_SZ.
 105         (aarch64_print_operand): Recognize PAIRREG.
 106         (operand_general_constraint_met_p): Check reg pair constraints for CASP
 107         instructions.
 108         * aarch64-dis.c (aarch64_ext_regno_pair): New extractor for paired reg.
 109         (do_special_decoding): Recognize F_LSE_SZ.
 110         * aarch64-asm.c (do_special_encoding): Recognize F_LSE_SZ.
 111
 112 2014-08-26  Maciej W. Rozycki  <macro@codesourcery.com>
 113
 114         * micromips-opc.c (decode_micromips_operand): Rename `B' to `+J'.
 115         (micromips_opcodes): Use "+J" in place of "B" for "hypcall",
 116         "sdbbp", "syscall" and "wait".
 117
 118 2014-08-21  Nathan Sidwell  <nathan@codesourcery.com>
 119             Maciej W. Rozycki  <macro@codesourcery.com>
 120
 121         * arm-dis.c (print_arm_address): Negate the GPR-relative offset
 122         returned if the U bit is set.
 123
 124 2014-08-21  Maciej W. Rozycki  <macro@codesourcery.com>
 125
 126         * micromips-opc.c (micromips_opcodes): Remove #ifdef-ed out
 127         48-bit "li" encoding.
 128
 129 2014-08-19  Andreas Arnez  <arnez@linux.vnet.ibm.com>
 130
 131         * s390-dis.c (s390_insn_length, s390_insn_matches_opcode)
 132         (s390_print_insn_with_opcode, opcode_mask_more_specific): New
 133         static functions, code was moved from...
 134         (print_insn_s390): ...here.
 135         (s390_extract_operand): Adjust comment.  Change type of first
 136         parameter from 'unsigned char *' to 'const bfd_byte *'.
 137         (union operand_value): New.
 138         (s390_extract_operand): Change return type to union operand_value.
 139         Also avoid integer overflow in sign-extension.
 140         (s390_print_insn_with_opcode): Adjust to changed return value from
 141         s390_extract_operand().  Change "%i" printf format to "%u" for
 142         unsigned values.
 143         (init_disasm): Simplify initialization of opc_index[].  This also
 144         fixes an access after the last element of s390_opcodes[].
 145         (print_insn_s390): Simplify the opcode search loop.
 146         Check architecture mask against all searched opcodes, not just the
 147         first matching one.
 148         (s390_print_insn_with_opcode): Drop function pointer dereferences
 149         without effect.
 150         (print_insn_s390): Likewise.
 151         (s390_insn_length): Simplify formula for return value.
 152         (s390_print_insn_with_opcode): Avoid special handling for the
 153         separator before the first operand.  Use new local variable
 154         'flags' in place of 'operand->flags'.
 155
 156 2014-08-14  Mike Frysinger  <vapier@gentoo.org>
 157
 158         * bfin-dis.c (struct private): Change int's to bfd_boolean's.
 159         (decode_LOGI2op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
 160         decode_dagMODik_0, decode_LDIMMhalf_0, decode_linkage_0):
 161         Change assignment of 1 to priv->comment to TRUE.
 162         (print_insn_bfin): Change legal to a bfd_boolean.  Change
 163         assignment of 0/1 with priv comment and parallel and legal
 164         to FALSE/TRUE.
 165
 166 2014-08-14  Mike Frysinger  <vapier@gentoo.org>
 167
 168         * bfin-dis.c (OUT): Define.
 169         (decode_CC2stat_0): Declare new op_names array.
 170         Replace multiple if statements with a single one.
 171
 172 2014-08-14  Mike Frysinger  <vapier@gentoo.org>
 173
 174         * bfin-dis.c (struct private): Add iw0.
 175         (_print_insn_bfin): Assign iw0 to priv.iw0.
 176         (print_insn_bfin): Drop ifetch and use priv.iw0.
 177
 178 2014-08-13  Mike Frysinger  <vapier@gentoo.org>
 179
 180         * bfin-dis.c (comment, parallel): Move from global scope ...
 181         (struct private): ... to this new struct.
 182         (decode_ProgCtrl_0, decode_CaCTRL_0, decode_PushPopReg_0,
 183         decode_PushPopMultiple_0, decode_ccMV_0, decode_CCflag_0,
 184         decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0,
 185         decode_LOGI2op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
 186         decode_dagMODik_0, decode_LoopSetup_0, decode_LDIMMhalf_0,
 187         decode_CALLa_0, decode_linkage_0, decode_pseudoDEBUG_0,
 188         decode_pseudoOChar_0, decode_pseudodbg_assert_0, _print_insn_bfin,
 189         print_insn_bfin): Declare private struct.  Use priv's comment and
 190         parallel members.
 191
 192 2014-08-13  Mike Frysinger  <vapier@gentoo.org>
 193
 194         * bfin-dis.c (ifetch): Do not align pc to 2 bytes.
 195         (_print_insn_bfin): Add check for unaligned pc.
 196
 197 2014-08-13  Mike Frysinger  <vapier@gentoo.org>
 198
 199         * bfin-dis.c (ifetch): New function.
 200         (_print_insn_bfin, print_insn_bfin): Call new ifetch and return
 201         -1 when it errors.
 202
 203 2014-07-29  Matthew Fortune  <matthew.fortune@imgtec.com>
 204
 205         * micromips-opc.c (COD): Rename throughout to...
 206         (CM): New define, update to use INSN_COPROC_MOVE.
 207         (LCD): Rename throughout to...
 208         (LC): New define, update to use INSN_LOAD_COPROC.
 209         * mips-opc.c: Likewise.
 210
 211 2014-07-29  Matthew Fortune  <matthew.fortune@imgtec.com>
 212
 213         * micromips-opc.c (COD, LCD) New macros.
 214         (cfc1, ctc1): Remove FP_S attribute.
 215         (dmfc1, mfc1, mfhc1): Add LCD attribute.
 216         (dmtc1, mtc1, mthc1): Add COD attribute.
 217         * mips-opc.c (cfc1, cftc1, ctc, cttc1): Remove FP_S attribute.
 218
 219 2014-07-22  Sergey Guriev  <sergey.s.guriev@intel.com>
 220             Alexander Ivchenko  <alexander.ivchenko@intel.com>
 221             Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
 222             Sergey Lega  <sergey.s.lega@intel.com>
 223             Anna Tikhonova  <anna.tikhonova@intel.com>
 224             Ilya Tocar  <ilya.tocar@intel.com>
 225             Andrey Turetskiy  <andrey.turetskiy@intel.com>
 226             Ilya Verbin  <ilya.verbin@intel.com>
 227             Kirill Yukhin  <kirill.yukhin@intel.com>
 228             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 229
 230         * i386-dis-evex.h: Updated.
 231         * i386-dis.c (PREFIX enum): Add PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
 232         PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0F3A16,
 233         PREFIX_EVEX_0F3A22, PREFIX_EVEX_0F3A50, PREFIX_EVEX_0F3A51,
 234         PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66,
 235         PREFIX_EVEX_0F3A67.
 236         (VEX_LEN enum): Add VEX_LEN_0F92_P_2, VEX_LEN_0F93_P_2,
 237         VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_2_LEN_0.
 238         (VEX_W enum): Add EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
 239         EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2, EVEX_W_0F57_P_0,
 240         EVEX_W_0F57_P_2, EVEX_W_0F78_P_2, EVEX_W_0F79_P_2, EVEX_W_0F7A_P_2,
 241         EVEX_W_0F7B_P_2, EVEX_W_0F3838_P_1, EVEX_W_0F3839_P_1,
 242         EVEX_W_0F3A16_P_2, EVEX_W_0F3A22_P_2, EVEX_W_0F3A50_P_2,
 243         EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2, EVEX_W_0F3A57_P_2,
 244         EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2.
 245         (prefix_table): Add entries for new instructions.
 246         (vex_len_table): Ditto.
 247         (vex_w_table): Ditto.
 248         (OP_E_memory): Update xmmq_mode handling.
 249         * i386-gen.c (cpu_flag_init): Add CPU_AVX512DQ_FLAGS.
 250         (cpu_flags): Add CpuAVX512DQ.
 251         * i386-init.h: Regenerared.
 252         * i386-opc.h (CpuAVX512DQ): New.
 253         (i386_cpu_flags): Add cpuavx512dq.
 254         * i386-opc.tbl: Add AVX512DQ instructions.
 255         * i386-tbl.h: Regenerate.
 256
 257 2014-07-22  Sergey Guriev  <sergey.s.guriev@intel.com>
 258             Alexander Ivchenko  <alexander.ivchenko@intel.com>
 259             Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
 260             Sergey Lega  <sergey.s.lega@intel.com>
 261             Anna Tikhonova  <anna.tikhonova@intel.com>
 262             Ilya Tocar  <ilya.tocar@intel.com>
 263             Andrey Turetskiy  <andrey.turetskiy@intel.com>
 264             Ilya Verbin  <ilya.verbin@intel.com>
 265             Kirill Yukhin  <kirill.yukhin@intel.com>
 266             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 267
 268         * i386-dis-evex.h: Add new instructions (prefixes bellow).
 269         * i386-dis.c (fetch_data): Add EdqwS, Edb, Edw, MaskBDE.
 270         (enum): Add dqw_swap_mode, db_mode, dw_mode, mask_bd_mode, REG_EVEX_0F71.
 271         (PREFIX enum): Add PREFIX_VEX_0F4A, PREFIX_VEX_0F99, PREFIX_VEX_0F3A31,
 272         PREFIX_VEX_0F3A33, PREFIX_EVEX_0F60, PREFIX_EVEX_0F61, PREFIX_EVEX_0F63,
 273         PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
 274         PREFIX_EVEX_0F69, PREFIX_EVEX_0F6B, PREFIX_EVEX_0F71_REG_2, PREFIX_EVEX_0F71_REG_4,
 275         PREFIX_EVEX_0F71_REG_6, PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_7,
 276         PREFIX_EVEX_0F74, PREFIX_EVEX_0F75, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5,
 277         PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5, PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9,
 278         PREFIX_EVEX_0FDA, PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
 279         PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3, PREFIX_EVEX_0FE4,
 280         PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8, PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA,
 281         PREFIX_EVEX_0FEC, PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
 282         PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8, PREFIX_EVEX_0FF9,
 283         PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD, PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804,
 284         PREFIX_EVEX_0F380B, PREFIX_EVEX_0F3810, PREFIX_EVEX_0F381C, PREFIX_EVEX_0F381D,
 285         PREFIX_EVEX_0F3820, PREFIX_EVEX_0F3826, PREFIX_EVEX_0F382B, PREFIX_EVEX_0F3830,
 286         PREFIX_EVEX_0F3838, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E, PREFIX_EVEX_0F3866,
 287         PREFIX_EVEX_0F3875, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879, PREFIX_EVEX_0F387A,
 288         PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387D, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F3A0F,
 289         PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15, PREFIX_EVEX_0F3A20, PREFIX_EVEX_0F3A3E,
 290         PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A42.
 291         (VEX_LEN enum): Add VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_2, VEX_LEN_0F44_P_2,
 292         VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_2, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
 293         VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_2,
 294         VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_2, VEX_LEN_0F99_P_0,
 295         VEX_LEN_0F99_P_2, VEX_LEN_0F3A31_P_2, VEX_LEN_0F3A33_P_2, VEX_W_0F41_P_2_LEN_1,
 296         VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_2_LEN_1,
 297         VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
 298         VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1, VEX_W_0F90_P_2_LEN_0,
 299         VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_3_LEN_0, VEX_W_0F93_P_3_LEN_0,
 300         VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0, VEX_W_0F99_P_2_LEN_0,
 301         VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A33_P_2_LEN_0.
 302         (VEX_W enum): Add EVEX_W_0F6B_P_2, EVEX_W_0F6F_P_3, EVEX_W_0F7F_P_3,
 303         EVEX_W_0F3810_P_1, EVEX_W_0F3810_P_2, EVEX_W_0F3811_P_2, EVEX_W_0F3812_P_2,
 304         EVEX_W_0F3820_P_1, EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2, EVEX_W_0F3828_P_1,
 305         EVEX_W_0F3829_P_1, EVEX_W_0F382B_P_2, EVEX_W_0F3830_P_1, EVEX_W_0F3866_P_2,
 306         EVEX_W_0F3875_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F387A_P_2,
 307         EVEX_W_0F387B_P_2, EVEX_W_0F387D_P_2, EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2,
 308         EVEX_W_0F3A3F_P_2, EVEX_W_0F3A42_P_2.
 309         (prefix_table): Add entries for new instructions.
 310         (vex_table) : Ditto.
 311         (vex_len_table): Ditto.
 312         (vex_w_table): Ditto.
 313         (intel_operand_size): Add db_mode, dw_mode, dqw_swap_mode,
 314         mask_bd_mode handling.
 315         (OP_E_register): Add dqw_swap_mode, dw_mode, db_mode, mask_bd_mode
 316         handling.
 317         (OP_E_memory): Add dqw_mode, dw_mode, dqw_swap_mode, dqb_mode, db_mode
 318         handling.
 319         (OP_G): Add db_mode, dw_mode, dqw_swap_mode, mask_bd_mode handling.
 320         (OP_EX): Add dqw_swap_mode handling.
 321         (OP_VEX): Add mask_bd_mode handling.
 322         (OP_Mask): Add mask_bd_mode handling.
 323         * i386-gen.c (cpu_flag_init): Add CPU_AVX512BW_FLAGS.
 324         (cpu_flags): Add CpuAVX512BW.
 325         * i386-init.h: Regenerated.
 326         * i386-opc.h (CpuAVX512BW): New.
 327         (i386_cpu_flags): Add cpuavx512bw.
 328         * i386-opc.tbl: Add AVX512BW instructions.
 329         * i386-tbl.h: Regenerate.
 330
 331 2014-07-22  Sergey Guriev  <sergey.s.guriev@intel.com>
 332             Alexander Ivchenko  <alexander.ivchenko@intel.com>
 333             Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
 334             Sergey Lega  <sergey.s.lega@intel.com>
 335             Anna Tikhonova  <anna.tikhonova@intel.com>
 336             Ilya Tocar  <ilya.tocar@intel.com>
 337             Andrey Turetskiy  <andrey.turetskiy@intel.com>
 338             Ilya Verbin  <ilya.verbin@intel.com>
 339             Kirill Yukhin  <kirill.yukhin@intel.com>
 340             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 341
 342         * i386-opc.tbl: Add AVX512VL and AVX512CD instructions.
 343         * i386-tbl.h: Regenerate.
 344
 345 2014-07-22  Sergey Guriev  <sergey.s.guriev@intel.com>
 346             Alexander Ivchenko  <alexander.ivchenko@intel.com>
 347             Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
 348             Sergey Lega  <sergey.s.lega@intel.com>
 349             Anna Tikhonova  <anna.tikhonova@intel.com>
 350             Ilya Tocar  <ilya.tocar@intel.com>
 351             Andrey Turetskiy  <andrey.turetskiy@intel.com>
 352             Ilya Verbin  <ilya.verbin@intel.com>
 353             Kirill Yukhin  <kirill.yukhin@intel.com>
 354             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 355
 356         * i386-dis.c (intel_operand_size): Support 128/256 length in
 357         vex_vsib_q_w_dq_mode.
 358         (OP_E_memory): Add ymmq_mode handling, handle new broadcast.
 359         * i386-gen.c (cpu_flag_init): Add CPU_AVX512VL_FLAGS.
 360         (cpu_flags): Add CpuAVX512VL.
 361         * i386-init.h: Regenerated.
 362         * i386-opc.h (CpuAVX512VL): New.
 363         (i386_cpu_flags): Add cpuavx512vl.
 364         (BROADCAST_1TO4, BROADCAST_1TO2): Define.
 365         * i386-opc.tbl: Add AVX512VL instructions.
 366         * i386-tbl.h: Regenerate.
 367
 368 2014-07-20  Stefan Kristiansson  <stefan.kristiansson@saunalahti.fi>
 369
 370         * or1k-desc.c, * or1k-desc.h, * or1k-opc.c, * or1k-opc.h,
 371         * or1k-opinst.c: Regenerate.
 372
 373 2014-07-08  Ilya Tocar  <ilya.tocar@intel.com>
 374
 375         * i386-dis-evex.h (EVEX_W_0F10_P_1_M_1): Fix vmovss.
 376         (EVEX_W_0F10_P_3_M_1): Fix vmovsd.
 377
 378 2014-07-04  Alan Modra  <amodra@gmail.com>
 379
 380         * configure.ac: Rename from configure.in.
 381         * Makefile.in: Regenerate.
 382         * config.in: Regenerate.
 383
 384 2014-07-04  Alan Modra  <amodra@gmail.com>
 385
 386         * configure.in: Include bfd/version.m4.
 387         (AC_INIT, AM_INIT_AUTOMAKE): Use modern form.
 388         (BFD_VERSION): Delete.
 389         * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Remove bfd/configure.in.
 390         * configure: Regenerate.
 391         * Makefile.in: Regenerate.
 392
 393 2014-07-01  Barney Stratford   <barney_stratford@fastmail.fm>
 394             Senthil Kumar Selvaraj  <senthil_kumar.selvaraj@atmel.com>
 395             Pitchumani Sivanupandi  <pitchumani.s@atmel.com>
 396             Soundararajan  <Sounderarajan.D@atmel.com>
 397
 398         * avr-dis.c (avr_operand): Handle constraint j for 16 bit lds/sts.
 399         (print_insn_avr): Do not select opcode if insn ISA is avrtiny and
 400         machine is not avrtiny.
 401
 402 2014-06-26  Philippe De Muyter <phdm@macqel.be>
 403
 404         * or1k-desc.h (spr_field_masks): Add U suffix to the end of long
 405         constants.
 406
 407 2014-06-12  Alan Modra  <amodra@gmail.com>
 408
 409         * or1k-asm.c, * or1k-desc.c, * or1k-desc.h, * or1k-dis.c,
 410         * or1k-ibld.c, * or1k-opc.c, * or1k-opc.h, * or1k-opinst.c: Regenerate.
 411
 412 2014-06-10  H.J. Lu  <hongjiu.lu@intel.com>
 413
 414         * i386-dis.c (fwait_prefix): New.
 415         (ckprefix): Set fwait_prefix.
 416         (print_insn): Properly print prefixes before fwait.
 417
 418 2014-06-07  Alan Modra  <amodra@gmail.com>
 419
 420         * ppc-opc.c (UISIGNOPT): Define and use with cmpli.
 421
 422 2014-06-05  Joel Brobecker  <brobecker@adacore.com>
 423
 424         * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Add dependency on
 425         bfd's development.sh.
 426         * Makefile.in, configure: Regenerate.
 427
 428 2014-06-03  Nick Clifton  <nickc@redhat.com>
 429
 430         * msp430-dis.c (msp430_doubleoperand): Use extension_word to
 431         decide when extended addressing is being used.
 432
 433 2014-06-02  Eric Botcazou  <ebotcazou@adacore.com>
 434
 435         * sparc-opc.c (cas): Disable for LEON.
 436         (casl): Likewise.
 437
 438 2014-05-20  Alan Modra  <amodra@gmail.com>
 439
 440         * m68k-dis.c: Don't include setjmp.h.
 441
 442 2014-05-09  H.J. Lu  <hongjiu.lu@intel.com>
 443
 444         * i386-dis.c (ADDR16_PREFIX): Removed.
 445         (ADDR32_PREFIX): Likewise.
 446         (DATA16_PREFIX): Likewise.
 447         (DATA32_PREFIX): Likewise.
 448         (prefix_name): Updated.
 449         (print_insn): Simplify data and address size prefixes processing.
 450
 451 2014-05-08  Stefan Kristiansson  <stefan.kristiansson@saunalahti.fi>
 452
 453         * or1k-desc.c: Regenerated.
 454         * or1k-desc.h: Likewise.
 455         * or1k-opc.c: Likewise.
 456         * or1k-opc.h: Likewise.
 457         * or1k-opinst.c: Likewise.
 458
 459 2014-05-07  Andrew Bennett  <andrew.bennett@imgtec.com>
 460
 461         * mips-opc.c (mips_builtin_opcodes): Add MIPS32r5 eretnc instruction.
 462         (I34): New define.
 463         (I36): New define.
 464         (I66): New define.
 465         (I68): New define.
 466         * mips-dis.c (mips_arch_choices): Add mips32r3, mips32r5, mips64r3 and
 467         mips64r5.
 468         (parse_mips_dis_option): Update MSA and virtualization support to
 469         allow mips64r3 and mips64r5.
 470
 471 2014-05-07  Andrew Bennett  <andrew.bennett@imgtec.com>
 472
 473         * mips-opc.c (G3): Remove I4.
 474
 475 2014-05-05  H.J. Lu  <hongjiu.lu@intel.com>
 476
 477         PR binutils/16893
 478         * i386-dis.c (twobyte_has_mandatory_prefix): New variable.
 479         (end_codep): Likewise.
 480         (mandatory_prefix): Likewise.
 481         (active_seg_prefix): Likewise.
 482         (ckprefix): Set active_seg_prefix to the active segment register
 483         prefix.
 484         (seg_prefix): Removed.
 485         (get_valid_dis386): Use the last of PREFIX_REPNZ and PREFIX_REPZ
 486         for prefix index.  Ignore the index if it is invalid and the
 487         mandatory prefix isn't required.
 488         (print_insn): Set mandatory_prefix if the PREFIX_XXX prefix is
 489         mandatory.  Don't set PREFIX_REPZ/PREFIX_REPNZ/PREFIX_LOCK bits
 490         in used_prefixes here.  Don't print unused prefixes.  Check
 491         active_seg_prefix for the active segment register prefix.
 492         Restore the DFLAG bit in sizeflag if the data size prefix is
 493         unused.  Check the unused mandatory PREFIX_XXX prefixes
 494         (append_seg): Only print the segment register which gets used.
 495         (OP_E_memory): Check active_seg_prefix for the segment register
 496         prefix.
 497         (OP_OFF): Likewise.
 498         (OP_OFF64): Likewise.
 499         (OP_DSreg): Set active_seg_prefix to PREFIX_DS if it is unset.
 500
 501 2014-05-02  H.J. Lu  <hongjiu.lu@intel.com>
 502
 503         PR binutils/16886
 504         * config.in: Regenerated.
 505         * configure: Likewise.
 506         * configure.in: Check if sigsetjmp is available.
 507         * h8500-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
 508         (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
 509         (print_insn_h8500): Replace setjmp with OPCODES_SIGSETJMP.
 510         * i386-dis.c (dis_private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
 511         (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
 512         (print_insn): Replace setjmp with OPCODES_SIGSETJMP.
 513         * ns32k-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
 514         (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
 515         (print_insn_ns32k): Replace setjmp with OPCODES_SIGSETJMP.
 516         * sysdep.h (OPCODES_SIGJMP_BUF): New macro.
 517         (OPCODES_SIGSETJMP): Likewise.
 518         (OPCODES_SIGLONGJMP): Likewise.
 519         * vax-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
 520         (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
 521         (print_insn_vax): Replace setjmp with OPCODES_SIGSETJMP.
 522         * xtensa-dis.c (dis_private): Replace jmp_buf with
 523         OPCODES_SIGJMP_BUF.
 524         (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
 525         (print_insn_xtensa): Replace setjmp with OPCODES_SIGSETJMP.
 526         * z8k-dis.c(instr_data_s): Replace jmp_buf with OPCODES_SIGJMP_BUF.
 527         (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
 528         (print_insn_z8k): Replace setjmp with OPCODES_SIGSETJMP.
 529
 530 2014-05-01  H.J. Lu  <hongjiu.lu@intel.com>
 531
 532         PR binutils/16891
 533         * i386-dis.c (print_insn): Handle prefixes before fwait.
 534
 535 2014-04-26  Alan Modra  <amodra@gmail.com>
 536
 537         * po/POTFILES.in: Regenerate.
 538
 539 2014-04-23  Andrew Bennett  <andrew.bennett@imgtec.com>
 540
 541         * mips-dis.c (mips_arch_choices): Update mips32r2 and mips64r2
 542         to allow the MIPS XPA ASE.
 543         (parse_mips_dis_option): Process the -Mxpa option.
 544         * mips-opc.c (XPA): New define.
 545         (mips_builtin_opcodes): Add MIPS XPA instructions and move the
 546         locations of the ctc0 and cfc0 instructions.
 547
 548 2014-04-22  Christian Svensson  <blue@cmd.nu>
 549
 550         * Makefile.am: Remove openrisc and or32 support.  Add support for or1k.
 551         * configure.in: Likewise.
 552         * disassemble.c: Likewise.
 553         * or1k-asm.c: New file.
 554         * or1k-desc.c: New file.
 555         * or1k-desc.h: New file.
 556         * or1k-dis.c: New file.
 557         * or1k-ibld.c: New file.
 558         * or1k-opc.c: New file.
 559         * or1k-opc.h: New file.
 560         * or1k-opinst.c: New file.
 561         * Makefile.in: Regenerate.
 562         * configure: Regenerate.
 563         * openrisc-asm.c: Delete.
 564         * openrisc-desc.c: Delete.
 565         * openrisc-desc.h: Delete.
 566         * openrisc-dis.c: Delete.
 567         * openrisc-ibld.c: Delete.
 568         * openrisc-opc.c: Delete.
 569         * openrisc-opc.h: Delete.
 570         * or32-dis.c: Delete.
 571         * or32-opc.c: Delete.
 572
 573 2014-04-04  Ilya Tocar  <ilya.tocar@intel.com>
 574
 575         * i386-dis.c (rm_table): Add encls, enclu.
 576         * i386-gen.c (cpu_flag_init): Add CPU_SE1_FLAGS,
 577         (cpu_flags): Add CpuSE1.
 578         * i386-opc.h (enum): Add CpuSE1.
 579         (i386_cpu_flags): Add cpuse1.
 580         * i386-opc.tbl: Add encls, enclu.
 581         * i386-init.h: Regenerated.
 582         * i386-tbl.h: Likewise.
 583
 584 2014-04-02  Anthony Green  <green@moxielogic.com>
 585
 586         * moxie-opc.c (moxie_form1_opc_info): Add sign-extension
 587         instructions, sex.b and sex.s.
 588
 589 2014-03-26  Jiong Wang  <jiong.wang@arm.com>
 590
 591         * aarch64-dis.c (aarch64_ext_ldst_elemlist): Check H/S undefined
 592         instructions.
 593
 594 2014-03-20  Ilya Tocar  <ilya.tocar@intel.com>
 595
 596         * i386-opc.tbl: Change memory size for vgatherpf0qps, vgatherpf1qps,
 597         vscatterpf0qps, vscatterpf1qps, vgatherqps, vpgatherqd, vpscatterqd,
 598         vscatterqps.
 599         * i386-tbl.h: Regenerate.
 600
 601 2014-03-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
 602
 603         * sparc-dis.c (v9_hpriv_reg_names): Names for %hstick_offset and
 604         %hstick_enable added.
 605
 606 2014-03-19  Nick Clifton  <nickc@redhat.com>
 607
 608         * rx-decode.opc (bwl): Allow for bogus instructions with a size
 609         field of 3.
 610         (sbwl, ubwl, SCALE): Likewise.
 611         * rx-decode.c: Regenerate.
 612
 613 2014-03-12  Alan Modra  <amodra@gmail.com>
 614
 615         * Makefile.in: Regenerate.
 616
 617 2014-03-05  Alan Modra  <amodra@gmail.com>
 618
 619         Update copyright years.
 620
 621 2014-03-04  Heiher  <r@hev.cc>
 622
 623         * mips-dis.c (mips_arch_choices): Usee ISA_MIPS64R2 for Loongson-3A.
 624
 625 2014-03-04  Richard Sandiford  <rdsandiford@googlemail.com>
 626
 627         * mips-opc.c (mips_builtin_opcodes): Move the udi* instructions
 628         so that they come after the Loongson extensions.
 629
 630 2014-03-03  Alan Modra  <amodra@gmail.com>
 631
 632         * i386-gen.c (process_copyright): Emit copyright notice on one line.
 633
 634 2014-02-28  Alan Modra  <amodra@gmail.com>
 635
 636         * msp430-decode.c: Regenerate.
 637
 638 2014-02-27  Jiong Wang  <jiong.wang@arm.com>
 639
 640         * aarch64-tbl.h (aarch64_opcode_table): Replace IMM0 with
 641         FPIMM0 for fcmeq, fcmgt, fcmge, fcmlt and fcmle.
 642
 643 2014-02-27  Yufeng Zhang  <yufeng.zhang@arm.com>
 644
 645         * aarch64-opc.c (print_register_offset_address): Call
 646         get_int_reg_name to prepare the register name.
 647
 648 2014-02-25  Ilya Tocar  <ilya.tocar@intel.com>
 649
 650         * i386-opc.tbl: Remove wrong variant of vcvtps2ph
 651         * i386-tbl.h: Regenerate.
 652
 653 2014-02-20  Ilya Tocar  <ilya.tocar@intel.com>
 654
 655         * i386-gen.c (cpu_flag_init): Add CPU_PREFETCHWT1_FLAGS/
 656         (cpu_flags): Add CpuPREFETCHWT1.
 657         * i386-init.h: Regenerate.
 658         * i386-opc.h (CpuPREFETCHWT1): New.
 659         (i386_cpu_flags): Add cpuprefetchwt1.
 660         * i386-opc.tbl: Cahnge CPU of prefetchwt1 from CpuAVX512PF to CpuPREFETCHWT1.
 661         * i386-tbl.h: Regenerate.
 662
 663 2014-02-20  Ilya Tocar  <ilya.tocar@intel.com>
 664
 665         * i386-opc.tbl: Change CPU of vptestnmq, vptestnmd from CpuAVX512CD,
 666         to CpuAVX512F.
 667         * i386-tbl.h: Regenerate.
 668
 669 2014-02-19  H.J. Lu  <hongjiu.lu@intel.com>
 670
 671         * i386-gen.c (output_cpu_flags): Don't output trailing space.
 672         (output_opcode_modifier): Likewise.
 673         (output_operand_type): Likewise.
 674         * i386-init.h: Regenerated.
 675         * i386-tbl.h: Likewise.
 676
 677 2014-02-12  Ilya Tocar  <ilya.tocar@intel.com>
 678
 679         * i386-dis.c (MOD enum): Add MOD_0FC7_REG_3, MOD_0FC7_REG_4,
 680         MOD_0FC7_REG_5.
 681         (PREFIX enum): Add PREFIX_0FAE_REG_7.
 682         (reg_table): Add MOD_0FC7_REG_3, MOD_0FC7_REG_4 MOD_0FC7_REG_5.
 683         (prefix_table): Add clflusopt.
 684         (mod_table): Add xrstors, xsavec, xsaves.
 685         * i386-gen.c (cpu_flag_init): Add CPU_CLFLUSHOPT_FLAGS,
 686         CPU_XSAVES_FLAGS, CPU_XSAVEC_FLAGS.
 687         (cpu_flags): Add CpuClflushOpt, CpuXSAVES, CpuXSAVEC.
 688         * i386-init.h: Regenerate.
 689         * i386-opc.tbl: Add clflushopt, xrstors, xrstors64, xsaves,
 690         xsaves64, xsavec, xsavec64.
 691         * i386-tbl.h: Regenerate.
 692
 693 2014-02-10  Alan Modra  <amodra@gmail.com>
 694
 695         * po/POTFILES.in: Regenerate.
 696         * po/opcodes.pot: Regenerate.
 697
 698 2014-01-30  Michael Zolotukhin  <michael.v.zolotukhin@gmail.com>
 699             Jan Beulich  <jbeulich@suse.com>
 700
 701         PR binutils/16490
 702         * i386-dis.c (OP_E_memory): Fix shift computation for
 703         vex_vsib_q_w_dq_mode.
 704
 705 2014-01-09  Bradley Nelson  <bradnelson@google.com>
 706             Roland McGrath  <mcgrathr@google.com>
 707
 708         * i386-dis.c (print_insn): Do not touch all_prefixes[-1] when
 709         last_rex_prefix is -1.
 710
 711 2014-01-08  H.J. Lu  <hongjiu.lu@intel.com>
 712
 713         * i386-gen.c (process_copyright): Update copyright year to 2014.
 714
 715 2014-01-03  Maciej W. Rozycki  <macro@codesourcery.com>
 716
 717         * nds32-asm.c (parse_operand): Fix out-of-range integer constant.
 718
 719 For older changes see ChangeLog-2013
 720 \f
 721 Copyright (C) 2014 Free Software Foundation, Inc.
 722
 723 Copying and distribution of this file, with or without modification,
 724 are permitted in any medium without royalty provided the copyright
 725 notice and this notice are preserved.
 726
 727 Local Variables:
 728 mode: change-log
 729 left-margin: 8
 730 fill-column: 74
 731 version-control: never
 732 End: