opcodes/ChangeLog

   1 2013-04-10  Jan Kratochvil  <jan.kratochvil@redhat.com>
   2
   3         * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
   4         warning workaround.
   5
   6 2013-04-08  Jan Beulich <jbeulich@suse.com>
   7
   8         * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
   9         * i386-tbl.h: Re-generate.
  10
  11 2013-04-06  David S. Miller  <davem@davemloft.net>
  12
  13         * sparc-dis.c (compare_opcodes): When encountering multiple aliases
  14         of an opcode, prefer the one with F_PREFERRED set.
  15         * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
  16         lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
  17         ops.  Make 64-bit VIS logical ops have "d" suffix in their names,
  18         mark existing mnenomics as aliases.  Add "cc" suffix to edge
  19         instructions generating condition codes, mark existing mnenomics
  20         as aliases.  Add "fp" prefix to VIS compare instructions, mark
  21         existing mnenomics as aliases.
  22
  23 2013-04-03  Nick Clifton  <nickc@redhat.com>
  24
  25         * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
  26         destination address by subtracting the operand from the current
  27         address.
  28         * v850-opc.c (insert_u16_loop): Disallow negative offsets.  Store
  29         a positive value in the insn.
  30         (extract_u16_loop): Do not negate the returned value.
  31         (D16_LOOP): Add V850_INVERSE_PCREL flag.
  32
  33         (ceilf.sw): Remove duplicate entry.
  34         (cvtf.hs): New entry.
  35         (cvtf.sh): Likewise.
  36         (fmaf.s): Likewise.
  37         (fmsf.s): Likewise.
  38         (fnmaf.s): Likewise.
  39         (fnmsf.s): Likewise.
  40         (maddf.s): Restrict to E3V5 architectures.
  41         (msubf.s): Likewise.
  42         (nmaddf.s): Likewise.
  43         (nmsubf.s): Likewise.
  44
  45 2013-03-27  H.J. Lu  <hongjiu.lu@intel.com>
  46
  47         * i386-dis.c (get_sib): Add the sizeflag argument.  Properly
  48         check address mode.
  49         (print_insn): Pass sizeflag to get_sib.
  50
  51 2013-03-27  Alexis Deruelle  <alexis.deruelle@gmail.com>
  52
  53         PR binutils/15068
  54         * tic6x-dis.c: Add support for displaying 16-bit insns.
  55
  56 2013-03-20  Alexis Deruelle  <alexis.deruelle@gmail.com>
  57
  58         PR gas/15095
  59         * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
  60         individual msb and lsb halves in src1 & src2 fields.  Discard the
  61         src1 (lsb) value and only use src2 (msb), discarding bit 0, to
  62         follow what Ti SDK does in that case as any value in the src1
  63         field yields the same output with SDK disassembler.
  64
  65 2013-03-12  Michael Eager <eager@eagercon.com>
  66
  67         * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
  68
  69 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
  70
  71         * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
  72
  73 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
  74
  75         * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
  76
  77 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
  78
  79         * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
  80
  81 2013-03-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
  82
  83         * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
  84         (thumb32_opcodes): Likewise.
  85         (print_insn_thumb32): Handle 'S' control char.
  86
  87 2013-03-08  Yann Sionneau  <yann.sionneau@gmail.com>
  88
  89         * lm32-desc.c: Regenerate.
  90
  91 2013-03-01  H.J. Lu  <hongjiu.lu@intel.com>
  92
  93         * i386-reg.tbl (riz): Add RegRex64.
  94         * i386-tbl.h: Regenerated.
  95
  96 2013-02-28  Yufeng Zhang  <yufeng.zhang@arm.com>
  97
  98         * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
  99         (aarch64_feature_crc): New static.
 100         (CRC): New macro.
 101         (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
 102         crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
 103         * aarch64-asm-2.c: Re-generate.
 104         * aarch64-dis-2.c: Ditto.
 105         * aarch64-opc-2.c: Ditto.
 106
 107 2013-02-27  Alan Modra  <amodra@gmail.com>
 108
 109         * rl78-decode.opc (rl78_decode_opcode): Fix typo.
 110         * rl78-decode.c: Regenerate.
 111
 112 2013-02-25  Kaushik Phatak  <Kaushik.Phatak@kpitcummins.com>
 113
 114         * rl78-decode.opc: Fix encoding of DIVWU insn.
 115         * rl78-decode.c: Regenerate.
 116
 117 2013-02-19  H.J. Lu  <hongjiu.lu@intel.com>
 118
 119         PR gas/15159
 120         * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
 121
 122         * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
 123         (cpu_flags): Add CpuSMAP.
 124
 125         * i386-opc.h (CpuSMAP): New.
 126         (i386_cpu_flags): Add cpusmap.
 127
 128         * i386-opc.tbl: Add clac and stac.
 129
 130         * i386-init.h: Regenerated.
 131         * i386-tbl.h: Likewise.
 132
 133 2013-02-15  Markos Chandras  <markos.chandras@imgtec.com>
 134
 135         * metag-dis.c: Initialize outf->bytes_per_chunk to 4
 136         which also makes the disassembler output be in little
 137         endian like it should be.
 138
 139 2013-02-14  Yufeng Zhang  <yufeng.zhang@arm.com>
 140
 141         * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
 142         fields to NULL.
 143         (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
 144
 145 2013-02-13  Maciej W. Rozycki  <macro@codesourcery.com>
 146
 147         * mips-dis.c (is_compressed_mode_p): Only match symbols from the
 148         section disassembled.
 149
 150 2013-02-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 151
 152         * arm-dis.c: Update strht pattern.
 153
 154 2013-02-09  Jürgen Urban  <JuergenUrban@gmx.de>
 155
 156         * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
 157         single-float.  Disable ll, lld, sc and scd for EE.  Disable the
 158         trunc.w.s macro for EE.
 159
 160 2013-02-06  Sandra Loosemore  <sandra@codesourcery.com>
 161             Andrew Jenner <andrew@codesourcery.com>
 162
 163         Based on patches from Altera Corporation.
 164
 165         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
 166         nios2-opc.c.
 167         * Makefile.in: Regenerated.
 168         * configure.in: Add case for bfd_nios2_arch.
 169         * configure: Regenerated.
 170         * disassemble.c (ARCH_nios2): Define.
 171         (disassembler): Add case for bfd_arch_nios2.
 172         * nios2-dis.c: New file.
 173         * nios2-opc.c: New file.
 174
 175 2013-02-04  Alan Modra  <amodra@gmail.com>
 176
 177         * po/POTFILES.in: Regenerate.
 178         * rl78-decode.c: Regenerate.
 179         * rx-decode.c: Regenerate.
 180
 181 2013-01-30  Yufeng Zhang  <yufeng.zhang@arm.com>
 182
 183         * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
 184         ushll2 with F_HAS_ALIAS.  Add entries for sxtl, sxtl2, uxtl and uxtl2.
 185         * aarch64-asm.c (convert_xtl_to_shll): New function.
 186         (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
 187         calling convert_xtl_to_shll.
 188         * aarch64-dis.c (convert_shll_to_xtl): New function.
 189         (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
 190         calling convert_shll_to_xtl.
 191         * aarch64-gen.c: Update copyright year.
 192         * aarch64-asm-2.c: Re-generate.
 193         * aarch64-dis-2.c: Re-generate.
 194         * aarch64-opc-2.c: Re-generate.
 195
 196 2013-01-24  Nick Clifton  <nickc@redhat.com>
 197
 198         * v850-dis.c: Add support for e3v5 architecture.
 199         * v850-opc.c: Likewise.
 200
 201 2013-01-17  Yufeng Zhang  <yufeng.zhang@arm.com>
 202
 203         * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
 204         * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
 205         * aarch64-opc.c (operand_general_constraint_met_p): For
 206         AARCH64_MOD_LSL, move the range check on the shift amount before the
 207         alignment check; change to call set_sft_amount_out_of_range_error
 208         instead of set_imm_out_of_range_error.
 209         * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
 210         (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
 211         8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
 212         SIMD_IMM_SFT.
 213
 214 2013-01-16  H.J. Lu  <hongjiu.lu@intel.com>
 215
 216         * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
 217
 218         * i386-init.h: Regenerated.
 219         * i386-tbl.h: Likewise.
 220
 221 2013-01-15  Nick Clifton  <nickc@redhat.com>
 222
 223         * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
 224         values.
 225         * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
 226
 227 2013-01-14  Will Newton <will.newton@imgtec.com>
 228
 229         * metag-dis.c (REG_WIDTH): Increase to 64.
 230
 231 2013-01-10  Peter Bergner <bergner@vnet.ibm.com>
 232
 233         * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
 234         * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
 235         XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
 236         (SH6): Update.
 237         <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
 238         "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
 239         "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
 240         <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
 241
 242 2013-01-10  Will Newton <will.newton@imgtec.com>
 243
 244         * Makefile.am: Add Meta.
 245         * configure.in: Add Meta.
 246         * disassemble.c: Add Meta support.
 247         * metag-dis.c: New file.
 248         * Makefile.in: Regenerate.
 249         * configure: Regenerate.
 250
 251 2013-01-07  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
 252
 253         * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
 254         (match_opcode): Rename to cr16_match_opcode.
 255
 256 2013-01-04  Juergen Urban <JuergenUrban@gmx.de>
 257
 258         * mips-dis.c: Add names for CP0 registers of r5900.
 259         * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
 260         instructions sq and lq.
 261         Add support for MIPS r5900 CPU.
 262         Add support for 128 bit MMI (Multimedia Instructions).
 263         Add support for EE instructions (Emotion Engine).
 264         Disable unsupported floating point instructions (64 bit and
 265         undefined compare operations).
 266         Enable instructions of MIPS ISA IV which are supported by r5900.
 267         Disable 64 bit co processor instructions.
 268         Disable 64 bit multiplication and division instructions.
 269         Disable instructions for co-processor 2 and 3, because these are
 270         not supported (preparation for later VU0 support (Vector Unit)).
 271         Disable cvt.w.s because this behaves like trunc.w.s and the
 272         correct execution can't be ensured on r5900.
 273         Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
 274         will confuse less developers and compilers.
 275
 276 2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>
 277
 278         * aarch64-opc.c (aarch64_print_operand): Change to print
 279         AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
 280         in comment.
 281         * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
 282         from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
 283         OP_MOV_IMM_WIDE.
 284
 285 2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>
 286
 287         * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
 288         PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
 289
 290 2013-01-02  H.J. Lu  <hongjiu.lu@intel.com>
 291
 292         * i386-gen.c (process_copyright): Update copyright year to 2013.
 293
 294 2013-01-02  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
 295
 296         * cr16-dis.c (match_opcode,make_instruction): Remove static
 297         declaration.
 298         (dwordU,wordU): Moved typedefs to opcode/cr16.h
 299         (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
 300
 301 For older changes see ChangeLog-2012
 302 \f
 303 Copyright (C) 2013 Free Software Foundation, Inc.
 304
 305 Copying and distribution of this file, with or without modification,
 306 are permitted in any medium without royalty provided the copyright
 307 notice and this notice are preserved.
 308
 309 Local Variables:
 310 mode: change-log
 311 left-margin: 8
 312 fill-column: 74
 313 version-control: never
 314 End: