1 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
3 * score-dis.c: New file.
4 * score-opc.h: New file.
5 * Makefile.am: Add Score files.
6 * Makefile.in: Regenerate.
7 * configure.in: Add support for Score target.
8 * configure: Regenerate.
9 * disassemble.c: Add support for Score target.
11 2006-09-16 Nick Clifton <nickc@redhat.com>
12 Pedro Alves <pedro_alves@portugalmail.pt>
14 * arm-dis.c: Make use of new STRING_COMMA_LEN and CONST_STRNEQ
15 macros defined in bfd.h.
16 * cris-dis.c: Likewise.
17 * h8300-dis.c: Likewise.
18 * i386-dis.c: Likewise.
19 * ia64-gen.c: Likewise.
22 2006-09-04 Paul Brook <paul@codesourcery.com>
24 * arm-dis.c (neon_opcode): Fix suffix on VMOVN.
26 2006-08-23 H.J. Lu <hongjiu.lu@intel.com>
28 * i386-dis.c (three_byte_table): Expand to 256 elements.
30 2006-08-04 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
32 * i386-dis.c (MXC,EMC): Define.
33 (OP_MXC): New function to handle cvt* (convert instructions) between
34 %xmm and %mm register correctly.
36 (prefix_user_table): Modified cvtpi2pd,cvtpd2pi and cvttpd2pi
37 instruction operands in PREGRP2,PREGRP3,PREGRP4 appropriately
40 2006-07-29 Richard Sandiford <richard@codesourcery.com>
42 * m68k-opc.c (m68k_opcodes): Fix operand specificer in the Coldfire
45 2006-07-19 Paul Brook <paul@codesourcery.com>
47 * armd-dis.c (arm_opcodes): Fix rbit opcode.
49 2006-07-18 H.J. Lu <hongjiu.lu@intel.com>
51 * i386-dis.c (grps): Change "sldtQ", "strQ" and "smswQ" to
52 "sldt", "str" and "smsw".
54 2006-07-15 H.J. Lu <hongjiu.lu@intel.com>
57 * i386-dis.c (GRP11_C6): NEW.
65 (GRPPADLCK1): Likewise.
66 (GRPPADLCK2): Likewise.
67 (dis386): Use GRP11_C6 and GRP11_C7 for entres 0xc6 and 0xc7,
69 (grps): Add entries for GRP11_C6 and GRP11_C7.
71 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
72 Michael Meissner <michael.meissner@amd.com>
74 * i386-dis.c (dis386): Add support for 4 operand instructions. Add
75 support for amdfam10 SSE4a/ABM instructions. Modify all
76 initializer macros to have additional arguments. Disallow REP
77 prefix for non-string instructions.
81 2006-07-05 Julian Brown <julian@codesourcery.com>
83 * arm-dis.c (coprocessor): Alter fmsrr disassembly syntax.
85 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
87 * i386-dis.c (dis386_twobyte): Use "nopQ" for 0x1f.
88 (twobyte_has_modrm): Set 1 for 0x1f.
90 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
92 * i386-dis.c (NOP_Fixup): Removed.
94 (NOP_Fixup2): Likewise.
95 (dis386): Use NOP_Fixup1 and NOP_Fixup2 on 0x90.
97 2006-06-12 Julian Brown <julian@codesourcery.com>
99 * arm-dis.c (print_insn_neon): Disassemble 32-bit immediates as signed
102 2006-06-10 H.J. Lu <hongjiu.lu@intel.com>
104 * i386.c (GRP10): Renamed to ...
106 (GRP11): Renamed to ...
108 (GRP12): Renamed to ...
110 (GRP13): Renamed to ...
112 (GRP14): Renamed to ...
114 (dis386_twobyte): Updated.
117 2006-06-09 Nick Clifton <nickc@redhat.com>
119 * po/fi.po: Updated Finnish translation.
121 2006-06-07 Joseph S. Myers <joseph@codesourcery.com>
123 * po/Make-in (pdf, ps): New dummy targets.
125 2006-06-06 Paul Brook <paul@codesourcery.com>
127 * arm-dis.c (coprocessor_opcodes): Add %c to unconditional arm
129 (neon_opcodes): Add conditional execution specifiers.
130 (thumb_opcodes): Ditto.
131 (thumb32_opcodes): Ditto.
132 (arm_conditional): Change 0xe to "al" and add "" to end.
133 (ifthen_state, ifthen_next_state, ifthen_address): New.
134 (IFTHEN_COND): Define.
135 (print_insn_coprocessor, print_insn_neon): Print thumb conditions.
136 (print_insn_arm): Change %c to use new values of arm_conditional.
137 (print_insn_thumb16): Print thumb conditions. Add %I.
138 (print_insn_thumb32): Print thumb conditions.
139 (find_ifthen_state): New function.
140 (print_insn): Track IT block state.
142 2006-06-06 Ben Elliston <bje@au.ibm.com>
143 Anton Blanchard <anton@samba.org>
144 Peter Bergner <bergner@vnet.ibm.com>
146 * ppc-dis.c (powerpc_dialect): Handle power6 option.
147 (print_ppc_disassembler_options): Mention power6.
149 2006-06-06 Thiemo Seufer <ths@mips.com>
150 Chao-ying Fu <fu@mips.com>
152 * mips-dis.c: Disassemble DSP64 instructions for MIPS64R2.
153 * mips-opc.c: Add DSP64 instructions.
155 2006-06-06 Alan Modra <amodra@bigpond.net.au>
157 * m68hc11-dis.c (print_insn): Warning fix.
159 2006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
161 * po/Make-in (top_builddir): Define.
163 2006-06-05 Alan Modra <amodra@bigpond.net.au>
165 * Makefile.am: Run "make dep-am".
166 * Makefile.in: Regenerate.
167 * config.in: Regenerate.
169 2006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
171 * Makefile.am (INCLUDES): Use @INCINTL@.
172 * acinclude.m4: Include new gettext macros.
173 * configure.in: Use ZW_GNU_GETTEXT_SISTER_DIR and AM_PO_SUBDIRS.
174 Remove local code for po/Makefile.
175 * Makefile.in, aclocal.m4, configure: Regenerated.
177 2006-05-30 Nick Clifton <nickc@redhat.com>
179 * po/es.po: Updated Spanish translation.
181 2006-05-25 Richard Sandiford <richard@codesourcery.com>
183 * m68k-opc.c (m68k_opcodes): Fix the masks of the Coldfire fmovemd
184 and fmovem entries. Put register list entries before immediate
185 mask entries. Use "l" rather than "L" in the fmovem entries.
186 * m68k-dis.c (match_insn_m68k): Remove the PRIV argument and work it
188 (m68k_scan_mask): New function, split out from...
189 (print_insn_m68k): ...here. If no architecture has been set,
190 first try printing an m680x0 instruction, then try a Coldfire one.
192 2006-05-24 Nick Clifton <nickc@redhat.com>
194 * po/ga.po: Updated Irish translation.
196 2006-05-22 Nick Clifton <nickc@redhat.com>
198 * crx-dis.c (EXTRACT): Make macro work on 64-bit hosts.
200 2006-05-22 Nick Clifton <nickc@redhat.com>
202 * po/nl.po: Updated translation.
204 2006-05-18 Alan Modra <amodra@bigpond.net.au>
206 * avr-dis.c: Formatting fix.
208 2006-05-14 Thiemo Seufer <ths@mips.com>
210 * mips16-opc.c (I1, I32, I64): New shortcut defines.
211 (mips16_opcodes): Change membership of instructions to their
214 2006-05-09 H.J. Lu <hongjiu.lu@intel.com>
216 * i386-dis.c (grps): Update sgdt/sidt for 64bit.
218 2006-05-05 Julian Brown <julian@codesourcery.com>
220 * arm-dis.c (coprocessor_opcodes): Don't interpret fldmx/fstmx as
223 2006-05-05 Thiemo Seufer <ths@mips.com>
224 David Ung <davidu@mips.com>
226 * mips-opc.c: Add macro for cache instruction.
228 2006-05-04 Thiemo Seufer <ths@mips.com>
229 Nigel Stephens <nigel@mips.com>
230 David Ung <davidu@mips.com>
232 * mips-dis.c (mips_arch_choices): Add smartmips instruction
233 decoding to MIPS32 and MIPS32R2. Limit DSP decoding to release
234 2 ISAs. Add MIPS3D decoding to MIPS32R2. Add MT decoding to
236 * mips-opc.c: fix random typos in comments.
237 (INSN_SMARTMIPS): New defines.
238 (mips_builtin_opcodes): Add paired single support for MIPS32R2.
239 Move bc3f, bc3fl, bc3t, bc3tl downwards. Move flushi, flushd,
240 flushid, wb upwards. Move cfc3, ctc3 downwards. Rework the
241 FP_S and FP_D flags to denote single and double register
242 accesses separately. Move dmfc3, dmtc3, mfc3, mtc3 downwards.
243 Allow jr.hb and jalr.hb for release 1 ISAs. Allow luxc1, suxc1
244 for MIPS32R2. Add SmartMIPS instructions. Add two-argument
245 variants of bc2f, bc2fl, bc2t, bc2tl. Add mfhc2, mthc2 to
247 * mips16-opc.c (mips16_opcodes): Add sdbbp instruction.
249 2006-05-03 Thiemo Seufer <ths@mips.com>
251 * mips-opc.c (mips_builtin_opcodes): Fix mftr argument order.
253 2006-05-02 Thiemo Seufer <ths@mips.com>
254 Nigel Stephens <nigel@mips.com>
255 David Ung <davidu@mips.com>
257 * mips-dis.c (print_insn_args): Force mips16 to odd addresses.
258 (print_mips16_insn_arg): Force mips16 to odd addresses.
260 2006-04-30 Thiemo Seufer <ths@mips.com>
261 David Ung <davidu@mips.com>
263 * mips-opc.c (mips_builtin_opcodes): Add udi instructions
265 * mips-dis.c (print_insn_args): Adds udi argument handling.
267 2006-04-28 James E Wilson <wilson@specifix.com>
269 * m68k-dis.c (match_insn_m68k): Restore fprintf_func before printing
272 2006-04-28 Thiemo Seufer <ths@mips.com>
273 David Ung <davidu@mips.com>
274 Nigel Stephens <nigel@mips.com>
276 * mips-dis.c (mips_cp0sel_names_mips3264r2): Add MT register
279 2006-04-28 Thiemo Seufer <ths@mips.com>
280 Nigel Stephens <nigel@mips.com>
281 David Ung <davidu@mips.com>
283 * mips-dis.c (print_insn_args): Add mips_opcode argument.
284 (print_insn_mips): Adjust print_insn_args call.
286 2006-04-28 Thiemo Seufer <ths@mips.com>
287 Nigel Stephens <nigel@mips.com>
289 * mips-dis.c (print_insn_args): Print $fcc only for FP
290 instructions, use $cc elsewise.
292 2006-04-28 Thiemo Seufer <ths@mips.com>
293 Nigel Stephens <nigel@mips.com>
295 * opcodes/mips-dis.c (mips16_to_32_reg_map, mips16_reg_names):
296 Map MIPS16 registers to O32 names.
297 (print_mips16_insn_arg): Use mips16_reg_names.
299 2006-04-26 Julian Brown <julian@codesourcery.com>
301 * arm-dis.c (print_insn_neon): Disassemble floating-point constant
304 2006-04-26 Nathan Sidwell <nathan@codesourcery.com>
305 Julian Brown <julian@codesourcery.com>
307 * opcodes/arm-dis.c (coprocessor_opcodes): Add %A, %B, %k, convert
308 %<code>[zy] into %[zy]<code>. Expand meaning of %<bitfield>['`?].
309 Add unified load/store instruction names.
310 (neon_opcode_table): New.
311 (arm_opcodes): Expand meaning of %<bitfield>['`?].
312 (arm_decode_bitfield): New.
313 (print_insn_coprocessor): Add pc argument. Add %A & %B specifiers.
314 Use arm_decode_bitfield and adjust numeric specifiers. Adjust %z & %y.
315 (print_insn_neon): New.
316 (print_insn_arm): Adjust print_insn_coprocessor call. Call
317 print_insn_neon. Use arm_decode_bitfield and adjust numeric specifiers.
318 (print_insn_thumb32): Likewise.
320 2006-04-19 Alan Modra <amodra@bigpond.net.au>
322 * Makefile.am: Run "make dep-am".
323 * Makefile.in: Regenerate.
325 2006-04-19 Alan Modra <amodra@bigpond.net.au>
327 * avr-dis.c (avr_operand): Warning fix.
329 * configure: Regenerate.
331 2006-04-16 Daniel Jacobowitz <dan@codesourcery.com>
333 * po/POTFILES.in: Regenerated.
335 2006-04-12 Hochstein <hochstein@algo.informatik.tu-darmstadt.de>
338 * avr-dis.c (avr_operand): Arrange for a comment to appear before
339 the symolic form of an address, so that the output of objdump -d
342 2006-04-10 DJ Delorie <dj@redhat.com>
344 * m32c-asm.c: Regenerate.
346 2006-04-06 Carlos O'Donell <carlos@codesourcery.com>
348 * Makefile.am: Add install-html target.
349 * Makefile.in: Regenerate.
351 2006-04-06 Nick Clifton <nickc@redhat.com>
353 * po/vi/po: Updated Vietnamese translation.
355 2006-03-31 Paul Koning <ni1d@arrl.net>
357 * pdp11-opc.c (pdp11_opcodes): Fix opcode for SEC instruction.
359 2006-03-16 Bernd Schmidt <bernd.schmidt@analog.com>
361 * bfin-dis.c (decode_dsp32shiftimm_0): Simplify and correct the
362 logic to identify halfword shifts.
364 2006-03-16 Paul Brook <paul@codesourcery.com>
366 * arm-dis.c (arm_opcodes): Rename swi to svc.
367 (thumb_opcodes): Ditto.
369 2006-03-13 DJ Delorie <dj@redhat.com>
371 * m32c-asm.c: Regenerate.
372 * m32c-desc.c: Likewise.
373 * m32c-desc.h: Likewise.
374 * m32c-dis.c: Likewise.
375 * m32c-ibld.c: Likewise.
376 * m32c-opc.c: Likewise.
377 * m32c-opc.h: Likewise.
379 2006-03-10 DJ Delorie <dj@redhat.com>
381 * m32c-desc.c: Regenerate with mul.l, mulu.l.
382 * m32c-opc.c: Likewise.
383 * m32c-opc.h: Likewise.
386 2006-03-09 Nick Clifton <nickc@redhat.com>
388 * po/sv.po: Updated Swedish translation.
390 2006-03-07 H.J. Lu <hongjiu.lu@intel.com>
393 * i386-dis.c (REP_Fixup): New function.
394 (AL): Remove duplicate.
399 (indirDXr): Likewise.
402 (dis386): Updated entries of ins, outs, movs, lods and stos.
404 2006-03-05 Nick Clifton <nickc@redhat.com>
406 * cgen-ibld.in (insert_normal): Cope with attempts to insert a
407 signed 32-bit value into an unsigned 32-bit field when the host is
409 * fr30-ibld.c: Regenerate.
410 * frv-ibld.c: Regenerate.
411 * ip2k-ibld.c: Regenerate.
412 * iq2000-asm.c: Regenerate.
413 * iq2000-ibld.c: Regenerate.
414 * m32c-ibld.c: Regenerate.
415 * m32r-ibld.c: Regenerate.
416 * openrisc-ibld.c: Regenerate.
417 * xc16x-ibld.c: Regenerate.
418 * xstormy16-ibld.c: Regenerate.
420 2006-03-03 Shrirang Khisti <shrirangk@kpitcummins.com)
422 * xc16x-asm.c: Regenerate.
423 * xc16x-dis.c: Regenerate.
425 2006-02-27 Carlos O'Donell <carlos@codesourcery.com>
427 * po/Make-in: Add html target.
429 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
431 * i386-dis.c (IS_3BYTE_OPCODE): New for 3-byte opcodes used by
432 Intel Merom New Instructions.
433 (THREE_BYTE_0): Likewise.
434 (THREE_BYTE_1): Likewise.
435 (three_byte_table): Likewise.
436 (dis386_twobyte): Use THREE_BYTE_0 for entry 0x38. Use
437 THREE_BYTE_1 for entry 0x3a.
438 (twobyte_has_modrm): Updated.
439 (twobyte_uses_SSE_prefix): Likewise.
440 (print_insn): Handle 3-byte opcodes used by Intel Merom New
443 2006-02-24 David S. Miller <davem@sunset.davemloft.net>
445 * sparc-dis.c (v9_priv_reg_names): Add "gl" entry.
446 (v9_hpriv_reg_names): New table.
447 (print_insn_sparc): Allow values up to 16 for '?' and '!'.
448 New cases '$' and '%' for read/write hyperprivileged register.
449 * sparc-opc.c (sparc_opcodes): Add new entries for UA2005
450 window handling and rdhpr/wrhpr instructions.
452 2006-02-24 DJ Delorie <dj@redhat.com>
454 * m32c-desc.c: Regenerate with linker relaxation attributes.
455 * m32c-desc.h: Likewise.
456 * m32c-dis.c: Likewise.
457 * m32c-opc.c: Likewise.
459 2006-02-24 Paul Brook <paul@codesourcery.com>
461 * arm-dis.c (arm_opcodes): Add V7 instructions.
462 (thumb32_opcodes): Ditto. Handle V7M MSR/MRS variants.
463 (print_arm_address): New function.
464 (print_insn_arm): Use it. Add 'P' and 'U' cases.
465 (psr_name): New function.
466 (print_insn_thumb32): Add 'U', 'C' and 'D' cases.
468 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
470 * ia64-opc-i.c (bXc): New.
472 (OpX2TaTbYaXcC): Likewise.
475 (ia64_opcodes_i): Add instructions for tf.
477 * ia64-opc.h (IMMU5b): New.
479 * ia64-asmtab.c: Regenerated.
481 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
483 * ia64-gen.c: Update copyright years.
484 * ia64-opc-b.c: Likewise.
486 2006-02-22 H.J. Lu <hongjiu.lu@intel.com>
488 * ia64-gen.c (lookup_regindex): Handle ".vm".
489 (print_dependency_table): Handle '\"'.
491 * ia64-ic.tbl: Updated from SDM 2.2.
492 * ia64-raw.tbl: Likewise.
493 * ia64-waw.tbl: Likewise.
494 * ia64-asmtab.c: Regenerated.
496 * ia64-opc-b.c (ia64_opcodes_b): Add vmsw.0 and vmsw.1.
498 2006-02-17 Shrirang Khisti <shrirangk@kpitcummins.com>
499 Anil Paranjape <anilp1@kpitcummins.com>
500 Shilin Shakti <shilins@kpitcummins.com>
502 * xc16x-desc.h: New file
503 * xc16x-desc.c: New file
504 * xc16x-opc.h: New file
505 * xc16x-opc.c: New file
506 * xc16x-ibld.c: New file
507 * xc16x-asm.c: New file
508 * xc16x-dis.c: New file
509 * Makefile.am: Entries for xc16x
510 * Makefile.in: Regenerate
511 * cofigure.in: Add xc16x target information.
512 * configure: Regenerate.
513 * disassemble.c: Add xc16x target information.
515 2006-02-11 H.J. Lu <hongjiu.lu@intel.com>
517 * i386-dis.c (dis386_twobyte): Use "movZ" for debug register
520 2006-02-11 H.J. Lu <hongjiu.lu@intel.com>
522 * i386-dis.c ('Z'): Add a new macro.
523 (dis386_twobyte): Use "movZ" for control register moves.
525 2006-02-10 Nick Clifton <nickc@redhat.com>
527 * iq2000-asm.c: Regenerate.
529 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
531 * m68k-dis.c (print_insn_m68k): Use bfd_m68k_mach_to_features.
533 2006-01-26 David Ung <davidu@mips.com>
535 * mips-opc.c: Add I33 masks to these MIPS32R2 instructions: prefx,
536 ceil.l.d, ceil.l.s, cvt.d.l, cvt.l.d, cvt.l.s, cvt.s.l, floor.l.d,
537 floor.l.s, ldxc1, lwxc1, madd.d, madd.s, msub.d, msub.s, nmadd.d,
538 nmadd.s, nmsub.d, nmsub.s, recip.d, recip.s, round.l.d, rsqrt.d,
539 rsqrt.s, sdxc1, swxc1, trunc.l.d, trunc.l.s.
541 2006-01-18 Arnold Metselaar <arnoldm@sourceware.org>
543 * z80-dis.c (struct buffer, prt_d, prt_d_n, arit_d, ld_r_d,
544 ld_d_r, pref_xd_cb): Use signed char to hold data to be
546 * z80-dis.c (TXTSIZ): Increase buffer size to 24, this fixes
547 buffer overflows when disassembling instructions like
549 * z80-dis.c (opc_ind, pref_xd_cb): Suppress '+' in an indexed
550 operand, if the offset is negative.
552 2006-01-17 Arnold Metselaar <arnoldm@sourceware.org>
554 * z80-dis.c (struct buffer, prt_d, prt_d_n, pref_xd_cb): Use
555 unsigned char to hold data to be disassembled.
557 2006-01-17 Andreas Schwab <schwab@suse.de>
560 * disassemble.c (disassemble_init_for_target): Set
561 disassembler_needs_relocs for bfd_arch_arm.
563 2006-01-16 Paul Brook <paul@codesourcery.com>
565 * m68k-opc.c (m68k_opcodes): Fix opcodes for ColdFire f?abss,
566 f?add?, and f?sub? instructions.
568 2006-01-16 Nick Clifton <nickc@redhat.com>
570 * po/zh_CN.po: New Chinese (simplified) translation.
571 * configure.in (ALL_LINGUAS): Add "zh_CH".
572 * configure: Regenerate.
574 2006-01-05 Paul Brook <paul@codesourcery.com>
576 * m68k-opc.c (m68k_opcodes): Add missing ColdFire fdsqrtd entry.
578 2006-01-06 DJ Delorie <dj@redhat.com>
580 * m32c-desc.c: Regenerate.
581 * m32c-opc.c: Regenerate.
582 * m32c-opc.h: Regenerate.
584 2006-01-03 DJ Delorie <dj@redhat.com>
586 * cgen-ibld.in (extract_normal): Avoid memory range errors.
587 * m32c-ibld.c: Regenerated.
589 For older changes see ChangeLog-2005
595 version-control: never