opcodes/ChangeLog

   1 2021-12-02  Marcus Nilsson  <brainbomb@gmail.com>
   2
   3         * avr-dis.c (avr_operand); Pass in disassemble_info and fill
   4         in insn_type on branching instructions.
   5
   6 2021-11-25  Andrew Burgess  <aburgess@redhat.com>
   7             Simon Cook  <simon.cook@embecosm.com>
   8
   9         * riscv-dis.c (enum riscv_option_arg_t): New enum typedef.
  10         (riscv_options): New static global.
  11         (disassembler_options_riscv): New function.
  12         (print_riscv_disassembler_options): Rewrite to use
  13         disassembler_options_riscv.
  14
  15 2021-11-25  Nick Clifton  <nickc@redhat.com>
  16
  17         PR 28614
  18         * aarch64-asm.c: Replace assert(0) with real code.
  19         * aarch64-dis.c: Likewise.
  20         * aarch64-opc.c: Likewise.
  21
  22 2021-11-25  Nick Clifton  <nickc@redhat.com>
  23
  24         * po/fr.po; Updated French translation.
  25
  26 2021-10-27  Maciej W. Rozycki  <macro@embecosm.com>
  27
  28         * Makefile.am: Remove obsolete comment.
  29         * configure.ac: Refer `libbfd.la' to link shared BFD library
  30         except for Cygwin.
  31         * Makefile.in: Regenerate.
  32         * configure: Regenerate.
  33
  34 2021-09-27  Nick Alcock  <nick.alcock@oracle.com>
  35
  36         * configure: Regenerate.
  37
  38 2021-09-25  Peter Bergner  <bergner@linux.ibm.com>
  39
  40         * ppc-opc.c (powerpc_opcodes) <mfppr, mfppr32, mtppr, mtppr32>: Enable
  41         on POWER5 and later.
  42
  43 2021-09-20  Andrew Burgess  <andrew.burgess@embecosm.com>
  44
  45         * riscv-dis.c (riscv_disassemble_insn): Print a .%dbyte opcode
  46         before an unknown instruction, '%d' is replaced with the
  47         instruction length.
  48
  49 2021-09-02  Nick Clifton  <nickc@redhat.com>
  50
  51         PR 28292
  52         * v850-opc.c (D16): Use BFD_RELOC_V850_LO16_SPLIT_OFFSET in place
  53         of BFD_RELOC_16.
  54
  55 2021-08-17  Shahab Vahedi <shahab@synopsys.com>
  56
  57         * arc-regs.h (DEF): Fix the register numbers.
  58
  59 2021-08-10  Nick Clifton  <nickc@redhat.com>
  60
  61         * po/sr.po: Updated Serbian translation.
  62
  63 2021-07-26  Chenghua Xu  <xuchenghua@loongson.cn>
  64
  65         * mips-dis.c (mips_arch_choices): Correct gs264e bfd_mach.
  66
  67 2021-06-07  Andreas Krebbel  <krebbel@linux.ibm.com>
  68
  69         * s390-opc.txt: Add qpaci.
  70
  71 2021-07-03  Nick Clifton  <nickc@redhat.com>
  72
  73         * configure: Regenerate.
  74         * po/opcodes.pot: Regenerate.
  75
  76 2021-07-03  Nick Clifton  <nickc@redhat.com>
  77
  78         * 2.37 release branch created.
  79
  80 2021-07-02  Alan Modra  <amodra@gmail.com>
  81
  82         * nds32-dis.c (nds32_find_reg_keyword): Constify arg and return.
  83         (nds32_parse_audio_ext, nds32_parse_opcode): Constify psys_reg.
  84         (nds32_field_table, nds32_opcode_table, nds32_keyword_table),
  85         (nds32_opcodes, nds32_operand_fields, nds32_keywords),
  86         (nds32_keyword_gpr): Move declarations to..
  87         * nds32-asm.h: ..here, constifying to match definitions.
  88
  89 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
  90
  91         * Makefile.am (GUILE): New variable.
  92         (CGEN): Use $(GUILE).
  93         * Makefile.in: Regenerate.
  94
  95 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
  96
  97         * mep-asm.c (macros): Mark static & const.
  98         (lookup_macro): Change return & m to const.
  99         (expand_macro): Change mac to const.
 100         (expand_string): Change pmacro to const.
 101
 102 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 103
 104         * nds32-asm.c (operand_fields): Rename to ...
 105         (nds32_operand_fields): ... this.
 106         (keyword_gpr): Rename to ...
 107         (nds32_keyword_gpr): ... this.
 108         (keyword_usr, keyword_dxr, keyword_sr, keyword_cp, keyword_cpr,
 109         keyword_fsr, keyword_fdr, keyword_abdim, keyword_abm,
 110         keyword_dpref_st, keyword_cctl_lv, keyword_standby_st,
 111         keyword_msync_st, keyword_im5_i, keyword_im5_m, keyword_accumulator,
 112         keyword_aridx, keyword_aridx2, keyword_aridxi, keyword_aridxi_mx):
 113         Mark static.
 114         (keywords): Rename to ...
 115         (nds32_keywords): ... this.
 116         * nds32-dis.c: Rename operand_fields to nds32_operand_fields,
 117         keywords to nds32_keywords, and keyword_gpr to nds32_keyword_gpr.
 118
 119 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 120
 121         * z80-dis.c (opc_ed): Make const.
 122         (pref_ed): Make p const.
 123
 124 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 125
 126         * microblaze-dis.c (get_field_special): Make op const.
 127         (read_insn_microblaze): Make opr & op const.  Rename opcodes to
 128         microblaze_opcodes.
 129         (print_insn_microblaze): Make op & pop const.
 130         (get_insn_microblaze): Make op const.  Rename opcodes to
 131         microblaze_opcodes.
 132         (microblaze_get_target_address): Likewise.
 133         * microblaze-opc.h (struct op_code_struct): Make const.
 134         Rename opcodes to microblaze_opcodes.
 135
 136 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 137
 138         * aarch64-gen.c (aarch64_opcode_table): Add const.
 139         * aarch64-tbl.h (aarch64_opcode_table): Likewise.
 140
 141 2021-06-22  Andrew Burgess  <andrew.burgess@embecosm.com>
 142
 143         * cgen-dis.c (count_decodable_bits): Use __builtin_popcount when
 144         available.
 145
 146 2021-06-22  Alan Modra  <amodra@gmail.com>
 147
 148         * pj-dis.c (print_insn_pj): Don't print trailing tab.  Do
 149         print separator for pcrel insns.
 150
 151 2021-06-19  Alan Modra  <amodra@gmail.com>
 152
 153         * vax-dis.c (print_insn_vax): Avoid pointer overflow.
 154
 155 2021-06-19  Alan Modra  <amodra@gmail.com>
 156
 157         * tic30-dis.c (get_register_operand): Don't ask strncpy to fill
 158         entire buffer.
 159
 160 2021-06-17  Alan Modra  <amodra@gmail.com>
 161
 162         * ppc-opc.c (powerpc_opcodes): Move cell db*cyc to proper location
 163         in table.
 164
 165 2021-06-03  Alan Modra  <amodra@gmail.com>
 166
 167         PR 1202
 168         * mcore-dis.c (print_insn_mcore): Correct loopt disassembly.
 169         Use unsigned int for inst.
 170
 171 2021-06-02  Shahab Vahedi  <shahab@synopsys.com>
 172
 173         * arc-dis.c (arc_option_arg_t): New enumeration.
 174         (arc_options): New variable.
 175         (disassembler_options_arc): New function.
 176         (print_arc_disassembler_options): Reimplement in terms of
 177         "disassembler_options_arc".
 178
 179 2021-05-29  Alan Modra  <amodra@gmail.com>
 180
 181         * ppc-dis.c (lookup_powerpc): Test deprecated field when -Many.
 182         Don't special case PPC_OPCODE_RAW.
 183         (lookup_prefix): Likewise.
 184         (lookup_vle, lookup_spe2): Similarly.  Add dialect parameter and..
 185         (print_insn_powerpc): ..update caller.
 186         * ppc-opc.c (EXT): Define.
 187         (powerpc_opcodes): Mark extended mnemonics with EXT.
 188         (prefix_opcodes, vle_opcodes): Likewise.
 189         (XISEL, XISEL_MASK): Add cr field and simplify.
 190         (powerpc_opcodes): Use XISEL with extended isel mnemonics and sort
 191         all isel variants to where the base mnemonic belongs.  Sort dstt,
 192         dststt and dssall.
 193
 194 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 195
 196         * mips-opc.c (mips_builtin_opcodes): Reorder legacy COP0, COP2,
 197         COP3 opcode instructions.
 198
 199 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 200
 201         * mips-opc.c (mips_builtin_opcodes): Update exclusion list for
 202         "ldc2", "ldc3", "lwc0", "lwc2", "lwc3", "sdc2", "sdc3", "swc0",
 203         "swc2", "swc3", "cfc0", "ctc0", "bc2f", "bc2fl", "bc2t",
 204         "bc2tl", "cfc2", "ctc2", "dmfc2", "dmtc2", "mfc2", "mtc2",
 205         "bc3f", "bc3fl", "bc3t", "bc3tl", "cfc3", "ctc3", "mfc3",
 206         "mtc3", "bc0f", "bc0fl", "bc0t", "bc0tl", "rfe", "c2", "c3",
 207         "cop2", and "cop3" entries.
 208
 209 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 210
 211         * mips-opc.c (mips_builtin_opcodes): Remove "dmfc3" and "dmtc3"
 212         entries and associated comments.
 213
 214 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 215
 216         * mips-opc.c (mips_builtin_opcodes): Move the "rfe" entry ahead
 217         of "c0".
 218
 219 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 220
 221         * mips-dis.c (mips_cp1_names_mips): New variable.
 222         (mips_arch_choices): Use it rather than `mips_cp1_names_numeric'
 223         for "r3000", "r4000", "r4010", "vr4100", "vr4111", "vr4120",
 224         "r4300", "r4400", "r4600", "r4650", "r5000", "vr5400", "vr5500",
 225         "r5900", "r6000", "rm7000", "rm9000", "r8000", "r10000",
 226         "r12000", "r14000", "r16000", "mips5", "loongson2e", and
 227         "loongson2f".
 228
 229 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 230
 231         * mips-dis.c (print_reg) <OP_REG_COPRO>: Move control register
 232         handling code over to...
 233         <OP_REG_CONTROL>: ... this new case.
 234         * mips-opc.c (decode_mips_operand) <'g', 'y'>: New cases.
 235         (mips_builtin_opcodes): Update "cfc1", "ctc1", "cttc1", "cttc2",
 236         "cfc0", "ctc0", "cfc2", "ctc2", "cfc3", and "ctc3" entries
 237         replacing the `G' operand code with `g'.  Update "cftc1" and
 238         "cftc2" entries replacing the `E' operand code with `y'.
 239         * micromips-opc.c (decode_micromips_operand) <'g'>: New case.
 240         (micromips_opcodes): Update "cfc1", "cfc2", "ctc1", and "ctc2"
 241         entries replacing the `G' operand code with `g'.
 242
 243 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 244
 245         * mips-dis.c (mips_cp0_names_r3900): New variable.
 246         (mips_arch_choices): Use it rather than `mips_cp0_names_numeric'
 247         for "r3900".
 248
 249 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 250
 251         * mips-opc.c (mips_builtin_opcodes): Switch "cttc2", "mttc2",
 252         and "mtthc2" to using the `G' rather than `g' operand code for
 253         the coprocessor control register referred.
 254
 255 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 256
 257         * micromips-opc.c (micromips_opcodes): Swap the two "dmtc1"
 258         entries with each other.
 259
 260 2021-05-27  Peter Bergner  <bergner@linux.ibm.com>
 261
 262         * ppc-opc.c (powerpc_opcodes) <xxmr, xxlnot>: New extended mnemonics.
 263
 264 2021-05-25  Alan Modra  <amodra@gmail.com>
 265
 266         * cris-desc.c: Regenerate.
 267         * cris-desc.h: Regenerate.
 268         * cris-opc.h: Regenerate.
 269         * po/POTFILES.in: Regenerate.
 270
 271 2021-05-24  Mike Frysinger  <vapier@gentoo.org>
 272
 273         * Makefile.am (HFILES): Add cris-desc.h & cris-opc.h.
 274         (TARGET_LIBOPCODES_CFILES): Add cris-desc.c.
 275         (CGEN_CPUS): Add cris.
 276         (CRIS_DEPS): Define.
 277         (stamp-cris): New rule.
 278         * cgen.sh: Handle desc action.
 279         * configure.ac (bfd_cris_arch): Add cris-desc.lo.
 280         * Makefile.in, configure: Regenerate.
 281
 282 2021-05-18  Job Noorman  <mtvec@pm.me>
 283
 284         PR 27814
 285         * riscv-dis.c (riscv_get_disassembler): Get elf attributes only for
 286         the elf objects.
 287
 288 2021-05-17  Alex Coplan  <alex.coplan@arm.com>
 289
 290         * arm-dis.c (mve_opcodes): Fix disassembly of
 291         MVE_VMOV2_GP_TO_VEC_LANE when idx == 1.
 292         (is_mve_encoding_conflict): MVE vector loads should not match
 293         when P = W = 0.
 294         (is_mve_unpredictable): It's not unpredictable to use the same
 295         source register twice (for MVE_VMOV2_GP_TO_VEC_LANE).
 296
 297 2021-05-11  Nick Clifton  <nickc@redhat.com>
 298
 299         PR 27840
 300         * tic30-dis.c (print_insn_tic30): Prevent attempts to read beyond
 301         the end of the code buffer.
 302
 303 2021-05-06  Stafford Horne  <shorne@gmail.com>
 304
 305         PR 21464
 306         * or1k-asm.c: Regenerate.
 307
 308 2021-05-01  Max Filippov  <jcmvbkbc@gmail.com>
 309
 310         * xtensa-dis.c (print_insn_xtensa): Fill in info->insn_type and
 311         info->insn_info_valid.
 312
 313 2021-04-26  Jan Beulich  <jbeulich@suse.com>
 314
 315         * i386-opc.tbl (lea): Add Optimize.
 316         * opcodes/i386-tbl.h: Re-generate.
 317
 318 2020-04-23  Max Filippov  <jcmvbkbc@gmail.com>
 319
 320         * xtensa-dis.c (print_xtensa_operand): For PC-relative operand
 321         of l32r fetch and display referenced literal value.
 322
 323 2021-04-23  Max Filippov  <jcmvbkbc@gmail.com>
 324
 325         * xtensa-dis.c (print_insn_xtensa): Set info->bytes_per_chunk
 326         to 4 for literal disassembly.
 327
 328 2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 329
 330         * aarch64-opc.c: Add new registers (RPAOS, RPALOS, PAALLOS, PAALL) support
 331         for TLBI instruction.
 332
 333 2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 334
 335         * aarch64-opc.c: Add new register (CIPAPA, CIGDPAPA) support for
 336         DC instruction.
 337
 338 2021-04-19  Jan Beulich  <jbeulich@suse.com>
 339
 340         * aarch64-asm.c (encode_asimd_fcvt): Add initializer for
 341         "qualifier".
 342         (convert_mov_to_movewide): Add initializer for "value".
 343
 344 2021-04-16  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 345
 346         * aarch64-opc.c: Add RME system registers.
 347
 348 2021-04-16  Lifang Xia <lifang_xia@c-sky.com>
 349
 350         * riscv-opc.c (riscv_opcodes): New insn alias for addi. Compress
 351         "addi d,CV,z" to "c.mv d,CV".
 352
 353 2021-04-12  Alan Modra  <amodra@gmail.com>
 354
 355         * configure.ac (--enable-checking): Add support.
 356         * config.in: Regenerate.
 357         * configure: Regenerate.
 358
 359 2021-04-09  Tejas Belagod  <tejas.belagod@arm.com>
 360
 361         * aarch64-tbl.h (struct aarch64_opcode aarch64_opcode_table): Reclassify
 362         LD64/ST64 instructions to lse_atomic instead of ldstexcl.
 363
 364 2021-04-09  Alan Modra  <amodra@gmail.com>
 365
 366         * ppc-dis.c (struct dis_private): Add "special".
 367         (POWERPC_DIALECT): Delete.  Replace uses with..
 368         (private_data): ..this.  New inline function.
 369         (disassemble_init_powerpc): Init "special" names.
 370         (skip_optional_operands): Add is_pcrel arg, set when detecting R
 371         field of prefix instructions.
 372         (bsearch_reloc, print_got_plt): New functions.
 373         (print_insn_powerpc): For pcrel instructions, print target address
 374         and symbol if known, and decode plt and got loads too.
 375
 376 2021-04-08  Alan Modra  <amodra@gmail.com>
 377
 378         PR 27684
 379         * ppc-opc.c (powerpc_opcodes): Correct usprg typos, add mfpir.
 380
 381 2021-04-08  Alan Modra  <amodra@gmail.com>
 382
 383         PR 27676
 384         * ppc-opc.c (DCBT_EO): Move earlier.
 385         (insert_thct, extract_thct, insert_thds, extract_thds): New functions.
 386         (powerpc_operands): Add THCT and THDS entries.
 387         (powerpc_opcodes): Add dcbtstct, dcbtstds, dcbna, dcbtct, dcbtds.
 388
 389 2021-04-06  Alan Modra  <amodra@gmail.com>
 390
 391         * dis-buf.c (generic_symbol_at_address): Return symbol* NULL.
 392         * s12z-dis.c (decode_possible_symbol): Use symbol returned from
 393         symbol_at_address_func.
 394
 395 2021-04-05  Alan Modra  <amodra@gmail.com>
 396
 397         * configure.ac: Don't check for limits.h, string.h, strings.h or
 398         stdlib.h.
 399         (AC_ISC_POSIX): Don't invoke.
 400         * sysdep.h: Include stdlib.h and string.h unconditionally.
 401         * i386-opc.h: Include limits.h unconditionally.
 402         * wasm32-dis.c: Likewise.
 403         * cgen-opc.c: Don't include alloca-conf.h.
 404         * config.in: Regenerate.
 405         * configure: Regenerate.
 406
 407 2021-04-01  Martin Liska  <mliska@suse.cz>
 408
 409         * arm-dis.c (strneq): Remove strneq and use startswith.
 410         * cr16-dis.c (print_insn_cr16): Likewise.
 411         * score-dis.c (streq): Likewise.
 412         (strneq): Likewise.
 413         * score7-dis.c (strneq): Likewise.
 414
 415 2021-04-01  Alan Modra  <amodra@gmail.com>
 416
 417         PR 27675
 418         * ppc-opc.c (powerpc_opcodes): Add mfummcr2 and mfmmcr2.
 419
 420 2021-03-31  Alan Modra  <amodra@gmail.com>
 421
 422         * sysdep.h (POISON_BFD_BOOLEAN): Define.
 423         * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h,
 424         * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h,
 425         * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c,
 426         * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c,
 427         * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c,
 428         * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c,
 429         * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c,
 430         * microblaze-dis.h, * micromips-opc.c, * mips-dis.c,
 431         * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c,
 432         * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c,
 433         * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c,
 434         * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c,
 435         * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false,
 436         and TRUE with true throughout.
 437
 438 2021-03-31  Alan Modra  <amodra@gmail.com>
 439
 440         * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h.
 441         * aarch64-dis.h: Likewise.
 442         * aarch64-opc.c: Likewise.
 443         * avr-dis.c: Likewise.
 444         * csky-dis.c: Likewise.
 445         * nds32-asm.c: Likewise.
 446         * nds32-dis.c: Likewise.
 447         * nfp-dis.c: Likewise.
 448         * riscv-dis.c: Likewise.
 449         * s12z-dis.c: Likewise.
 450         * wasm32-dis.c: Likewise.
 451
 452 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 453
 454         * i386-opc.c (cs, ds, ss, es, fs, gs): Delete.
 455         (i386_seg_prefixes): New.
 456         * i386-opc.h (cs, ds, ss, es, fs, gs): Delete.
 457         (i386_seg_prefixes): Declare.
 458
 459 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 460
 461         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Delete.
 462
 463 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 464
 465         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Adjust values.
 466         * i386-reg.tbl (st): Move down.
 467         (st(0)): Delete. Extend comment.
 468         * i386-tbl.h: Re-generate.
 469
 470 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 471
 472         * i386-opc.tbl (movq, movabs): Move next to mov counterparts.
 473         (cmpsd): Move next to cmps.
 474         (movsd): Move next to movs.
 475         (cmpxchg16b): Move to separate section.
 476         (fisttp, fisttpll): Likewise.
 477         (monitor, mwait): Likewise.
 478         * i386-tbl.h: Re-generate.
 479
 480 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 481
 482         * i386-opc.tbl (psadbw): Add <sse2:comm>.
 483         (vpsadbw): Add C.
 484         * i386-tbl.h: Re-generate.
 485
 486 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 487
 488         * i386-opc.tbl (mmx, sse, sse2, sse3, ssse3, sse41, sse42, aes,
 489         pclmul, gfni): New templates. Use them wherever possible. Move
 490         SSE4.1 pextrw into respective section.
 491         * i386-tbl.h: Re-generate.
 492
 493 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 494
 495         * i386-gen.c (output_i386_opcode): Widen type of "opcode". Use
 496         strtoull(). Bump upper loop bound. Widen masks. Sanity check
 497         "length".
 498         * i386-opc.tbl (Prefix_0X66, Prefix_0XF2, Prefix_0XF3): Delete.
 499         Convert all of their uses to representation in opcode.
 500
 501 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 502
 503         * i386-opc.h (struct insn_template): Shrink base_opcode to 16
 504         bits. Shrink extension_opcode to 9 bits. Make it signed. Change
 505         value of None. Shrink operands to 3 bits.
 506
 507 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 508
 509         * i386-gen.c (process_i386_opcode_modifier): New parameter
 510         "space".
 511         (output_i386_opcode): New local variable "space". Adjust
 512         process_i386_opcode_modifier() invocation.
 513         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 514         invocation.
 515         * i386-tbl.h: Re-generate.
 516
 517 2021-03-29  Alan Modra  <amodra@gmail.com>
 518
 519         * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
 520         (fp_qualifier_p, get_data_pattern): Likewise.
 521         (aarch64_get_operand_modifier_from_value): Likewise.
 522         (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
 523         (operand_variant_qualifier_p): Likewise.
 524         (qualifier_value_in_range_constraint_p): Likewise.
 525         (aarch64_get_qualifier_esize): Likewise.
 526         (aarch64_get_qualifier_nelem): Likewise.
 527         (aarch64_get_qualifier_standard_value): Likewise.
 528         (get_lower_bound, get_upper_bound): Likewise.
 529         (aarch64_find_best_match, match_operands_qualifier): Likewise.
 530         (aarch64_print_operand): Likewise.
 531         * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
 532         (operand_need_sign_extension, operand_need_shift_by_two): Likewise.
 533         (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
 534         * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
 535         * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
 536         (print_insn_tic6x): Likewise.
 537
 538 2021-03-29  Alan Modra  <amodra@gmail.com>
 539
 540         * arc-dis.c (extract_operand_value): Correct NULL cast.
 541         * frv-opc.h: Regenerate.
 542
 543 2021-03-26  Jan Beulich  <jbeulich@suse.com>
 544
 545         * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to
 546         MMX form.
 547         * i386-tbl.h: Re-generate.
 548
 549 2021-03-25  Abid Qadeer  <abidh@codesourcery.com>
 550
 551         * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
 552         immediate in br.n instruction.
 553
 554 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 555
 556         * i386-dis.c (XMGatherD, VexGatherD): New.
 557         (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
 558         (print_insn): Check masking for S/G insns.
 559         (OP_E_memory): New local variable check_gather. Extend mandatory
 560         SIB check. Check register conflicts for (EVEX-encoded) gathers.
 561         Extend check for disallowed 16-bit addressing.
 562         (OP_VEX): New local variables modrm_reg and sib_index. Convert
 563         if()s to switch(). Check register conflicts for (VEX-encoded)
 564         gathers. Drop no longer reachable cases.
 565         * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
 566         vgatherdp*.
 567
 568 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 569
 570         * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
 571         zeroing-masking without masking.
 572
 573 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 574
 575         * i386-opc.tbl (invlpgb): Fix multi-operand form.
 576         (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
 577         single-operand forms as deprecated.
 578         * i386-tbl.h: Re-generate.
 579
 580 2021-03-25  Alan Modra  <amodra@gmail.com>
 581
 582         PR 27647
 583         * ppc-opc.c (XLOCB_MASK): Delete.
 584         (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
 585         XLBH_MASK.
 586         (powerpc_opcodes): Accept a BH field on all extended forms of
 587         bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
 588
 589 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 590
 591         * i386-gen.c (output_i386_opcode): Drop processing of
 592         opcode_length. Calculate length from base_opcode. Adjust prefix
 593         encoding determination.
 594         (process_i386_opcodes): Drop output of fake opcode_length.
 595         * i386-opc.h (struct insn_template): Drop opcode_length field.
 596         * i386-opc.tbl: Drop opcode length field from all templates.
 597         * i386-tbl.h: Re-generate.
 598
 599 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 600
 601         * i386-gen.c (process_i386_opcode_modifier): Return void. New
 602         parameter "prefix". Drop local variable "regular_encoding".
 603         Record prefix setting / check for consistency.
 604         (output_i386_opcode): Parse opcode_length and base_opcode
 605         earlier. Derive prefix encoding. Drop no longer applicable
 606         consistency checking. Adjust process_i386_opcode_modifier()
 607         invocation.
 608         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 609         invocation.
 610         * i386-tbl.h: Re-generate.
 611
 612 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 613
 614         * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
 615         check.
 616         * i386-opc.h (Prefix_*): Move #define-s.
 617         * i386-opc.tbl: Move pseudo prefix enumerator values to
 618         extension opcode field. Introduce pseudopfx template.
 619         * i386-tbl.h: Re-generate.
 620
 621 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 622
 623         * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
 624         comment.
 625         * i386-tbl.h: Re-generate.
 626
 627 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 628
 629         * i386-opc.h (struct insn_template): Move cpu_flags field past
 630         opcode_modifier one.
 631         * i386-tbl.h: Re-generate.
 632
 633 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 634
 635         * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
 636         * i386-opc.h (OpcodeSpace): New enumerator.
 637         (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
 638         (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
 639         SPACE_XOP09, SPACE_XOP0A): ... respectively.
 640         (struct i386_opcode_modifier): New field opcodespace. Shrink
 641         opcodeprefix field.
 642         i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
 643         SpaceXOP09, SpaceXOP0A): Define. Use them to replace
 644         OpcodePrefix uses.
 645         * i386-tbl.h: Re-generate.
 646
 647 2021-03-22  Martin Liska  <mliska@suse.cz>
 648
 649         * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
 650         * arc-dis.c (parse_option): Likewise.
 651         * arm-dis.c (parse_arm_disassembler_options): Likewise.
 652         * cris-dis.c (print_with_operands): Likewise.
 653         * h8300-dis.c (bfd_h8_disassemble): Likewise.
 654         * i386-dis.c (print_insn): Likewise.
 655         * ia64-gen.c (fetch_insn_class): Likewise.
 656         (parse_resource_users): Likewise.
 657         (in_iclass): Likewise.
 658         (lookup_specifier): Likewise.
 659         (insert_opcode_dependencies): Likewise.
 660         * mips-dis.c (parse_mips_ase_option): Likewise.
 661         (parse_mips_dis_option): Likewise.
 662         * s390-dis.c (disassemble_init_s390): Likewise.
 663         * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
 664
 665 2021-03-16  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
 666
 667         * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
 668
 669 2021-03-12  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 670
 671         * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
 672         icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
 673
 674 2021-03-12  Alan Modra  <amodra@gmail.com>
 675
 676         * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
 677
 678 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 679
 680         * i386-dis.c (OP_XMM): Re-order checks.
 681
 682 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 683
 684         * i386-dis.c (putop): Drop need_vex check when also checking
 685         vex.evex.
 686         (intel_operand_size, OP_E_memory): Drop vex.evex check when also
 687         checking vex.b.
 688
 689 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 690
 691         * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
 692         checks. Move case label past broadcast check.
 693
 694 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 695
 696         * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
 697         vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
 698         REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
 699         EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
 700         EVEX_W_0F38C7_M_0_L_2): Delete.
 701         (REG_EVEX_0F38C7_M_0_L_2): New.
 702         (intel_operand_size): Handle VEX and EVEX the same for
 703         vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
 704         vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
 705         (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
 706         vex_vsib_q_w_d_mode uses.
 707         * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
 708         0F38A1, and 0F38A3 entries.
 709         * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
 710         entry.
 711         * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
 712         * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
 713         0F38A3 entries.
 714
 715 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 716
 717         * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
 718         REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
 719         MOD_VEX_0FXOP_09_12): Rename to ...
 720         (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
 721         REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
 722         (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
 723         RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
 724         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 725         X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
 726         (reg_table): Adjust comments.
 727         (x86_64_table): Move X86_64_0F24, X86_64_0F26,
 728         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 729         X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
 730         (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
 731         (vex_len_table): Adjust opcode 0A_12 entry.
 732         (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
 733         MOD_C5_32BIT, and MOD_XOP_09_12 entries.
 734         (rm_table): Move hreset entry.
 735
 736 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 737
 738         * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
 739         EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
 740         EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
 741         EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
 742         EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
 743         (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
 744         (get_valid_dis386): Also handle 512-bit vector length when
 745         vectoring into vex_len_table[].
 746         * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
 747         0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
 748         entries.
 749         * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
 750         0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
 751         * i386-dis-evex-prefix.h: Adjust 0F7E entry.
 752         * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
 753         entries.
 754
 755 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 756
 757         * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
 758         Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
 759         EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
 760         * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
 761         entries.
 762         * i386-dis-evex-len.h (evex_len_table): Likewise.
 763         * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
 764
 765 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 766
 767         * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
 768         MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
 769         MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
 770         MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
 771         MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
 772         MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
 773         MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
 774         MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
 775         EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
 776         EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
 777         EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
 778         EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
 779         EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
 780         EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
 781         EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
 782         EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
 783         EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
 784         EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
 785         EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
 786         EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
 787         EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
 788         EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
 789         EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
 790         EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
 791         EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
 792         EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
 793         EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
 794         EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
 795         EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
 796         EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
 797         EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
 798         EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
 799         REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
 800         REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
 801         MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
 802         MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
 803         EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
 804         EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
 805         EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
 806         EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
 807         EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
 808         EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
 809         EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
 810         EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
 811         EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
 812         EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
 813         EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
 814         EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
 815         EVEX_W_0F3A43_L_n): New.
 816         * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
 817         0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
 818         0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
 819         * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
 820         for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
 821         0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
 822         0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
 823         * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
 824         0F385B, 0F38C6, and 0F38C7 entries.
 825         * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
 826         0F38C6 and 0F38C7.
 827         * i386-dis-evex-w.h: No longer link to evex_len_table[] for
 828         opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
 829         0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
 830         evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
 831
 832 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 833
 834         * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
 835         MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
 836         MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
 837         MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
 838         MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
 839         MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
 840         MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
 841         MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
 842         MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
 843         MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
 844         MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
 845         MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
 846         MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
 847         MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
 848         MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
 849         MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
 850         MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
 851         MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
 852         MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
 853         MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
 854         MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
 855         MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
 856         MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
 857         MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
 858         MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
 859         PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
 860         PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
 861         PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
 862         PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
 863         PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
 864         VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
 865         VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
 866         VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
 867         VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
 868         VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
 869         VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
 870         VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
 871         VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
 872         VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
 873         VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
 874         VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
 875         VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
 876         VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
 877         VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
 878         VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
 879         VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
 880         VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
 881         VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
 882         VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
 883         VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
 884         VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
 885         VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
 886         VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
 887         VEX_W_0F99_P_2_LEN_0): Delete.
 888         MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
 889         MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
 890         MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
 891         MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
 892         MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
 893         PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
 894         PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
 895         PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
 896         PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
 897         PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
 898         PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
 899         PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
 900         PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
 901         PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
 902         PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
 903         PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
 904         PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
 905         PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
 906         PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
 907         VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
 908         VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
 909         VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
 910         VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
 911         VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
 912         VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
 913         VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
 914         VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
 915         (prefix_table): No longer link to vex_len_table[] for opcodes
 916         0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
 917         0F92, 0F93, 0F98, and 0F99.
 918         (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
 919         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 920         0F98, and 0F99.
 921         (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
 922         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 923         0F98, and 0F99.
 924         (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
 925         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 926         0F98, and 0F99.
 927         (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
 928         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 929         0F98, and 0F99.
 930
 931 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 932
 933         * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
 934         Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
 935         REG_VEX_0F73_M_0 respectively.
 936         (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
 937         MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
 938         MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
 939         MOD_VEX_0F73_REG_7): Delete.
 940         (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
 941         (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
 942         PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
 943         PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
 944         PREFIX_VEX_0F3AF0_L_0 respectively.
 945         (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
 946         VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
 947         VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
 948         VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
 949         (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
 950         VEX_LEN_0F38F7): New.
 951         (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
 952         (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
 953         0F72, and 0F73. No longer link to vex_len_table[] for opcode
 954         0F38F3.
 955         (prefix_table): No longer link to vex_len_table[] for opcodes
 956         0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 957         (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
 958         0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
 959         0F38F6, 0F38F7, and 0F3AF0.
 960         (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
 961         prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 962         (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
 963         0F73.
 964
 965 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 966
 967         * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
 968         REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
 969         (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
 970         MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
 971         MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
 972         (MOD_0F71, MOD_0F72, MOD_0F73): New.
 973         (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
 974         73.
 975         (reg_table): No longer link to mod_table[] for opcodes 0F71,
 976         0F72, and 0F73.
 977         (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
 978         0F73.
 979
 980 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 981
 982         * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
 983         MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
 984         (reg_table): Don't link to mod_table[] where not needed. Add
 985         PREFIX_IGNORED to nop entries.
 986         (prefix_table): Replace PREFIX_OPCODE in nop entries.
 987         (mod_table): Add nop entries next to prefetch ones. Drop
 988         MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
 989         MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
 990         (rm_table): Add PREFIX_IGNORED to nop entries. Drop
 991         PREFIX_OPCODE from endbr* entries.
 992         (get_valid_dis386): Also consider entry's name when zapping
 993         vindex.
 994         (print_insn): Handle PREFIX_IGNORED.
 995
 996 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 997
 998         * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
 999         IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
1000         element.
1001         * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
1002         HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
1003         (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
1004         PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
1005         (struct i386_opcode_modifier): Delete notrackprefixok,
1006         islockable, hleprefixok, and repprefixok fields. Add prefixok
1007         field.
1008         * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
1009         HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
1010         (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
1011         not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
1012         Replace HLEPrefixOk.
1013         * opcodes/i386-tbl.h: Re-generate.
1014
1015 2021-03-09  Jan Beulich  <jbeulich@suse.com>
1016
1017         * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
1018         * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
1019         64-bit form.
1020         * opcodes/i386-tbl.h: Re-generate.
1021
1022 2021-03-03  Jan Beulich  <jbeulich@suse.com>
1023
1024         * i386-gen.c (output_i386_opcode): Don't get operand count. Look
1025         for {} instead of {0}. Don't look for '0'.
1026         * i386-opc.tbl: Drop operand count field. Drop redundant operand
1027         size specifiers.
1028
1029 2021-02-19  Nelson Chu  <nelson.chu@sifive.com>
1030
1031         PR 27158
1032         * riscv-dis.c (print_insn_args): Updated encoding macros.
1033         * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
1034         (match_c_addi16sp): Updated encoding macros.
1035         (match_c_lui): Likewise.
1036         (match_c_lui_with_hint): Likewise.
1037         (match_c_addi4spn): Likewise.
1038         (match_c_slli): Likewise.
1039         (match_slli_as_c_slli): Likewise.
1040         (match_c_slli64): Likewise.
1041         (match_srxi_as_c_srxi): Likewise.
1042         (riscv_insn_types): Added .insn css/cl/cs.
1043
1044 2021-02-18  Nelson Chu  <nelson.chu@sifive.com>
1045
1046         * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
1047         (default_priv_spec): Updated type to riscv_spec_class.
1048         (parse_riscv_dis_option): Updated.
1049         * riscv-opc.c: Moved stuff and make the file tidy.
1050
1051 2021-02-17  Alan Modra  <amodra@gmail.com>
1052
1053         * wasm32-dis.c: Include limits.h.
1054         (CHAR_BIT): Provide backup define.
1055         (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
1056         Correct signed overflow checking.
1057
1058 2021-02-16  Jan Beulich  <jbeulich@suse.com>
1059
1060         * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
1061         * i386-tbl.h: Re-generate.
1062
1063 2021-02-16  Jan Beulich  <jbeulich@suse.com>
1064
1065         * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
1066         Oword.
1067         * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
1068
1069 2021-02-15  Andreas Krebbel  <krebbel@linux.ibm.com>
1070
1071         * s390-mkopc.c (main): Accept arch14 as cpu string.
1072         * s390-opc.txt: Add new arch14 instructions.
1073
1074 2021-02-04  Nick Alcock  <nick.alcock@oracle.com>
1075
1076         * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
1077         favour of LIBINTL.
1078         * configure: Regenerated.
1079
1080 2021-02-08  Mike Frysinger  <vapier@gentoo.org>
1081
1082         * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
1083         * tic54x-opc.c (regs): Rename to ...
1084         (tic54x_regs): ... this.
1085         (mmregs): Rename to ...
1086         (tic54x_mmregs): ... this.
1087         (condition_codes): Rename to ...
1088         (tic54x_condition_codes): ... this.
1089         (cc2_codes): Rename to ...
1090         (tic54x_cc2_codes): ... this.
1091         (cc3_codes): Rename to ...
1092         (tic54x_cc3_codes): ... this.
1093         (status_bits): Rename to ...
1094         (tic54x_status_bits): ... this.
1095         (misc_symbols): Rename to ...
1096         (tic54x_misc_symbols): ... this.
1097
1098 2021-02-04  Nelson Chu  <nelson.chu@sifive.com>
1099
1100         * riscv-opc.c (MASK_RVB_IMM): Removed.
1101         (riscv_opcodes): Removed zb* instructions.
1102         (riscv_ext_version_table): Removed versions for zb*.
1103
1104 2021-01-26  Alan Modra  <amodra@gmail.com>
1105
1106         * i386-gen.c (parse_template): Ensure entire template_instance
1107         is initialised.
1108
1109 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
1110
1111         * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
1112         (riscv_fpr_names_abi): Likewise.
1113         (riscv_opcodes): Likewise.
1114         (riscv_insn_types): Likewise.
1115
1116 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
1117
1118         * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
1119
1120 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
1121
1122         * riscv-dis.c: Comments tidy and improvement.
1123         * riscv-opc.c: Likewise.
1124
1125 2021-01-13  Alan Modra  <amodra@gmail.com>
1126
1127         * Makefile.in: Regenerate.
1128
1129 2021-01-12  H.J. Lu  <hongjiu.lu@intel.com>
1130
1131         PR binutils/26792
1132         * configure.ac: Use GNU_MAKE_JOBSERVER.
1133         * aclocal.m4: Regenerated.
1134         * configure: Likewise.
1135
1136 2021-01-12  Nick Clifton  <nickc@redhat.com>
1137
1138         * po/sr.po: Updated Serbian translation.
1139
1140 2021-01-11  H.J. Lu  <hongjiu.lu@intel.com>
1141
1142         PR ld/27173
1143         * configure: Regenerated.
1144
1145 2021-01-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
1146
1147         * aarch64-asm-2.c: Regenerate.
1148         * aarch64-dis-2.c: Likewise.
1149         * aarch64-opc-2.c: Likewise.
1150         * aarch64-opc.c (aarch64_print_operand):
1151         Delete handling of AARCH64_OPND_CSRE_CSR.
1152         * aarch64-tbl.h (aarch64_feature_csre): Delete.
1153         (CSRE): Likewise.
1154         (_CSRE_INSN): Likewise.
1155         (aarch64_opcode_table): Delete csr.
1156
1157 2021-01-11  Nick Clifton  <nickc@redhat.com>
1158
1159         * po/de.po: Updated German translation.
1160         * po/fr.po: Updated French translation.
1161         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1162         * po/sv.po: Updated Swedish translation.
1163         * po/uk.po: Updated Ukranian translation.
1164
1165 2021-01-09  H.J. Lu  <hongjiu.lu@intel.com>
1166
1167         * configure: Regenerated.
1168
1169 2021-01-09  Nick Clifton  <nickc@redhat.com>
1170
1171         * configure: Regenerate.
1172         * po/opcodes.pot: Regenerate.
1173
1174 2021-01-09  Nick Clifton  <nickc@redhat.com>
1175
1176         * 2.36 release branch crated.
1177
1178 2021-01-08  Peter Bergner  <bergner@linux.ibm.com>
1179
1180         * ppc-opc.c (insert_dw, (extract_dw): New functions.
1181         (DW, (XRC_MASK): Define.
1182         (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
1183
1184 2021-01-09  Alan Modra  <amodra@gmail.com>
1185
1186         * configure: Regenerate.
1187
1188 2021-01-08  Nick Clifton  <nickc@redhat.com>
1189
1190         * po/sv.po: Updated Swedish translation.
1191
1192 2021-01-08  Nick Clifton  <nickc@redhat.com>
1193
1194         PR 27129
1195         * aarch64-dis.c (determine_disassembling_preference): Move call to
1196         aarch64_match_operands_constraint outside of the assertion.
1197         * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
1198         Replace with a return of FALSE.
1199
1200         PR 27139
1201         * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
1202         core system register.
1203
1204 2021-01-07  Samuel Thibault  <samuel.thibault@gnu.org>
1205
1206         * configure: Regenerate.
1207
1208 2021-01-07  Nick Clifton  <nickc@redhat.com>
1209
1210         * po/fr.po: Updated French translation.
1211
1212 2021-01-07  Fredrik Noring  <noring@nocrew.org>
1213
1214         * m68k-opc.c (chkl): Change minimum architecture requirement to
1215         m68020.
1216
1217 2021-01-07  Philipp Tomsich  <prt@gnu.org>
1218
1219         * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
1220
1221 2021-01-07  Claire Xenia Wolf  <claire@symbioticeda.com>
1222             Jim Wilson  <jimw@sifive.com>
1223             Andrew Waterman  <andrew@sifive.com>
1224             Maxim Blinov  <maxim.blinov@embecosm.com>
1225             Kito Cheng  <kito.cheng@sifive.com>
1226             Nelson Chu  <nelson.chu@sifive.com>
1227
1228         * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
1229         (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
1230
1231 2021-01-01  Alan Modra  <amodra@gmail.com>
1232
1233         Update year range in copyright notice of all files.
1234
1235 For older changes see ChangeLog-2020
1236 \f
1237 Copyright (C) 2021-2022 Free Software Foundation, Inc.
1238
1239 Copying and distribution of this file, with or without modification,
1240 are permitted in any medium without royalty provided the copyright
1241 notice and this notice are preserved.
1242
1243 Local Variables:
1244 mode: change-log
1245 left-margin: 8
1246 fill-column: 74
1247 version-control: never
1248 End: