opcodes/ChangeLog

   1 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
   2             Michael Collison <michael.collison@arm.com>
   3
   4         * arm-dis.c (thumb32_opcodes): Add new instructions.
   5         (enum mve_instructions): Likewise.
   6         (is_mve_encoding_conflict): Handle new instructions.
   7         (is_mve_undefined): Likewise.
   8         (is_mve_unpredictable): Likewise.
   9         (print_mve_size): Likewise.
  10
  11 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  12             Michael Collison <michael.collison@arm.com>
  13
  14         * arm-dis.c (thumb32_opcodes): Add new instructions.
  15         (enum mve_instructions): Likewise.
  16         (is_mve_encoding_conflict): Handle new instructions.
  17         (is_mve_undefined): Likewise.
  18         (is_mve_unpredictable): Likewise.
  19         (print_mve_size): Likewise.
  20         (print_insn_mve): Likewise.
  21
  22 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  23             Michael Collison <michael.collison@arm.com>
  24
  25         * arm-dis.c (thumb32_opcodes): Add new instructions.
  26         (print_insn_thumb32): Handle new instructions.
  27
  28 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  29             Michael Collison <michael.collison@arm.com>
  30
  31         * arm-dis.c (enum mve_instructions): Add new instructions.
  32         (enum mve_undefined): Add new reasons.
  33         (is_mve_encoding_conflict): Handle new instructions.
  34         (is_mve_undefined): Likewise.
  35         (is_mve_unpredictable): Likewise.
  36         (print_mve_undefined): Likewise.
  37         (print_mve_size): Likewise.
  38         (print_mve_shift_n): Likewise.
  39         (print_insn_mve): Likewise.
  40
  41 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  42             Michael Collison <michael.collison@arm.com>
  43
  44         * arm-dis.c (enum mve_instructions): Add new instructions.
  45         (is_mve_encoding_conflict): Handle new instructions.
  46         (is_mve_unpredictable): Likewise.
  47         (print_mve_rotate): Likewise.
  48         (print_mve_size): Likewise.
  49         (print_insn_mve): Likewise.
  50
  51 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  52             Michael Collison <michael.collison@arm.com>
  53
  54         * arm-dis.c (enum mve_instructions): Add new instructions.
  55         (is_mve_encoding_conflict): Handle new instructions.
  56         (is_mve_unpredictable): Likewise.
  57         (print_mve_size): Likewise.
  58         (print_insn_mve): Likewise.
  59
  60 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  61             Michael Collison <michael.collison@arm.com>
  62
  63         * arm-dis.c (enum mve_instructions): Add new instructions.
  64         (enum mve_undefined): Add new reasons.
  65         (is_mve_encoding_conflict): Handle new instructions.
  66         (is_mve_undefined): Likewise.
  67         (is_mve_unpredictable): Likewise.
  68         (print_mve_undefined): Likewise.
  69         (print_mve_size): Likewise.
  70         (print_insn_mve): Likewise.
  71
  72 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  73             Michael Collison <michael.collison@arm.com>
  74
  75         * arm-dis.c (enum mve_instructions): Add new instructions.
  76         (is_mve_encoding_conflict): Handle new instructions.
  77         (is_mve_undefined): Likewise.
  78         (is_mve_unpredictable): Likewise.
  79         (print_mve_size): Likewise.
  80         (print_insn_mve): Likewise.
  81
  82 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  83             Michael Collison <michael.collison@arm.com>
  84
  85         * arm-dis.c (enum mve_instructions): Add new instructions.
  86         (enum mve_unpredictable): Add new reasons.
  87         (enum mve_undefined): Likewise.
  88         (is_mve_okay_in_it): Handle new isntructions.
  89         (is_mve_encoding_conflict): Likewise.
  90         (is_mve_undefined): Likewise.
  91         (is_mve_unpredictable): Likewise.
  92         (print_mve_vmov_index): Likewise.
  93         (print_simd_imm8): Likewise.
  94         (print_mve_undefined): Likewise.
  95         (print_mve_unpredictable): Likewise.
  96         (print_mve_size): Likewise.
  97         (print_insn_mve): Likewise.
  98
  99 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 100             Michael Collison <michael.collison@arm.com>
 101
 102         * arm-dis.c (enum mve_instructions): Add new instructions.
 103         (enum mve_unpredictable): Add new reasons.
 104         (enum mve_undefined): Likewise.
 105         (is_mve_encoding_conflict): Handle new instructions.
 106         (is_mve_undefined): Likewise.
 107         (is_mve_unpredictable): Likewise.
 108         (print_mve_undefined): Likewise.
 109         (print_mve_unpredictable): Likewise.
 110         (print_mve_rounding_mode): Likewise.
 111         (print_mve_vcvt_size): Likewise.
 112         (print_mve_size): Likewise.
 113         (print_insn_mve): Likewise.
 114
 115 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 116             Michael Collison <michael.collison@arm.com>
 117
 118         * arm-dis.c (enum mve_instructions): Add new instructions.
 119         (enum mve_unpredictable): Add new reasons.
 120         (enum mve_undefined): Likewise.
 121         (is_mve_undefined): Handle new instructions.
 122         (is_mve_unpredictable): Likewise.
 123         (print_mve_undefined): Likewise.
 124         (print_mve_unpredictable): Likewise.
 125         (print_mve_size): Likewise.
 126         (print_insn_mve): Likewise.
 127
 128 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 129             Michael Collison <michael.collison@arm.com>
 130
 131         * arm-dis.c (enum mve_instructions): Add new instructions.
 132         (enum mve_undefined): Add new reasons.
 133         (insns): Add new instructions.
 134         (is_mve_encoding_conflict):
 135         (print_mve_vld_str_addr): New print function.
 136         (is_mve_undefined): Handle new instructions.
 137         (is_mve_unpredictable): Likewise.
 138         (print_mve_undefined): Likewise.
 139         (print_mve_size): Likewise.
 140         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
 141         (print_insn_mve):  Handle new operands.
 142
 143 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 144             Michael Collison <michael.collison@arm.com>
 145
 146         * arm-dis.c (enum mve_instructions): Add new instructions.
 147         (enum mve_unpredictable): Add new reasons.
 148         (is_mve_encoding_conflict): Handle new instructions.
 149         (is_mve_unpredictable): Likewise.
 150         (mve_opcodes): Add new instructions.
 151         (print_mve_unpredictable): Handle new reasons.
 152         (print_mve_register_blocks): New print function.
 153         (print_mve_size): Handle new instructions.
 154         (print_insn_mve): Likewise.
 155
 156 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 157             Michael Collison <michael.collison@arm.com>
 158
 159         * arm-dis.c (enum mve_instructions): Add new instructions.
 160         (enum mve_unpredictable): Add new reasons.
 161         (enum mve_undefined): Likewise.
 162         (is_mve_encoding_conflict): Handle new instructions.
 163         (is_mve_undefined): Likewise.
 164         (is_mve_unpredictable): Likewise.
 165         (coprocessor_opcodes): Move NEON VDUP from here...
 166         (neon_opcodes): ... to here.
 167         (mve_opcodes): Add new instructions.
 168         (print_mve_undefined):  Handle new reasons.
 169         (print_mve_unpredictable): Likewise.
 170         (print_mve_size): Handle new instructions.
 171         (print_insn_neon): Handle vdup.
 172         (print_insn_mve): Handle new operands.
 173
 174 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 175             Michael Collison <michael.collison@arm.com>
 176
 177         * arm-dis.c (enum mve_instructions): Add new instructions.
 178         (enum mve_unpredictable): Add new values.
 179         (mve_opcodes): Add new instructions.
 180         (vec_condnames): New array with vector conditions.
 181         (mve_predicatenames): New array with predicate suffixes.
 182         (mve_vec_sizename): New array with vector sizes.
 183         (enum vpt_pred_state): New enum with vector predication states.
 184         (struct vpt_block): New struct type for vpt blocks.
 185         (vpt_block_state): Global struct to keep track of state.
 186         (mve_extract_pred_mask): New helper function.
 187         (num_instructions_vpt_block): Likewise.
 188         (mark_outside_vpt_block): Likewise.
 189         (mark_inside_vpt_block): Likewise.
 190         (invert_next_predicate_state): Likewise.
 191         (update_next_predicate_state): Likewise.
 192         (update_vpt_block_state): Likewise.
 193         (is_vpt_instruction): Likewise.
 194         (is_mve_encoding_conflict): Add entries for new instructions.
 195         (is_mve_unpredictable): Likewise.
 196         (print_mve_unpredictable): Handle new cases.
 197         (print_instruction_predicate): Likewise.
 198         (print_mve_size): New function.
 199         (print_vec_condition): New function.
 200         (print_insn_mve): Handle vpt blocks and new print operands.
 201
 202 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 203
 204         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
 205         8, 14 and 15 for Armv8.1-M Mainline.
 206
 207 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 208             Michael Collison <michael.collison@arm.com>
 209
 210         * arm-dis.c (enum mve_instructions): New enum.
 211         (enum mve_unpredictable): Likewise.
 212         (enum mve_undefined): Likewise.
 213         (struct mopcode32): New struct.
 214         (is_mve_okay_in_it): New function.
 215         (is_mve_architecture): Likewise.
 216         (arm_decode_field): Likewise.
 217         (arm_decode_field_multiple): Likewise.
 218         (is_mve_encoding_conflict): Likewise.
 219         (is_mve_undefined): Likewise.
 220         (is_mve_unpredictable): Likewise.
 221         (print_mve_undefined): Likewise.
 222         (print_mve_unpredictable): Likewise.
 223         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
 224         (print_insn_mve): New function.
 225         (print_insn_thumb32): Handle MVE architecture.
 226         (select_arm_features): Force thumb for Armv8.1-m Mainline.
 227
 228 2019-05-10  Nick Clifton  <nickc@redhat.com>
 229
 230         PR 24538
 231         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
 232         end of the table prematurely.
 233
 234 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 235
 236         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
 237         macros for R6.
 238
 239 2019-05-11  Alan Modra  <amodra@gmail.com>
 240
 241         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
 242         when -Mraw is in effect.
 243
 244 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 245
 246         * aarch64-dis-2.c: Regenerate.
 247         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
 248         (OP_SVE_BBB): New variant set.
 249         (OP_SVE_DDDD): New variant set.
 250         (OP_SVE_HHH): New variant set.
 251         (OP_SVE_HHHU): New variant set.
 252         (OP_SVE_SSS): New variant set.
 253         (OP_SVE_SSSU): New variant set.
 254         (OP_SVE_SHH): New variant set.
 255         (OP_SVE_SBBU): New variant set.
 256         (OP_SVE_DSS): New variant set.
 257         (OP_SVE_DHHU): New variant set.
 258         (OP_SVE_VMV_HSD_BHS): New variant set.
 259         (OP_SVE_VVU_HSD_BHS): New variant set.
 260         (OP_SVE_VVVU_SD_BH): New variant set.
 261         (OP_SVE_VVVU_BHSD): New variant set.
 262         (OP_SVE_VVV_QHD_DBS): New variant set.
 263         (OP_SVE_VVV_HSD_BHS): New variant set.
 264         (OP_SVE_VVV_HSD_BHS2): New variant set.
 265         (OP_SVE_VVV_BHS_HSD): New variant set.
 266         (OP_SVE_VV_BHS_HSD): New variant set.
 267         (OP_SVE_VVV_SD): New variant set.
 268         (OP_SVE_VVU_BHS_HSD): New variant set.
 269         (OP_SVE_VZVV_SD): New variant set.
 270         (OP_SVE_VZVV_BH): New variant set.
 271         (OP_SVE_VZV_SD): New variant set.
 272         (aarch64_opcode_table): Add sve2 instructions.
 273
 274 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 275
 276         * aarch64-asm-2.c: Regenerated.
 277         * aarch64-dis-2.c: Regenerated.
 278         * aarch64-opc-2.c: Regenerated.
 279         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 280         for SVE_SHLIMM_UNPRED_22.
 281         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
 282         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
 283         operand.
 284
 285 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 286
 287         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 288         sve_size_tsz_bhs iclass encode.
 289         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 290         sve_size_tsz_bhs iclass decode.
 291
 292 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 293
 294         * aarch64-asm-2.c: Regenerated.
 295         * aarch64-dis-2.c: Regenerated.
 296         * aarch64-opc-2.c: Regenerated.
 297         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 298         for SVE_Zm4_11_INDEX.
 299         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
 300         (fields): Handle SVE_i2h field.
 301         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
 302         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
 303
 304 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 305
 306         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 307         sve_shift_tsz_bhsd iclass encode.
 308         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 309         sve_shift_tsz_bhsd iclass decode.
 310
 311 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 312
 313         * aarch64-asm-2.c: Regenerated.
 314         * aarch64-dis-2.c: Regenerated.
 315         * aarch64-opc-2.c: Regenerated.
 316         * aarch64-asm.c (aarch64_ins_sve_shrimm):
 317         (aarch64_encode_variant_using_iclass): Handle
 318         sve_shift_tsz_hsd iclass encode.
 319         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 320         sve_shift_tsz_hsd iclass decode.
 321         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 322         for SVE_SHRIMM_UNPRED_22.
 323         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
 324         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
 325         operand.
 326
 327 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 328
 329         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 330         sve_size_013 iclass encode.
 331         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 332         sve_size_013 iclass decode.
 333
 334 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 335
 336         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 337         sve_size_bh iclass encode.
 338         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 339         sve_size_bh iclass decode.
 340
 341 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 342
 343         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 344         sve_size_sd2 iclass encode.
 345         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 346         sve_size_sd2 iclass decode.
 347         * aarch64-opc.c (fields): Handle SVE_sz2 field.
 348         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
 349
 350 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 351
 352         * aarch64-asm-2.c: Regenerated.
 353         * aarch64-dis-2.c: Regenerated.
 354         * aarch64-opc-2.c: Regenerated.
 355         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 356         for SVE_ADDR_ZX.
 357         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
 358         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
 359
 360 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 361
 362         * aarch64-asm-2.c: Regenerated.
 363         * aarch64-dis-2.c: Regenerated.
 364         * aarch64-opc-2.c: Regenerated.
 365         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 366         for SVE_Zm3_11_INDEX.
 367         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
 368         (fields): Handle SVE_i3l and SVE_i3h2 fields.
 369         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
 370         fields.
 371         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
 372
 373 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 374
 375         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 376         sve_size_hsd2 iclass encode.
 377         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 378         sve_size_hsd2 iclass decode.
 379         * aarch64-opc.c (fields): Handle SVE_size field.
 380         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
 381
 382 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 383
 384         * aarch64-asm-2.c: Regenerated.
 385         * aarch64-dis-2.c: Regenerated.
 386         * aarch64-opc-2.c: Regenerated.
 387         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 388         for SVE_IMM_ROT3.
 389         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
 390         (fields): Handle SVE_rot3 field.
 391         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
 392         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
 393
 394 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 395
 396         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
 397         instructions.
 398
 399 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 400
 401         * aarch64-tbl.h
 402         (aarch64_feature_sve2, aarch64_feature_sve2aes,
 403         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
 404         aarch64_feature_sve2bitperm): New feature sets.
 405         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
 406         for feature set addresses.
 407         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
 408         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
 409
 410 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
 411             Faraz Shahbazker  <fshahbazker@wavecomp.com>
 412
 413         * mips-dis.c (mips_calculate_combination_ases): Add ISA
 414         argument and set ASE_EVA_R6 appropriately.
 415         (set_default_mips_dis_options): Pass ISA to above.
 416         (parse_mips_dis_option): Likewise.
 417         * mips-opc.c (EVAR6): New macro.
 418         (mips_builtin_opcodes): Add llwpe, scwpe.
 419
 420 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
 421
 422         * aarch64-asm-2.c: Regenerated.
 423         * aarch64-dis-2.c: Regenerated.
 424         * aarch64-opc-2.c: Regenerated.
 425         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
 426         AARCH64_OPND_TME_UIMM16.
 427         (aarch64_print_operand): Likewise.
 428         * aarch64-tbl.h (QL_IMM_NIL): New.
 429         (TME): New.
 430         (_TME_INSN): New.
 431         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
 432
 433 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
 434
 435         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
 436
 437 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
 438             Faraz Shahbazker  <fshahbazker@wavecomp.com>
 439
 440         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
 441
 442 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
 443
 444         * s12z-opc.h: Add extern "C" bracketing to help
 445         users who wish to use this interface in c++ code.
 446
 447 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
 448
 449         * s12z-opc.c (bm_decode): Handle bit map operations with the
 450         "reserved0" mode.
 451
 452 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 453
 454         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
 455         specifier.  Add entries for VLDR and VSTR of system registers.
 456         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
 457         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
 458         of %J and %K format specifier.
 459
 460 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 461
 462         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
 463         Add new entries for VSCCLRM instruction.
 464         (print_insn_coprocessor): Handle new %C format control code.
 465
 466 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 467
 468         * arm-dis.c (enum isa): New enum.
 469         (struct sopcode32): New structure.
 470         (coprocessor_opcodes): change type of entries to struct sopcode32 and
 471         set isa field of all current entries to ANY.
 472         (print_insn_coprocessor): Change type of insn to struct sopcode32.
 473         Only match an entry if its isa field allows the current mode.
 474
 475 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 476
 477         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
 478         CLRM.
 479         (print_insn_thumb32): Add logic to print %n CLRM register list.
 480
 481 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 482
 483         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
 484         and %Q patterns.
 485
 486 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 487
 488         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
 489         (print_insn_thumb32): Edit the switch case for %Z.
 490
 491 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 492
 493         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
 494
 495 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 496
 497         * arm-dis.c (thumb32_opcodes): New instruction bfl.
 498
 499 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 500
 501         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
 502
 503 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 504
 505         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
 506         Arm register with r13 and r15 unpredictable.
 507         (thumb32_opcodes): New instructions for bfx and bflx.
 508
 509 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 510
 511         * arm-dis.c (thumb32_opcodes): New instructions for bf.
 512
 513 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 514
 515         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
 516
 517 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 518
 519         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
 520
 521 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 522
 523         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
 524
 525 2019-04-12  John Darrington <john@darrington.wattle.id.au>
 526
 527         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
 528         "optr". ("operator" is a reserved word in c++).
 529
 530 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
 531
 532         * aarch64-opc.c (aarch64_print_operand): Add case for
 533         AARCH64_OPND_Rt_SP.
 534         (verify_constraints): Likewise.
 535         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
 536         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
 537         to accept Rt|SP as first operand.
 538         (AARCH64_OPERANDS): Add new Rt_SP.
 539         * aarch64-asm-2.c: Regenerated.
 540         * aarch64-dis-2.c: Regenerated.
 541         * aarch64-opc-2.c: Regenerated.
 542
 543 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
 544
 545         * aarch64-asm-2.c: Regenerated.
 546         * aarch64-dis-2.c: Likewise.
 547         * aarch64-opc-2.c: Likewise.
 548         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
 549
 550 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
 551
 552         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
 553
 554 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
 555
 556         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
 557         * i386-init.h: Regenerated.
 558
 559 2019-04-07  Alan Modra  <amodra@gmail.com>
 560
 561         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
 562         op_separator to control printing of spaces, comma and parens
 563         rather than need_comma, need_paren and spaces vars.
 564
 565 2019-04-07  Alan Modra  <amodra@gmail.com>
 566
 567         PR 24421
 568         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
 569         (print_insn_neon, print_insn_arm): Likewise.
 570
 571 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
 572
 573         * i386-dis-evex.h (evex_table): Updated to support BF16
 574         instructions.
 575         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
 576         and EVEX_W_0F3872_P_3.
 577         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
 578         (cpu_flags): Add bitfield for CpuAVX512_BF16.
 579         * i386-opc.h (enum): Add CpuAVX512_BF16.
 580         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
 581         * i386-opc.tbl: Add AVX512 BF16 instructions.
 582         * i386-init.h: Regenerated.
 583         * i386-tbl.h: Likewise.
 584
 585 2019-04-05  Alan Modra  <amodra@gmail.com>
 586
 587         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
 588         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
 589         to favour printing of "-" branch hint when using the "y" bit.
 590         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
 591
 592 2019-04-05  Alan Modra  <amodra@gmail.com>
 593
 594         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
 595         opcode until first operand is output.
 596
 597 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
 598
 599         PR gas/24349
 600         * ppc-opc.c (valid_bo_pre_v2): Add comments.
 601         (valid_bo_post_v2): Add support for 'at' branch hints.
 602         (insert_bo): Only error on branch on ctr.
 603         (get_bo_hint_mask): New function.
 604         (insert_boe): Add new 'branch_taken' formal argument.  Add support
 605         for inserting 'at' branch hints.
 606         (extract_boe): Add new 'branch_taken' formal argument.  Add support
 607         for extracting 'at' branch hints.
 608         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
 609         (BOE): Delete operand.
 610         (BOM, BOP): New operands.
 611         (RM): Update value.
 612         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
 613         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
 614         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
 615         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
 616         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
 617         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
 618         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
 619         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
 620         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
 621         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
 622         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
 623         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
 624         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
 625         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
 626         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
 627         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
 628         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
 629         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
 630         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
 631         bttarl+>: New extended mnemonics.
 632
 633 2019-03-28  Alan Modra  <amodra@gmail.com>
 634
 635         PR 24390
 636         * ppc-opc.c (BTF): Define.
 637         (powerpc_opcodes): Use for mtfsb*.
 638         * ppc-dis.c (print_insn_powerpc): Print fields with both
 639         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
 640
 641 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 642
 643         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
 644         (mapping_symbol_for_insn): Implement new algorithm.
 645         (print_insn): Remove duplicate code.
 646
 647 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 648
 649         * aarch64-dis.c (print_insn_aarch64):
 650         Implement override.
 651
 652 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 653
 654         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
 655         order.
 656
 657 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 658
 659         * aarch64-dis.c (last_stop_offset): New.
 660         (print_insn_aarch64): Use stop_offset.
 661
 662 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
 663
 664         PR gas/24359
 665         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
 666         CPU_ANY_AVX2_FLAGS.
 667         * i386-init.h: Regenerated.
 668
 669 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
 670
 671         PR gas/24348
 672         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
 673         vmovdqu16, vmovdqu32 and vmovdqu64.
 674         * i386-tbl.h: Regenerated.
 675
 676 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
 677
 678         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
 679         from vstrszb, vstrszh, and vstrszf.
 680
 681 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
 682
 683         * s390-opc.txt: Add instruction descriptions.
 684
 685 2019-02-08  Jim Wilson  <jimw@sifive.com>
 686
 687         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
 688         <bne>: Likewise.
 689
 690 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
 691
 692         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
 693
 694 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
 695
 696         PR binutils/23212
 697         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
 698         * aarch64-opc.c (verify_elem_sd): New.
 699         (fields): Add FLD_sz entr.
 700         * aarch64-tbl.h (_SIMD_INSN): New.
 701         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
 702         fmulx scalar and vector by element isns.
 703
 704 2019-02-07  Nick Clifton  <nickc@redhat.com>
 705
 706         * po/sv.po: Updated Swedish translation.
 707
 708 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
 709
 710         * s390-mkopc.c (main): Accept arch13 as cpu string.
 711         * s390-opc.c: Add new instruction formats and instruction opcode
 712         masks.
 713         * s390-opc.txt: Add new arch13 instructions.
 714
 715 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 716
 717         * aarch64-tbl.h (QL_LDST_AT): Update macro.
 718         (aarch64_opcode): Change encoding for stg, stzg
 719         st2g and st2zg.
 720         * aarch64-asm-2.c: Regenerated.
 721         * aarch64-dis-2.c: Regenerated.
 722         * aarch64-opc-2.c: Regenerated.
 723
 724 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 725
 726         * aarch64-asm-2.c: Regenerated.
 727         * aarch64-dis-2.c: Likewise.
 728         * aarch64-opc-2.c: Likewise.
 729         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
 730
 731 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 732             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
 733
 734         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
 735         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
 736         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
 737         * aarch64-dis.h (ext_addr_simple_2): Likewise.
 738         * aarch64-opc.c (operand_general_constraint_met_p): Remove
 739         case for ldstgv_indexed.
 740         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
 741         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
 742         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
 743         * aarch64-asm-2.c: Regenerated.
 744         * aarch64-dis-2.c: Regenerated.
 745         * aarch64-opc-2.c: Regenerated.
 746
 747 2019-01-23  Nick Clifton  <nickc@redhat.com>
 748
 749         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 750
 751 2019-01-21  Nick Clifton  <nickc@redhat.com>
 752
 753         * po/de.po: Updated German translation.
 754         * po/uk.po: Updated Ukranian translation.
 755
 756 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
 757         * mips-dis.c (mips_arch_choices): Fix typo in
 758         gs464, gs464e and gs264e descriptors.
 759
 760 2019-01-19  Nick Clifton  <nickc@redhat.com>
 761
 762         * configure: Regenerate.
 763         * po/opcodes.pot: Regenerate.
 764
 765 2018-06-24  Nick Clifton  <nickc@redhat.com>
 766
 767         2.32 branch created.
 768
 769 2019-01-09  John Darrington <john@darrington.wattle.id.au>
 770
 771         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
 772         if it is null.
 773         -dis.c (opr_emit_disassembly): Do not omit an index if it is
 774         zero.
 775
 776 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
 777
 778         * configure: Regenerate.
 779
 780 2019-01-07  Alan Modra  <amodra@gmail.com>
 781
 782         * configure: Regenerate.
 783         * po/POTFILES.in: Regenerate.
 784
 785 2019-01-03  John Darrington <john@darrington.wattle.id.au>
 786
 787         * s12z-opc.c: New file.
 788         * s12z-opc.h: New file.
 789         * s12z-dis.c: Removed all code not directly related to display
 790         of instructions.  Used the interface provided by the new files
 791         instead.
 792         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
 793         * Makefile.in: Regenerate.
 794         * configure.ac (bfd_s12z_arch): Correct the dependencies.
 795         * configure: Regenerate.
 796
 797 2019-01-01  Alan Modra  <amodra@gmail.com>
 798
 799         Update year range in copyright notice of all files.
 800
 801 For older changes see ChangeLog-2018
 802 \f
 803 Copyright (C) 2019 Free Software Foundation, Inc.
 804
 805 Copying and distribution of this file, with or without modification,
 806 are permitted in any medium without royalty provided the copyright
 807 notice and this notice are preserved.
 808
 809 Local Variables:
 810 mode: change-log
 811 left-margin: 8
 812 fill-column: 74
 813 version-control: never
 814 End: