opcodes/ChangeLog

   1 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
   2 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
   3
   4         * aarch64-tbl.h (ARMV8_6): New macro.
   5
   6 2019-11-07  Jan Beulich  <jbeulich@suse.com>
   7
   8         * i386-dis.c (prefix_table): Add mcommit.
   9         (rm_table): Add rdpru.
  10         * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
  11         CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
  12         (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
  13         * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
  14         (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
  15         * i386-opc.tbl (mcommit, rdpru): New.
  16         * i386-init.h, i386-tbl.h: Re-generate.
  17
  18 2019-11-07  Jan Beulich  <jbeulich@suse.com>
  19
  20         * i386-dis.c (OP_Mwait): Drop local variable "names", use
  21         "names32" instead.
  22         (OP_Monitor): Drop local variable "op1_names", re-purpose
  23         "names" for it instead, and replace former "names" uses by
  24         "names32" ones.
  25
  26 2019-11-07  Jan Beulich  <jbeulich@suse.com>
  27
  28         PR/gas 25167
  29         * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
  30         operand-less forms.
  31         * opcodes/i386-tbl.h: Re-generate.
  32
  33 2019-11-05  Jan Beulich  <jbeulich@suse.com>
  34
  35         * i386-dis.c (OP_Mwaitx): Delete.
  36         (prefix_table): Use OP_Mwait for mwaitx entry.
  37         (OP_Mwait): Also handle mwaitx.
  38
  39 2019-11-05  Jan Beulich  <jbeulich@suse.com>
  40
  41         * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
  42         PREFIX_0F01_REG_7_MOD_3_RM_3): New.
  43         (prefix_table): Add respective entries.
  44         (rm_table): Link to those entries.
  45
  46 2019-11-05  Jan Beulich  <jbeulich@suse.com>
  47
  48         * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
  49         (REG_0F1C_P_0_MOD_0): ... this.
  50         (REG_0F1E_MOD_3): Rename to ...
  51         (REG_0F1E_P_1_MOD_3): ... this.
  52         (RM_0F01_REG_5): Rename to ...
  53         (RM_0F01_REG_5_MOD_3): ... this.
  54         (RM_0F01_REG_7): Rename to ...
  55         (RM_0F01_REG_7_MOD_3): ... this.
  56         (RM_0F1E_MOD_3_REG_7): Rename to ...
  57         (RM_0F1E_P_1_MOD_3_REG_7): ... this.
  58         (RM_0FAE_REG_6): Rename to ...
  59         (RM_0FAE_REG_6_MOD_3_P_0): ... this.
  60         (RM_0FAE_REG_7): Rename to ...
  61         (RM_0FAE_REG_7_MOD_3): ... this.
  62         (PREFIX_MOD_0_0F01_REG_5): Rename to ...
  63         (PREFIX_0F01_REG_5_MOD_0): ... this.
  64         (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
  65         (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
  66         (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
  67         (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
  68         (PREFIX_0FAE_REG_0): Rename to ...
  69         (PREFIX_0FAE_REG_0_MOD_3): ... this.
  70         (PREFIX_0FAE_REG_1): Rename to ...
  71         (PREFIX_0FAE_REG_1_MOD_3): ... this.
  72         (PREFIX_0FAE_REG_2): Rename to ...
  73         (PREFIX_0FAE_REG_2_MOD_3): ... this.
  74         (PREFIX_0FAE_REG_3): Rename to ...
  75         (PREFIX_0FAE_REG_3_MOD_3): ... this.
  76         (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
  77         (PREFIX_0FAE_REG_4_MOD_0): ... this.
  78         (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
  79         (PREFIX_0FAE_REG_4_MOD_3): ... this.
  80         (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
  81         (PREFIX_0FAE_REG_5_MOD_0): ... this.
  82         (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
  83         (PREFIX_0FAE_REG_5_MOD_3): ... this.
  84         (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
  85         (PREFIX_0FAE_REG_6_MOD_0): ... this.
  86         (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
  87         (PREFIX_0FAE_REG_6_MOD_3): ... this.
  88         (PREFIX_0FAE_REG_7): Rename to ...
  89         (PREFIX_0FAE_REG_7_MOD_0): ... this.
  90         (PREFIX_MOD_0_0FC3): Rename to ...
  91         (PREFIX_0FC3_MOD_0): ... this.
  92         (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
  93         (PREFIX_0FC7_REG_6_MOD_0): ... this.
  94         (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
  95         (PREFIX_0FC7_REG_6_MOD_3): ... this.
  96         (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
  97         (PREFIX_0FC7_REG_7_MOD_3): ... this.
  98         (reg_table, prefix_table, mod_table, rm_table): Adjust
  99         accordingly.
 100
 101 2019-11-04  Nick Clifton  <nickc@redhat.com>
 102
 103         * v850-dis.c (get_v850_sreg_name): New function.  Returns the name
 104         of a v850 system register.  Move the v850_sreg_names array into
 105         this function.
 106         (get_v850_reg_name): Likewise for ordinary register names.
 107         (get_v850_vreg_name): Likewise for vector register names.
 108         (get_v850_cc_name): Likewise for condition codes.
 109         * get_v850_float_cc_name): Likewise for floating point condition
 110         codes.
 111         (get_v850_cacheop_name): Likewise for cache-ops.
 112         (get_v850_prefop_name): Likewise for pref-ops.
 113         (disassemble): Use the new accessor functions.
 114
 115 2019-10-30  Delia Burduv   <delia.burduv@arm.com>
 116
 117         * aarch64-opc.c (print_immediate_offset_address): Don't print the
 118         immediate for the writeback form of ldraa/ldrab if it is 0.
 119         * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
 120         * aarch64-opc-2.c: Regenerated.
 121
 122 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 123
 124         * i386-gen.c (operand_type_shorthands): Delete.
 125         (operand_type_init): Expand previous shorthands.
 126         (set_bitfield_from_shorthand): Rename back to ...
 127         (set_bitfield_from_cpu_flag_init): ... this.  Drop processing
 128         of operand_type_init[].
 129         (set_bitfield): Adjust call to the above function.
 130         * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
 131         RegXMM, RegYMM, RegZMM): Define.
 132         * i386-reg.tbl: Expand prior shorthands.
 133
 134 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 135
 136         * i386-gen.c (output_i386_opcode): Change order of fields
 137         emitted to output.
 138         * i386-opc.h (struct insn_template): Move operands field.
 139         Convert extension_opcode field to unsigned short.
 140         * i386-tbl.h: Re-generate.
 141
 142 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 143
 144         * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
 145         of W.
 146         * i386-opc.h (W): Extend comment.
 147         * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
 148         general purpose variants not allowing for byte operands.
 149         * i386-tbl.h: Re-generate.
 150
 151 2019-10-29  Nick Clifton  <nickc@redhat.com>
 152
 153         * tic30-dis.c (print_branch): Correct size of operand array.
 154
 155 2019-10-29  Nick Clifton  <nickc@redhat.com>
 156
 157         * d30v-dis.c (print_insn): Check that operand index is valid
 158         before attempting to access the operands array.
 159
 160 2019-10-29  Nick Clifton  <nickc@redhat.com>
 161
 162         * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
 163         locating the bit to be tested.
 164
 165 2019-10-29  Nick Clifton  <nickc@redhat.com>
 166
 167         * s12z-dis.c (opr_emit_disassembly): Check for illegal register
 168         values.
 169         (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
 170         (print_insn_s12z):  Check for illegal size values.
 171
 172 2019-10-28  Nick Clifton  <nickc@redhat.com>
 173
 174         * csky-dis.c (csky_chars_to_number): Check for a negative
 175         count. Use an unsigned integer to construct the return value.
 176
 177 2019-10-28  Nick Clifton  <nickc@redhat.com>
 178
 179         * tic30-dis.c (OPERAND_BUFFER_LEN): Define.  Use as length of
 180         operand buffer.  Set value to 15 not 13.
 181         (get_register_operand): Use OPERAND_BUFFER_LEN.
 182         (get_indirect_operand): Likewise.
 183         (print_two_operand): Likewise.
 184         (print_three_operand): Likewise.
 185         (print_oar_insn): Likewise.
 186
 187 2019-10-28  Nick Clifton  <nickc@redhat.com>
 188
 189         * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
 190         (bit_extract_simple): Likewise.
 191         (bit_copy): Likewise.
 192         (pirnt_insn_ns32k): Ensure that uninitialised elements in the
 193         index_offset array are not accessed.
 194
 195 2019-10-28  Nick Clifton  <nickc@redhat.com>
 196
 197         * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
 198         operand.
 199
 200 2019-10-25  Nick Clifton  <nickc@redhat.com>
 201
 202         * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
 203         access to opcodes.op array element.
 204
 205 2019-10-23  Nick Clifton  <nickc@redhat.com>
 206
 207         * rx-dis.c (get_register_name): Fix spelling typo in error
 208         message.
 209         (get_condition_name, get_flag_name, get_double_register_name)
 210         (get_double_register_high_name, get_double_register_low_name)
 211         (get_double_control_register_name, get_double_condition_name)
 212         (get_opsize_name, get_size_name): Likewise.
 213
 214 2019-10-22  Nick Clifton  <nickc@redhat.com>
 215
 216         * rx-dis.c (get_size_name): New function.  Provides safe
 217         access to name array.
 218         (get_opsize_name): Likewise.
 219         (print_insn_rx): Use the accessor functions.
 220
 221 2019-10-16  Nick Clifton  <nickc@redhat.com>
 222
 223         * rx-dis.c (get_register_name): New function.  Provides safe
 224         access to name array.
 225         (get_condition_name, get_flag_name, get_double_register_name)
 226         (get_double_register_high_name, get_double_register_low_name)
 227         (get_double_control_register_name, get_double_condition_name):
 228         Likewise.
 229         (print_insn_rx): Use the accessor functions.
 230
 231 2019-10-09  Nick Clifton  <nickc@redhat.com>
 232
 233         PR 25041
 234         * avr-dis.c (avr_operand): Fix construction of address for lds/sts
 235         instructions.
 236
 237 2019-10-07  Jan Beulich  <jbeulich@suse.com>
 238
 239         * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
 240         (cmpsd): Likewise. Move EsSeg to other operand.
 241         * opcodes/i386-tbl.h: Re-generate.
 242
 243 2019-09-23  Alan Modra  <amodra@gmail.com>
 244
 245         * m68k-dis.c: Include cpu-m68k.h
 246
 247 2019-09-23  Alan Modra  <amodra@gmail.com>
 248
 249         * mips-dis.c: Include elfxx-mips.h.  Move "elf-bfd.h" and
 250         "elf/mips.h" earlier.
 251
 252 2018-09-20  Jan Beulich  <jbeulich@suse.com>
 253
 254         PR gas/25012
 255         * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
 256         with SReg operand.
 257         * i386-tbl.h: Re-generate.
 258
 259 2019-09-18  Alan Modra  <amodra@gmail.com>
 260
 261         * arc-ext.c: Update throughout for bfd section macro changes.
 262
 263 2019-09-18  Simon Marchi  <simon.marchi@polymtl.ca>
 264
 265         * Makefile.in: Re-generate.
 266         * configure: Re-generate.
 267
 268 2019-09-17  Maxim Blinov  <maxim.blinov@embecosm.com>
 269
 270         * riscv-opc.c (riscv_opcodes): Change subset field
 271         to insn_class field for all instructions.
 272         (riscv_insn_types): Likewise.
 273
 274 2019-09-16  Phil Blundell  <pb@pbcl.net>
 275
 276         * configure: Regenerated.
 277
 278 2019-09-10  Miod Vallat  <miod@online.fr>
 279
 280         PR 24982
 281         * m68k-opc.c: Correct aliases for tdivsl and tdivul.
 282
 283 2019-09-09  Phil Blundell  <pb@pbcl.net>
 284
 285         binutils 2.33 branch created.
 286
 287 2019-09-03  Nick Clifton  <nickc@redhat.com>
 288
 289         PR 24961
 290         * tic30-dis.c (get_indirect_operand): Check for bufcnt being
 291         greater than zero before indexing via (bufcnt -1).
 292
 293 2019-09-03  Nick Clifton  <nickc@redhat.com>
 294
 295         PR 24958
 296         * mmix-dis.c (MAX_REG_NAME_LEN): Define.
 297         (MAX_SPEC_REG_NAME_LEN): Define.
 298         (struct mmix_dis_info): Use defined constants for array lengths.
 299         (get_reg_name): New function.
 300         (get_sprec_reg_name): New function.
 301         (print_insn_mmix): Use new functions.
 302
 303 2019-08-27  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 304
 305         * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
 306         (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
 307         (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
 308
 309 2019-08-22  Kyrylo Tkachov <kyrylo.tkachov@arm.com>
 310
 311         * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
 312         tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
 313         (aarch64_sys_reg_supported_p): Update checks for the above.
 314
 315 2019-08-12  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 316
 317         * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
 318         cases MVE_SQRSHRL and MVE_UQRSHLL.
 319         (print_insn_mve): Add case for specifier 'k' to check
 320         specific bit of the instruction.
 321
 322 2019-08-07  Phillipe Antoine  <p.antoine@catenacyber.fr>
 323
 324         PR 24854
 325         * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
 326         encountering an unknown machine type.
 327         (print_insn_arc): Handle arc_insn_length returning 0.  In error
 328         cases return -1 rather than calling abort.
 329
 330 2019-08-07  Jan Beulich  <jbeulich@suse.com>
 331
 332         * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
 333         (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
 334         IgnoreSize.
 335         * i386-tbl.h: Re-generate.
 336
 337 2019-08-05  Barnaby Wilks  <barnaby.wilks@arm.com>
 338
 339         * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
 340         instructions.
 341
 342 2019-07-30  Mel Chen <mel.chen@sifive.com>
 343
 344         * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
 345         fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
 346
 347         * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
 348         fscsr.
 349
 350 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 351
 352         * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
 353         and MPY class instructions.
 354         (parse_option): Add nps400 option.
 355         (print_arc_disassembler_options): Add nps400 info.
 356
 357 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 358
 359         * arc-ext-tbl.h (bspeek): Remove it, added to main table.
 360         (bspop): Likewise.
 361         (modapp): Likewise.
 362         * arc-opc.c (RAD_CHK): Add.
 363         * arc-tbl.h: Regenerate.
 364
 365 2019-07-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 366
 367         * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
 368         (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
 369
 370 2019-07-22  Barnaby Wilks  <barnaby.wilks@arm.com>
 371
 372         * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
 373         instructions as UNPREDICTABLE.
 374
 375 2019-07-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
 376
 377         * bpf-desc.c: Regenerated.
 378
 379 2019-07-17  Jan Beulich  <jbeulich@suse.com>
 380
 381         * i386-gen.c (static_assert): Define.
 382         (main): Use it.
 383         * i386-opc.h (Opcode_Modifier_Max): Rename to ...
 384         (Opcode_Modifier_Num): ... this.
 385         (Mem): Delete.
 386
 387 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 388
 389         * i386-gen.c (operand_types): Move RegMem ...
 390         (opcode_modifiers): ... here.
 391         * i386-opc.h (RegMem): Move to opcode modifer enum.
 392         (union i386_operand_type): Move regmem field ...
 393         (struct i386_opcode_modifier): ... here.
 394         * i386-opc.tbl (RegMem): Define.
 395         (mov, movq): Move RegMem on segment, control, debug, and test
 396         register flavors.
 397         (pextrb): Move RegMem on register only flavors. Add IgnoreSize
 398         to non-SSE2AVX flavor.
 399         (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
 400         Move RegMem on register only flavors. Drop IgnoreSize from
 401         legacy encoding flavors.
 402         (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
 403         flavors.
 404         (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
 405         register only flavors.
 406         (vmovd): Move RegMem and drop IgnoreSize on register only
 407         flavor. Change opcode and operand order to store form.
 408         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 409
 410 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 411
 412         * i386-gen.c (operand_type_init, operand_types): Replace SReg
 413         entries.
 414         * i386-opc.h (SReg2, SReg3): Replace by ...
 415         (SReg): ... this.
 416         (union i386_operand_type): Replace sreg fields.
 417         * i386-opc.tbl (mov, ): Use SReg.
 418         (push, pop): Likewies. Drop i386 and x86-64 specific segment
 419         register flavors.
 420         * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
 421         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 422
 423 2019-07-15  Jose E. Marchesi  <jose.marchesi@oracle.com>
 424
 425         * bpf-desc.c: Regenerate.
 426         * bpf-opc.c: Likewise.
 427         * bpf-opc.h: Likewise.
 428
 429 2019-07-14  Jose E. Marchesi  <jose.marchesi@oracle.com>
 430
 431         * bpf-desc.c: Regenerate.
 432         * bpf-opc.c: Likewise.
 433
 434 2019-07-10  Hans-Peter Nilsson  <hp@bitrange.com>
 435
 436         * arm-dis.c (print_insn_coprocessor): Rename index to
 437         index_operand.
 438
 439 2019-07-05  Kito Cheng <kito.cheng@sifive.com>
 440
 441         * riscv-opc.c (riscv_insn_types): Add r4 type.
 442
 443         * riscv-opc.c (riscv_insn_types): Add b and j type.
 444
 445         * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
 446         format for sb type and correct s type.
 447
 448 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 449
 450         * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
 451         SVE FMOV alias of FCPY.
 452
 453 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 454
 455         * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
 456         to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
 457
 458 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 459
 460         * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
 461         registers in an instruction prefixed by MOVPRFX.
 462
 463 2019-07-01  Matthew Malcomson  <matthew.malcomson@arm.com>
 464
 465         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
 466         sve_size_13 icode to account for variant behaviour of
 467         pmull{t,b}.
 468         * aarch64-dis-2.c: Regenerate.
 469         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
 470         sve_size_13 icode to account for variant behaviour of
 471         pmull{t,b}.
 472         * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
 473         (OP_SVE_VVV_Q_D): Add new qualifier.
 474         (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
 475         (struct aarch64_opcode): Split pmull{t,b} into those requiring
 476         AES and those not.
 477
 478 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 479
 480         * opcodes/i386-gen.c (operand_type_init): Remove
 481         OPERAND_TYPE_VEC_IMM4 entry.
 482         (operand_types): Remove Vec_Imm4.
 483         * opcodes/i386-opc.h (Vec_Imm4): Delete.
 484         (union i386_operand_type): Remove vec_imm4.
 485         * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
 486         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 487
 488 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 489
 490         * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
 491         vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
 492         rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
 493         vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
 494         xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
 495         monitorx, mwaitx): Drop ImmExt from operand-less forms.
 496         * i386-tbl.h: Re-generate.
 497
 498 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 499
 500         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 501         register operands.
 502         * i386-tbl.h: Re-generate.
 503
 504 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 505
 506         * i386-opc.tbl (C): New.
 507         (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
 508         pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
 509         por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
 510         cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
 511         pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
 512         cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
 513         cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
 514         vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
 515         vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
 516         vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
 517         vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
 518         vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
 519         vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
 520         vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
 521         vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
 522         vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
 523         vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
 524         vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
 525         vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
 526         vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
 527         vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
 528         vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
 529         vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
 530         vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
 531         vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
 532         vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
 533         flavors.
 534         * i386-tbl.h: Re-generate.
 535
 536 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 537
 538         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 539         register operands.
 540         * i386-tbl.h: Re-generate.
 541
 542 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 543
 544         * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
 545         * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
 546         vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
 547         * i386-tbl.h: Re-generate.
 548
 549 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 550
 551         * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
 552         Disp8MemShift from register only templates.
 553         * i386-tbl.h: Re-generate.
 554
 555 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 556
 557         * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
 558         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
 559         MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
 560         EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
 561         EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
 562         EVEX_W_0F11_P_3_M_1): Delete.
 563         (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
 564         EVEX_W_0F11_P_3): New.
 565         * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
 566         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
 567         MOD_EVEX_0F11_PREFIX_3 table entries.
 568         * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
 569         PREFIX_EVEX_0F11 table entries.
 570         * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
 571         EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
 572         EVEX_W_0F11_P_3_M_{0,1} table entries.
 573
 574 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 575
 576         * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
 577         Delete.
 578
 579 2019-06-27  H.J. Lu  <hongjiu.lu@intel.com>
 580
 581         PR binutils/24719
 582         * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 583         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 584         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 585         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 586         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 587         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 588         EVEX_LEN_0F38C7_R_6_P_2_W_1.
 589         * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
 590         PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
 591         PREFIX_EVEX_0F38C6_REG_6 entries.
 592         * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
 593         EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
 594         EVEX_W_0F38C7_R_6_P_2 entries.
 595         * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 596         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 597         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 598         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 599         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 600         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 601         EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
 602
 603 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 604
 605         * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
 606         VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
 607         VEX_LEN_0F2D_P_3): Delete.
 608         (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
 609         vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
 610         (prefix_table): ... here.
 611
 612 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 613
 614         * i386-dis.c (Iq): Delete.
 615         (Id): New.
 616         (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
 617         TBM insns.
 618         (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
 619         vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
 620         (OP_E_memory): Also honor needindex when deciding whether an
 621         address size prefix needs printing.
 622         (OP_I): Remove handling of q_mode. Add handling of d_mode.
 623
 624 2019-06-26  Jim Wilson  <jimw@sifive.com>
 625
 626         PR binutils/24739
 627         * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
 628         Set info->display_endian to info->endian_code.
 629
 630 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 631
 632         * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
 633         entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
 634         OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
 635         OPERAND_TYPE_ACC64 entries.
 636         * i386-init.h: Re-generate.
 637
 638 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 639
 640         * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
 641         Delete.
 642         (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
 643         of dqa_mode.
 644         * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
 645         entries here.
 646         * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
 647         entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
 648
 649 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 650
 651         * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
 652         variables.
 653
 654 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 655
 656         * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
 657         Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
 658         movnti.
 659         * i386-opc.tbl (movnti): Add IgnoreSize.
 660         * i386-tbl.h: Re-generate.
 661
 662 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 663
 664         * i386-opc.tbl (and): Mark Imm8S form for optimization.
 665         * i386-tbl.h: Re-generate.
 666
 667 2019-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 668
 669         * i386-dis-evex.h: Break into ...
 670         * i386-dis-evex-len.h: New file.
 671         * i386-dis-evex-mod.h: Likewise.
 672         * i386-dis-evex-prefix.h: Likewise.
 673         * i386-dis-evex-reg.h: Likewise.
 674         * i386-dis-evex-w.h: Likewise.
 675         * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
 676         i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
 677         i386-dis-evex-mod.h.
 678
 679 2019-06-19  H.J. Lu  <hongjiu.lu@intel.com>
 680
 681         PR binutils/24700
 682         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
 683         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
 684         EVEX_W_0F385B_P_2.
 685         (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
 686         EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
 687         EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
 688         EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
 689         EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
 690         EVEX_LEN_0F385B_P_2_W_1.
 691         * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
 692         (EVEX_LEN_0F3819_P_2_W_1): Likewise.
 693         (EVEX_LEN_0F381A_P_2_W_0): Likewise.
 694         (EVEX_LEN_0F381A_P_2_W_1): Likewise.
 695         (EVEX_LEN_0F381B_P_2_W_0): Likewise.
 696         (EVEX_LEN_0F381B_P_2_W_1): Likewise.
 697         (EVEX_LEN_0F385A_P_2_W_0): Likewise.
 698         (EVEX_LEN_0F385A_P_2_W_1): Likewise.
 699         (EVEX_LEN_0F385B_P_2_W_0): Likewise.
 700         (EVEX_LEN_0F385B_P_2_W_1): Likewise.
 701
 702 2019-06-17  H.J. Lu  <hongjiu.lu@intel.com>
 703
 704         PR binutils/24691
 705         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
 706         EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
 707         EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
 708         (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
 709         EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
 710         EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
 711         EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
 712         EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
 713         EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
 714         EVEX_LEN_0F3A43_P_2_W_1.
 715         * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
 716         (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
 717         (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
 718         (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
 719         (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
 720         (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
 721         (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
 722         (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
 723         (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
 724         (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
 725         (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
 726         (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
 727
 728 2019-06-14  Nick Clifton  <nickc@redhat.com>
 729
 730         * po/fr.po; Updated French translation.
 731
 732 2019-06-13  Stafford Horne  <shorne@gmail.com>
 733
 734         * or1k-asm.c: Regenerated.
 735         * or1k-desc.c: Regenerated.
 736         * or1k-desc.h: Regenerated.
 737         * or1k-dis.c: Regenerated.
 738         * or1k-ibld.c: Regenerated.
 739         * or1k-opc.c: Regenerated.
 740         * or1k-opc.h: Regenerated.
 741         * or1k-opinst.c: Regenerated.
 742
 743 2019-06-12  Peter Bergner  <bergner@linux.ibm.com>
 744
 745         * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
 746
 747 2019-06-05  H.J. Lu  <hongjiu.lu@intel.com>
 748
 749         PR binutils/24633
 750         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
 751         EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
 752         (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
 753         EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
 754         EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
 755         EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
 756         EVEX_LEN_0F3A1B_P_2_W_1.
 757         * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
 758         (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
 759         (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
 760         (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
 761         (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
 762         (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
 763         (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
 764         (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
 765
 766 2019-06-04  H.J. Lu  <hongjiu.lu@intel.com>
 767
 768         PR binutils/24626
 769         * i386-dis.c (print_insn): Check for unused VEX.vvvv and
 770         EVEX.vvvv when disassembling VEX and EVEX instructions.
 771         (OP_VEX): Set vex.register_specifier to 0 after readding
 772         vex.register_specifier.
 773         (OP_Vex_2src_1): Likewise.
 774         (OP_Vex_2src_2): Likewise.
 775         (OP_LWP_E): Likewise.
 776         (OP_EX_Vex): Don't check vex.register_specifier.
 777         (OP_XMM_Vex): Likewise.
 778
 779 2019-06-04  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 780             Lili Cui  <lili.cui@intel.com>
 781
 782         * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
 783         * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
 784         instructions.
 785         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
 786         CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
 787         (cpu_flags): Add CpuAVX512_VP2INTERSECT.
 788         * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
 789         (i386_cpu_flags): Add cpuavx512_vp2intersect.
 790         * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
 791         * i386-init.h: Regenerated.
 792         * i386-tbl.h: Likewise.
 793
 794 2019-06-04  Xuepeng Guo  <xuepeng.guo@intel.com>
 795             Lili Cui  <lili.cui@intel.com>
 796
 797         * doc/c-i386.texi: Document enqcmd.
 798         * testsuite/gas/i386/enqcmd-intel.d: New file.
 799         * testsuite/gas/i386/enqcmd-inval.l: Likewise.
 800         * testsuite/gas/i386/enqcmd-inval.s: Likewise.
 801         * testsuite/gas/i386/enqcmd.d: Likewise.
 802         * testsuite/gas/i386/enqcmd.s: Likewise.
 803         * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
 804         * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
 805         * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
 806         * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
 807         * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
 808         * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
 809         enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
 810         and x86-64-enqcmd.
 811
 812 2019-06-04  Alan Hayward  <alan.hayward@arm.com>
 813
 814         * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
 815
 816 2019-06-03  Alan Modra  <amodra@gmail.com>
 817
 818         * ppc-dis.c (prefix_opcd_indices): Correct size.
 819
 820 2019-05-28  H.J. Lu  <hongjiu.lu@intel.com>
 821
 822         PR gas/24625
 823         * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
 824         Disp8ShiftVL.
 825         * i386-tbl.h: Regenerated.
 826
 827 2019-05-24  Alan Modra  <amodra@gmail.com>
 828
 829         * po/POTFILES.in: Regenerate.
 830
 831 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 832             Alan Modra  <amodra@gmail.com>
 833
 834         * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
 835         (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
 836         (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
 837         (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
 838         XTOP>): Define and add entries.
 839         (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
 840         (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
 841         pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
 842         plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
 843
 844 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 845             Alan Modra  <amodra@gmail.com>
 846
 847         * ppc-dis.c (ppc_opts): Add "future" entry.
 848         (PREFIX_OPCD_SEGS): Define.
 849         (prefix_opcd_indices): New array.
 850         (disassemble_init_powerpc): Initialize prefix_opcd_indices.
 851         (lookup_prefix): New function.
 852         (print_insn_powerpc): Handle 64-bit prefix instructions.
 853         * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
 854         (PMRR, POWERXX): Define.
 855         (prefix_opcodes): New instruction table.
 856         (prefix_num_opcodes): New constant.
 857
 858 2019-05-23  Jose E. Marchesi  <jose.marchesi@oracle.com>
 859
 860         * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
 861         * configure: Regenerated.
 862         * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
 863         and cpu/bpf.opc.
 864         (HFILES): Add bpf-desc.h and bpf-opc.h.
 865         (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
 866         bpf-ibld.c and bpf-opc.c.
 867         (BPF_DEPS): Define.
 868         * Makefile.in: Regenerated.
 869         * disassemble.c (ARCH_bpf): Define.
 870         (disassembler): Add case for bfd_arch_bpf.
 871         (disassemble_init_for_target): Likewise.
 872         (enum epbf_isa_attr): Define.
 873         * disassemble.h: extern print_insn_bpf.
 874         * bpf-asm.c: Generated.
 875         * bpf-opc.h: Likewise.
 876         * bpf-opc.c: Likewise.
 877         * bpf-ibld.c: Likewise.
 878         * bpf-dis.c: Likewise.
 879         * bpf-desc.h: Likewise.
 880         * bpf-desc.c: Likewise.
 881
 882 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 883
 884         * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
 885         and VMSR with the new operands.
 886
 887 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 888
 889         * arm-dis.c (enum mve_instructions): New enum
 890         for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
 891         and cneg.
 892         (mve_opcodes): New instructions as above.
 893         (is_mve_encoding_conflict): Add cases for csinc, csinv,
 894         csneg and csel.
 895         (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
 896
 897 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 898
 899         * arm-dis.c (emun mve_instructions): Updated for new instructions.
 900         (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
 901         sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
 902         uqshl, urshrl and urshr.
 903         (is_mve_okay_in_it): Add new instructions to TRUE list.
 904         (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
 905         (print_insn_mve): Updated to accept new %j,
 906         %<bitfield>m and %<bitfield>n patterns.
 907
 908 2019-05-21  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 909
 910         * mips-opc.c (mips_builtin_opcodes): Change source register
 911         constraint for DAUI.
 912
 913 2019-05-20  Nick Clifton  <nickc@redhat.com>
 914
 915         * po/fr.po: Updated French translation.
 916
 917 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 918             Michael Collison <michael.collison@arm.com>
 919
 920         * arm-dis.c (thumb32_opcodes): Add new instructions.
 921         (enum mve_instructions): Likewise.
 922         (enum mve_undefined): Add new reasons.
 923         (is_mve_encoding_conflict): Handle new instructions.
 924         (is_mve_undefined): Likewise.
 925         (is_mve_unpredictable): Likewise.
 926         (print_mve_undefined): Likewise.
 927         (print_mve_size): Likewise.
 928
 929 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 930             Michael Collison <michael.collison@arm.com>
 931
 932         * arm-dis.c (thumb32_opcodes): Add new instructions.
 933         (enum mve_instructions): Likewise.
 934         (is_mve_encoding_conflict): Handle new instructions.
 935         (is_mve_undefined): Likewise.
 936         (is_mve_unpredictable): Likewise.
 937         (print_mve_size): Likewise.
 938
 939 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 940             Michael Collison <michael.collison@arm.com>
 941
 942         * arm-dis.c (thumb32_opcodes): Add new instructions.
 943         (enum mve_instructions): Likewise.
 944         (is_mve_encoding_conflict): Likewise.
 945         (is_mve_unpredictable): Likewise.
 946         (print_mve_size): Likewise.
 947
 948 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 949             Michael Collison <michael.collison@arm.com>
 950
 951         * arm-dis.c (thumb32_opcodes): Add new instructions.
 952         (enum mve_instructions): Likewise.
 953         (is_mve_encoding_conflict): Handle new instructions.
 954         (is_mve_undefined): Likewise.
 955         (is_mve_unpredictable): Likewise.
 956         (print_mve_size): Likewise.
 957
 958 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 959             Michael Collison <michael.collison@arm.com>
 960
 961         * arm-dis.c (thumb32_opcodes): Add new instructions.
 962         (enum mve_instructions): Likewise.
 963         (is_mve_encoding_conflict): Handle new instructions.
 964         (is_mve_undefined): Likewise.
 965         (is_mve_unpredictable): Likewise.
 966         (print_mve_size): Likewise.
 967         (print_insn_mve): Likewise.
 968
 969 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 970             Michael Collison <michael.collison@arm.com>
 971
 972         * arm-dis.c (thumb32_opcodes): Add new instructions.
 973         (print_insn_thumb32): Handle new instructions.
 974
 975 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 976             Michael Collison <michael.collison@arm.com>
 977
 978         * arm-dis.c (enum mve_instructions): Add new instructions.
 979         (enum mve_undefined): Add new reasons.
 980         (is_mve_encoding_conflict): Handle new instructions.
 981         (is_mve_undefined): Likewise.
 982         (is_mve_unpredictable): Likewise.
 983         (print_mve_undefined): Likewise.
 984         (print_mve_size): Likewise.
 985         (print_mve_shift_n): Likewise.
 986         (print_insn_mve): Likewise.
 987
 988 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 989             Michael Collison <michael.collison@arm.com>
 990
 991         * arm-dis.c (enum mve_instructions): Add new instructions.
 992         (is_mve_encoding_conflict): Handle new instructions.
 993         (is_mve_unpredictable): Likewise.
 994         (print_mve_rotate): Likewise.
 995         (print_mve_size): Likewise.
 996         (print_insn_mve): Likewise.
 997
 998 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 999             Michael Collison <michael.collison@arm.com>
1000
1001         * arm-dis.c (enum mve_instructions): Add new instructions.
1002         (is_mve_encoding_conflict): Handle new instructions.
1003         (is_mve_unpredictable): Likewise.
1004         (print_mve_size): Likewise.
1005         (print_insn_mve): Likewise.
1006
1007 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1008             Michael Collison <michael.collison@arm.com>
1009
1010         * arm-dis.c (enum mve_instructions): Add new instructions.
1011         (enum mve_undefined): Add new reasons.
1012         (is_mve_encoding_conflict): Handle new instructions.
1013         (is_mve_undefined): Likewise.
1014         (is_mve_unpredictable): Likewise.
1015         (print_mve_undefined): Likewise.
1016         (print_mve_size): Likewise.
1017         (print_insn_mve): Likewise.
1018
1019 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1020             Michael Collison <michael.collison@arm.com>
1021
1022         * arm-dis.c (enum mve_instructions): Add new instructions.
1023         (is_mve_encoding_conflict): Handle new instructions.
1024         (is_mve_undefined): Likewise.
1025         (is_mve_unpredictable): Likewise.
1026         (print_mve_size): Likewise.
1027         (print_insn_mve): Likewise.
1028
1029 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1030             Michael Collison <michael.collison@arm.com>
1031
1032         * arm-dis.c (enum mve_instructions): Add new instructions.
1033         (enum mve_unpredictable): Add new reasons.
1034         (enum mve_undefined): Likewise.
1035         (is_mve_okay_in_it): Handle new isntructions.
1036         (is_mve_encoding_conflict): Likewise.
1037         (is_mve_undefined): Likewise.
1038         (is_mve_unpredictable): Likewise.
1039         (print_mve_vmov_index): Likewise.
1040         (print_simd_imm8): Likewise.
1041         (print_mve_undefined): Likewise.
1042         (print_mve_unpredictable): Likewise.
1043         (print_mve_size): Likewise.
1044         (print_insn_mve): Likewise.
1045
1046 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1047             Michael Collison <michael.collison@arm.com>
1048
1049         * arm-dis.c (enum mve_instructions): Add new instructions.
1050         (enum mve_unpredictable): Add new reasons.
1051         (enum mve_undefined): Likewise.
1052         (is_mve_encoding_conflict): Handle new instructions.
1053         (is_mve_undefined): Likewise.
1054         (is_mve_unpredictable): Likewise.
1055         (print_mve_undefined): Likewise.
1056         (print_mve_unpredictable): Likewise.
1057         (print_mve_rounding_mode): Likewise.
1058         (print_mve_vcvt_size): Likewise.
1059         (print_mve_size): Likewise.
1060         (print_insn_mve): Likewise.
1061
1062 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1063             Michael Collison <michael.collison@arm.com>
1064
1065         * arm-dis.c (enum mve_instructions): Add new instructions.
1066         (enum mve_unpredictable): Add new reasons.
1067         (enum mve_undefined): Likewise.
1068         (is_mve_undefined): Handle new instructions.
1069         (is_mve_unpredictable): Likewise.
1070         (print_mve_undefined): Likewise.
1071         (print_mve_unpredictable): Likewise.
1072         (print_mve_size): Likewise.
1073         (print_insn_mve): Likewise.
1074
1075 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1076             Michael Collison <michael.collison@arm.com>
1077
1078         * arm-dis.c (enum mve_instructions): Add new instructions.
1079         (enum mve_undefined): Add new reasons.
1080         (insns): Add new instructions.
1081         (is_mve_encoding_conflict):
1082         (print_mve_vld_str_addr): New print function.
1083         (is_mve_undefined): Handle new instructions.
1084         (is_mve_unpredictable): Likewise.
1085         (print_mve_undefined): Likewise.
1086         (print_mve_size): Likewise.
1087         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1088         (print_insn_mve):  Handle new operands.
1089
1090 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1091             Michael Collison <michael.collison@arm.com>
1092
1093         * arm-dis.c (enum mve_instructions): Add new instructions.
1094         (enum mve_unpredictable): Add new reasons.
1095         (is_mve_encoding_conflict): Handle new instructions.
1096         (is_mve_unpredictable): Likewise.
1097         (mve_opcodes): Add new instructions.
1098         (print_mve_unpredictable): Handle new reasons.
1099         (print_mve_register_blocks): New print function.
1100         (print_mve_size): Handle new instructions.
1101         (print_insn_mve): Likewise.
1102
1103 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1104             Michael Collison <michael.collison@arm.com>
1105
1106         * arm-dis.c (enum mve_instructions): Add new instructions.
1107         (enum mve_unpredictable): Add new reasons.
1108         (enum mve_undefined): Likewise.
1109         (is_mve_encoding_conflict): Handle new instructions.
1110         (is_mve_undefined): Likewise.
1111         (is_mve_unpredictable): Likewise.
1112         (coprocessor_opcodes): Move NEON VDUP from here...
1113         (neon_opcodes): ... to here.
1114         (mve_opcodes): Add new instructions.
1115         (print_mve_undefined):  Handle new reasons.
1116         (print_mve_unpredictable): Likewise.
1117         (print_mve_size): Handle new instructions.
1118         (print_insn_neon): Handle vdup.
1119         (print_insn_mve): Handle new operands.
1120
1121 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1122             Michael Collison <michael.collison@arm.com>
1123
1124         * arm-dis.c (enum mve_instructions): Add new instructions.
1125         (enum mve_unpredictable): Add new values.
1126         (mve_opcodes): Add new instructions.
1127         (vec_condnames): New array with vector conditions.
1128         (mve_predicatenames): New array with predicate suffixes.
1129         (mve_vec_sizename): New array with vector sizes.
1130         (enum vpt_pred_state): New enum with vector predication states.
1131         (struct vpt_block): New struct type for vpt blocks.
1132         (vpt_block_state): Global struct to keep track of state.
1133         (mve_extract_pred_mask): New helper function.
1134         (num_instructions_vpt_block): Likewise.
1135         (mark_outside_vpt_block): Likewise.
1136         (mark_inside_vpt_block): Likewise.
1137         (invert_next_predicate_state): Likewise.
1138         (update_next_predicate_state): Likewise.
1139         (update_vpt_block_state): Likewise.
1140         (is_vpt_instruction): Likewise.
1141         (is_mve_encoding_conflict): Add entries for new instructions.
1142         (is_mve_unpredictable): Likewise.
1143         (print_mve_unpredictable): Handle new cases.
1144         (print_instruction_predicate): Likewise.
1145         (print_mve_size): New function.
1146         (print_vec_condition): New function.
1147         (print_insn_mve): Handle vpt blocks and new print operands.
1148
1149 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1150
1151         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1152         8, 14 and 15 for Armv8.1-M Mainline.
1153
1154 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1155             Michael Collison <michael.collison@arm.com>
1156
1157         * arm-dis.c (enum mve_instructions): New enum.
1158         (enum mve_unpredictable): Likewise.
1159         (enum mve_undefined): Likewise.
1160         (struct mopcode32): New struct.
1161         (is_mve_okay_in_it): New function.
1162         (is_mve_architecture): Likewise.
1163         (arm_decode_field): Likewise.
1164         (arm_decode_field_multiple): Likewise.
1165         (is_mve_encoding_conflict): Likewise.
1166         (is_mve_undefined): Likewise.
1167         (is_mve_unpredictable): Likewise.
1168         (print_mve_undefined): Likewise.
1169         (print_mve_unpredictable): Likewise.
1170         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1171         (print_insn_mve): New function.
1172         (print_insn_thumb32): Handle MVE architecture.
1173         (select_arm_features): Force thumb for Armv8.1-m Mainline.
1174
1175 2019-05-10  Nick Clifton  <nickc@redhat.com>
1176
1177         PR 24538
1178         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1179         end of the table prematurely.
1180
1181 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
1182
1183         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1184         macros for R6.
1185
1186 2019-05-11  Alan Modra  <amodra@gmail.com>
1187
1188         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1189         when -Mraw is in effect.
1190
1191 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1192
1193         * aarch64-dis-2.c: Regenerate.
1194         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1195         (OP_SVE_BBB): New variant set.
1196         (OP_SVE_DDDD): New variant set.
1197         (OP_SVE_HHH): New variant set.
1198         (OP_SVE_HHHU): New variant set.
1199         (OP_SVE_SSS): New variant set.
1200         (OP_SVE_SSSU): New variant set.
1201         (OP_SVE_SHH): New variant set.
1202         (OP_SVE_SBBU): New variant set.
1203         (OP_SVE_DSS): New variant set.
1204         (OP_SVE_DHHU): New variant set.
1205         (OP_SVE_VMV_HSD_BHS): New variant set.
1206         (OP_SVE_VVU_HSD_BHS): New variant set.
1207         (OP_SVE_VVVU_SD_BH): New variant set.
1208         (OP_SVE_VVVU_BHSD): New variant set.
1209         (OP_SVE_VVV_QHD_DBS): New variant set.
1210         (OP_SVE_VVV_HSD_BHS): New variant set.
1211         (OP_SVE_VVV_HSD_BHS2): New variant set.
1212         (OP_SVE_VVV_BHS_HSD): New variant set.
1213         (OP_SVE_VV_BHS_HSD): New variant set.
1214         (OP_SVE_VVV_SD): New variant set.
1215         (OP_SVE_VVU_BHS_HSD): New variant set.
1216         (OP_SVE_VZVV_SD): New variant set.
1217         (OP_SVE_VZVV_BH): New variant set.
1218         (OP_SVE_VZV_SD): New variant set.
1219         (aarch64_opcode_table): Add sve2 instructions.
1220
1221 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1222
1223         * aarch64-asm-2.c: Regenerated.
1224         * aarch64-dis-2.c: Regenerated.
1225         * aarch64-opc-2.c: Regenerated.
1226         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1227         for SVE_SHLIMM_UNPRED_22.
1228         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1229         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1230         operand.
1231
1232 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1233
1234         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1235         sve_size_tsz_bhs iclass encode.
1236         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1237         sve_size_tsz_bhs iclass decode.
1238
1239 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1240
1241         * aarch64-asm-2.c: Regenerated.
1242         * aarch64-dis-2.c: Regenerated.
1243         * aarch64-opc-2.c: Regenerated.
1244         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1245         for SVE_Zm4_11_INDEX.
1246         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1247         (fields): Handle SVE_i2h field.
1248         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1249         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1250
1251 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1252
1253         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1254         sve_shift_tsz_bhsd iclass encode.
1255         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1256         sve_shift_tsz_bhsd iclass decode.
1257
1258 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1259
1260         * aarch64-asm-2.c: Regenerated.
1261         * aarch64-dis-2.c: Regenerated.
1262         * aarch64-opc-2.c: Regenerated.
1263         * aarch64-asm.c (aarch64_ins_sve_shrimm):
1264         (aarch64_encode_variant_using_iclass): Handle
1265         sve_shift_tsz_hsd iclass encode.
1266         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1267         sve_shift_tsz_hsd iclass decode.
1268         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1269         for SVE_SHRIMM_UNPRED_22.
1270         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1271         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1272         operand.
1273
1274 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1275
1276         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1277         sve_size_013 iclass encode.
1278         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1279         sve_size_013 iclass decode.
1280
1281 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1282
1283         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1284         sve_size_bh iclass encode.
1285         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1286         sve_size_bh iclass decode.
1287
1288 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1289
1290         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1291         sve_size_sd2 iclass encode.
1292         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1293         sve_size_sd2 iclass decode.
1294         * aarch64-opc.c (fields): Handle SVE_sz2 field.
1295         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1296
1297 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1298
1299         * aarch64-asm-2.c: Regenerated.
1300         * aarch64-dis-2.c: Regenerated.
1301         * aarch64-opc-2.c: Regenerated.
1302         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1303         for SVE_ADDR_ZX.
1304         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1305         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1306
1307 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1308
1309         * aarch64-asm-2.c: Regenerated.
1310         * aarch64-dis-2.c: Regenerated.
1311         * aarch64-opc-2.c: Regenerated.
1312         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1313         for SVE_Zm3_11_INDEX.
1314         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1315         (fields): Handle SVE_i3l and SVE_i3h2 fields.
1316         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1317         fields.
1318         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1319
1320 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1321
1322         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1323         sve_size_hsd2 iclass encode.
1324         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1325         sve_size_hsd2 iclass decode.
1326         * aarch64-opc.c (fields): Handle SVE_size field.
1327         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1328
1329 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1330
1331         * aarch64-asm-2.c: Regenerated.
1332         * aarch64-dis-2.c: Regenerated.
1333         * aarch64-opc-2.c: Regenerated.
1334         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1335         for SVE_IMM_ROT3.
1336         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1337         (fields): Handle SVE_rot3 field.
1338         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1339         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1340
1341 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1342
1343         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1344         instructions.
1345
1346 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1347
1348         * aarch64-tbl.h
1349         (aarch64_feature_sve2, aarch64_feature_sve2aes,
1350         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1351         aarch64_feature_sve2bitperm): New feature sets.
1352         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1353         for feature set addresses.
1354         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1355         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1356
1357 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
1358             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1359
1360         * mips-dis.c (mips_calculate_combination_ases): Add ISA
1361         argument and set ASE_EVA_R6 appropriately.
1362         (set_default_mips_dis_options): Pass ISA to above.
1363         (parse_mips_dis_option): Likewise.
1364         * mips-opc.c (EVAR6): New macro.
1365         (mips_builtin_opcodes): Add llwpe, scwpe.
1366
1367 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
1368
1369         * aarch64-asm-2.c: Regenerated.
1370         * aarch64-dis-2.c: Regenerated.
1371         * aarch64-opc-2.c: Regenerated.
1372         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1373         AARCH64_OPND_TME_UIMM16.
1374         (aarch64_print_operand): Likewise.
1375         * aarch64-tbl.h (QL_IMM_NIL): New.
1376         (TME): New.
1377         (_TME_INSN): New.
1378         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1379
1380 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
1381
1382         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1383
1384 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
1385             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1386
1387         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1388
1389 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1390
1391         * s12z-opc.h: Add extern "C" bracketing to help
1392         users who wish to use this interface in c++ code.
1393
1394 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1395
1396         * s12z-opc.c (bm_decode): Handle bit map operations with the
1397         "reserved0" mode.
1398
1399 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1400
1401         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1402         specifier.  Add entries for VLDR and VSTR of system registers.
1403         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1404         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
1405         of %J and %K format specifier.
1406
1407 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1408
1409         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1410         Add new entries for VSCCLRM instruction.
1411         (print_insn_coprocessor): Handle new %C format control code.
1412
1413 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1414
1415         * arm-dis.c (enum isa): New enum.
1416         (struct sopcode32): New structure.
1417         (coprocessor_opcodes): change type of entries to struct sopcode32 and
1418         set isa field of all current entries to ANY.
1419         (print_insn_coprocessor): Change type of insn to struct sopcode32.
1420         Only match an entry if its isa field allows the current mode.
1421
1422 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1423
1424         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
1425         CLRM.
1426         (print_insn_thumb32): Add logic to print %n CLRM register list.
1427
1428 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1429
1430         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1431         and %Q patterns.
1432
1433 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1434
1435         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1436         (print_insn_thumb32): Edit the switch case for %Z.
1437
1438 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1439
1440         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1441
1442 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1443
1444         * arm-dis.c (thumb32_opcodes): New instruction bfl.
1445
1446 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1447
1448         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1449
1450 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1451
1452         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1453         Arm register with r13 and r15 unpredictable.
1454         (thumb32_opcodes): New instructions for bfx and bflx.
1455
1456 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1457
1458         * arm-dis.c (thumb32_opcodes): New instructions for bf.
1459
1460 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1461
1462         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1463
1464 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1465
1466         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1467
1468 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1469
1470         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1471
1472 2019-04-12  John Darrington <john@darrington.wattle.id.au>
1473
1474         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1475         "optr". ("operator" is a reserved word in c++).
1476
1477 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1478
1479         * aarch64-opc.c (aarch64_print_operand): Add case for
1480         AARCH64_OPND_Rt_SP.
1481         (verify_constraints): Likewise.
1482         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1483         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1484         to accept Rt|SP as first operand.
1485         (AARCH64_OPERANDS): Add new Rt_SP.
1486         * aarch64-asm-2.c: Regenerated.
1487         * aarch64-dis-2.c: Regenerated.
1488         * aarch64-opc-2.c: Regenerated.
1489
1490 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1491
1492         * aarch64-asm-2.c: Regenerated.
1493         * aarch64-dis-2.c: Likewise.
1494         * aarch64-opc-2.c: Likewise.
1495         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1496
1497 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
1498
1499         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1500
1501 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
1502
1503         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1504         * i386-init.h: Regenerated.
1505
1506 2019-04-07  Alan Modra  <amodra@gmail.com>
1507
1508         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1509         op_separator to control printing of spaces, comma and parens
1510         rather than need_comma, need_paren and spaces vars.
1511
1512 2019-04-07  Alan Modra  <amodra@gmail.com>
1513
1514         PR 24421
1515         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1516         (print_insn_neon, print_insn_arm): Likewise.
1517
1518 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
1519
1520         * i386-dis-evex.h (evex_table): Updated to support BF16
1521         instructions.
1522         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1523         and EVEX_W_0F3872_P_3.
1524         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1525         (cpu_flags): Add bitfield for CpuAVX512_BF16.
1526         * i386-opc.h (enum): Add CpuAVX512_BF16.
1527         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1528         * i386-opc.tbl: Add AVX512 BF16 instructions.
1529         * i386-init.h: Regenerated.
1530         * i386-tbl.h: Likewise.
1531
1532 2019-04-05  Alan Modra  <amodra@gmail.com>
1533
1534         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1535         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1536         to favour printing of "-" branch hint when using the "y" bit.
1537         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1538
1539 2019-04-05  Alan Modra  <amodra@gmail.com>
1540
1541         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1542         opcode until first operand is output.
1543
1544 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
1545
1546         PR gas/24349
1547         * ppc-opc.c (valid_bo_pre_v2): Add comments.
1548         (valid_bo_post_v2): Add support for 'at' branch hints.
1549         (insert_bo): Only error on branch on ctr.
1550         (get_bo_hint_mask): New function.
1551         (insert_boe): Add new 'branch_taken' formal argument.  Add support
1552         for inserting 'at' branch hints.
1553         (extract_boe): Add new 'branch_taken' formal argument.  Add support
1554         for extracting 'at' branch hints.
1555         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1556         (BOE): Delete operand.
1557         (BOM, BOP): New operands.
1558         (RM): Update value.
1559         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1560         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1561         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1562         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1563         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1564         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1565         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1566         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1567         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1568         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1569         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1570         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1571         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1572         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1573         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1574         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1575         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1576         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1577         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1578         bttarl+>: New extended mnemonics.
1579
1580 2019-03-28  Alan Modra  <amodra@gmail.com>
1581
1582         PR 24390
1583         * ppc-opc.c (BTF): Define.
1584         (powerpc_opcodes): Use for mtfsb*.
1585         * ppc-dis.c (print_insn_powerpc): Print fields with both
1586         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1587
1588 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1589
1590         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1591         (mapping_symbol_for_insn): Implement new algorithm.
1592         (print_insn): Remove duplicate code.
1593
1594 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1595
1596         * aarch64-dis.c (print_insn_aarch64):
1597         Implement override.
1598
1599 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1600
1601         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1602         order.
1603
1604 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1605
1606         * aarch64-dis.c (last_stop_offset): New.
1607         (print_insn_aarch64): Use stop_offset.
1608
1609 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
1610
1611         PR gas/24359
1612         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1613         CPU_ANY_AVX2_FLAGS.
1614         * i386-init.h: Regenerated.
1615
1616 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
1617
1618         PR gas/24348
1619         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1620         vmovdqu16, vmovdqu32 and vmovdqu64.
1621         * i386-tbl.h: Regenerated.
1622
1623 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1624
1625         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
1626         from vstrszb, vstrszh, and vstrszf.
1627
1628 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1629
1630         * s390-opc.txt: Add instruction descriptions.
1631
1632 2019-02-08  Jim Wilson  <jimw@sifive.com>
1633
1634         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1635         <bne>: Likewise.
1636
1637 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1638
1639         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1640
1641 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1642
1643         PR binutils/23212
1644         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1645         * aarch64-opc.c (verify_elem_sd): New.
1646         (fields): Add FLD_sz entr.
1647         * aarch64-tbl.h (_SIMD_INSN): New.
1648         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1649         fmulx scalar and vector by element isns.
1650
1651 2019-02-07  Nick Clifton  <nickc@redhat.com>
1652
1653         * po/sv.po: Updated Swedish translation.
1654
1655 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
1656
1657         * s390-mkopc.c (main): Accept arch13 as cpu string.
1658         * s390-opc.c: Add new instruction formats and instruction opcode
1659         masks.
1660         * s390-opc.txt: Add new arch13 instructions.
1661
1662 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1663
1664         * aarch64-tbl.h (QL_LDST_AT): Update macro.
1665         (aarch64_opcode): Change encoding for stg, stzg
1666         st2g and st2zg.
1667         * aarch64-asm-2.c: Regenerated.
1668         * aarch64-dis-2.c: Regenerated.
1669         * aarch64-opc-2.c: Regenerated.
1670
1671 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1672
1673         * aarch64-asm-2.c: Regenerated.
1674         * aarch64-dis-2.c: Likewise.
1675         * aarch64-opc-2.c: Likewise.
1676         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1677
1678 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1679             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
1680
1681         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1682         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1683         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1684         * aarch64-dis.h (ext_addr_simple_2): Likewise.
1685         * aarch64-opc.c (operand_general_constraint_met_p): Remove
1686         case for ldstgv_indexed.
1687         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1688         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1689         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1690         * aarch64-asm-2.c: Regenerated.
1691         * aarch64-dis-2.c: Regenerated.
1692         * aarch64-opc-2.c: Regenerated.
1693
1694 2019-01-23  Nick Clifton  <nickc@redhat.com>
1695
1696         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1697
1698 2019-01-21  Nick Clifton  <nickc@redhat.com>
1699
1700         * po/de.po: Updated German translation.
1701         * po/uk.po: Updated Ukranian translation.
1702
1703 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
1704         * mips-dis.c (mips_arch_choices): Fix typo in
1705         gs464, gs464e and gs264e descriptors.
1706
1707 2019-01-19  Nick Clifton  <nickc@redhat.com>
1708
1709         * configure: Regenerate.
1710         * po/opcodes.pot: Regenerate.
1711
1712 2018-06-24  Nick Clifton  <nickc@redhat.com>
1713
1714         2.32 branch created.
1715
1716 2019-01-09  John Darrington <john@darrington.wattle.id.au>
1717
1718         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
1719         if it is null.
1720         -dis.c (opr_emit_disassembly): Do not omit an index if it is
1721         zero.
1722
1723 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
1724
1725         * configure: Regenerate.
1726
1727 2019-01-07  Alan Modra  <amodra@gmail.com>
1728
1729         * configure: Regenerate.
1730         * po/POTFILES.in: Regenerate.
1731
1732 2019-01-03  John Darrington <john@darrington.wattle.id.au>
1733
1734         * s12z-opc.c: New file.
1735         * s12z-opc.h: New file.
1736         * s12z-dis.c: Removed all code not directly related to display
1737         of instructions.  Used the interface provided by the new files
1738         instead.
1739         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
1740         * Makefile.in: Regenerate.
1741         * configure.ac (bfd_s12z_arch): Correct the dependencies.
1742         * configure: Regenerate.
1743
1744 2019-01-01  Alan Modra  <amodra@gmail.com>
1745
1746         Update year range in copyright notice of all files.
1747
1748 For older changes see ChangeLog-2018
1749 \f
1750 Copyright (C) 2019 Free Software Foundation, Inc.
1751
1752 Copying and distribution of this file, with or without modification,
1753 are permitted in any medium without royalty provided the copyright
1754 notice and this notice are preserved.
1755
1756 Local Variables:
1757 mode: change-log
1758 left-margin: 8
1759 fill-column: 74
1760 version-control: never
1761 End: