opcodes/ChangeLog

   1 2022-01-17  Nick Clifton  <nickc@redhat.com>
   2
   3         * Makefile.in: Regenerate.
   4         * po/opcodes.pot: Regenerate.
   5
   6 2021-12-02  Marcus Nilsson  <brainbomb@gmail.com>
   7
   8         * avr-dis.c (avr_operand); Pass in disassemble_info and fill
   9         in insn_type on branching instructions.
  10
  11 2021-11-25  Andrew Burgess  <aburgess@redhat.com>
  12             Simon Cook  <simon.cook@embecosm.com>
  13
  14         * riscv-dis.c (enum riscv_option_arg_t): New enum typedef.
  15         (riscv_options): New static global.
  16         (disassembler_options_riscv): New function.
  17         (print_riscv_disassembler_options): Rewrite to use
  18         disassembler_options_riscv.
  19
  20 2021-11-25  Nick Clifton  <nickc@redhat.com>
  21
  22         PR 28614
  23         * aarch64-asm.c: Replace assert(0) with real code.
  24         * aarch64-dis.c: Likewise.
  25         * aarch64-opc.c: Likewise.
  26
  27 2021-11-25  Nick Clifton  <nickc@redhat.com>
  28
  29         * po/fr.po; Updated French translation.
  30
  31 2021-10-27  Maciej W. Rozycki  <macro@embecosm.com>
  32
  33         * Makefile.am: Remove obsolete comment.
  34         * configure.ac: Refer `libbfd.la' to link shared BFD library
  35         except for Cygwin.
  36         * Makefile.in: Regenerate.
  37         * configure: Regenerate.
  38
  39 2021-09-27  Nick Alcock  <nick.alcock@oracle.com>
  40
  41         * configure: Regenerate.
  42
  43 2021-09-25  Peter Bergner  <bergner@linux.ibm.com>
  44
  45         * ppc-opc.c (powerpc_opcodes) <mfppr, mfppr32, mtppr, mtppr32>: Enable
  46         on POWER5 and later.
  47
  48 2021-09-20  Andrew Burgess  <andrew.burgess@embecosm.com>
  49
  50         * riscv-dis.c (riscv_disassemble_insn): Print a .%dbyte opcode
  51         before an unknown instruction, '%d' is replaced with the
  52         instruction length.
  53
  54 2021-09-02  Nick Clifton  <nickc@redhat.com>
  55
  56         PR 28292
  57         * v850-opc.c (D16): Use BFD_RELOC_V850_LO16_SPLIT_OFFSET in place
  58         of BFD_RELOC_16.
  59
  60 2021-08-17  Shahab Vahedi <shahab@synopsys.com>
  61
  62         * arc-regs.h (DEF): Fix the register numbers.
  63
  64 2021-08-10  Nick Clifton  <nickc@redhat.com>
  65
  66         * po/sr.po: Updated Serbian translation.
  67
  68 2021-07-26  Chenghua Xu  <xuchenghua@loongson.cn>
  69
  70         * mips-dis.c (mips_arch_choices): Correct gs264e bfd_mach.
  71
  72 2021-06-07  Andreas Krebbel  <krebbel@linux.ibm.com>
  73
  74         * s390-opc.txt: Add qpaci.
  75
  76 2021-07-03  Nick Clifton  <nickc@redhat.com>
  77
  78         * configure: Regenerate.
  79         * po/opcodes.pot: Regenerate.
  80
  81 2021-07-03  Nick Clifton  <nickc@redhat.com>
  82
  83         * 2.37 release branch created.
  84
  85 2021-07-02  Alan Modra  <amodra@gmail.com>
  86
  87         * nds32-dis.c (nds32_find_reg_keyword): Constify arg and return.
  88         (nds32_parse_audio_ext, nds32_parse_opcode): Constify psys_reg.
  89         (nds32_field_table, nds32_opcode_table, nds32_keyword_table),
  90         (nds32_opcodes, nds32_operand_fields, nds32_keywords),
  91         (nds32_keyword_gpr): Move declarations to..
  92         * nds32-asm.h: ..here, constifying to match definitions.
  93
  94 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
  95
  96         * Makefile.am (GUILE): New variable.
  97         (CGEN): Use $(GUILE).
  98         * Makefile.in: Regenerate.
  99
 100 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 101
 102         * mep-asm.c (macros): Mark static & const.
 103         (lookup_macro): Change return & m to const.
 104         (expand_macro): Change mac to const.
 105         (expand_string): Change pmacro to const.
 106
 107 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 108
 109         * nds32-asm.c (operand_fields): Rename to ...
 110         (nds32_operand_fields): ... this.
 111         (keyword_gpr): Rename to ...
 112         (nds32_keyword_gpr): ... this.
 113         (keyword_usr, keyword_dxr, keyword_sr, keyword_cp, keyword_cpr,
 114         keyword_fsr, keyword_fdr, keyword_abdim, keyword_abm,
 115         keyword_dpref_st, keyword_cctl_lv, keyword_standby_st,
 116         keyword_msync_st, keyword_im5_i, keyword_im5_m, keyword_accumulator,
 117         keyword_aridx, keyword_aridx2, keyword_aridxi, keyword_aridxi_mx):
 118         Mark static.
 119         (keywords): Rename to ...
 120         (nds32_keywords): ... this.
 121         * nds32-dis.c: Rename operand_fields to nds32_operand_fields,
 122         keywords to nds32_keywords, and keyword_gpr to nds32_keyword_gpr.
 123
 124 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 125
 126         * z80-dis.c (opc_ed): Make const.
 127         (pref_ed): Make p const.
 128
 129 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 130
 131         * microblaze-dis.c (get_field_special): Make op const.
 132         (read_insn_microblaze): Make opr & op const.  Rename opcodes to
 133         microblaze_opcodes.
 134         (print_insn_microblaze): Make op & pop const.
 135         (get_insn_microblaze): Make op const.  Rename opcodes to
 136         microblaze_opcodes.
 137         (microblaze_get_target_address): Likewise.
 138         * microblaze-opc.h (struct op_code_struct): Make const.
 139         Rename opcodes to microblaze_opcodes.
 140
 141 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 142
 143         * aarch64-gen.c (aarch64_opcode_table): Add const.
 144         * aarch64-tbl.h (aarch64_opcode_table): Likewise.
 145
 146 2021-06-22  Andrew Burgess  <andrew.burgess@embecosm.com>
 147
 148         * cgen-dis.c (count_decodable_bits): Use __builtin_popcount when
 149         available.
 150
 151 2021-06-22  Alan Modra  <amodra@gmail.com>
 152
 153         * pj-dis.c (print_insn_pj): Don't print trailing tab.  Do
 154         print separator for pcrel insns.
 155
 156 2021-06-19  Alan Modra  <amodra@gmail.com>
 157
 158         * vax-dis.c (print_insn_vax): Avoid pointer overflow.
 159
 160 2021-06-19  Alan Modra  <amodra@gmail.com>
 161
 162         * tic30-dis.c (get_register_operand): Don't ask strncpy to fill
 163         entire buffer.
 164
 165 2021-06-17  Alan Modra  <amodra@gmail.com>
 166
 167         * ppc-opc.c (powerpc_opcodes): Move cell db*cyc to proper location
 168         in table.
 169
 170 2021-06-03  Alan Modra  <amodra@gmail.com>
 171
 172         PR 1202
 173         * mcore-dis.c (print_insn_mcore): Correct loopt disassembly.
 174         Use unsigned int for inst.
 175
 176 2021-06-02  Shahab Vahedi  <shahab@synopsys.com>
 177
 178         * arc-dis.c (arc_option_arg_t): New enumeration.
 179         (arc_options): New variable.
 180         (disassembler_options_arc): New function.
 181         (print_arc_disassembler_options): Reimplement in terms of
 182         "disassembler_options_arc".
 183
 184 2021-05-29  Alan Modra  <amodra@gmail.com>
 185
 186         * ppc-dis.c (lookup_powerpc): Test deprecated field when -Many.
 187         Don't special case PPC_OPCODE_RAW.
 188         (lookup_prefix): Likewise.
 189         (lookup_vle, lookup_spe2): Similarly.  Add dialect parameter and..
 190         (print_insn_powerpc): ..update caller.
 191         * ppc-opc.c (EXT): Define.
 192         (powerpc_opcodes): Mark extended mnemonics with EXT.
 193         (prefix_opcodes, vle_opcodes): Likewise.
 194         (XISEL, XISEL_MASK): Add cr field and simplify.
 195         (powerpc_opcodes): Use XISEL with extended isel mnemonics and sort
 196         all isel variants to where the base mnemonic belongs.  Sort dstt,
 197         dststt and dssall.
 198
 199 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 200
 201         * mips-opc.c (mips_builtin_opcodes): Reorder legacy COP0, COP2,
 202         COP3 opcode instructions.
 203
 204 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 205
 206         * mips-opc.c (mips_builtin_opcodes): Update exclusion list for
 207         "ldc2", "ldc3", "lwc0", "lwc2", "lwc3", "sdc2", "sdc3", "swc0",
 208         "swc2", "swc3", "cfc0", "ctc0", "bc2f", "bc2fl", "bc2t",
 209         "bc2tl", "cfc2", "ctc2", "dmfc2", "dmtc2", "mfc2", "mtc2",
 210         "bc3f", "bc3fl", "bc3t", "bc3tl", "cfc3", "ctc3", "mfc3",
 211         "mtc3", "bc0f", "bc0fl", "bc0t", "bc0tl", "rfe", "c2", "c3",
 212         "cop2", and "cop3" entries.
 213
 214 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 215
 216         * mips-opc.c (mips_builtin_opcodes): Remove "dmfc3" and "dmtc3"
 217         entries and associated comments.
 218
 219 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 220
 221         * mips-opc.c (mips_builtin_opcodes): Move the "rfe" entry ahead
 222         of "c0".
 223
 224 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 225
 226         * mips-dis.c (mips_cp1_names_mips): New variable.
 227         (mips_arch_choices): Use it rather than `mips_cp1_names_numeric'
 228         for "r3000", "r4000", "r4010", "vr4100", "vr4111", "vr4120",
 229         "r4300", "r4400", "r4600", "r4650", "r5000", "vr5400", "vr5500",
 230         "r5900", "r6000", "rm7000", "rm9000", "r8000", "r10000",
 231         "r12000", "r14000", "r16000", "mips5", "loongson2e", and
 232         "loongson2f".
 233
 234 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 235
 236         * mips-dis.c (print_reg) <OP_REG_COPRO>: Move control register
 237         handling code over to...
 238         <OP_REG_CONTROL>: ... this new case.
 239         * mips-opc.c (decode_mips_operand) <'g', 'y'>: New cases.
 240         (mips_builtin_opcodes): Update "cfc1", "ctc1", "cttc1", "cttc2",
 241         "cfc0", "ctc0", "cfc2", "ctc2", "cfc3", and "ctc3" entries
 242         replacing the `G' operand code with `g'.  Update "cftc1" and
 243         "cftc2" entries replacing the `E' operand code with `y'.
 244         * micromips-opc.c (decode_micromips_operand) <'g'>: New case.
 245         (micromips_opcodes): Update "cfc1", "cfc2", "ctc1", and "ctc2"
 246         entries replacing the `G' operand code with `g'.
 247
 248 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 249
 250         * mips-dis.c (mips_cp0_names_r3900): New variable.
 251         (mips_arch_choices): Use it rather than `mips_cp0_names_numeric'
 252         for "r3900".
 253
 254 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 255
 256         * mips-opc.c (mips_builtin_opcodes): Switch "cttc2", "mttc2",
 257         and "mtthc2" to using the `G' rather than `g' operand code for
 258         the coprocessor control register referred.
 259
 260 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 261
 262         * micromips-opc.c (micromips_opcodes): Swap the two "dmtc1"
 263         entries with each other.
 264
 265 2021-05-27  Peter Bergner  <bergner@linux.ibm.com>
 266
 267         * ppc-opc.c (powerpc_opcodes) <xxmr, xxlnot>: New extended mnemonics.
 268
 269 2021-05-25  Alan Modra  <amodra@gmail.com>
 270
 271         * cris-desc.c: Regenerate.
 272         * cris-desc.h: Regenerate.
 273         * cris-opc.h: Regenerate.
 274         * po/POTFILES.in: Regenerate.
 275
 276 2021-05-24  Mike Frysinger  <vapier@gentoo.org>
 277
 278         * Makefile.am (HFILES): Add cris-desc.h & cris-opc.h.
 279         (TARGET_LIBOPCODES_CFILES): Add cris-desc.c.
 280         (CGEN_CPUS): Add cris.
 281         (CRIS_DEPS): Define.
 282         (stamp-cris): New rule.
 283         * cgen.sh: Handle desc action.
 284         * configure.ac (bfd_cris_arch): Add cris-desc.lo.
 285         * Makefile.in, configure: Regenerate.
 286
 287 2021-05-18  Job Noorman  <mtvec@pm.me>
 288
 289         PR 27814
 290         * riscv-dis.c (riscv_get_disassembler): Get elf attributes only for
 291         the elf objects.
 292
 293 2021-05-17  Alex Coplan  <alex.coplan@arm.com>
 294
 295         * arm-dis.c (mve_opcodes): Fix disassembly of
 296         MVE_VMOV2_GP_TO_VEC_LANE when idx == 1.
 297         (is_mve_encoding_conflict): MVE vector loads should not match
 298         when P = W = 0.
 299         (is_mve_unpredictable): It's not unpredictable to use the same
 300         source register twice (for MVE_VMOV2_GP_TO_VEC_LANE).
 301
 302 2021-05-11  Nick Clifton  <nickc@redhat.com>
 303
 304         PR 27840
 305         * tic30-dis.c (print_insn_tic30): Prevent attempts to read beyond
 306         the end of the code buffer.
 307
 308 2021-05-06  Stafford Horne  <shorne@gmail.com>
 309
 310         PR 21464
 311         * or1k-asm.c: Regenerate.
 312
 313 2021-05-01  Max Filippov  <jcmvbkbc@gmail.com>
 314
 315         * xtensa-dis.c (print_insn_xtensa): Fill in info->insn_type and
 316         info->insn_info_valid.
 317
 318 2021-04-26  Jan Beulich  <jbeulich@suse.com>
 319
 320         * i386-opc.tbl (lea): Add Optimize.
 321         * opcodes/i386-tbl.h: Re-generate.
 322
 323 2020-04-23  Max Filippov  <jcmvbkbc@gmail.com>
 324
 325         * xtensa-dis.c (print_xtensa_operand): For PC-relative operand
 326         of l32r fetch and display referenced literal value.
 327
 328 2021-04-23  Max Filippov  <jcmvbkbc@gmail.com>
 329
 330         * xtensa-dis.c (print_insn_xtensa): Set info->bytes_per_chunk
 331         to 4 for literal disassembly.
 332
 333 2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 334
 335         * aarch64-opc.c: Add new registers (RPAOS, RPALOS, PAALLOS, PAALL) support
 336         for TLBI instruction.
 337
 338 2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 339
 340         * aarch64-opc.c: Add new register (CIPAPA, CIGDPAPA) support for
 341         DC instruction.
 342
 343 2021-04-19  Jan Beulich  <jbeulich@suse.com>
 344
 345         * aarch64-asm.c (encode_asimd_fcvt): Add initializer for
 346         "qualifier".
 347         (convert_mov_to_movewide): Add initializer for "value".
 348
 349 2021-04-16  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 350
 351         * aarch64-opc.c: Add RME system registers.
 352
 353 2021-04-16  Lifang Xia <lifang_xia@c-sky.com>
 354
 355         * riscv-opc.c (riscv_opcodes): New insn alias for addi. Compress
 356         "addi d,CV,z" to "c.mv d,CV".
 357
 358 2021-04-12  Alan Modra  <amodra@gmail.com>
 359
 360         * configure.ac (--enable-checking): Add support.
 361         * config.in: Regenerate.
 362         * configure: Regenerate.
 363
 364 2021-04-09  Tejas Belagod  <tejas.belagod@arm.com>
 365
 366         * aarch64-tbl.h (struct aarch64_opcode aarch64_opcode_table): Reclassify
 367         LD64/ST64 instructions to lse_atomic instead of ldstexcl.
 368
 369 2021-04-09  Alan Modra  <amodra@gmail.com>
 370
 371         * ppc-dis.c (struct dis_private): Add "special".
 372         (POWERPC_DIALECT): Delete.  Replace uses with..
 373         (private_data): ..this.  New inline function.
 374         (disassemble_init_powerpc): Init "special" names.
 375         (skip_optional_operands): Add is_pcrel arg, set when detecting R
 376         field of prefix instructions.
 377         (bsearch_reloc, print_got_plt): New functions.
 378         (print_insn_powerpc): For pcrel instructions, print target address
 379         and symbol if known, and decode plt and got loads too.
 380
 381 2021-04-08  Alan Modra  <amodra@gmail.com>
 382
 383         PR 27684
 384         * ppc-opc.c (powerpc_opcodes): Correct usprg typos, add mfpir.
 385
 386 2021-04-08  Alan Modra  <amodra@gmail.com>
 387
 388         PR 27676
 389         * ppc-opc.c (DCBT_EO): Move earlier.
 390         (insert_thct, extract_thct, insert_thds, extract_thds): New functions.
 391         (powerpc_operands): Add THCT and THDS entries.
 392         (powerpc_opcodes): Add dcbtstct, dcbtstds, dcbna, dcbtct, dcbtds.
 393
 394 2021-04-06  Alan Modra  <amodra@gmail.com>
 395
 396         * dis-buf.c (generic_symbol_at_address): Return symbol* NULL.
 397         * s12z-dis.c (decode_possible_symbol): Use symbol returned from
 398         symbol_at_address_func.
 399
 400 2021-04-05  Alan Modra  <amodra@gmail.com>
 401
 402         * configure.ac: Don't check for limits.h, string.h, strings.h or
 403         stdlib.h.
 404         (AC_ISC_POSIX): Don't invoke.
 405         * sysdep.h: Include stdlib.h and string.h unconditionally.
 406         * i386-opc.h: Include limits.h unconditionally.
 407         * wasm32-dis.c: Likewise.
 408         * cgen-opc.c: Don't include alloca-conf.h.
 409         * config.in: Regenerate.
 410         * configure: Regenerate.
 411
 412 2021-04-01  Martin Liska  <mliska@suse.cz>
 413
 414         * arm-dis.c (strneq): Remove strneq and use startswith.
 415         * cr16-dis.c (print_insn_cr16): Likewise.
 416         * score-dis.c (streq): Likewise.
 417         (strneq): Likewise.
 418         * score7-dis.c (strneq): Likewise.
 419
 420 2021-04-01  Alan Modra  <amodra@gmail.com>
 421
 422         PR 27675
 423         * ppc-opc.c (powerpc_opcodes): Add mfummcr2 and mfmmcr2.
 424
 425 2021-03-31  Alan Modra  <amodra@gmail.com>
 426
 427         * sysdep.h (POISON_BFD_BOOLEAN): Define.
 428         * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h,
 429         * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h,
 430         * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c,
 431         * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c,
 432         * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c,
 433         * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c,
 434         * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c,
 435         * microblaze-dis.h, * micromips-opc.c, * mips-dis.c,
 436         * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c,
 437         * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c,
 438         * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c,
 439         * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c,
 440         * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false,
 441         and TRUE with true throughout.
 442
 443 2021-03-31  Alan Modra  <amodra@gmail.com>
 444
 445         * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h.
 446         * aarch64-dis.h: Likewise.
 447         * aarch64-opc.c: Likewise.
 448         * avr-dis.c: Likewise.
 449         * csky-dis.c: Likewise.
 450         * nds32-asm.c: Likewise.
 451         * nds32-dis.c: Likewise.
 452         * nfp-dis.c: Likewise.
 453         * riscv-dis.c: Likewise.
 454         * s12z-dis.c: Likewise.
 455         * wasm32-dis.c: Likewise.
 456
 457 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 458
 459         * i386-opc.c (cs, ds, ss, es, fs, gs): Delete.
 460         (i386_seg_prefixes): New.
 461         * i386-opc.h (cs, ds, ss, es, fs, gs): Delete.
 462         (i386_seg_prefixes): Declare.
 463
 464 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 465
 466         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Delete.
 467
 468 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 469
 470         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Adjust values.
 471         * i386-reg.tbl (st): Move down.
 472         (st(0)): Delete. Extend comment.
 473         * i386-tbl.h: Re-generate.
 474
 475 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 476
 477         * i386-opc.tbl (movq, movabs): Move next to mov counterparts.
 478         (cmpsd): Move next to cmps.
 479         (movsd): Move next to movs.
 480         (cmpxchg16b): Move to separate section.
 481         (fisttp, fisttpll): Likewise.
 482         (monitor, mwait): Likewise.
 483         * i386-tbl.h: Re-generate.
 484
 485 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 486
 487         * i386-opc.tbl (psadbw): Add <sse2:comm>.
 488         (vpsadbw): Add C.
 489         * i386-tbl.h: Re-generate.
 490
 491 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 492
 493         * i386-opc.tbl (mmx, sse, sse2, sse3, ssse3, sse41, sse42, aes,
 494         pclmul, gfni): New templates. Use them wherever possible. Move
 495         SSE4.1 pextrw into respective section.
 496         * i386-tbl.h: Re-generate.
 497
 498 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 499
 500         * i386-gen.c (output_i386_opcode): Widen type of "opcode". Use
 501         strtoull(). Bump upper loop bound. Widen masks. Sanity check
 502         "length".
 503         * i386-opc.tbl (Prefix_0X66, Prefix_0XF2, Prefix_0XF3): Delete.
 504         Convert all of their uses to representation in opcode.
 505
 506 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 507
 508         * i386-opc.h (struct insn_template): Shrink base_opcode to 16
 509         bits. Shrink extension_opcode to 9 bits. Make it signed. Change
 510         value of None. Shrink operands to 3 bits.
 511
 512 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 513
 514         * i386-gen.c (process_i386_opcode_modifier): New parameter
 515         "space".
 516         (output_i386_opcode): New local variable "space". Adjust
 517         process_i386_opcode_modifier() invocation.
 518         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 519         invocation.
 520         * i386-tbl.h: Re-generate.
 521
 522 2021-03-29  Alan Modra  <amodra@gmail.com>
 523
 524         * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
 525         (fp_qualifier_p, get_data_pattern): Likewise.
 526         (aarch64_get_operand_modifier_from_value): Likewise.
 527         (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
 528         (operand_variant_qualifier_p): Likewise.
 529         (qualifier_value_in_range_constraint_p): Likewise.
 530         (aarch64_get_qualifier_esize): Likewise.
 531         (aarch64_get_qualifier_nelem): Likewise.
 532         (aarch64_get_qualifier_standard_value): Likewise.
 533         (get_lower_bound, get_upper_bound): Likewise.
 534         (aarch64_find_best_match, match_operands_qualifier): Likewise.
 535         (aarch64_print_operand): Likewise.
 536         * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
 537         (operand_need_sign_extension, operand_need_shift_by_two): Likewise.
 538         (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
 539         * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
 540         * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
 541         (print_insn_tic6x): Likewise.
 542
 543 2021-03-29  Alan Modra  <amodra@gmail.com>
 544
 545         * arc-dis.c (extract_operand_value): Correct NULL cast.
 546         * frv-opc.h: Regenerate.
 547
 548 2021-03-26  Jan Beulich  <jbeulich@suse.com>
 549
 550         * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to
 551         MMX form.
 552         * i386-tbl.h: Re-generate.
 553
 554 2021-03-25  Abid Qadeer  <abidh@codesourcery.com>
 555
 556         * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
 557         immediate in br.n instruction.
 558
 559 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 560
 561         * i386-dis.c (XMGatherD, VexGatherD): New.
 562         (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
 563         (print_insn): Check masking for S/G insns.
 564         (OP_E_memory): New local variable check_gather. Extend mandatory
 565         SIB check. Check register conflicts for (EVEX-encoded) gathers.
 566         Extend check for disallowed 16-bit addressing.
 567         (OP_VEX): New local variables modrm_reg and sib_index. Convert
 568         if()s to switch(). Check register conflicts for (VEX-encoded)
 569         gathers. Drop no longer reachable cases.
 570         * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
 571         vgatherdp*.
 572
 573 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 574
 575         * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
 576         zeroing-masking without masking.
 577
 578 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 579
 580         * i386-opc.tbl (invlpgb): Fix multi-operand form.
 581         (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
 582         single-operand forms as deprecated.
 583         * i386-tbl.h: Re-generate.
 584
 585 2021-03-25  Alan Modra  <amodra@gmail.com>
 586
 587         PR 27647
 588         * ppc-opc.c (XLOCB_MASK): Delete.
 589         (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
 590         XLBH_MASK.
 591         (powerpc_opcodes): Accept a BH field on all extended forms of
 592         bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
 593
 594 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 595
 596         * i386-gen.c (output_i386_opcode): Drop processing of
 597         opcode_length. Calculate length from base_opcode. Adjust prefix
 598         encoding determination.
 599         (process_i386_opcodes): Drop output of fake opcode_length.
 600         * i386-opc.h (struct insn_template): Drop opcode_length field.
 601         * i386-opc.tbl: Drop opcode length field from all templates.
 602         * i386-tbl.h: Re-generate.
 603
 604 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 605
 606         * i386-gen.c (process_i386_opcode_modifier): Return void. New
 607         parameter "prefix". Drop local variable "regular_encoding".
 608         Record prefix setting / check for consistency.
 609         (output_i386_opcode): Parse opcode_length and base_opcode
 610         earlier. Derive prefix encoding. Drop no longer applicable
 611         consistency checking. Adjust process_i386_opcode_modifier()
 612         invocation.
 613         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 614         invocation.
 615         * i386-tbl.h: Re-generate.
 616
 617 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 618
 619         * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
 620         check.
 621         * i386-opc.h (Prefix_*): Move #define-s.
 622         * i386-opc.tbl: Move pseudo prefix enumerator values to
 623         extension opcode field. Introduce pseudopfx template.
 624         * i386-tbl.h: Re-generate.
 625
 626 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 627
 628         * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
 629         comment.
 630         * i386-tbl.h: Re-generate.
 631
 632 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 633
 634         * i386-opc.h (struct insn_template): Move cpu_flags field past
 635         opcode_modifier one.
 636         * i386-tbl.h: Re-generate.
 637
 638 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 639
 640         * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
 641         * i386-opc.h (OpcodeSpace): New enumerator.
 642         (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
 643         (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
 644         SPACE_XOP09, SPACE_XOP0A): ... respectively.
 645         (struct i386_opcode_modifier): New field opcodespace. Shrink
 646         opcodeprefix field.
 647         i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
 648         SpaceXOP09, SpaceXOP0A): Define. Use them to replace
 649         OpcodePrefix uses.
 650         * i386-tbl.h: Re-generate.
 651
 652 2021-03-22  Martin Liska  <mliska@suse.cz>
 653
 654         * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
 655         * arc-dis.c (parse_option): Likewise.
 656         * arm-dis.c (parse_arm_disassembler_options): Likewise.
 657         * cris-dis.c (print_with_operands): Likewise.
 658         * h8300-dis.c (bfd_h8_disassemble): Likewise.
 659         * i386-dis.c (print_insn): Likewise.
 660         * ia64-gen.c (fetch_insn_class): Likewise.
 661         (parse_resource_users): Likewise.
 662         (in_iclass): Likewise.
 663         (lookup_specifier): Likewise.
 664         (insert_opcode_dependencies): Likewise.
 665         * mips-dis.c (parse_mips_ase_option): Likewise.
 666         (parse_mips_dis_option): Likewise.
 667         * s390-dis.c (disassemble_init_s390): Likewise.
 668         * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
 669
 670 2021-03-16  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
 671
 672         * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
 673
 674 2021-03-12  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 675
 676         * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
 677         icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
 678
 679 2021-03-12  Alan Modra  <amodra@gmail.com>
 680
 681         * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
 682
 683 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 684
 685         * i386-dis.c (OP_XMM): Re-order checks.
 686
 687 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 688
 689         * i386-dis.c (putop): Drop need_vex check when also checking
 690         vex.evex.
 691         (intel_operand_size, OP_E_memory): Drop vex.evex check when also
 692         checking vex.b.
 693
 694 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 695
 696         * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
 697         checks. Move case label past broadcast check.
 698
 699 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 700
 701         * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
 702         vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
 703         REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
 704         EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
 705         EVEX_W_0F38C7_M_0_L_2): Delete.
 706         (REG_EVEX_0F38C7_M_0_L_2): New.
 707         (intel_operand_size): Handle VEX and EVEX the same for
 708         vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
 709         vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
 710         (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
 711         vex_vsib_q_w_d_mode uses.
 712         * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
 713         0F38A1, and 0F38A3 entries.
 714         * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
 715         entry.
 716         * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
 717         * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
 718         0F38A3 entries.
 719
 720 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 721
 722         * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
 723         REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
 724         MOD_VEX_0FXOP_09_12): Rename to ...
 725         (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
 726         REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
 727         (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
 728         RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
 729         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 730         X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
 731         (reg_table): Adjust comments.
 732         (x86_64_table): Move X86_64_0F24, X86_64_0F26,
 733         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 734         X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
 735         (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
 736         (vex_len_table): Adjust opcode 0A_12 entry.
 737         (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
 738         MOD_C5_32BIT, and MOD_XOP_09_12 entries.
 739         (rm_table): Move hreset entry.
 740
 741 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 742
 743         * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
 744         EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
 745         EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
 746         EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
 747         EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
 748         (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
 749         (get_valid_dis386): Also handle 512-bit vector length when
 750         vectoring into vex_len_table[].
 751         * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
 752         0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
 753         entries.
 754         * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
 755         0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
 756         * i386-dis-evex-prefix.h: Adjust 0F7E entry.
 757         * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
 758         entries.
 759
 760 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 761
 762         * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
 763         Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
 764         EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
 765         * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
 766         entries.
 767         * i386-dis-evex-len.h (evex_len_table): Likewise.
 768         * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
 769
 770 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 771
 772         * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
 773         MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
 774         MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
 775         MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
 776         MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
 777         MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
 778         MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
 779         MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
 780         EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
 781         EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
 782         EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
 783         EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
 784         EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
 785         EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
 786         EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
 787         EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
 788         EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
 789         EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
 790         EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
 791         EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
 792         EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
 793         EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
 794         EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
 795         EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
 796         EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
 797         EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
 798         EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
 799         EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
 800         EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
 801         EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
 802         EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
 803         EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
 804         REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
 805         REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
 806         MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
 807         MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
 808         EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
 809         EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
 810         EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
 811         EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
 812         EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
 813         EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
 814         EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
 815         EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
 816         EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
 817         EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
 818         EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
 819         EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
 820         EVEX_W_0F3A43_L_n): New.
 821         * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
 822         0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
 823         0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
 824         * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
 825         for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
 826         0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
 827         0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
 828         * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
 829         0F385B, 0F38C6, and 0F38C7 entries.
 830         * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
 831         0F38C6 and 0F38C7.
 832         * i386-dis-evex-w.h: No longer link to evex_len_table[] for
 833         opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
 834         0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
 835         evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
 836
 837 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 838
 839         * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
 840         MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
 841         MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
 842         MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
 843         MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
 844         MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
 845         MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
 846         MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
 847         MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
 848         MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
 849         MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
 850         MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
 851         MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
 852         MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
 853         MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
 854         MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
 855         MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
 856         MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
 857         MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
 858         MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
 859         MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
 860         MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
 861         MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
 862         MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
 863         MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
 864         PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
 865         PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
 866         PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
 867         PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
 868         PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
 869         VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
 870         VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
 871         VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
 872         VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
 873         VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
 874         VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
 875         VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
 876         VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
 877         VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
 878         VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
 879         VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
 880         VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
 881         VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
 882         VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
 883         VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
 884         VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
 885         VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
 886         VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
 887         VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
 888         VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
 889         VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
 890         VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
 891         VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
 892         VEX_W_0F99_P_2_LEN_0): Delete.
 893         MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
 894         MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
 895         MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
 896         MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
 897         MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
 898         PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
 899         PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
 900         PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
 901         PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
 902         PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
 903         PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
 904         PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
 905         PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
 906         PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
 907         PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
 908         PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
 909         PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
 910         PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
 911         PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
 912         VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
 913         VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
 914         VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
 915         VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
 916         VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
 917         VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
 918         VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
 919         VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
 920         (prefix_table): No longer link to vex_len_table[] for opcodes
 921         0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
 922         0F92, 0F93, 0F98, and 0F99.
 923         (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
 924         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 925         0F98, and 0F99.
 926         (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
 927         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 928         0F98, and 0F99.
 929         (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
 930         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 931         0F98, and 0F99.
 932         (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
 933         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 934         0F98, and 0F99.
 935
 936 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 937
 938         * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
 939         Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
 940         REG_VEX_0F73_M_0 respectively.
 941         (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
 942         MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
 943         MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
 944         MOD_VEX_0F73_REG_7): Delete.
 945         (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
 946         (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
 947         PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
 948         PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
 949         PREFIX_VEX_0F3AF0_L_0 respectively.
 950         (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
 951         VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
 952         VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
 953         VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
 954         (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
 955         VEX_LEN_0F38F7): New.
 956         (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
 957         (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
 958         0F72, and 0F73. No longer link to vex_len_table[] for opcode
 959         0F38F3.
 960         (prefix_table): No longer link to vex_len_table[] for opcodes
 961         0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 962         (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
 963         0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
 964         0F38F6, 0F38F7, and 0F3AF0.
 965         (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
 966         prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 967         (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
 968         0F73.
 969
 970 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 971
 972         * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
 973         REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
 974         (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
 975         MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
 976         MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
 977         (MOD_0F71, MOD_0F72, MOD_0F73): New.
 978         (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
 979         73.
 980         (reg_table): No longer link to mod_table[] for opcodes 0F71,
 981         0F72, and 0F73.
 982         (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
 983         0F73.
 984
 985 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 986
 987         * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
 988         MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
 989         (reg_table): Don't link to mod_table[] where not needed. Add
 990         PREFIX_IGNORED to nop entries.
 991         (prefix_table): Replace PREFIX_OPCODE in nop entries.
 992         (mod_table): Add nop entries next to prefetch ones. Drop
 993         MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
 994         MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
 995         (rm_table): Add PREFIX_IGNORED to nop entries. Drop
 996         PREFIX_OPCODE from endbr* entries.
 997         (get_valid_dis386): Also consider entry's name when zapping
 998         vindex.
 999         (print_insn): Handle PREFIX_IGNORED.
1000
1001 2021-03-09  Jan Beulich  <jbeulich@suse.com>
1002
1003         * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
1004         IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
1005         element.
1006         * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
1007         HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
1008         (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
1009         PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
1010         (struct i386_opcode_modifier): Delete notrackprefixok,
1011         islockable, hleprefixok, and repprefixok fields. Add prefixok
1012         field.
1013         * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
1014         HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
1015         (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
1016         not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
1017         Replace HLEPrefixOk.
1018         * opcodes/i386-tbl.h: Re-generate.
1019
1020 2021-03-09  Jan Beulich  <jbeulich@suse.com>
1021
1022         * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
1023         * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
1024         64-bit form.
1025         * opcodes/i386-tbl.h: Re-generate.
1026
1027 2021-03-03  Jan Beulich  <jbeulich@suse.com>
1028
1029         * i386-gen.c (output_i386_opcode): Don't get operand count. Look
1030         for {} instead of {0}. Don't look for '0'.
1031         * i386-opc.tbl: Drop operand count field. Drop redundant operand
1032         size specifiers.
1033
1034 2021-02-19  Nelson Chu  <nelson.chu@sifive.com>
1035
1036         PR 27158
1037         * riscv-dis.c (print_insn_args): Updated encoding macros.
1038         * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
1039         (match_c_addi16sp): Updated encoding macros.
1040         (match_c_lui): Likewise.
1041         (match_c_lui_with_hint): Likewise.
1042         (match_c_addi4spn): Likewise.
1043         (match_c_slli): Likewise.
1044         (match_slli_as_c_slli): Likewise.
1045         (match_c_slli64): Likewise.
1046         (match_srxi_as_c_srxi): Likewise.
1047         (riscv_insn_types): Added .insn css/cl/cs.
1048
1049 2021-02-18  Nelson Chu  <nelson.chu@sifive.com>
1050
1051         * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
1052         (default_priv_spec): Updated type to riscv_spec_class.
1053         (parse_riscv_dis_option): Updated.
1054         * riscv-opc.c: Moved stuff and make the file tidy.
1055
1056 2021-02-17  Alan Modra  <amodra@gmail.com>
1057
1058         * wasm32-dis.c: Include limits.h.
1059         (CHAR_BIT): Provide backup define.
1060         (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
1061         Correct signed overflow checking.
1062
1063 2021-02-16  Jan Beulich  <jbeulich@suse.com>
1064
1065         * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
1066         * i386-tbl.h: Re-generate.
1067
1068 2021-02-16  Jan Beulich  <jbeulich@suse.com>
1069
1070         * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
1071         Oword.
1072         * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
1073
1074 2021-02-15  Andreas Krebbel  <krebbel@linux.ibm.com>
1075
1076         * s390-mkopc.c (main): Accept arch14 as cpu string.
1077         * s390-opc.txt: Add new arch14 instructions.
1078
1079 2021-02-04  Nick Alcock  <nick.alcock@oracle.com>
1080
1081         * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
1082         favour of LIBINTL.
1083         * configure: Regenerated.
1084
1085 2021-02-08  Mike Frysinger  <vapier@gentoo.org>
1086
1087         * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
1088         * tic54x-opc.c (regs): Rename to ...
1089         (tic54x_regs): ... this.
1090         (mmregs): Rename to ...
1091         (tic54x_mmregs): ... this.
1092         (condition_codes): Rename to ...
1093         (tic54x_condition_codes): ... this.
1094         (cc2_codes): Rename to ...
1095         (tic54x_cc2_codes): ... this.
1096         (cc3_codes): Rename to ...
1097         (tic54x_cc3_codes): ... this.
1098         (status_bits): Rename to ...
1099         (tic54x_status_bits): ... this.
1100         (misc_symbols): Rename to ...
1101         (tic54x_misc_symbols): ... this.
1102
1103 2021-02-04  Nelson Chu  <nelson.chu@sifive.com>
1104
1105         * riscv-opc.c (MASK_RVB_IMM): Removed.
1106         (riscv_opcodes): Removed zb* instructions.
1107         (riscv_ext_version_table): Removed versions for zb*.
1108
1109 2021-01-26  Alan Modra  <amodra@gmail.com>
1110
1111         * i386-gen.c (parse_template): Ensure entire template_instance
1112         is initialised.
1113
1114 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
1115
1116         * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
1117         (riscv_fpr_names_abi): Likewise.
1118         (riscv_opcodes): Likewise.
1119         (riscv_insn_types): Likewise.
1120
1121 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
1122
1123         * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
1124
1125 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
1126
1127         * riscv-dis.c: Comments tidy and improvement.
1128         * riscv-opc.c: Likewise.
1129
1130 2021-01-13  Alan Modra  <amodra@gmail.com>
1131
1132         * Makefile.in: Regenerate.
1133
1134 2021-01-12  H.J. Lu  <hongjiu.lu@intel.com>
1135
1136         PR binutils/26792
1137         * configure.ac: Use GNU_MAKE_JOBSERVER.
1138         * aclocal.m4: Regenerated.
1139         * configure: Likewise.
1140
1141 2021-01-12  Nick Clifton  <nickc@redhat.com>
1142
1143         * po/sr.po: Updated Serbian translation.
1144
1145 2021-01-11  H.J. Lu  <hongjiu.lu@intel.com>
1146
1147         PR ld/27173
1148         * configure: Regenerated.
1149
1150 2021-01-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
1151
1152         * aarch64-asm-2.c: Regenerate.
1153         * aarch64-dis-2.c: Likewise.
1154         * aarch64-opc-2.c: Likewise.
1155         * aarch64-opc.c (aarch64_print_operand):
1156         Delete handling of AARCH64_OPND_CSRE_CSR.
1157         * aarch64-tbl.h (aarch64_feature_csre): Delete.
1158         (CSRE): Likewise.
1159         (_CSRE_INSN): Likewise.
1160         (aarch64_opcode_table): Delete csr.
1161
1162 2021-01-11  Nick Clifton  <nickc@redhat.com>
1163
1164         * po/de.po: Updated German translation.
1165         * po/fr.po: Updated French translation.
1166         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1167         * po/sv.po: Updated Swedish translation.
1168         * po/uk.po: Updated Ukranian translation.
1169
1170 2021-01-09  H.J. Lu  <hongjiu.lu@intel.com>
1171
1172         * configure: Regenerated.
1173
1174 2021-01-09  Nick Clifton  <nickc@redhat.com>
1175
1176         * configure: Regenerate.
1177         * po/opcodes.pot: Regenerate.
1178
1179 2021-01-09  Nick Clifton  <nickc@redhat.com>
1180
1181         * 2.36 release branch crated.
1182
1183 2021-01-08  Peter Bergner  <bergner@linux.ibm.com>
1184
1185         * ppc-opc.c (insert_dw, (extract_dw): New functions.
1186         (DW, (XRC_MASK): Define.
1187         (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
1188
1189 2021-01-09  Alan Modra  <amodra@gmail.com>
1190
1191         * configure: Regenerate.
1192
1193 2021-01-08  Nick Clifton  <nickc@redhat.com>
1194
1195         * po/sv.po: Updated Swedish translation.
1196
1197 2021-01-08  Nick Clifton  <nickc@redhat.com>
1198
1199         PR 27129
1200         * aarch64-dis.c (determine_disassembling_preference): Move call to
1201         aarch64_match_operands_constraint outside of the assertion.
1202         * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
1203         Replace with a return of FALSE.
1204
1205         PR 27139
1206         * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
1207         core system register.
1208
1209 2021-01-07  Samuel Thibault  <samuel.thibault@gnu.org>
1210
1211         * configure: Regenerate.
1212
1213 2021-01-07  Nick Clifton  <nickc@redhat.com>
1214
1215         * po/fr.po: Updated French translation.
1216
1217 2021-01-07  Fredrik Noring  <noring@nocrew.org>
1218
1219         * m68k-opc.c (chkl): Change minimum architecture requirement to
1220         m68020.
1221
1222 2021-01-07  Philipp Tomsich  <prt@gnu.org>
1223
1224         * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
1225
1226 2021-01-07  Claire Xenia Wolf  <claire@symbioticeda.com>
1227             Jim Wilson  <jimw@sifive.com>
1228             Andrew Waterman  <andrew@sifive.com>
1229             Maxim Blinov  <maxim.blinov@embecosm.com>
1230             Kito Cheng  <kito.cheng@sifive.com>
1231             Nelson Chu  <nelson.chu@sifive.com>
1232
1233         * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
1234         (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
1235
1236 2021-01-01  Alan Modra  <amodra@gmail.com>
1237
1238         Update year range in copyright notice of all files.
1239
1240 For older changes see ChangeLog-2020
1241 \f
1242 Copyright (C) 2021-2022 Free Software Foundation, Inc.
1243
1244 Copying and distribution of this file, with or without modification,
1245 are permitted in any medium without royalty provided the copyright
1246 notice and this notice are preserved.
1247
1248 Local Variables:
1249 mode: change-log
1250 left-margin: 8
1251 fill-column: 74
1252 version-control: never
1253 End: