opcodes/ChangeLog

   1 2020-09-28  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
   2
   3         * aarch64-opc.c: Add ETE system registers TRCEXTINSELR<0-3> and TRCRSR.
   4
   5 2020-09-28  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
   6
   7         * aarch64-opc.c: Add TRBE system registers TRBIDR_EL1 , TRBBASER_EL1 ,
   8         TRBLIMITR_EL1 , TRBMAR_EL1 , TRBPTR_EL1, TRBSR_EL1 and TRBTRG_EL1.
   9
  10 2020-09-26  Alan Modra  <amodra@gmail.com>
  11
  12         * csky-opc.h: Formatting.
  13         (GENERAL_REG_BANK): Correct spelling.  Update use throughout file.
  14         (get_register_name): Mask arch with CSKY_ARCH_MASK for shift,
  15         and shift 1u.
  16         (get_register_number): Likewise.
  17         * csky-dis.c (get_gr_name, get_cr_name): Don't mask mach_flag.
  18
  19 2020-09-24  Lili Cui  <lili.cui@intel.com>
  20
  21         PR 26654
  22         * i386-dis.c (enum): Put MOD_VEX_0F38* together.
  23
  24 2020-09-24  Andrew Burgess <andrew.burgess@embecosm.com>
  25
  26         * csky-dis.c (csky_output_operand): Enclose body of if in curly
  27         braces.
  28
  29 2020-09-24  Lili Cui  <lili.cui@intel.com>
  30
  31         * i386-dis.c (enum): Add PREFIX_0F01_REG_1_RM_5,
  32         PREFIX_0F01_REG_1_RM_6, PREFIX_0F01_REG_1_RM_7,
  33         X86_64_0F01_REG_1_RM_5_P_2, X86_64_0F01_REG_1_RM_6_P_2,
  34         X86_64_0F01_REG_1_RM_7_P_2.
  35         (prefix_table): Likewise.
  36         (x86_64_table): Likewise.
  37         (rm_table): Likewise.
  38         * i386-gen.c (cpu_flag_init): Add CPU_TDX_FLAGS
  39         and CPU_ANY_TDX_FLAGS.
  40         (cpu_flags): Add CpuTDX.
  41         * i386-opc.h (enum): Add CpuTDX.
  42         (i386_cpu_flags): Add cputdx.
  43         * i386-opc.tbl: Add TDX insns.
  44         * i386-init.h: Regenerate.
  45         * i386-tbl.h: Likewise.
  46
  47 2020-09-17 Cooper Qu <<cooper.qu@linux.alibaba.com>>
  48
  49         * csky-dis.c (using_abi): New.
  50         (parse_csky_dis_options): New function.
  51         (get_gr_name): New function.
  52         (get_cr_name): New function.
  53         (csky_output_operand): Use get_gr_name and get_cr_name to
  54         disassemble and add handle of OPRND_TYPE_IMM5b_LS.
  55         (print_insn_csky): Parse disassembler options.
  56         * csky-opc.h (OPRND_TYPE_IMM5b_LS): New enum.
  57         (GENARAL_REG_BANK): Define.
  58         (REG_SUPPORT_ALL): Define.
  59         (REG_SUPPORT_ALL): New.
  60         (ASH): Define.
  61         (REG_SUPPORT_A): Define.
  62         (REG_SUPPORT_B): Define.
  63         (REG_SUPPORT_C): Define.
  64         (REG_SUPPORT_D): Define.
  65         (REG_SUPPORT_E): Define.
  66         (csky_abiv1_general_regs): New.
  67         (csky_abiv1_control_regs): New.
  68         (csky_abiv2_general_regs): New.
  69         (csky_abiv2_control_regs): New.
  70         (get_register_name): New function.
  71         (get_register_number): New function.
  72         (csky_get_general_reg_name): New function.
  73         (csky_get_general_regno): New function.
  74         (csky_get_control_reg_name): New function.
  75         (csky_get_control_regno): New function.
  76         (csky_v2_opcodes): Prefer two oprerans format for bclri and
  77         bseti, strengthen the operands legality check of addc, zext
  78         and sext.
  79
  80 2020-09-23  Lili Cui  <lili.cui@intel.com>
  81
  82         * i386-dis.c (enum): Add REG_0F38D8_PREFIX_1,
  83         MOD_0F38FA_PREFIX_1, MOD_0F38FB_PREFIX_1,
  84         MOD_0F38DC_PREFIX_1, MOD_0F38DD_PREFIX_1,
  85         MOD_0F38DE_PREFIX_1, MOD_0F38DF_PREFIX_1,
  86         PREFIX_0F38D8, PREFIX_0F38FA, PREFIX_0F38FB.
  87         (reg_table): New instructions (see prefixes above).
  88         (prefix_table): Likewise.
  89         (three_byte_table): Likewise.
  90         (mod_table): Likewise
  91         * i386-gen.c (cpu_flag_init): Add CPU_KL_FLAGS, CPU_WIDE_KL_FLAGS,
  92         CPU_ANY_KL_FLAGS and CPU_ANY_WIDE_KL_FLAGS.
  93         (cpu_flags): Likewise.
  94         (operand_type_init): Likewise.
  95         * i386-opc.h (enum): Add CpuKL and CpuWide_KL.
  96         (i386_cpu_flags): Add cpukl and cpuwide_kl.
  97         * i386-opc.tbl: Add KL and WIDE_KL insns.
  98         * i386-init.h: Regenerate.
  99         * i386-tbl.h: Likewise.
 100
 101 2020-09-21  Alan Modra  <amodra@gmail.com>
 102
 103         * rx-dis.c (flag_names): Add missing comma.
 104         (register_names, flag_names, double_register_names),
 105         (double_register_high_names, double_register_low_names),
 106         (double_control_register_names, double_condition_names): Remove
 107         trailing commas.
 108
 109 2020-09-18  David Faust  <david.faust@oracle.com>
 110
 111         * bpf-desc.c: Regenerate.
 112         * bpf-desc.h: Likewise.
 113         * bpf-opc.c: Likewise.
 114         * bpf-opc.h: Likewise.
 115
 116 2020-09-16  Andrew Burgess <andrew.burgess@embecosm.com>
 117
 118         * csky-dis.c (csky_get_disassembler): Don't return NULL when there
 119         is no BFD.
 120
 121 2020-09-16  Alan Modra  <amodra@gmail.com>
 122
 123         * ppc-dis.c (ppc_symbol_is_valid): Adjust elf_symbol_from invocation.
 124
 125 2020-09-10  Nick Clifton  <nickc@redhat.com>
 126
 127         * ppc-dis.c (ppc_symbol_is_valid): New function.  Returns false
 128         for hidden, local, no-type symbols.
 129         (disassemble_init_powerpc): Point the symbol_is_valid field in the
 130         info structure at the new function.
 131
 132 2020-09-10  Cooper Qu  <cooper.qu@linux.alibaba.com>
 133
 134         * csky-opc.h (csky_v2_opcodes): Add L2Cache instructions.
 135         * testsuite/gas/csky/cskyv2_ck860.d : Adjust to icache.iva
 136         opcode fixing.
 137
 138 2020-09-10  Nick Clifton  <nickc@redhat.com>
 139
 140         * csky-dis.c (csky_output_operand): Coerce the immediate values to
 141         long before printing.
 142
 143 2020-09-10  Alan Modra  <amodra@gmail.com>
 144
 145         * csky-dis.c (csky_output_operand): Don't sprintf str to itself.
 146
 147 2020-09-07  Cooper Qu  <cooper.qu@linux.alibaba.com>
 148
 149         * csky-opc.h (csky_v2_opcodes): Change mvtc and mulsw's
 150         ISA flag.
 151
 152 2020-09-07  Cooper Qu  <cooper.qu@linux.alibaba.com>
 153
 154         * csky-dis.c (csky_output_operand): Add handlers for
 155         OPRND_TYPE_HFLOAT_FMOVI, OPRND_TYPE_SFLOAT_FMOVI and
 156         OPRND_TYPE_DFLOAT_FMOVI. Refine OPRND_TYPE_FREGLIST_DASH
 157         to support FPUV3 instructions.
 158         * csky-opc.h (enum operand_type): New enum OPRND_TYPE_IMM9b,
 159         OPRND_TYPE_HFLOAT_FMOVI, OPRND_TYPE_SFLOAT_FMOVI and
 160         OPRND_TYPE_DFLOAT_FMOVI.
 161         (OPRND_MASK_4_5, OPRND_MASK_6, OPRND_MASK_6_7, OPRND_MASK_6_8,
 162          OPRND_MASK_7, OPRND_MASK_7_8, OPRND_MASK_17_24,
 163          OPRND_MASK_20, OPRND_MASK_20_21, OPRND_MASK_20_22,
 164          OPRND_MASK_20_23, OPRND_MASK_20_24, OPRND_MASK_20_25,
 165          OPRND_MASK_0_3or5_8, OPRND_MASK_0_3or6_7, OPRND_MASK_0_3or25,
 166          OPRND_MASK_0_4or21_24, OPRND_MASK_5or20_21,
 167          OPRND_MASK_5or20_22, OPRND_MASK_5or20_23, OPRND_MASK_5or20_24,
 168          OPRND_MASK_5or20_25, OPRND_MASK_8_9or21_25,
 169          OPRND_MASK_8_9or16_25, OPRND_MASK_4_6or20, OPRND_MASK_5_7or20,
 170          OPRND_MASK_4_5or20or25, OPRND_MASK_4_6or20or25,
 171          OPRND_MASK_4_7or20or25, OPRND_MASK_6_9or17_24,
 172          OPRND_MASK_6_7or20, OPRND_MASK_6or20, OPRND_MASK_7or20,
 173          OPRND_MASK_5or8_9or16_25, OPRND_MASK_5or8_9or20_25): Define.
 174         (csky_v2_opcodes): Add FPUV3 instructions.
 175
 176 2020-09-08  Alex Coplan  <alex.coplan@arm.com>
 177
 178         * aarch64-dis.c (print_operands): Pass CPU features to
 179         aarch64_print_operand().
 180         * aarch64-opc.c (aarch64_print_operand): Use CPU features to determine
 181         preferred disassembly of system registers.
 182         (SR_RNG): Refactor to use new SR_FEAT2 macro.
 183         (SR_FEAT2): New.
 184         (SR_V8_1_A): New.
 185         (SR_V8_4_A): New.
 186         (SR_V8_A): New.
 187         (SR_V8_R): New.
 188         (SR_EXPAND_ELx): New.
 189         (SR_EXPAND_EL12): New.
 190         (aarch64_sys_regs): Specify which registers are only on
 191         A-profile, add R-profile system registers.
 192         (ENC_BARLAR): New.
 193         (PRBARn_ELx): New.
 194         (PRLARn_ELx): New.
 195         (aarch64_sys_ins_reg_supported_p): Reject EL3 registers for
 196         Armv8-R AArch64.
 197
 198 2020-09-08  Alex Coplan  <alex.coplan@arm.com>
 199
 200         * aarch64-tbl.h (aarch64_feature_v8_r): New.
 201         (ARMV8_R): New.
 202         (V8_R_INSN): New.
 203         (aarch64_opcode_table): Add dfb.
 204         * aarch64-opc-2.c: Regenerate.
 205         * aarch64-asm-2.c: Regenerate.
 206         * aarch64-dis-2.c: Regenerate.
 207
 208 2020-09-08  Alex Coplan  <alex.coplan@arm.com>
 209
 210         * aarch64-dis.c (arch_variant): New.
 211         (determine_disassembling_preference): Disassemble according to
 212         arch variant.
 213         (select_aarch64_variant): New.
 214         (print_insn_aarch64): Set feature set.
 215
 216 2020-09-02  Alan Modra  <amodra@gmail.com>
 217
 218         * v850-opc.c (insert_i5div1, insert_i5div2, insert_i5div3),
 219         (insert_d5_4, insert_d8_6, insert_d8_7, insert_v8, insert_d9),
 220         (insert_u16_loop, insert_d16_15, insert_d16_16, insert_d17_16),
 221         (insert_d22, insert_d23, insert_d23_align1, insert_i9, insert_u9),
 222         (insert_spe, insert_r4, insert_POS, insert_WIDTH, insert_SELID),
 223         (insert_VECTOR8, insert_VECTOR5, insert_CACHEOP, insert_PREFOP),
 224         (nsert_IMM10U, insert_SRSEL1, insert_SRSEL2): Use unsigned long
 225         for value parameter and update code to suit.
 226         (extract_d9, extract_d16_15, extract_d16_16, extract_d17_16),
 227         (extract_d22, extract_d23, extract_i9): Use unsigned long variables.
 228
 229 2020-09-02  Alan Modra  <amodra@gmail.com>
 230
 231         * i386-dis.c (OP_E_memory): Don't cast to signed type when
 232         negating.
 233         (get32, get32s): Use unsigned types in shift expressions.
 234
 235 2020-09-02  Alan Modra  <amodra@gmail.com>
 236
 237         * csky-dis.c (print_insn_csky): Use unsigned type for "given".
 238
 239 2020-09-02  Alan Modra  <amodra@gmail.com>
 240
 241         * crx-dis.c: Whitespace.
 242         (print_arg): Use unsigned type for longdisp and mask variables,
 243         and for left shift constant.
 244
 245 2020-09-02  Alan Modra  <amodra@gmail.com>
 246
 247         * cgen-ibld.in (insert_normal, extract_normal): Use 1UL in left shift.
 248         * bpf-ibld.c: Regenerate.
 249         * epiphany-ibld.c: Regenerate.
 250         * fr30-ibld.c: Regenerate.
 251         * frv-ibld.c: Regenerate.
 252         * ip2k-ibld.c: Regenerate.
 253         * iq2000-ibld.c: Regenerate.
 254         * lm32-ibld.c: Regenerate.
 255         * m32c-ibld.c: Regenerate.
 256         * m32r-ibld.c: Regenerate.
 257         * mep-ibld.c: Regenerate.
 258         * mt-ibld.c: Regenerate.
 259         * or1k-ibld.c: Regenerate.
 260         * xc16x-ibld.c: Regenerate.
 261         * xstormy16-ibld.c: Regenerate.
 262
 263 2020-09-02  Alan Modra  <amodra@gmail.com>
 264
 265         * bfin-dis.c (MASKBITS): Use SIGNBIT.
 266
 267 2020-09-02  Cooper Qu  <cooper.qu@linux.alibaba.com>
 268
 269         * csky-opc.h (csky_v2_opcodes): Move divul and divsl
 270         to CSKYV2_ISA_3E3R3 instruction set.
 271
 272 2020-09-02  Cooper Qu  <cooper.qu@linux.alibaba.com>
 273
 274         * csky-opc.h (csky_v2_opcodes): Fix Encode of mulsws.
 275
 276 2020-09-01  Alan Modra  <amodra@gmail.com>
 277
 278         * mep-ibld.c: Regenerate.
 279
 280 2020-08-31  Cooper Qu  <cooper.qu@linux.alibaba.com>
 281
 282         * csky-dis.c (csky_output_operand): Assign dis_info.value for
 283         OPRND_TYPE_VREG.
 284
 285 2020-08-30  Alan Modra  <amodra@gmail.com>
 286
 287         * cr16-dis.c: Formatting.
 288         (parameter): Delete struct typedef.  Use dwordU instead
 289         throughout file.
 290         (make_argument <arg_idxr>): Simplify detection of cbitb, sbitb
 291         and tbitb.
 292         (make_argument <arg_cr>): Extract 20-bit field not 16-bit.
 293
 294 2020-08-29  Alan Modra  <amodra@gmail.com>
 295
 296         PR 26446
 297         * csky-opc.h (MAX_OPRND_NUM): Define to 5.
 298         (union csky_operand): Use MAX_OPRND_NUM to size oprnds array.
 299
 300 2020-08-28  Alan Modra  <amodra@gmail.com>
 301
 302         PR 26449
 303         PR 26450
 304         * cgen-ibld.in (insert_1): Use 1UL in forming mask.
 305         (extract_normal): Likewise.
 306         (insert_normal): Likewise, and move past zero length test.
 307         (put_insn_int_value): Handle mask for zero length, use 1UL.
 308         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
 309         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
 310         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
 311         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
 312
 313 2020-08-28  Cooper Qu  <cooper.qu@linux.alibaba.com>
 314
 315         * csky-dis.c (CSKY_DEFAULT_ISA): Define.
 316         (csky_dis_info): Add member isa.
 317         (csky_find_inst_info): Skip instructions that do not belong to
 318         current CPU.
 319         (csky_get_disassembler): Get infomation from attribute section.
 320         (print_insn_csky): Set defualt ISA flag.
 321         * csky.h (CSKY_ISA_VDSP_2): Rename from CSKY_ISA_VDSP_V2.
 322         * csky-opc.h (struct csky_opcode): Change isa_flag16 and
 323         isa_flag32'type to unsigned 64 bits.
 324
 325 2020-08-26  Jose E. Marchesi  <jemarch@gnu.org>
 326
 327         * disassemble.c (enum epbf_isa_attr): Add ISA_XBPFBE, ISA_EBPFMAX.
 328
 329 2020-08-26  David Faust  <david.faust@oracle.com>
 330
 331         * bpf-desc.c: Regenerate.
 332         * bpf-desc.h: Likewise.
 333         * bpf-opc.c: Likewise.
 334         * bpf-opc.h: Likewise.
 335         * disassemble.c (disassemble_init_for_target): Set bits for xBPF
 336         ISA when appropriate.
 337
 338 2020-08-25  Alan Modra  <amodra@gmail.com>
 339
 340         PR 26504
 341         * vax-dis.c (parse_disassembler_options): Always add at least one
 342         to entry_addr_total_slots.
 343
 344 2020-08-24  Cooper Qu  <cooper.qu@linux.alibaba.com>
 345
 346         * csky-dis.c (csky_find_inst_info): Skip CK860's instructions
 347         in other CPUs to speed up disassembling.
 348         * csky-opc.h (csky_v2_opcodes): Add CK860's instructions,
 349         Change plsli.u16 to plsli.16, change sync's operand format.
 350
 351 2020-08-21  Cooper Qu  <cooper.qu@linux.alibaba.com>
 352
 353         * csky-opc.h (csky_v2_opcodes): Add instruction bnezad.
 354
 355 2020-08-21  Nick Clifton  <nickc@redhat.com>
 356
 357         * aarch64-dis.c (get_sym_code_type): Return FALSE for non-ELF
 358         symbols.
 359
 360 2020-08-21  Cooper Qu  <cooper.qu@linux.alibaba.com>
 361
 362         * csky-opc.h (csky_v2_opcodes): Add two operands form for bloop.
 363
 364 2020-08-19  Alan Modra  <amodra@gmail.com>
 365
 366         * ppc-opc.c (powerpc_opcodes): Replace OBF with BF for vcmpsq,
 367         vcmpuq and xvtlsbb.
 368
 369 2020-08-18  Peter Bergner  <bergner@linux.ibm.com>
 370
 371         * ppc-opc.c (powerpc_opcodes) <xvcvbf16sp>: Rename from this...
 372         <xvcvbf16spn>: ...to this.
 373
 374 2020-08-12  Alex Coplan  <alex.coplan@arm.com>
 375
 376         * aarch64-opc.c (aarch64_sys_regs): Add MPAM registers.
 377
 378 2020-08-12  Nick Clifton  <nickc@redhat.com>
 379
 380         * po/sr.po: Updated Serbian translation.
 381
 382 2020-08-11  Alan Modra  <amodra@gmail.com>
 383
 384         * ppc-opc.c (powerpc_opcodes): Move cctpl, cctpm and cctph.
 385
 386 2020-08-10  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 387
 388         * aarch64-opc.c (aarch64_print_operand):
 389         (aarch64_sys_reg_deprecated_p): Functions paramaters changed.
 390         (aarch64_sys_reg_supported_p): Function removed.
 391         (aarch64_sys_ins_reg_supported_p): Functions paramaters changed.
 392         (aarch64_sys_ins_reg_supported_p): Merged aarch64_sys_reg_supported_p
 393         into this function.
 394
 395 2020-08-10  Alan Modra  <amodra@gmail.com>
 396
 397         * ppc-opc.c (powerpc_opcodes): Add many mtspr and mfspr extended
 398         instructions.
 399
 400 2020-08-10  Alan Modra  <amodra@gmail.com>
 401
 402         * ppc-opc.c (powerpc_opcodes): Add exser, msgsndu, msgclru.
 403         Enable icbt for power5, miso for power8.
 404
 405 2020-08-10  Alan Modra  <amodra@gmail.com>
 406
 407         * ppc-opc.c (powerpc_opcodes): Prioritise mtfprd and mtvrd over
 408         mtvsrd, and similarly for mfvsrd.
 409
 410 2020-08-04  Christian Groessler  <chris@groessler.org>
 411             Tadashi G. Takaoka <tadashi.g.takaoka@gmail.com>
 412
 413         * z8kgen.c (opt): Fix "sout imm16,rs" and "soutb imm16,rbs"
 414         opcodes (special "out" to absolute address).
 415         * z8k-opc.h: Regenerate.
 416
 417 2020-07-30  H.J. Lu  <hongjiu.lu@intel.com>
 418
 419         PR gas/26305
 420         * i386-opc.h (Prefix_Disp8): New.
 421         (Prefix_Disp16): Likewise.
 422         (Prefix_Disp32): Likewise.
 423         (Prefix_Load): Likewise.
 424         (Prefix_Store): Likewise.
 425         (Prefix_VEX): Likewise.
 426         (Prefix_VEX3): Likewise.
 427         (Prefix_EVEX): Likewise.
 428         (Prefix_REX): Likewise.
 429         (Prefix_NoOptimize): Likewise.
 430         * i386-opc.tbl: Use Prefix_XXX on pseudo prefixes.  Add {disp16}.
 431         * i386-tbl.h: Regenerated.
 432
 433 2020-07-29  Andreas Arnez  <arnez@linux.ibm.com>
 434
 435         * s390-mkopc.c (insertExpandedMnemonic): Handle unreachable
 436         default case with abort() instead of printing an error message and
 437         continuing, to avoid a maybe-uninitialized warning.
 438
 439 2020-07-24  Nick Clifton  <nickc@redhat.com>
 440
 441         * po/de.po: Updated German translation.
 442
 443 2020-07-21  Jan Beulich  <jbeulich@suse.com>
 444
 445         * i386-dis.c (OP_E_memory): Revert previous change.
 446
 447 2020-07-15  H.J. Lu  <hongjiu.lu@intel.com>
 448
 449         PR gas/26237
 450         * i386-dis.c (OP_E_memory): Don't display eiz with no scale
 451         without base nor index registers.
 452
 453 2020-07-15  Jan Beulich  <jbeulich@suse.com>
 454
 455         * i386-dis.c (putop): Move 'V' and 'W' handling.
 456
 457 2020-07-15  Jan Beulich  <jbeulich@suse.com>
 458
 459         * i386-dis.c (dis386): Adjust 'V' description. Use P-based
 460         construct for push/pop of register.
 461         (putop): Honor cond when handling 'P'. Drop handling of plain
 462         'V'.
 463
 464 2020-07-15  Jan Beulich  <jbeulich@suse.com>
 465
 466         * i386-dis.c (dis386): Adjust 'P', 'T', 'U', and '@'
 467         description. Drop '&' description. Use P for push of immediate,
 468         pushf/popf, enter, and leave. Use %LP for lret/retf.
 469         (dis386_twobyte): Use P for push/pop of fs/gs.
 470         (reg_table): Use P for push/pop. Use @ for near call/jmp.
 471         (x86_64_table): Use P for far call/jmp.
 472         (putop): Drop handling of 'U' and '&'. Move and adjust handling
 473         of '@'. Adjust handling of 'P' and 'T'. Drop case_P and case_Q
 474         labels.
 475         (OP_J): Drop marking of REX_W as used for v_mode (ISA-dependent)
 476         and dqw_mode (unconditional).
 477
 478 2020-07-14  H.J. Lu  <hongjiu.lu@intel.com>
 479
 480         PR gas/26237
 481         * i386-dis.c (OP_E_memory): Without base nor index registers,
 482         32-bit displacement to 64 bits.
 483
 484 2020-07-14  Claudiu Zissulescu  <claziss@gmail.com>
 485
 486         * arc-dis.c (print_insn_arc): Detect and emit a warning when a
 487         faulty double register pair is detected.
 488
 489 2020-07-14  Jan Beulich  <jbeulich@suse.com>
 490
 491         * i386-dis.c (OP_D): Print dr<N> instead of db<N> in Intel mode.
 492
 493 2020-07-14  Jan Beulich  <jbeulich@suse.com>
 494
 495         * i386-dis.c (OP_R, Rm): Delete.
 496         (MOD_0F24, MOD_0F26): Rename to ...
 497         (X86_64_0F24, X86_64_0F26): ... respectively.
 498         (dis386): Update 'L' and 'Z' comments.
 499         (dis386_twobyte): Replace Rm by Em. Change opcode 0F24 and 0F26
 500         table references.
 501         (mod_table): Move opcode 0F24 and 0F26 entries ...
 502         (x86_64_table): ... here.
 503         (putop): Drop handling of 'L'. Set modrm.mod to 3 for 'Z'. Move
 504         'Z' case block.
 505
 506 2020-07-14  Jan Beulich  <jbeulich@suse.com>
 507
 508         * i386-dis.c (Rd, Rdq, MaskR): Delete.
 509         (MOD_EVEX_0F3828_P_1, MOD_EVEX_0F382A_P_1_W_1,
 510         MOD_EVEX_0F3838_P_1, MOD_EVEX_0F383A_P_1_W_0,
 511         MOD_EVEX_0F387A_W_0, MOD_EVEX_0F387B_W_0,
 512         MOD_EVEX_0F387C): New enumerators.
 513         (reg_table): Use Edq for rdssp.
 514         (prefix_table): Use Edq for incssp.
 515         (mod_table): Use Rm for move to/from %tr. Use MaskE for kand*,
 516         kandn*, knot*, kor*, kxnor*, kxor*, kadd*, kunpck*, kortest*,
 517         ktest*, and kshift*. Use Edq / MaskE for kmov*.
 518         * i386-dis-evex.h: Reference mod_table[] for opcode 0F387C.
 519         * i386-dis-evex-mod.h: New entries for opcodes 0F3828, 0F382A,
 520         0F3838, 0F383A, 0F387A, 0F387B, and 0F387C.
 521         * i386-dis-evex-prefix.h: Reference mod_table[] for opcodes
 522         0F3828_P_1 and 0F3838_P_1.
 523         * i386-dis-evex-w.h: Reference mod_table[] for opcodes
 524         0F382A_P_1, 0F383A_P_1, 0F387A, and 0F387B.
 525
 526 2020-07-14  Jan Beulich  <jbeulich@suse.com>
 527
 528         * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_3,
 529         PREFIX_0FAE_REG_5_MOD_0, PREFIX_0FC3_MOD_0, PREFIX_0F38C8,
 530         PREFIX_0F38C9, PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC,
 531         PREFIX_0F38CD, PREFIX_0F38F9, PREFIX_0F3ACC, PREFIX_VEX_0F77,
 532         PREFIX_VEX_0F38F2, PREFIX_VEX_0F38F3_REG_1,
 533         PREFIX_VEX_0F38F3_REG_2, PREFIX_VEX_0F38F3_REG_3): Delete.
 534         (MOD_0F38F9_PREFIX_0, VEX_LEN_0F77_P_0, VEX_LEN_0F38F2_P_0,
 535         VEX_LEN_0F38F3_R_1_P_0, VEX_LEN_0F38F3_R_2_P_0,
 536         VEX_LEN_0F38F3_R_3_P_0): Rename to ...
 537         (MOD_0F38F9, VEX_LEN_0F77, VEX_LEN_0F38F2, VEX_LEN_0F38F3_R_1,
 538         VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3): ... these respectively.
 539         (reg_table, prefix_table, three_byte_table, vex_table,
 540         vex_len_table, mod_table, rm_table): Replace / remove respective
 541         entries.
 542         (intel_operand_size, OP_E_register, OP_G): Avoid undue setting
 543         of PREFIX_DATA in used_prefixes.
 544
 545 2020-07-14  Jan Beulich  <jbeulich@suse.com>
 546
 547         * i386-dis.c (MOD_VEX_0F3A30_L_0_W_0, MOD_VEX_0F3A30_L_0_W_1,
 548         MOD_VEX_0F3A31_L_0_W_0, MOD_VEX_0F3A31_L_0_W_1,
 549         MOD_VEX_0F3A32_L_0_W_0, MOD_VEX_0F3A32_L_0_W_1,
 550         MOD_VEX_0F3A33_L_0_W_0, MOD_VEX_0F3A33_L_0_W_1): Replace by ...
 551         (MOD_VEX_0F3A30_L_0, MOD_VEX_0F3A31_L_0,
 552         MOD_VEX_0F3A32_L_0, MOD_VEX_0F3A33_L_0): ... these.
 553         (VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
 554         VEX_W_0F3A33_L_0): Delete.
 555         (dis386): Adjust "BW" description.
 556         (vex_len_table): Refer to mod_table[] for opcodes 0F3A30,
 557         0F3A31, 0F3A32, and 0F3A33.
 558         (vex_w_table): Delete opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
 559         entries.
 560         (mod_table): Replace opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
 561         entries.
 562
 563 2020-07-14  Jan Beulich  <jbeulich@suse.com>
 564
 565         * i386-dis.c (PREFIX_0F6C, PREFIX_0F6D, PREFIX_0F73_REG_3,
 566         PREFIX_0F73_REG_7, PREFIX_0F3810, PREFIX_0F3814, PREFIX_0F3815,
 567         PREFIX_0F3817, PREFIX_0F3820, PREFIX_0F3821, PREFIX_0F3822,
 568         PREFIX_0F3823, PREFIX_0F3824, PREFIX_0F3825, PREFIX_0F3828,
 569         PREFIX_0F3829, PREFIX_0F382A, PREFIX_0F382B, PREFIX_0F3830,
 570         PREFIX_0F3831, PREFIX_0F3832, PREFIX_0F3833, PREFIX_0F3834,
 571         PREFIX_0F3835, PREFIX_0F3837, PREFIX_0F3838, PREFIX_0F3839,
 572         PREFIX_0F383A, PREFIX_0F383B, PREFIX_0F383C, PREFIX_0F383D,
 573         PREFIX_0F383E, PREFIX_0F383F, PREFIX_0F3840, PREFIX_0F3841,
 574         PREFIX_0F3880, PREFIX_0F3881, PREFIX_0F3882, PREFIX_0F38CF,
 575         PREFIX_0F38DB, PREFIX_0F38DC, PREFIX_0F38DD, PREFIX_0F38DE,
 576         PREFIX_0F38DF, PREFIX_0F38F5, PREFIX_0F3A08, PREFIX_0F3A09,
 577         PREFIX_0F3A0A, PREFIX_0F3A0B, PREFIX_0F3A0C, PREFIX_0F3A0D,
 578         PREFIX_0F3A0E, PREFIX_0F3A14, PREFIX_0F3A15, PREFIX_0F3A16,
 579         PREFIX_0F3A17, PREFIX_0F3A20, PREFIX_0F3A21, PREFIX_0F3A22,
 580         PREFIX_0F3A40, PREFIX_0F3A41, PREFIX_0F3A42, PREFIX_0F3A44,
 581         PREFIX_0F3A60, PREFIX_0F3A61, PREFIX_0F3A62, PREFIX_0F3A63,
 582         PREFIX_0F3ACE, PREFIX_0F3ACF, PREFIX_0F3ADF, PREFIX_VEX_0F60,
 583         PREFIX_VEX_0F61, PREFIX_VEX_0F62, PREFIX_VEX_0F63,
 584         PREFIX_VEX_0F64, PREFIX_VEX_0F65, PREFIX_VEX_0F66,
 585         PREFIX_VEX_0F67, PREFIX_VEX_0F68, PREFIX_VEX_0F69,
 586         PREFIX_VEX_0F6A, PREFIX_VEX_0F6B, PREFIX_VEX_0F6C,
 587         PREFIX_VEX_0F6D, PREFIX_VEX_0F6E, PREFIX_VEX_0F71_REG_2,
 588         PREFIX_VEX_0F71_REG_4, PREFIX_VEX_0F71_REG_6,
 589         PREFIX_VEX_0F72_REG_2, PREFIX_VEX_0F72_REG_4,
 590         PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
 591         PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
 592         PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74,
 593         PREFIX_VEX_0F75, PREFIX_VEX_0F76, PREFIX_VEX_0FC4,
 594         PREFIX_VEX_0FC5, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
 595         PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
 596         PREFIX_VEX_0FD6, PREFIX_VEX_0FD7, PREFIX_VEX_0FD8,
 597         PREFIX_VEX_0FD9, PREFIX_VEX_0FDA, PREFIX_VEX_0FDB,
 598         PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
 599         PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
 600         PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
 601         PREFIX_VEX_0FE5, PREFIX_VEX_0FE7, PREFIX_VEX_0FE8,
 602         PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
 603         PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
 604         PREFIX_VEX_0FEF, PREFIX_VEX_0FF1, PREFIX_VEX_0FF2,
 605         PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
 606         PREFIX_VEX_0FF6, PREFIX_VEX_0FF7, PREFIX_VEX_0FF8,
 607         PREFIX_VEX_0FF9, PREFIX_VEX_0FFA, PREFIX_VEX_0FFB,
 608         PREFIX_VEX_0FFC, PREFIX_VEX_0FFD, PREFIX_VEX_0FFE,
 609         PREFIX_VEX_0F3800, PREFIX_VEX_0F3801, PREFIX_VEX_0F3802,
 610         PREFIX_VEX_0F3803, PREFIX_VEX_0F3804, PREFIX_VEX_0F3805,
 611         PREFIX_VEX_0F3806, PREFIX_VEX_0F3807, PREFIX_VEX_0F3808,
 612         PREFIX_VEX_0F3809, PREFIX_VEX_0F380A, PREFIX_VEX_0F380B,
 613         PREFIX_VEX_0F380C, PREFIX_VEX_0F380D, PREFIX_VEX_0F380E,
 614         PREFIX_VEX_0F380F, PREFIX_VEX_0F3813, PREFIX_VEX_0F3816,
 615         PREFIX_VEX_0F3817, PREFIX_VEX_0F3818, PREFIX_VEX_0F3819,
 616         PREFIX_VEX_0F381A, PREFIX_VEX_0F381C, PREFIX_VEX_0F381D,
 617         PREFIX_VEX_0F381E, PREFIX_VEX_0F3820, PREFIX_VEX_0F3821,
 618         PREFIX_VEX_0F3822, PREFIX_VEX_0F3823, PREFIX_VEX_0F3824,
 619         PREFIX_VEX_0F3825, PREFIX_VEX_0F3828, PREFIX_VEX_0F3829,
 620         PREFIX_VEX_0F382A, PREFIX_VEX_0F382B, PREFIX_VEX_0F382C,
 621         PREFIX_VEX_0F382D, PREFIX_VEX_0F382E, PREFIX_VEX_0F382F,
 622         PREFIX_VEX_0F3830, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
 623         PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
 624         PREFIX_VEX_0F3836, PREFIX_VEX_0F3837, PREFIX_VEX_0F3838,
 625         PREFIX_VEX_0F3839, PREFIX_VEX_0F383A, PREFIX_VEX_0F383B,
 626         PREFIX_VEX_0F383C, PREFIX_VEX_0F383D, PREFIX_VEX_0F383E,
 627         PREFIX_VEX_0F383F, PREFIX_VEX_0F3840, PREFIX_VEX_0F3841,
 628         PREFIX_VEX_0F3845, PREFIX_VEX_0F3846, PREFIX_VEX_0F3847,
 629         PREFIX_VEX_0F3858, PREFIX_VEX_0F3859, PREFIX_VEX_0F385A,
 630         PREFIX_VEX_0F3878, PREFIX_VEX_0F3879, PREFIX_VEX_0F388C,
 631         PREFIX_VEX_0F388E, PREFIX_VEX_0F3890, PREFIX_VEX_0F3891,
 632         PREFIX_VEX_0F3892, PREFIX_VEX_0F3893, PREFIX_VEX_0F3896,
 633         PREFIX_VEX_0F3897, PREFIX_VEX_0F3898, PREFIX_VEX_0F3899,
 634         PREFIX_VEX_0F389A, PREFIX_VEX_0F389B, PREFIX_VEX_0F389C,
 635         PREFIX_VEX_0F389D, PREFIX_VEX_0F389E, PREFIX_VEX_0F389F,
 636         PREFIX_VEX_0F38A6, PREFIX_VEX_0F38A7, PREFIX_VEX_0F38A8,
 637         PREFIX_VEX_0F38A9, PREFIX_VEX_0F38AA, PREFIX_VEX_0F38AB,
 638         PREFIX_VEX_0F38AC, PREFIX_VEX_0F38AD, PREFIX_VEX_0F38AE,
 639         PREFIX_VEX_0F38AF, PREFIX_VEX_0F38B6, PREFIX_VEX_0F38B7,
 640         PREFIX_VEX_0F38B8, PREFIX_VEX_0F38B9, PREFIX_VEX_0F38BA,
 641         PREFIX_VEX_0F38BB, PREFIX_VEX_0F38BC, PREFIX_VEX_0F38BD,
 642         PREFIX_VEX_0F38BE, PREFIX_VEX_0F38BF, PREFIX_VEX_0F38CF,
 643         PREFIX_VEX_0F38DB, PREFIX_VEX_0F38DC, PREFIX_VEX_0F38DD,
 644         PREFIX_VEX_0F38DE, PREFIX_VEX_0F38DF, PREFIX_VEX_0F3A00,
 645         PREFIX_VEX_0F3A01, PREFIX_VEX_0F3A02, PREFIX_VEX_0F3A04,
 646         PREFIX_VEX_0F3A05, PREFIX_VEX_0F3A06, PREFIX_VEX_0F3A08,
 647         PREFIX_VEX_0F3A09, PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B,
 648         PREFIX_VEX_0F3A0C, PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E,
 649         PREFIX_VEX_0F3A0F, PREFIX_VEX_0F3A14, PREFIX_VEX_0F3A15,
 650         PREFIX_VEX_0F3A16, PREFIX_VEX_0F3A17, PREFIX_VEX_0F3A18,
 651         PREFIX_VEX_0F3A19, PREFIX_VEX_0F3A1D, PREFIX_VEX_0F3A20,
 652         PREFIX_VEX_0F3A21, PREFIX_VEX_0F3A22, PREFIX_VEX_0F3A30,
 653         PREFIX_VEX_0F3A31, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3A33,
 654         PREFIX_VEX_0F3A38, PREFIX_VEX_0F3A39, PREFIX_VEX_0F3A40,
 655         PREFIX_VEX_0F3A41, PREFIX_VEX_0F3A42, PREFIX_VEX_0F3A44,
 656         PREFIX_VEX_0F3A46, PREFIX_VEX_0F3A48, PREFIX_VEX_0F3A49,
 657         PREFIX_VEX_0F3A4A, PREFIX_VEX_0F3A4B, PREFIX_VEX_0F3A4C,
 658         PREFIX_VEX_0F3A5C, PREFIX_VEX_0F3A5D, PREFIX_VEX_0F3A5E,
 659         PREFIX_VEX_0F3A5F, PREFIX_VEX_0F3A60, PREFIX_VEX_0F3A61,
 660         PREFIX_VEX_0F3A62, PREFIX_VEX_0F3A63, PREFIX_VEX_0F3A68,
 661         PREFIX_VEX_0F3A69, PREFIX_VEX_0F3A6A, PREFIX_VEX_0F3A6B,
 662         PREFIX_VEX_0F3A6C, PREFIX_VEX_0F3A6D, PREFIX_VEX_0F3A6E,
 663         PREFIX_VEX_0F3A6F, PREFIX_VEX_0F3A78, PREFIX_VEX_0F3A79,
 664         PREFIX_VEX_0F3A7A, PREFIX_VEX_0F3A7B, PREFIX_VEX_0F3A7C,
 665         PREFIX_VEX_0F3A7D, PREFIX_VEX_0F3A7E, PREFIX_VEX_0F3A7F,
 666         PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF, PREFIX_VEX_0F3ADF,
 667         PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F66,
 668         PREFIX_EVEX_0F6E, PREFIX_EVEX_0F71_REG_2,
 669         PREFIX_EVEX_0F71_REG_4, PREFIX_EVEX_0F71_REG_6,
 670         PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
 671         PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
 672         PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
 673         PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_6,
 674         PREFIX_EVEX_0F73_REG_7, PREFIX_EVEX_0F74, PREFIX_EVEX_0F75,
 675         PREFIX_EVEX_0F76, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5,
 676         PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF,
 677         PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB,
 678         PREFIX_EVEX_0FEF, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3816,
 679         PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B,
 680         PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F382C,
 681         PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
 682         PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F,
 683         PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843,
 684         PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846,
 685         PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D,
 686         PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3850,
 687         PREFIX_EVEX_0F3851, PREFIX_EVEX_0F3854, PREFIX_EVEX_0F3855,
 688         PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B,
 689         PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863, PREFIX_EVEX_0F3864,
 690         PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3866, PREFIX_EVEX_0F3870,
 691         PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3875,
 692         PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387A,
 693         PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387D,
 694         PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3883,
 695         PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
 696         PREFIX_EVEX_0F388B, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F388F,
 697         PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892,
 698         PREFIX_EVEX_0F3893, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1,
 699         PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38B4,
 700         PREFIX_EVEX_0F38B5, PREFIX_EVEX_0F38C4,
 701         PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2,
 702         PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6,
 703         PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2,
 704         PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6,
 705         PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB,
 706         PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00,
 707         PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A05,
 708         PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A,
 709         PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15,
 710         PREFIX_EVEX_0F3A16, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18,
 711         PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B,
 712         PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A20,
 713         PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A22, PREFIX_EVEX_0F3A23,
 714         PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27,
 715         PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A,
 716         PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F,
 717         PREFIX_EVEX_0F3A42, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A50,
 718         PREFIX_EVEX_0F3A51, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55,
 719         PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66,
 720         PREFIX_EVEX_0F3A67, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
 721         PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73): Delete.
 722         (MOD_0F382A_PREFIX_2, MOD_0F38F5_PREFIX_2,
 723         MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
 724         MOD_VEX_0F381A_PREFIX_2, MOD_VEX_0F382A_PREFIX_2,
 725         MOD_VEX_0F382C_PREFIX_2, MOD_VEX_0F382D_PREFIX_2,
 726         MOD_VEX_0F382E_PREFIX_2, MOD_VEX_0F382F_PREFIX_2,
 727         MOD_VEX_0F385A_PREFIX_2, MOD_VEX_0F388C_PREFIX_2,
 728         MOD_VEX_0F388E_PREFIX_2, MOD_VEX_W_0_0F3A30_P_2_LEN_0,
 729         MOD_VEX_W_1_0F3A30_P_2_LEN_0, MOD_VEX_W_0_0F3A31_P_2_LEN_0,
 730         MOD_VEX_W_1_0F3A31_P_2_LEN_0, MOD_VEX_W_0_0F3A32_P_2_LEN_0,
 731         MOD_VEX_W_1_0F3A32_P_2_LEN_0, MOD_VEX_W_0_0F3A33_P_2_LEN_0,
 732         MOD_VEX_W_1_0F3A33_P_2_LEN_0, MOD_EVEX_0F381A_P_2_W_0,
 733         MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
 734         MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
 735         MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0,
 736         MOD_EVEX_0F385B_P_2_W_1, VEX_LEN_0F6E_P_2,
 737         VEX_LEN_0FC4_P_2, VEX_LEN_0FC5_P_2, VEX_LEN_0FD6_P_2,
 738         VEX_LEN_0FF7_P_2, VEX_LEN_0F3816_P_2, VEX_LEN_0F3819_P_2,
 739         VEX_LEN_0F381A_P_2_M_0, VEX_LEN_0F3836_P_2,
 740         VEX_LEN_0F3841_P_2, VEX_LEN_0F385A_P_2_M_0,
 741         VEX_LEN_0F38DB_P_2, VEX_LEN_0F3A00_P_2, VEX_LEN_0F3A01_P_2,
 742         VEX_LEN_0F3A06_P_2, VEX_LEN_0F3A14_P_2, VEX_LEN_0F3A15_P_2,
 743         VEX_LEN_0F3A16_P_2, VEX_LEN_0F3A17_P_2, VEX_LEN_0F3A18_P_2,
 744         VEX_LEN_0F3A19_P_2, VEX_LEN_0F3A20_P_2, VEX_LEN_0F3A21_P_2,
 745         VEX_LEN_0F3A22_P_2, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A31_P_2,
 746         VEX_LEN_0F3A32_P_2, VEX_LEN_0F3A33_P_2, VEX_LEN_0F3A38_P_2,
 747         VEX_LEN_0F3A39_P_2, VEX_LEN_0F3A41_P_2, VEX_LEN_0F3A46_P_2,
 748         VEX_LEN_0F3A60_P_2, VEX_LEN_0F3A61_P_2, VEX_LEN_0F3A62_P_2,
 749         VEX_LEN_0F3A63_P_2, VEX_LEN_0F3ADF_P_2, EVEX_LEN_0F6E_P_2,
 750         EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2, EVEX_LEN_0FD6_P_2,
 751         EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3819_P_2_W_0,
 752         EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0_M_0,
 753         EVEX_LEN_0F381A_P_2_W_1_M_0, EVEX_LEN_0F381B_P_2_W_0_M_0,
 754         EVEX_LEN_0F381B_P_2_W_1_M_0, EVEX_LEN_0F3836_P_2,
 755         EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
 756         EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0,
 757         EVEX_LEN_0F38C6_REG_1_PREFIX_2, EVEX_LEN_0F38C6_REG_2_PREFIX_2,
 758         EVEX_LEN_0F38C6_REG_5_PREFIX_2, EVEX_LEN_0F38C6_REG_6_PREFIX_2,
 759         EVEX_LEN_0F38C7_R_1_P_2_W_0, EVEX_LEN_0F38C7_R_1_P_2_W_1,
 760         EVEX_LEN_0F38C7_R_2_P_2_W_0, EVEX_LEN_0F38C7_R_2_P_2_W_1,
 761         EVEX_LEN_0F38C7_R_5_P_2_W_0, EVEX_LEN_0F38C7_R_5_P_2_W_1,
 762         EVEX_LEN_0F38C7_R_6_P_2_W_0, EVEX_LEN_0F38C7_R_6_P_2_W_1,
 763         EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1,
 764         EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
 765         EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A18_P_2_W_0,
 766         EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
 767         EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
 768         EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
 769         EVEX_LEN_0F3A1B_P_2_W_1, EVEX_LEN_0F3A20_P_2,
 770         EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2,
 771         EVEX_LEN_0F3A23_P_2_W_0, EVEX_LEN_0F3A23_P_2_W_1,
 772         EVEX_LEN_0F3A38_P_2_W_0, EVEX_LEN_0F3A38_P_2_W_1,
 773         EVEX_LEN_0F3A39_P_2_W_0, EVEX_LEN_0F3A39_P_2_W_1,
 774         EVEX_LEN_0F3A3A_P_2_W_0, EVEX_LEN_0F3A3A_P_2_W_1,
 775         EVEX_LEN_0F3A3B_P_2_W_0, EVEX_LEN_0F3A3B_P_2_W_1,
 776         EVEX_LEN_0F3A43_P_2_W_0, EVEX_LEN_0F3A43_P_2_W_1
 777         VEX_W_0F380C_P_2, VEX_W_0F380D_P_2, VEX_W_0F380E_P_2,
 778         VEX_W_0F380F_P_2, VEX_W_0F3813_P_2, VEX_W_0F3816_P_2,
 779         VEX_W_0F3818_P_2, VEX_W_0F3819_P_2,
 780         VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F382C_P_2_M_0,
 781         VEX_W_0F382D_P_2_M_0, VEX_W_0F382E_P_2_M_0,
 782         VEX_W_0F382F_P_2_M_0, VEX_W_0F3836_P_2,
 783         VEX_W_0F3846_P_2, VEX_W_0F3858_P_2, VEX_W_0F3859_P_2,
 784         VEX_W_0F385A_P_2_M_0_L_0, VEX_W_0F3878_P_2,
 785         VEX_W_0F3879_P_2, VEX_W_0F38CF_P_2, VEX_W_0F3A00_P_2,
 786         VEX_W_0F3A01_P_2, VEX_W_0F3A02_P_2, VEX_W_0F3A04_P_2,
 787         VEX_W_0F3A05_P_2, VEX_W_0F3A06_P_2_L_0,
 788         VEX_W_0F3A18_P_2_L_0, VEX_W_0F3A19_P_2_L_0,
 789         VEX_W_0F3A1D_P_2, VEX_W_0F3A30_P_2_LEN_0,
 790         VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0,
 791         VEX_W_0F3A33_P_2_LEN_0, VEX_W_0F3A38_P_2_L_0,
 792         VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0,
 793         VEX_W_0F3A4A_P_2, VEX_W_0F3A4B_P_2, VEX_W_0F3A4C_P_2,
 794         VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2, EVEX_W_0F66_P_2,
 795         EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2,
 796         EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2,
 797         EVEX_W_0F76_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE7_P_2,
 798         EVEX_W_0F380D_P_2, EVEX_W_0F3819_P_2,
 799         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2,
 800         EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
 801         EVEX_W_0F3837_P_2, EVEX_W_0F3859_P_2,
 802         EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2,
 803         EVEX_W_0F3870_P_2, EVEX_W_0F387A_P_2,
 804         EVEX_W_0F387B_P_2, EVEX_W_0F3883_P_2,
 805         EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2,
 806         EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
 807         EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2,
 808         EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2,
 809         EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
 810         EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
 811         EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2,
 812         EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2,
 813         EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
 814         EVEX_W_0F3A1B_P_2, EVEX_W_0F3A21_P_2,
 815         EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2,
 816         EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
 817         EVEX_W_0F3A3B_P_2, EVEX_W_0F3A42_P_2,
 818         EVEX_W_0F3A43_P_2, EVEX_W_0F3A70_P_2,
 819         EVEX_W_0F3A72_P_2): Rename to ...
 820         (MOD_0F382A, MOD_0F38F5, MOD_VEX_0FD7, MOD_VEX_0FE7,
 821         MOD_VEX_0F381A, MOD_VEX_0F382A, MOD_VEX_0F382C, MOD_VEX_0F382D,
 822         MOD_VEX_0F382E, MOD_VEX_0F382F, MOD_VEX_0F385A, MOD_VEX_0F388C,
 823         MOD_VEX_0F388E, MOD_VEX_0F3A30_L_0_W_0,
 824         MOD_VEX_0F3A30_L_0_W_1, MOD_VEX_0F3A31_L_0_W_0,
 825         MOD_VEX_0F3A31_L_0_W_1, MOD_VEX_0F3A32_L_0_W_0,
 826         MOD_VEX_0F3A32_L_0_W_1, MOD_VEX_0F3A33_L_0_W_0,
 827         MOD_VEX_0F3A33_L_0_W_1, MOD_EVEX_0F381A_W_0,
 828         MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0, MOD_EVEX_0F381B_W_1,
 829         MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1, MOD_EVEX_0F385B_W_0,
 830         MOD_EVEX_0F385B_W_1, VEX_LEN_0F6E, VEX_LEN_0FC4, VEX_LEN_0FC5,
 831         VEX_LEN_0FD6, VEX_LEN_0FF7, VEX_LEN_0F3816, VEX_LEN_0F3819,
 832         VEX_LEN_0F381A_M_0, VEX_LEN_0F3836, VEX_LEN_0F3841,
 833         VEX_LEN_0F385A_M_0, VEX_LEN_0F38DB, VEX_LEN_0F3A00,
 834         VEX_LEN_0F3A01, VEX_LEN_0F3A06, VEX_LEN_0F3A14, VEX_LEN_0F3A15,
 835         VEX_LEN_0F3A16, VEX_LEN_0F3A17, VEX_LEN_0F3A18, VEX_LEN_0F3A19,
 836         VEX_LEN_0F3A20, VEX_LEN_0F3A21, VEX_LEN_0F3A22, VEX_LEN_0F3A30,
 837         VEX_LEN_0F3A31, VEX_LEN_0F3A32, VEX_LEN_0F3A33, VEX_LEN_0F3A38,
 838         VEX_LEN_0F3A39, VEX_LEN_0F3A41, VEX_LEN_0F3A46, VEX_LEN_0F3A60,
 839         VEX_LEN_0F3A61, VEX_LEN_0F3A62, VEX_LEN_0F3A63, VEX_LEN_0F3ADF,
 840         EVEX_LEN_0F6E, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
 841         EVEX_LEN_0F3816, EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
 842         EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
 843         EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
 844         EVEX_LEN_0F3836, EVEX_LEN_0F385A_W_0_M_0,
 845         EVEX_LEN_0F385A_W_1_M_0, EVEX_LEN_0F385B_W_0_M_0,
 846         EVEX_LEN_0F385B_W_1_M_0, EVEX_LEN_0F38C6_R_1_M_0,
 847         EVEX_LEN_0F38C6_R_2_M_0, EVEX_LEN_0F38C6_R_5_M_0,
 848         EVEX_LEN_0F38C6_R_6_M_0, EVEX_LEN_0F38C7_R_1_M_0_W_0,
 849         EVEX_LEN_0F38C7_R_1_M_0_W_1, EVEX_LEN_0F38C7_R_2_M_0_W_0,
 850         EVEX_LEN_0F38C7_R_2_M_0_W_1, EVEX_LEN_0F38C7_R_5_M_0_W_0,
 851         EVEX_LEN_0F38C7_R_5_M_0_W_1, EVEX_LEN_0F38C7_R_6_M_0_W_0,
 852         EVEX_LEN_0F38C7_R_6_M_0_W_1, EVEX_LEN_0F3A00_W_1,
 853         EVEX_LEN_0F3A01_W_1, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
 854         EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A18_W_0,
 855         EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
 856         EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0,
 857         EVEX_LEN_0F3A1A_W_1, EVEX_LEN_0F3A1B_W_0,
 858         EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A20, EVEX_LEN_0F3A21_W_0,
 859         EVEX_LEN_0F3A22, EVEX_LEN_0F3A23_W_0, EVEX_LEN_0F3A23_W_1,
 860         EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
 861         EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1,
 862         EVEX_LEN_0F3A3A_W_0, EVEX_LEN_0F3A3A_W_1,
 863         EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
 864         EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1
 865         VEX_W_0F380C, VEX_W_0F380D, VEX_W_0F380E, VEX_W_0F380F,
 866         VEX_W_0F3813, VEX_W_0F3816_L_1, VEX_W_0F3818,
 867         VEX_W_0F3819_L_1, VEX_W_0F381A_M_0_L_1, VEX_W_0F382C_M_0,
 868         VEX_W_0F382D_M_0, VEX_W_0F382E_M_0, VEX_W_0F382F_M_0,
 869         VEX_W_0F3836, VEX_W_0F3846, VEX_W_0F3858, VEX_W_0F3859,
 870         VEX_W_0F385A_M_0_L_0, VEX_W_0F3878, VEX_W_0F3879,
 871         VEX_W_0F38CF, VEX_W_0F3A00_L_1, VEX_W_0F3A01_L_1,
 872         VEX_W_0F3A02, VEX_W_0F3A04, VEX_W_0F3A05, VEX_W_0F3A06_L_1,
 873         VEX_W_0F3A18_L_1, VEX_W_0F3A19_L_1, VEX_W_0F3A1D,
 874         VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
 875         VEX_W_0F3A33_L_0, VEX_W_0F3A38_L_1, VEX_W_0F3A39_L_1,
 876         VEX_W_0F3A46_L_1, VEX_W_0F3A4A, VEX_W_0F3A4B, VEX_W_0F3A4C,
 877         VEX_W_0F3ACE, VEX_W_0F3ACF, EVEX_W_0F66, EVEX_W_0F72_R_2,
 878         EVEX_W_0F72_R_6, EVEX_W_0F73_R_2, EVEX_W_0F73_R_6,
 879         EVEX_W_0F76, EVEX_W_0FD6_L_0, EVEX_W_0FE7, EVEX_W_0F380D,
 880         EVEX_W_0F3819, EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F381E,
 881         EVEX_W_0F381F, EVEX_W_0F3837, EVEX_W_0F3859, EVEX_W_0F385A,
 882         EVEX_W_0F385B, EVEX_W_0F3870, EVEX_W_0F387A, EVEX_W_0F387B,
 883         EVEX_W_0F3883, EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1,
 884         EVEX_W_0F38A3, EVEX_W_0F38C7_R_1_M_0,
 885         EVEX_W_0F38C7_R_2_M_0, EVEX_W_0F38C7_R_5_M_0,
 886         EVEX_W_0F38C7_R_6_M_0, EVEX_W_0F3A00, EVEX_W_0F3A01,
 887         EVEX_W_0F3A05, EVEX_W_0F3A08, EVEX_W_0F3A09, EVEX_W_0F3A0A,
 888         EVEX_W_0F3A0B, EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A,
 889         EVEX_W_0F3A1B, EVEX_W_0F3A21, EVEX_W_0F3A23, EVEX_W_0F3A38,
 890         EVEX_W_0F3A39, EVEX_W_0F3A3A, EVEX_W_0F3A3B, EVEX_W_0F3A42,
 891         EVEX_W_0F3A43, EVEX_W_0F3A70, EVEX_W_0F3A72): ... these
 892         respectively.
 893         (dis386_twobyte, three_byte_table, vex_table, vex_len_table,
 894         vex_w_table, mod_table): Replace / remove respective entries.
 895         (print_insn): Move up dp->prefix_requirement handling. Handle
 896         PREFIX_DATA.
 897         * i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-mod.h,
 898         i386-dis-evex-prefix.h, i386-dis-evex-reg.h, i386-dis-evex-w.h:
 899         Replace / remove respective entries.
 900
 901 2020-07-14  Jan Beulich  <jbeulich@suse.com>
 902
 903         * i386-dis.c (PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
 904         PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F): Delete.
 905         (prefix_table): Add EXxEVexS operand to vcvttss2si, vcvttsd2si,
 906         vcvtss2si, vcvtsd2si, vucomiss, and vucomisd table entries.
 907         Retain X macro and PREFIX_OPCODE use from tjhe EVEX table for
 908         the latter two.
 909         * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
 910         0F2C, 0F2D, 0F2E, and 0F2F.
 911         * i386-dis-evex-prefix.h: Delete opcode 0F2C, 0F2D, 0F2E, and
 912         0F2F table entries.
 913
 914 2020-07-14  Jan Beulich  <jbeulich@suse.com>
 915
 916         * i386-dis.c (OP_VexR, VexScalarR): New.
 917         (OP_EX_Vex, OP_XMM_Vex, EXdVexScalarS, EXqVexScalarS,
 918         XMVexScalar, d_scalar_swap_mode, q_scalar_swap_mode,
 919         need_vex_reg): Delete.
 920         (prefix_table): Replace VexScalar by VexScalarR and
 921         XMVexScalar by XMScalar for vmovss and vmovsd. Replace
 922         EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
 923         (vex_len_table): Replace EXqVexScalarS by EXqS.
 924         (get_valid_dis386): Don't set need_vex_reg.
 925         (print_insn): Don't initialize need_vex_reg.
 926         (intel_operand_size, OP_E_memory): Drop d_scalar_swap_mode and
 927         q_scalar_swap_mode cases.
 928         (OP_EX): Don't check for d_scalar_swap_mode and
 929         q_scalar_swap_mode.
 930         (OP_VEX): Done check need_vex_reg.
 931         * i386-dis-evex-w.h: Replace VexScalar by VexScalarR and
 932         XMVexScalar by XMScalar for vmovss and vmovsd. Replace
 933         EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
 934
 935 2020-07-14  Jan Beulich  <jbeulich@suse.com>
 936
 937         * i386-dis.c (Vex128, Vex256, vex128_mode, vex256_mode): Delete.
 938         (VEX_W_0F381A_P_2_M_0, VEX_W_0F385A_P_2_M_0, VEX_W_0F3A06_P_2,
 939         VEX_W_0F3A18_P_2, VEX_W_0F3A19_P_2, VEX_W_0F3A38_P_2,
 940         VEX_W_0F3A39_P_2, VEX_W_0F3A46_P_2): Rename to ...
 941         (VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F385A_P_2_M_0_L_0,
 942         VEX_W_0F3A06_P_2_L_0, VEX_W_0F3A18_P_2_L_0,
 943         VEX_W_0F3A19_P_2_L_0, VEX_W_0F3A38_P_2_L_0,
 944         VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0): ... respectively.
 945         (vex_table): Replace Vex128 by Vex.
 946         (vex_len_table): Likewise. Adjust referenced enum names.
 947         (vex_w_table): Replace Vex128 and Vex256 by Vex. Adjust
 948         referenced enum names.
 949         (OP_VEX): Drop vex128_mode and vex256_mode cases.
 950         * i386-dis-evex-len.h (evex_len_table): Replace Vex128 by Vex.
 951
 952 2020-07-14  Jan Beulich  <jbeulich@suse.com>
 953
 954         * i386-dis.c (dis386): "LW" description now applies to "DQ".
 955         (putop): Handle "DQ". Don't handle "LW" anymore.
 956         (prefix_table, mod_table): Replace %LW by %DQ.
 957         * i386-dis-evex-len.h, i386-dis-evex-prefix.h: Likewise.
 958
 959 2020-07-14  Jan Beulich  <jbeulich@suse.com>
 960
 961         * i386-dis.c (OP_E_memory): Move xmm_mw_mode, xmm_mb_mode,
 962         dqd_mode, xmm_md_mode, d_mode, d_swap_mode, and
 963         d_scalar_swap_mode case handling. Move shift adjsutment into
 964         the case its applicable to.
 965
 966 2020-07-14  Jan Beulich  <jbeulich@suse.com>
 967
 968         * i386-dis.c (EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2): Delete.
 969         (EXbScalar, EXwScalar): Fold to ...
 970         (EXbwUnit): ... this.
 971         (b_scalar_mode, w_scalar_mode): Fold to ...
 972         (bw_unit_mode): ... this.
 973         (intel_operand_size, OP_E_memory): Replace b_scalar_mode /
 974         w_scalar_mode handling by bw_unit_mode one.
 975         * i386-dis-evex-w.h: Move entries for opcodes 0F3862 and 0F3863
 976         ...
 977         * i386-dis-evex-prefix.h: ... here.
 978
 979 2020-07-14  Jan Beulich  <jbeulich@suse.com>
 980
 981         * i386-dis.c (PCMPESTR_Fixup): Delete.
 982         (dis386): Adjust "LQ" description.
 983         (prefix_table): Make %LQ apply to AT&T case only for cvtsi2ss,
 984         cvtsi2sd, ptwrite, vcvtsi2ss, and vcvtsi2sd. Replace use of
 985         PCMPESTR_Fixup by !%LQ and EXx for pcmpestrm, pcmpestri,
 986         vpcmpestrm, and vpcmpestri.
 987         (putop): Honor "cond" when handling LQ.
 988         * i386-dis-evex-prefix.h: Make %LQ apply to AT&T case only for
 989         vcvtsi2ss and vcvtusi2ss.
 990         * i386-dis-evex-w.h: Make %LQ apply to AT&T case only for
 991         vcvtsi2sd and vcvtusi2sd.
 992
 993 2020-07-14  Jan Beulich  <jbeulich@suse.com>
 994
 995         * i386-dis.c (VCMP_Fixup, VCMP): Delete.
 996         (simd_cmp_op): Add const.
 997         (vex_cmp_op): Move up and drop initial 8 entries. Add const.
 998         (CMP_Fixup): Handle VEX case.
 999         (prefix_table): Replace VCMP by CMP.
1000         * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Likewise.
1001
1002 2020-07-14  Jan Beulich  <jbeulich@suse.com>
1003
1004         * i386-dis.c (MOVBE_Fixup): Delete.
1005         (Mv): Define.
1006         (prefix_table): Use Mv for movbe entries.
1007
1008 2020-07-14  Jan Beulich  <jbeulich@suse.com>
1009
1010         * i386-dis.c (CRC32_Fixup): Delete.
1011         (prefix_table): Use Eb/Ev for crc32 entries.
1012
1013 2020-07-14  Jan Beulich  <jbeulich@suse.com>
1014
1015         * i386-dis.c (OP_E_register, OP_G, OP_REG, CRC32_Fixup):
1016         Conditionalize invocations of "USED_REX (0)".
1017
1018 2020-07-14  Jan Beulich  <jbeulich@suse.com>
1019
1020         * i386-dis.c (eBX, eCX, eDX, eSP, eBP, eSI, eDI, DL, BL, AH,
1021         CH, DH, BH, AX, DX): Delete.
1022         (OP_IMREG): Drop handling of eBX_reg, eCX_reg, eDX_reg, eSP_reg,
1023         eBP_reg, eSI_reg, eDI_reg, dl_reg, bl_reg, ah_reg, ch_reg,
1024         dh_reg, bh_reg, ax_reg, and dx_reg. Simplify what's left.
1025
1026 2020-07-10  Lili Cui  <lili.cui@intel.com>
1027
1028         * i386-dis.c (TMM): New.
1029         (EXtmm): Likewise.
1030         (VexTmm): Likewise.
1031         (MVexSIBMEM): Likewise.
1032         (tmm_mode): Likewise.
1033         (vex_sibmem_mode): Likewise.
1034         (REG_VEX_0F3849_X86_64_P_0_W_0_M_1): Likewise.
1035         (MOD_VEX_0F3849_X86_64_P_0_W_0): Likewise.
1036         (MOD_VEX_0F3849_X86_64_P_2_W_0): Likewise.
1037         (MOD_VEX_0F3849_X86_64_P_3_W_0): Likewise.
1038         (MOD_VEX_0F384B_X86_64_P_1_W_0): Likewise.
1039         (MOD_VEX_0F384B_X86_64_P_2_W_0): Likewise.
1040         (MOD_VEX_0F384B_X86_64_P_3_W_0): Likewise.
1041         (MOD_VEX_0F385C_X86_64_P_1_W_0): Likewise.
1042         (MOD_VEX_0F385E_X86_64_P_0_W_0): Likewise.
1043         (MOD_VEX_0F385E_X86_64_P_1_W_0): Likewise.
1044         (MOD_VEX_0F385E_X86_64_P_2_W_0): Likewise.
1045         (MOD_VEX_0F385E_X86_64_P_3_W_0): Likewise.
1046         (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0): Likewise.
1047         (PREFIX_VEX_0F3849_X86_64): Likewise.
1048         (PREFIX_VEX_0F384B_X86_64): Likewise.
1049         (PREFIX_VEX_0F385C_X86_64): Likewise.
1050         (PREFIX_VEX_0F385E_X86_64): Likewise.
1051         (X86_64_VEX_0F3849): Likewise.
1052         (X86_64_VEX_0F384B): Likewise.
1053         (X86_64_VEX_0F385C): Likewise.
1054         (X86_64_VEX_0F385E): Likewise.
1055         (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0): Likewise.
1056         (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0): Likewise.
1057         (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0): Likewise.
1058         (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0): Likewise.
1059         (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0): Likewise.
1060         (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0): Likewise.
1061         (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0): Likewise.
1062         (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0): Likewise.
1063         (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0): Likewise.
1064         (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0): Likewise.
1065         (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0): Likewise.
1066         (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0): Likewise.
1067         (VEX_W_0F3849_X86_64_P_0): Likewise.
1068         (VEX_W_0F3849_X86_64_P_2): Likewise.
1069         (VEX_W_0F3849_X86_64_P_3): Likewise.
1070         (VEX_W_0F384B_X86_64_P_1): Likewise.
1071         (VEX_W_0F384B_X86_64_P_2): Likewise.
1072         (VEX_W_0F384B_X86_64_P_3): Likewise.
1073         (VEX_W_0F385C_X86_64_P_1): Likewise.
1074         (VEX_W_0F385E_X86_64_P_0): Likewise.
1075         (VEX_W_0F385E_X86_64_P_1): Likewise.
1076         (VEX_W_0F385E_X86_64_P_2): Likewise.
1077         (VEX_W_0F385E_X86_64_P_3): Likewise.
1078         (names_tmm): Likewise.
1079         (att_names_tmm): Likewise.
1080         (intel_operand_size): Handle void_mode.
1081         (OP_XMM): Handle tmm_mode.
1082         (OP_EX): Likewise.
1083         (OP_VEX): Likewise.
1084         * i386-gen.c (cpu_flag_init): Add entries for CpuAMX_INT8,
1085         CpuAMX_BF16 and CpuAMX_TILE.
1086         (operand_type_shorthands): Add RegTMM.
1087         (operand_type_init): Likewise.
1088         (operand_types): Add Tmmword.
1089         (cpu_flag_init): Add CPU_AMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
1090         (cpu_flags): Add CpuAMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
1091         * i386-opc.h (CpuAMX_INT8): New.
1092         (CpuAMX_BF16): Likewise.
1093         (CpuAMX_TILE): Likewise.
1094         (SIBMEM): Likewise.
1095         (Tmmword): Likewise.
1096         (i386_cpu_flags): Add cpuamx_int8, cpuamx_bf16 and cpuamx_tile.
1097         (i386_opcode_modifier): Extend width of fields vexvvvv and sib.
1098         (i386_operand_type): Add tmmword.
1099         * i386-opc.tbl: Add AMX instructions.
1100         * i386-reg.tbl: Add AMX registers.
1101         * i386-init.h: Regenerated.
1102         * i386-tbl.h: Likewise.
1103
1104 2020-07-08  Jan Beulich  <jbeulich@suse.com>
1105
1106         * i386-dis.c (OP_LWPCB_E, OP_LWP_E): Delete.
1107         (REG_XOP_LWPCB, REG_XOP_LWP, REG_XOP_TBM_01, REG_XOP_TBM_02):
1108         Rename to ...
1109         (REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
1110         REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0): ... these
1111         respectively.
1112         (MOD_VEX_0FXOP_09_12, VEX_LEN_0FXOP_08_85, VEX_LEN_0FXOP_08_86,
1113         VEX_LEN_0FXOP_08_87, VEX_LEN_0FXOP_08_8E, VEX_LEN_0FXOP_08_8F,
1114         VEX_LEN_0FXOP_08_95, VEX_LEN_0FXOP_08_96, VEX_LEN_0FXOP_08_97,
1115         VEX_LEN_0FXOP_08_9E, VEX_LEN_0FXOP_08_9F, VEX_LEN_0FXOP_08_A3,
1116         VEX_LEN_0FXOP_08_A6, VEX_LEN_0FXOP_08_B6, VEX_LEN_0FXOP_08_C0,
1117         VEX_LEN_0FXOP_08_C1, VEX_LEN_0FXOP_08_C2, VEX_LEN_0FXOP_08_C3,
1118         VEX_LEN_0FXOP_09_01, VEX_LEN_0FXOP_09_02, VEX_LEN_0FXOP_09_12_M_1,
1119         VEX_LEN_0FXOP_09_90, VEX_LEN_0FXOP_09_91, VEX_LEN_0FXOP_09_92,
1120         VEX_LEN_0FXOP_09_93, VEX_LEN_0FXOP_09_94, VEX_LEN_0FXOP_09_95,
1121         VEX_LEN_0FXOP_09_96, VEX_LEN_0FXOP_09_97, VEX_LEN_0FXOP_09_98,
1122         VEX_LEN_0FXOP_09_99, VEX_LEN_0FXOP_09_9A, VEX_LEN_0FXOP_09_9B,
1123         VEX_LEN_0FXOP_09_C1, VEX_LEN_0FXOP_09_C2, VEX_LEN_0FXOP_09_C3,
1124         VEX_LEN_0FXOP_09_C6, VEX_LEN_0FXOP_09_C7, VEX_LEN_0FXOP_09_CB,
1125         VEX_LEN_0FXOP_09_D1, VEX_LEN_0FXOP_09_D2, VEX_LEN_0FXOP_09_D3,
1126         VEX_LEN_0FXOP_09_D6, VEX_LEN_0FXOP_09_D7, VEX_LEN_0FXOP_09_DB,
1127         VEX_LEN_0FXOP_09_E1, VEX_LEN_0FXOP_09_E2, VEX_LEN_0FXOP_09_E3,
1128         VEX_LEN_0FXOP_0A_12, VEX_W_0FXOP_08_85_L_0,
1129         VEX_W_0FXOP_08_86_L_0, VEX_W_0FXOP_08_87_L_0,
1130         VEX_W_0FXOP_08_8E_L_0, VEX_W_0FXOP_08_8F_L_0,
1131         VEX_W_0FXOP_08_95_L_0, VEX_W_0FXOP_08_96_L_0,
1132         VEX_W_0FXOP_08_97_L_0, VEX_W_0FXOP_08_9E_L_0,
1133         VEX_W_0FXOP_08_9F_L_0, VEX_W_0FXOP_08_A6_L_0,
1134         VEX_W_0FXOP_08_B6_L_0, VEX_W_0FXOP_08_C0_L_0,
1135         VEX_W_0FXOP_08_C1_L_0, VEX_W_0FXOP_08_C2_L_0,
1136         VEX_W_0FXOP_08_C3_L_0, VEX_W_0FXOP_08_CC_L_0,
1137         VEX_W_0FXOP_08_CD_L_0, VEX_W_0FXOP_08_CE_L_0,
1138         VEX_W_0FXOP_08_CF_L_0, VEX_W_0FXOP_08_EC_L_0,
1139         VEX_W_0FXOP_08_ED_L_0, VEX_W_0FXOP_08_EE_L_0,
1140         VEX_W_0FXOP_08_EF_L_0, VEX_W_0FXOP_09_C1_L_0,
1141         VEX_W_0FXOP_09_C2_L_0, VEX_W_0FXOP_09_C3_L_0,
1142         VEX_W_0FXOP_09_C6_L_0, VEX_W_0FXOP_09_C7_L_0,
1143         VEX_W_0FXOP_09_CB_L_0, VEX_W_0FXOP_09_D1_L_0,
1144         VEX_W_0FXOP_09_D2_L_0, VEX_W_0FXOP_09_D3_L_0,
1145         VEX_W_0FXOP_09_D6_L_0, VEX_W_0FXOP_09_D7_L_0,
1146         VEX_W_0FXOP_09_DB_L_0, VEX_W_0FXOP_09_E1_L_0,
1147         VEX_W_0FXOP_09_E2_L_0, VEX_W_0FXOP_09_E3_L_0): New enumerators.
1148         (reg_table): Re-order XOP entries. Adjust their operands.
1149         (xop_table): Replace 08_85, 08_86, 08_87, 08_8E, 08_8F, 08_95,
1150         08_96, 08_97, 08_9E, 08_9F, 08_A3, 08_A6, 08_B6, 08_C0, 08_C1,
1151         08_C2, 08_C3, 09_01, 09_02, 09_12, 09_90, 09_91, 09_92, 09_93,
1152         09_94, 09_95, 09_96, 09_97, 09_98, 09_99, 09_9A, 09_9B, 09_C1,
1153         09_C2, 09_C3, 09_C6, 09_C7, 09_CB, 09_D1, 09_D2, 09_D3, 09_D6,
1154         09_D7, 09_DB, 09_E1, 09_E2, 09_E3, and VEX_LEN_0FXOP_0A_12
1155         entries by references ...
1156         (vex_len_table): ... to resepctive new entries here. For several
1157         new and existing entries reference ...
1158         (vex_w_table): ... new entries here.
1159         (mod_table): New MOD_VEX_0FXOP_09_12 entry.
1160
1161 2020-07-08  Jan Beulich  <jbeulich@suse.com>
1162
1163         * i386-dis.c (XMVexScalarI4): Define.
1164         (VEX_LEN_0F3A6A_P_2, VEX_LEN_0F3A6B_P_2, VEX_LEN_0F3A6E_P_2,
1165         VEX_LEN_0F3A6F_P_2, VEX_LEN_0F3A7A_P_2, VEX_LEN_0F3A7B_P_2,
1166         VEX_LEN_0F3A7E_P_2, VEX_LEN_0F3A7F_P_2): Delete.
1167         (vex_len_table): Move scalar FMA4 entries ...
1168         (prefix_table): ... here.
1169         (OP_REG_VexI4): Handle scalar_mode.
1170         * i386-opc.tbl: Use VexLIG for scalar FMA4 insns.
1171         * i386-tbl.h: Re-generate.
1172
1173 2020-07-08  Jan Beulich  <jbeulich@suse.com>
1174
1175         * i386-dis.c (OP_Vex_2src_1, OP_Vex_2src_2, Vex_2src_1,
1176         Vex_2src_2): Delete.
1177         (OP_VexW, VexW): New.
1178         (xop_table): Use EXx for rotates by immediate. Use EXx and VexW
1179         for shifts and rotates by register.
1180
1181 2020-07-08  Jan Beulich  <jbeulich@suse.com>
1182
1183         * i386-dis.c (OP_EX_VexImmW, OP_XMM_VexW, EXVexImmW, XMVexW,
1184         VEX_W_0F3A48_P_2, VEX_W_0F3A49_P_2, vex_w_done, get_vex_imm8,
1185         OP_EX_VexReg): Delete.
1186         (OP_VexI4, VexI4): New.
1187         (vex_w_table): Move vpermil2ps and vpermil2pd entries ...
1188         (prefix_table): ... here.
1189         (print_insn): Drop setting of vex_w_done.
1190
1191 2020-07-08  Jan Beulich  <jbeulich@suse.com>
1192
1193         * i386-dis.c (OP_EX_VexW, EXVexW, EXdVexW, EXqVexW): Delete.
1194         (prefix_table, vex_len_table): Replace operands for FMA4 insns.
1195         (xop_table): Replace operands of 4-operand insns.
1196         (OP_REG_VexI4): Move VEX.W based operand swaping here.
1197
1198 2020-07-07  Claudiu Zissulescu  <claziss@synopsys.com>
1199
1200         * arc-opc.c (insert_rbd): New function.
1201         (RBD): Define.
1202         (RBDdup): Likewise.
1203         * arc-tbl.h (vadd2, vadd4h, vmac2h, vmpy2h, vsub4h): Update
1204         instructions.
1205
1206 2020-07-07  Jan Beulich  <jbeulich@suse.com>
1207
1208         * i386-dis.c (EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2,
1209         EVEX_W_0F3828_P_1, EVEX_W_0F3829_P_1, EVEX_W_0F3854_P_2,
1210         EVEX_W_0F3866_P_2, EVEX_W_0F3875_P_2, EVEX_W_0F387D_P_2,
1211         EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2, EVEX_W_0F3A3F_P_2):
1212         Delete.
1213         (putop): Handle "BW".
1214         * i386-dis-evex-w.h: Move entries for opcodes 0F3826, 0F3826,
1215         0F3828, 0F3829, 0F3854, 0F3866, 0F3875, 0F387D, 0F388D, 0F3A3E,
1216         and 0F3A3F ...
1217         * i386-dis-evex-prefix.h: ... here.
1218
1219 2020-07-06  Jan Beulich  <jbeulich@suse.com>
1220
1221         * i386-dis.c (VEX_LEN_0FXOP_09_80, VEX_LEN_0FXOP_09_81): Delete.
1222         (VEX_LEN_0FXOP_09_82_W_0, VEX_LEN_0FXOP_09_83_W_0,
1223         VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81, VEX_W_0FXOP_09_82,
1224         VEX_W_0FXOP_09_83): New enumerators.
1225         (xop_table): Reference the above.
1226         (vex_len_table): Replace vfrczp* entries by vfrczs* ones.
1227         (vex_w_table): New VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81,
1228         VEX_W_0FXOP_09_82, and VEX_W_0FXOP_09_83 entries.
1229         (get_valid_dis386): Return bad_opcode for XOP.PP != 0.
1230
1231 2020-07-06  Jan Beulich  <jbeulich@suse.com>
1232
1233         * i386-dis.c (EVEX_W_0F3838_P_1,
1234         EVEX_W_0F3839_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3855_P_2,
1235         EVEX_W_0F3868_P_3, EVEX_W_0F3871_P_2, EVEX_W_0F3873_P_2,
1236         EVEX_W_0F3A50_P_2, EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2,
1237         EVEX_W_0F3A57_P_2, EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2,
1238         EVEX_W_0F3A71_P_2, EVEX_W_0F3A73_P_2): Delete.
1239         (putop): Centralize management of last[]. Delete SAVE_LAST.
1240         * i386-dis-evex-w.h: Move entries for opcodes 0F3838, 0F3839,
1241         0F3840, 0F3855, 0F3868, 0F3871, 0F3873, 0F3A50, 0F3A51, 0F3A56,
1242         0F3A57, 0F3A66, 0F3A67, 0F3A71, and 0F3A73 ...
1243         * i386-dis-evex-prefix.h: here.
1244
1245 2020-07-06  Jan Beulich  <jbeulich@suse.com>
1246
1247         * i386-dis.c (MOD_EVEX_0F381A_P_2_W_0, MOD_EVEX_0F381A_P_2_W_1,
1248         MOD_EVEX_0F381B_P_2_W_0, MOD_EVEX_0F381B_P_2_W_1,
1249         MOD_EVEX_0F385A_P_2_W_0, MOD_EVEX_0F385A_P_2_W_1,
1250         MOD_EVEX_0F385B_P_2_W_0, MOD_EVEX_0F385B_P_2_W_1): New
1251         enumerators.
1252         (EVEX_LEN_0F381A_P_2_W_0, EVEX_LEN_0F381A_P_2_W_1,
1253         EVEX_LEN_0F381B_P_2_W_0, EVEX_LEN_0F381B_P_2_W_1,
1254         EVEX_LEN_0F385A_P_2_W_0, EVEX_LEN_0F385A_P_2_W_1,
1255         EVEX_LEN_0F385B_P_2_W_0, EVEX_LEN_0F385B_P_2_W_1): Rename to ...
1256         (EVEX_LEN_0F381A_P_2_W_0_M_0, EVEX_LEN_0F381A_P_2_W_1_M_0,
1257         EVEX_LEN_0F381B_P_2_W_0_M_0, EVEX_LEN_0F381B_P_2_W_1_M_0,
1258         EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
1259         EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0): ...
1260         these, respectively.
1261         * i386-dis-evex-len.h: Adjust comments.
1262         * i386-dis-evex-mod.h: New MOD_EVEX_0F381A_P_2_W_0,
1263         MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
1264         MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
1265         MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0, and
1266         MOD_EVEX_0F385B_P_2_W_1 table entries.
1267         * i386-dis-evex-w.h: Reference mod_table[] for
1268         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2, and
1269         EVEX_W_0F385B_P_2.
1270
1271 2020-07-06  Jan Beulich  <jbeulich@suse.com>
1272
1273         * i386-dis-evex-len.h (vbroadcastf32x8, vbroadcasti32x8,
1274         vinsertf32x8, vinsertf64x4, vextractf32x8, vextractf64x4): Use
1275         EXymm.
1276         (vinserti32x8, vinserti64x4, vextracti32x8, vextracti64x4):
1277         Likewise. Mark 256-bit entries invalid.
1278
1279 2020-07-06  Jan Beulich  <jbeulich@suse.com>
1280
1281         * i386-dis.c (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
1282         PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
1283         PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
1284         PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
1285         PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
1286         PREFIX_EVEX_0F382B): Delete.
1287         (EVEX_W_0F62_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6B_P_2,
1288         EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0FD2_P_2,
1289         EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FF2_P_2,
1290         EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2,
1291         EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F382B_P_2): Rename
1292         to ...
1293         (EVEX_W_0F62, EVEX_W_0F6A, EVEX_W_0F6B, EVEX_W_0F6C,
1294         EVEX_W_0F6D, EVEX_W_0FD2, EVEX_W_0FD3, EVEX_W_0FD4,
1295         EVEX_W_0FF2, EVEX_W_0FF3, EVEX_W_0FF4, EVEX_W_0FFA,
1296         EVEX_W_0FFB, EVEX_W_0FFE, EVEX_W_0F382B): ... these
1297         respectively.
1298         * i386-dis-evex.h (evex_table): Reference VEX_W table entries
1299         for opcodes 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4,
1300         0FF2, 0FF3, 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
1301         * i386-dis-evex-prefix.h (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
1302         PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
1303         PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
1304         PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
1305         PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
1306         PREFIX_EVEX_0F382B): Remove table entries.
1307         * i386-dis-evex-w.h: Reference VEX table entries for opcodes
1308         0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4, 0FF2, 0FF3,
1309         0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
1310
1311 2020-07-06  Jan Beulich  <jbeulich@suse.com>
1312
1313         * i386-dis.c (EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3836_P_2,
1314         EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1): New
1315         enumerators.
1316         * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0F3816_P_2,
1317         EVEX_LEN_0F3836_P_2, EVEX_LEN_0F3A00_P_2_W_1, and
1318         EVEX_LEN_0F3A01_P_2_W_1 table entries.
1319         * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
1320         entries.
1321
1322 2020-07-06  Jan Beulich  <jbeulich@suse.com>
1323
1324         * i386-dis.c (EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2,
1325         EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
1326         EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
1327         EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2): New enumerators.
1328         * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0FC4_P_2,
1329         EVEX_LEN_0FC5_P_2, EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2,
1330         EVEX_LEN_0F3A16_P_2, EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
1331         EVEX_LEN_0F3A21_P_2_W_0, and EVEX_LEN_0F3A22_P_2 table entries.
1332         * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
1333         entries.
1334
1335 2020-07-06  Jan Beulich  <jbeulich@suse.com>
1336
1337         * i386-dis.c (PREFIX_EVEX_0F3A1D, EVEX_W_0F3A1D_P_2): Delete.
1338         (VEX_W_0F3813_P_2, VEX_W_0F3A1D_P_2): New enumerators.
1339         (prefix_table): Reference VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2
1340         respectively.
1341         (vex_w_table): New VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2 table
1342         entries.
1343         * i386-dis-evex.h (evex_table): Reference VEX table entry for
1344         opcode 0F3A1D.
1345         * i386-dis-evex-prefix.h (PREFIX_EVEX_0F3A1D): Delete table
1346         entry.
1347         * i386-dis-evex-w.h (EVEX_W_0F3A1D_P_2): Likewise.
1348
1349 2020-07-06  Jan Beulich  <jbeulich@suse.com>
1350
1351         * i386-dis.c (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
1352         PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
1353         PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
1354         PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
1355         PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
1356         PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
1357         PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
1358         PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
1359         PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
1360         PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
1361         PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
1362         PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
1363         PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
1364         PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
1365         PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
1366         PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
1367         PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
1368         PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
1369         PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
1370         PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
1371         PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
1372         PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
1373         PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
1374         PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
1375         PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
1376         PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
1377         PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF,
1378         EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2, EVEX_W_0F3858_P_2,
1379         EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F3A04_P_2,
1380         EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2): Delete.
1381         (prefix_table): Add EXxEVexR to FMA table entries.
1382         (OP_Rounding): Move abort() invocation.
1383         * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
1384         0F60, 0F61, 0F63, 0F67, 0F68, 0F69, 0FD1, 0FD5, 0FD8, 0FD9,
1385         0FDA, 0FDC, 0FDD, 0FDE, 0FE0, 0FE1, 0FE3, 0FE4, 0FE5, 0FE8,
1386         0FE9, 0FEA, 0FEC, 0FED, 0FEE, 0FF1, 0FF5, 0FF6, 0FF8, 0FF9,
1387         0FFC, 0FFD, 0F3800, 0F3804, 0F380B, 0F380C, 0F3818, 0F381C,
1388         0F381D, 0F383C, 0F383E, 0F3858, 0F3878, 0F3879, 0F3896, 0F3897,
1389         0F3898, 0F3899, 0F389C, 0F389D, 0F389E, 0F389F, 0F38A6, 0F38A7,
1390         0F38A8, 0F38A9, 0F38AC, 0F38AD, 0F38AE, 0F38AF, 0F38B6, 0F38B7,
1391         0F38B8, 0F38B9, 0F38BA, 0F38BB, 0F38BC, 0F38BD, 0F38BE, 0F38BF,
1392         0F38CF, 0F38DC, 0F38DD, 0F38DE, 0F38DF, 0F3A04, 0F3A0F, 0F3A44,
1393         0F3ACE, 0F3ACF.
1394         * i386-dis-evex-prefix.h (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
1395         PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
1396         PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
1397         PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
1398         PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
1399         PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
1400         PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
1401         PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
1402         PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
1403         PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
1404         PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
1405         PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
1406         PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
1407         PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
1408         PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
1409         PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
1410         PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
1411         PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
1412         PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
1413         PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
1414         PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
1415         PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
1416         PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
1417         PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
1418         PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
1419         PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
1420         PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF):
1421         Delete table entries.
1422         * i386-dis-evex-w.h (EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2,
1423         EVEX_W_0F3858_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2,
1424         EVEX_W_0F3A04_P_2, EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2):
1425         Likewise.
1426
1427 2020-07-06  Jan Beulich  <jbeulich@suse.com>
1428
1429         * i386-dis.c (EXqScalarS): Delete.
1430         (vex_len_table): Replace EXqScalarS by EXqVexScalarS.
1431         * i386-dis-evex-w.h (vmovq): Use EXqVexScalarS.
1432
1433 2020-07-06  Jan Beulich  <jbeulich@suse.com>
1434
1435         * i386-dis.c (safe-ctype.h): Include.
1436         (EXdScalar, EXqScalar): Delete.
1437         (d_scalar_mode, q_scalar_mode): Delete.
1438         (prefix_table, vex_len_table): Use EXxmm_md in place of
1439         EXdScalar and EXxmm_mq in place of EXqScalar.
1440         (intel_operand_size, OP_E_memory, OP_EX): Remove uses of
1441         d_scalar_mode and q_scalar_mode.
1442         * i386-dis-evex-w.h (vmovss): Use EXxmm_md.
1443         (vmovsd): Use EXxmm_mq.
1444
1445 2020-07-06  Yuri Chornoivan  <yurchor@ukr.net>
1446
1447         PR 26204
1448         * arc-dis.c: Fix spelling mistake.
1449         * po/opcodes.pot: Regenerate.
1450
1451 2020-07-06  Nick Clifton  <nickc@redhat.com>
1452
1453         * po/pt_BR.po: Updated Brazilian Portugugese translation.
1454         * po/uk.po: Updated Ukranian translation.
1455
1456 2020-07-04  Nick Clifton  <nickc@redhat.com>
1457
1458         * configure: Regenerate.
1459         * po/opcodes.pot: Regenerate.
1460
1461 2020-07-04  Nick Clifton  <nickc@redhat.com>
1462
1463         Binutils 2.35 branch created.
1464
1465 2020-07-02  H.J. Lu  <hongjiu.lu@intel.com>
1466
1467         * i386-gen.c (opcode_modifiers): Add VexSwapSources.
1468         * i386-opc.h (VexSwapSources): New.
1469         (i386_opcode_modifier): Add vexswapsources.
1470         * i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions
1471         with two source operands swapped.
1472         * i386-tbl.h: Regenerated.
1473
1474 2020-06-30  Nelson Chu  <nelson.chu@sifive.com>
1475
1476         * riscv-dis.c (print_insn_args, case 'E'): Updated.  Let the
1477         unprivileged CSR can also be initialized.
1478
1479 2020-06-29  Alan Modra  <amodra@gmail.com>
1480
1481         * arm-dis.c: Use C style comments.
1482         * cr16-opc.c: Likewise.
1483         * ft32-dis.c: Likewise.
1484         * moxie-opc.c: Likewise.
1485         * tic54x-dis.c: Likewise.
1486         * s12z-opc.c: Remove useless comment.
1487         * xgate-dis.c: Likewise.
1488
1489 2020-06-26  H.J. Lu  <hongjiu.lu@intel.com>
1490
1491         * i386-opc.tbl: Add a blank line.
1492
1493 2020-06-26  H.J. Lu  <hongjiu.lu@intel.com>
1494
1495         * i386-gen.c (opcode_modifiers): Replace VecSIB with SIB.
1496         (VecSIB128): Renamed to ...
1497         (VECSIB128): This.
1498         (VecSIB256): Renamed to ...
1499         (VECSIB256): This.
1500         (VecSIB512): Renamed to ...
1501         (VECSIB512): This.
1502         (VecSIB): Renamed to ...
1503         (SIB): This.
1504         (i386_opcode_modifier): Replace vecsib with sib.
1505         * i386-opc.tbl (VecSIB128): New.
1506         (VecSIB256): Likewise.
1507         (VecSIB512): Likewise.
1508         Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VecSIB128, VecSIB256
1509         and VecSIB512, respectively.
1510
1511 2020-06-26  Jan Beulich  <jbeulich@suse.com>
1512
1513         * i386-dis.c: Adjust description of I macro.
1514         (x86_64_table): Drop use of I.
1515         (float_mem): Replace use of I.
1516         (putop): Remove handling of I. Adjust setting/clearing of "alt".
1517
1518 2020-06-26  Jan Beulich  <jbeulich@suse.com>
1519
1520         * i386-dis.c: (print_insn): Avoid straight assignment to
1521         priv.orig_sizeflag when processing -M sub-options.
1522
1523 2020-06-25  Jan Beulich  <jbeulich@suse.com>
1524
1525         * i386-dis.c: Adjust description of J macro.
1526         (dis386, x86_64_table, mod_table): Replace J.
1527         (putop): Remove handling of J.
1528
1529 2020-06-25  Jan Beulich  <jbeulich@suse.com>
1530
1531         * i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt.
1532
1533 2020-06-25  Jan Beulich  <jbeulich@suse.com>
1534
1535         * i386-dis.c: Adjust description of "LQ" macro.
1536         (dis386_twobyte): Use LQ for sysret.
1537         (putop): Adjust handling of LQ.
1538
1539 2020-06-22  Nelson Chu  <nelson.chu@sifive.com>
1540
1541         * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
1542         * riscv-dis.c: Include elfxx-riscv.h.
1543
1544 2020-06-18  H.J. Lu  <hongjiu.lu@intel.com>
1545
1546         * i386-dis.c (prefix_table): Revert the last vmgexit change.
1547
1548 2020-06-17  Lili Cui  <lili.cui@intel.com>
1549
1550         * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
1551
1552 2020-06-14  H.J. Lu  <hongjiu.lu@intel.com>
1553
1554         PR gas/26115
1555         * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
1556         * i386-opc.tbl: Likewise.
1557         * i386-tbl.h: Regenerated.
1558
1559 2020-06-12  Nelson Chu  <nelson.chu@sifive.com>
1560
1561         * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
1562
1563 2020-06-11  Alex Coplan  <alex.coplan@arm.com>
1564
1565         * aarch64-opc.c (SYSREG): New macro for describing system registers.
1566         (SR_CORE): Likewise.
1567         (SR_FEAT): Likewise.
1568         (SR_RNG): Likewise.
1569         (SR_V8_1): Likewise.
1570         (SR_V8_2): Likewise.
1571         (SR_V8_3): Likewise.
1572         (SR_V8_4): Likewise.
1573         (SR_PAN): Likewise.
1574         (SR_RAS): Likewise.
1575         (SR_SSBS): Likewise.
1576         (SR_SVE): Likewise.
1577         (SR_ID_PFR2): Likewise.
1578         (SR_PROFILE): Likewise.
1579         (SR_MEMTAG): Likewise.
1580         (SR_SCXTNUM): Likewise.
1581         (aarch64_sys_regs): Refactor to store feature information in the table.
1582         (aarch64_sys_reg_supported_p): Collapse logic for system registers
1583         that now describe their own features.
1584         (aarch64_pstatefield_supported_p): Likewise.
1585
1586 2020-06-09  H.J. Lu  <hongjiu.lu@intel.com>
1587
1588         * i386-dis.c (prefix_table): Fix a typo in comments.
1589
1590 2020-06-09  Jan Beulich  <jbeulich@suse.com>
1591
1592         * i386-dis.c (rex_ignored): Delete.
1593         (ckprefix): Drop rex_ignored initialization.
1594         (get_valid_dis386): Drop setting of rex_ignored.
1595         (print_insn): Drop checking of rex_ignored. Don't record data
1596         size prefix as used with VEX-and-alike encodings.
1597
1598 2020-06-09  Jan Beulich  <jbeulich@suse.com>
1599
1600         * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
1601         MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
1602         (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
1603         (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
1604         (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
1605         VEX_0F12, and VEX_0F16.
1606         (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
1607         VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
1608         (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
1609         from movlps and movhlps. New MOD_0F12_PREFIX_2,
1610         MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
1611         MOD_VEX_0F16_PREFIX_2 entries.
1612
1613 2020-06-09  Jan Beulich  <jbeulich@suse.com>
1614
1615         * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
1616         MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
1617         (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1618         PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
1619         PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
1620         PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
1621         EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
1622         EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
1623         EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
1624         EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
1625         EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
1626         EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
1627         EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
1628         EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
1629         EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
1630         EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
1631         EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
1632         EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
1633         EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
1634         EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
1635         EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
1636         EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
1637         EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
1638         EVEX_W_0FC6_P_2): Delete.
1639         (print_insn): Add EVEX.W vs embedded prefix consistency check
1640         to prefix validation.
1641         * i386-dis-evex.h (evex_table): Don't further descend for
1642         vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
1643         and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
1644         and 0F2B.
1645         * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
1646         * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
1647         vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
1648         vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
1649         2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
1650         Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1651         PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
1652         PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
1653         PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
1654         * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
1655         EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
1656         EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
1657         EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
1658         EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
1659         EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
1660         EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
1661         EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
1662         EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
1663         EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
1664         EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
1665         EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
1666         EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
1667         EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
1668         EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
1669         EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
1670         EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
1671         EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
1672
1673 2020-06-09  Jan Beulich  <jbeulich@suse.com>
1674
1675         * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
1676         vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
1677         (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
1678         vmovmskpX.
1679         (print_insn): Drop pointless check against bad_opcode. Split
1680         prefix validation into legacy and VEX-and-alike parts.
1681         (putop): Re-work 'X' macro handling.
1682
1683 2020-06-09  Jan Beulich  <jbeulich@suse.com>
1684
1685         * i386-dis.c (MOD_0F51): Rename to ...
1686         (MOD_0F50): ... this.
1687
1688 2020-06-08  Alex Coplan  <alex.coplan@arm.com>
1689
1690         * arm-dis.c (arm_opcodes): Add dfb.
1691         (thumb32_opcodes): Add dfb.
1692
1693 2020-06-08  Jan Beulich  <jbeulich@suse.com>
1694
1695         * i386-opc.h (reg_entry): Const-qualify reg_name field.
1696
1697 2020-06-06  Alan Modra  <amodra@gmail.com>
1698
1699         * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
1700
1701 2020-06-05  Alan Modra  <amodra@gmail.com>
1702
1703         * cgen-dis.c (hash_insn_array): Increase size of buf.  Assert
1704         size is large enough.
1705
1706 2020-06-04  Jose E. Marchesi  <jose.marchesi@oracle.com>
1707
1708         * disassemble.c (disassemble_init_for_target): Set endian_code for
1709         bpf targets.
1710         * bpf-desc.c: Regenerate.
1711         * bpf-opc.c: Likewise.
1712         * bpf-dis.c: Likewise.
1713
1714 2020-06-03  Jose E. Marchesi  <jose.marchesi@oracle.com>
1715
1716         * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
1717         (cgen_put_insn_value): Likewise.
1718         (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
1719         * cgen-dis.in (print_insn): Likewise.
1720         * cgen-ibld.in (insert_1): Likewise.
1721         (insert_1): Likewise.
1722         (insert_insn_normal): Likewise.
1723         (extract_1): Likewise.
1724         * bpf-dis.c: Regenerate.
1725         * bpf-ibld.c: Likewise.
1726         * bpf-ibld.c: Likewise.
1727         * cgen-dis.in: Likewise.
1728         * cgen-ibld.in: Likewise.
1729         * cgen-opc.c: Likewise.
1730         * epiphany-dis.c: Likewise.
1731         * epiphany-ibld.c: Likewise.
1732         * fr30-dis.c: Likewise.
1733         * fr30-ibld.c: Likewise.
1734         * frv-dis.c: Likewise.
1735         * frv-ibld.c: Likewise.
1736         * ip2k-dis.c: Likewise.
1737         * ip2k-ibld.c: Likewise.
1738         * iq2000-dis.c: Likewise.
1739         * iq2000-ibld.c: Likewise.
1740         * lm32-dis.c: Likewise.
1741         * lm32-ibld.c: Likewise.
1742         * m32c-dis.c: Likewise.
1743         * m32c-ibld.c: Likewise.
1744         * m32r-dis.c: Likewise.
1745         * m32r-ibld.c: Likewise.
1746         * mep-dis.c: Likewise.
1747         * mep-ibld.c: Likewise.
1748         * mt-dis.c: Likewise.
1749         * mt-ibld.c: Likewise.
1750         * or1k-dis.c: Likewise.
1751         * or1k-ibld.c: Likewise.
1752         * xc16x-dis.c: Likewise.
1753         * xc16x-ibld.c: Likewise.
1754         * xstormy16-dis.c: Likewise.
1755         * xstormy16-ibld.c: Likewise.
1756
1757 2020-06-04  Jose E. Marchesi  <jemarch@gnu.org>
1758
1759         * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
1760         (print_insn_): Handle instruction endian.
1761         * bpf-dis.c: Regenerate.
1762         * bpf-desc.c: Regenerate.
1763         * epiphany-dis.c: Likewise.
1764         * epiphany-desc.c: Likewise.
1765         * fr30-dis.c: Likewise.
1766         * fr30-desc.c: Likewise.
1767         * frv-dis.c: Likewise.
1768         * frv-desc.c: Likewise.
1769         * ip2k-dis.c: Likewise.
1770         * ip2k-desc.c: Likewise.
1771         * iq2000-dis.c: Likewise.
1772         * iq2000-desc.c: Likewise.
1773         * lm32-dis.c: Likewise.
1774         * lm32-desc.c: Likewise.
1775         * m32c-dis.c: Likewise.
1776         * m32c-desc.c: Likewise.
1777         * m32r-dis.c: Likewise.
1778         * m32r-desc.c: Likewise.
1779         * mep-dis.c: Likewise.
1780         * mep-desc.c: Likewise.
1781         * mt-dis.c: Likewise.
1782         * mt-desc.c: Likewise.
1783         * or1k-dis.c: Likewise.
1784         * or1k-desc.c: Likewise.
1785         * xc16x-dis.c: Likewise.
1786         * xc16x-desc.c: Likewise.
1787         * xstormy16-dis.c: Likewise.
1788         * xstormy16-desc.c: Likewise.
1789
1790 2020-06-03  Nick Clifton  <nickc@redhat.com>
1791
1792         * po/sr.po: Updated Serbian translation.
1793
1794 2020-06-03  Nelson Chu  <nelson.chu@sifive.com>
1795
1796         * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
1797         (riscv_get_priv_spec_class): Likewise.
1798
1799 2020-06-01  Alan Modra  <amodra@gmail.com>
1800
1801         * bpf-desc.c: Regenerate.
1802
1803 2020-05-28  Jose E. Marchesi  <jose.marchesi@oracle.com>
1804             David Faust <david.faust@oracle.com>
1805
1806         * bpf-desc.c: Regenerate.
1807         * bpf-opc.h: Likewise.
1808         * bpf-opc.c: Likewise.
1809         * bpf-dis.c: Likewise.
1810
1811 2020-05-28  Alan Modra  <amodra@gmail.com>
1812
1813         * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
1814         values.
1815
1816 2020-05-28  Alan Modra  <amodra@gmail.com>
1817
1818         * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
1819         immediates.
1820         (print_insn_ns32k): Revert last change.
1821
1822 2020-05-28  Nick Clifton  <nickc@redhat.com>
1823
1824         * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
1825         static.
1826
1827 2020-05-26  Sandra Loosemore  <sandra@codesourcery.com>
1828
1829         Fix extraction of signed constants in nios2 disassembler (again).
1830
1831         * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
1832         extractions of signed fields.
1833
1834 2020-05-26  Stefan Schulze Frielinghaus  <stefansf@linux.ibm.com>
1835
1836         * s390-opc.txt: Relocate vector load/store instructions with
1837         additional alignment parameter and change architecture level
1838         constraint from z14 to z13.
1839
1840 2020-05-21  Alan Modra  <amodra@gmail.com>
1841
1842         * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
1843         * sparc-dis.c: Likewise.
1844         * tic4x-dis.c: Likewise.
1845         * xtensa-dis.c: Likewise.
1846         * bpf-desc.c: Regenerate.
1847         * epiphany-desc.c: Regenerate.
1848         * fr30-desc.c: Regenerate.
1849         * frv-desc.c: Regenerate.
1850         * ip2k-desc.c: Regenerate.
1851         * iq2000-desc.c: Regenerate.
1852         * lm32-desc.c: Regenerate.
1853         * m32c-desc.c: Regenerate.
1854         * m32r-desc.c: Regenerate.
1855         * mep-asm.c: Regenerate.
1856         * mep-desc.c: Regenerate.
1857         * mt-desc.c: Regenerate.
1858         * or1k-desc.c: Regenerate.
1859         * xc16x-desc.c: Regenerate.
1860         * xstormy16-desc.c: Regenerate.
1861
1862 2020-05-20  Nelson Chu  <nelson.chu@sifive.com>
1863
1864         * riscv-opc.c (riscv_ext_version_table): The table used to store
1865         all information about the supported spec and the corresponding ISA
1866         versions.  Currently, only Zicsr is supported to verify the
1867         correctness of Z sub extension settings.  Others will be supported
1868         in the future patches.
1869         (struct isa_spec_t, isa_specs): List for all supported ISA spec
1870         classes and the corresponding strings.
1871         (riscv_get_isa_spec_class): New function.  Get the corresponding ISA
1872         spec class by giving a ISA spec string.
1873         * riscv-opc.c (struct priv_spec_t): New structure.
1874         (struct priv_spec_t priv_specs): List for all supported privilege spec
1875         classes and the corresponding strings.
1876         (riscv_get_priv_spec_class): New function.  Get the corresponding
1877         privilege spec class by giving a spec string.
1878         (riscv_get_priv_spec_name): New function.  Get the corresponding
1879         privilege spec string by giving a CSR version class.
1880         * riscv-dis.c: Updated since DECLARE_CSR is changed.
1881         * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
1882         according to the chosen version.  Build a hash table riscv_csr_hash to
1883         store the valid CSR for the chosen pirv verison.  Dump the direct
1884         CSR address rather than it's name if it is invalid.
1885         (parse_riscv_dis_option_without_args): New function.  Parse the options
1886         without arguments.
1887         (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
1888         parse the options without arguments first, and then handle the options
1889         with arguments.  Add the new option -Mpriv-spec, which has argument.
1890         * riscv-dis.c (print_riscv_disassembler_options): Add description
1891         about the new OBJDUMP option.
1892
1893 2020-05-19  Peter Bergner  <bergner@linux.ibm.com>
1894
1895         * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
1896         WC values on POWER10 sync, dcbf  and wait instructions.
1897         (insert_pl, extract_pl): New functions.
1898         (L2OPT, LS, WC): Use insert_ls and extract_ls.
1899         (LS3): New , 3-bit L for sync.
1900         (LS3, L3OPT): New, 3-bit L for sync and dcbf.
1901         (SC2, PL): New, 2-bit SC and PL for sync and wait.
1902         (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
1903         (XOPL3, XWCPL, XSYNCLS): New opcode macros.
1904         (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
1905         plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
1906         <wait>: Enable PL operand on POWER10.
1907         <dcbf>: Enable L3OPT operand on POWER10.
1908         <sync>: Enable SC2 operand on POWER10.
1909
1910 2020-05-19  Stafford Horne  <shorne@gmail.com>
1911
1912         PR 25184
1913         * or1k-asm.c: Regenerate.
1914         * or1k-desc.c: Regenerate.
1915         * or1k-desc.h: Regenerate.
1916         * or1k-dis.c: Regenerate.
1917         * or1k-ibld.c: Regenerate.
1918         * or1k-opc.c: Regenerate.
1919         * or1k-opc.h: Regenerate.
1920         * or1k-opinst.c: Regenerate.
1921
1922 2020-05-11  Alan Modra  <amodra@gmail.com>
1923
1924         * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
1925         xsmaxcqp, xsmincqp.
1926
1927 2020-05-11  Alan Modra  <amodra@gmail.com>
1928
1929         * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
1930         stxvrbx, stxvrhx, stxvrwx, stxvrdx.
1931
1932 2020-05-11  Alan Modra  <amodra@gmail.com>
1933
1934         * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
1935
1936 2020-05-11  Alan Modra  <amodra@gmail.com>
1937
1938         * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
1939         vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
1940
1941 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
1942
1943         * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
1944         mnemonics.
1945
1946 2020-05-11  Alan Modra  <amodra@gmail.com>
1947
1948         * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
1949         (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
1950         vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
1951         (prefix_opcodes): Add xxeval.
1952
1953 2020-05-11  Alan Modra  <amodra@gmail.com>
1954
1955         * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
1956         xxgenpcvwm, xxgenpcvdm.
1957
1958 2020-05-11  Alan Modra  <amodra@gmail.com>
1959
1960         * ppc-opc.c (MP, VXVAM_MASK): Define.
1961         (VXVAPS_MASK): Use VXVA_MASK.
1962         (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
1963         vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
1964         vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
1965         vcntmbb, vcntmbh, vcntmbw, vcntmbd.
1966
1967 2020-05-11  Alan Modra  <amodra@gmail.com>
1968             Peter Bergner  <bergner@linux.ibm.com>
1969
1970         * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
1971         New functions.
1972         (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
1973         YMSK2, XA6a, XA6ap, XB6a entries.
1974         (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
1975         (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
1976         (PPCVSX4): Define.
1977         (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
1978         xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
1979         xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
1980         xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
1981         xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
1982         xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
1983         xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
1984         (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
1985         pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
1986         pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
1987         pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
1988         pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
1989         pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
1990         pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
1991
1992 2020-05-11  Alan Modra  <amodra@gmail.com>
1993
1994         * ppc-opc.c (insert_imm32, extract_imm32): New functions.
1995         (insert_xts, extract_xts): New functions.
1996         (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
1997         (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
1998         (VXRC_MASK, VXSH_MASK): Define.
1999         (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
2000         vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
2001         vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
2002         vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
2003         vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
2004         (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
2005         xxblendvh, xxblendvw, xxblendvd, xxpermx.
2006
2007 2020-05-11  Alan Modra  <amodra@gmail.com>
2008
2009         * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
2010         vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
2011         vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
2012         vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
2013         xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
2014
2015 2020-05-11  Alan Modra  <amodra@gmail.com>
2016
2017         * ppc-opc.c (insert_xtp, extract_xtp): New functions.
2018         (XTP, DQXP, DQXP_MASK): Define.
2019         (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
2020         (prefix_opcodes): Add plxvp and pstxvp.
2021
2022 2020-05-11  Alan Modra  <amodra@gmail.com>
2023
2024         * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
2025         vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
2026         vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
2027
2028 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
2029
2030         * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
2031
2032 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
2033
2034         * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
2035         (L1OPT): Define.
2036         (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
2037
2038 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
2039
2040         * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
2041
2042 2020-05-11  Alan Modra  <amodra@gmail.com>
2043
2044         * ppc-dis.c (powerpc_init_dialect): Default to "power10".
2045
2046 2020-05-11  Alan Modra  <amodra@gmail.com>
2047
2048         * ppc-dis.c (ppc_opts): Add "power10" entry.
2049         (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
2050         * ppc-opc.c (POWER10): Rename from POWERXX.  Update all uses.
2051
2052 2020-05-11  Nick Clifton  <nickc@redhat.com>
2053
2054         * po/fr.po: Updated French translation.
2055
2056 2020-04-30  Alex Coplan  <alex.coplan@arm.com>
2057
2058         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
2059         * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
2060         (operand_general_constraint_met_p): validate
2061         AARCH64_OPND_UNDEFINED.
2062         * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
2063         for FLD_imm16_2.
2064         * aarch64-asm-2.c: Regenerated.
2065         * aarch64-dis-2.c: Regenerated.
2066         * aarch64-opc-2.c: Regenerated.
2067
2068 2020-04-29  Nick Clifton  <nickc@redhat.com>
2069
2070         PR 22699
2071         * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
2072         and SETRC insns.
2073
2074 2020-04-29  Nick Clifton  <nickc@redhat.com>
2075
2076         * po/sv.po: Updated Swedish translation.
2077
2078 2020-04-29  Nick Clifton  <nickc@redhat.com>
2079
2080         PR 22699
2081         * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U.  Use
2082         IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
2083         * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
2084         IMM0_8U case.
2085
2086 2020-04-21  Andreas Schwab  <schwab@linux-m68k.org>
2087
2088         PR 25848
2089         * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
2090         cmpi only on m68020up and cpu32.
2091
2092 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
2093
2094         * aarch64-asm.c (aarch64_ins_none): New.
2095         * aarch64-asm.h (ins_none): New declaration.
2096         * aarch64-dis.c (aarch64_ext_none): New.
2097         * aarch64-dis.h (ext_none): New declaration.
2098         * aarch64-opc.c (aarch64_print_operand): Update case for
2099         AARCH64_OPND_BARRIER_PSB.
2100         * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
2101         (AARCH64_OPERANDS): Update inserter/extracter for
2102         AARCH64_OPND_BARRIER_PSB to use new dummy functions.
2103         * aarch64-asm-2.c: Regenerated.
2104         * aarch64-dis-2.c: Regenerated.
2105         * aarch64-opc-2.c: Regenerated.
2106
2107 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
2108
2109         * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
2110         (aarch64_feature_ras, RAS): Likewise.
2111         (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
2112         (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
2113         autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
2114         autiaz, autiasp, autibz, autibsp to be CORE_INSN.
2115         * aarch64-asm-2.c: Regenerated.
2116         * aarch64-dis-2.c: Regenerated.
2117         * aarch64-opc-2.c: Regenerated.
2118
2119 2020-04-17  Fredrik Strupe  <fredrik@strupe.net>
2120
2121         * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
2122         (print_insn_neon): Support disassembly of conditional
2123         instructions.
2124
2125 2020-02-16  David Faust  <david.faust@oracle.com>
2126
2127         * bpf-desc.c: Regenerate.
2128         * bpf-desc.h: Likewise.
2129         * bpf-opc.c: Regenerate.
2130         * bpf-opc.h: Likewise.
2131
2132 2020-04-07  Lili Cui  <lili.cui@intel.com>
2133
2134         * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
2135         (prefix_table): New instructions (see prefixes above).
2136         (rm_table): Likewise
2137         * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
2138         CPU_ANY_TSXLDTRK_FLAGS.
2139         (cpu_flags): Add CpuTSXLDTRK.
2140         * i386-opc.h (enum): Add CpuTSXLDTRK.
2141         (i386_cpu_flags): Add cputsxldtrk.
2142         * i386-opc.tbl: Add XSUSPLDTRK insns.
2143         * i386-init.h: Regenerate.
2144         * i386-tbl.h: Likewise.
2145
2146 2020-04-02  Lili Cui  <lili.cui@intel.com>
2147
2148         * i386-dis.c (prefix_table): New instructions serialize.
2149         * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
2150         CPU_ANY_SERIALIZE_FLAGS.
2151         (cpu_flags): Add CpuSERIALIZE.
2152         * i386-opc.h (enum): Add CpuSERIALIZE.
2153         (i386_cpu_flags): Add cpuserialize.
2154         * i386-opc.tbl: Add SERIALIZE insns.
2155         * i386-init.h: Regenerate.
2156         * i386-tbl.h: Likewise.
2157
2158 2020-03-26  Alan Modra  <amodra@gmail.com>
2159
2160         * disassemble.h (opcodes_assert): Declare.
2161         (OPCODES_ASSERT): Define.
2162         * disassemble.c: Don't include assert.h.  Include opintl.h.
2163         (opcodes_assert): New function.
2164         * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
2165         (bfd_h8_disassemble): Reduce size of data array.  Correctly
2166         calculate maxlen.  Omit insn decoding when insn length exceeds
2167         maxlen.  Exit from nibble loop when looking for E, before
2168         accessing next data byte.  Move processing of E outside loop.
2169         Replace tests of maxlen in loop with assertions.
2170
2171 2020-03-26  Alan Modra  <amodra@gmail.com>
2172
2173         * arc-dis.c (find_format): Init needs_limm.  Simplify use of limm.
2174
2175 2020-03-25  Alan Modra  <amodra@gmail.com>
2176
2177         * z80-dis.c (suffix): Init mybuf.
2178
2179 2020-03-22  Alan Modra  <amodra@gmail.com>
2180
2181         * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
2182         successflly read from section.
2183
2184 2020-03-22  Alan Modra  <amodra@gmail.com>
2185
2186         * arc-dis.c (find_format): Use ISO C string concatenation rather
2187         than line continuation within a string.  Don't access needs_limm
2188         before testing opcode != NULL.
2189
2190 2020-03-22  Alan Modra  <amodra@gmail.com>
2191
2192         * ns32k-dis.c (print_insn_arg): Update comment.
2193         (print_insn_ns32k): Reduce size of index_offset array, and
2194         initialize, passing -1 to print_insn_arg for args that are not
2195         an index.  Don't exit arg loop early.  Abort on bad arg number.
2196
2197 2020-03-22  Alan Modra  <amodra@gmail.com>
2198
2199         * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
2200         * s12z-opc.c: Formatting.
2201         (operands_f): Return an int.
2202         (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
2203         (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
2204         (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
2205         (exg_sex_discrim): Likewise.
2206         (create_immediate_operand, create_bitfield_operand),
2207         (create_register_operand_with_size, create_register_all_operand),
2208         (create_register_all16_operand, create_simple_memory_operand),
2209         (create_memory_operand, create_memory_auto_operand): Don't
2210         segfault on malloc failure.
2211         (z_ext24_decode): Return an int status, negative on fail, zero
2212         on success.
2213         (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
2214         (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
2215         (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
2216         (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
2217         (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
2218         (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
2219         (loop_primitive_decode, shift_decode, psh_pul_decode),
2220         (bit_field_decode): Similarly.
2221         (z_decode_signed_value, decode_signed_value): Similarly.  Add arg
2222         to return value, update callers.
2223         (x_opr_decode_with_size): Check all reads, returning NULL on fail.
2224         Don't segfault on NULL operand.
2225         (decode_operation): Return OP_INVALID on first fail.
2226         (decode_s12z): Check all reads, returning -1 on fail.
2227
2228 2020-03-20  Alan Modra  <amodra@gmail.com>
2229
2230         * metag-dis.c (print_insn_metag): Don't ignore status from
2231         read_memory_func.
2232
2233 2020-03-20  Alan Modra  <amodra@gmail.com>
2234
2235         * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
2236         Initialize parts of buffer not written when handling a possible
2237         2-byte insn at end of section.  Don't attempt decoding of such
2238         an insn by the 4-byte machinery.
2239
2240 2020-03-20  Alan Modra  <amodra@gmail.com>
2241
2242         * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
2243         partially filled buffer.  Prevent lookup of 4-byte insns when
2244         only VLE 2-byte insns are possible due to section size.  Print
2245         ".word" rather than ".long" for 2-byte leftovers.
2246
2247 2020-03-17  Sergey Belyashov  <sergey.belyashov@gmail.com>
2248
2249         PR 25641
2250         * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
2251
2252 2020-03-13  Jan Beulich  <jbeulich@suse.com>
2253
2254         * i386-dis.c (X86_64_0D): Rename to ...
2255         (X86_64_0E): ... this.
2256
2257 2020-03-09  H.J. Lu  <hongjiu.lu@intel.com>
2258
2259         * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
2260         * Makefile.in: Regenerated.
2261
2262 2020-03-09  Jan Beulich  <jbeulich@suse.com>
2263
2264         * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
2265         3-operand pseudos.
2266         * i386-tbl.h: Re-generate.
2267
2268 2020-03-09  Jan Beulich  <jbeulich@suse.com>
2269
2270         * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
2271         vprot*, vpsha*, and vpshl*.
2272         * i386-tbl.h: Re-generate.
2273
2274 2020-03-09  Jan Beulich  <jbeulich@suse.com>
2275
2276         * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
2277         vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
2278         * i386-tbl.h: Re-generate.
2279
2280 2020-03-09  Jan Beulich  <jbeulich@suse.com>
2281
2282         * i386-gen.c (set_bitfield): Ignore zero-length field names.
2283         * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
2284         cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
2285         * i386-tbl.h: Re-generate.
2286
2287 2020-03-09  Jan Beulich  <jbeulich@suse.com>
2288
2289         * i386-gen.c (struct template_arg, struct template_instance,
2290         struct template_param, struct template, templates,
2291         parse_template, expand_templates): New.
2292         (process_i386_opcodes): Various local variables moved to
2293         expand_templates. Call parse_template and expand_templates.
2294         * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
2295         * i386-tbl.h: Re-generate.
2296
2297 2020-03-06  Jan Beulich  <jbeulich@suse.com>
2298
2299         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
2300         vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
2301         register and memory source templates. Replace VexW= by VexW*
2302         where applicable.
2303         * i386-tbl.h: Re-generate.
2304
2305 2020-03-06  Jan Beulich  <jbeulich@suse.com>
2306
2307         * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
2308         VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
2309         * i386-tbl.h: Re-generate.
2310
2311 2020-03-06  Jan Beulich  <jbeulich@suse.com>
2312
2313         * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
2314         * i386-tbl.h: Re-generate.
2315
2316 2020-03-06  Jan Beulich  <jbeulich@suse.com>
2317
2318         * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
2319         (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
2320         pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
2321         VexW0 on SSE2AVX variants.
2322         (vmovq): Drop NoRex64 from XMM/XMM variants.
2323         (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
2324         vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
2325         applicable use VexW0.
2326         * i386-tbl.h: Re-generate.
2327
2328 2020-03-06  Jan Beulich  <jbeulich@suse.com>
2329
2330         * i386-gen.c (opcode_modifiers): Remove Rex64 field.
2331         * i386-opc.h (Rex64): Delete.
2332         (struct i386_opcode_modifier): Remove rex64 field.
2333         * i386-opc.tbl (crc32): Drop Rex64.
2334         Replace Rex64 with Size64 everywhere else.
2335         * i386-tbl.h: Re-generate.
2336
2337 2020-03-06  Jan Beulich  <jbeulich@suse.com>
2338
2339         * i386-dis.c (OP_E_memory): Exclude recording of used address
2340         prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
2341         addressed memory operands for MPX insns.
2342
2343 2020-03-06  Jan Beulich  <jbeulich@suse.com>
2344
2345         * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
2346         invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
2347         adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
2348         (ptwrite): Split into non-64-bit and 64-bit forms.
2349         * i386-tbl.h: Re-generate.
2350
2351 2020-03-06  Jan Beulich  <jbeulich@suse.com>
2352
2353         * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
2354         template.
2355         * i386-tbl.h: Re-generate.
2356
2357 2020-03-04  Jan Beulich  <jbeulich@suse.com>
2358
2359         * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
2360         (prefix_table): Move vmmcall here. Add vmgexit.
2361         (rm_table): Replace vmmcall entry by prefix_table[] escape.
2362         * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
2363         (cpu_flags): Add CpuSEV_ES entry.
2364         * i386-opc.h (CpuSEV_ES): New.
2365         (union i386_cpu_flags): Add cpusev_es field.
2366         * i386-opc.tbl (vmgexit): New.
2367         * i386-init.h, i386-tbl.h: Re-generate.
2368
2369 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
2370
2371         * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
2372         with MnemonicSize.
2373         * i386-opc.h (IGNORESIZE): New.
2374         (DEFAULTSIZE): Likewise.
2375         (IgnoreSize): Removed.
2376         (DefaultSize): Likewise.
2377         (MnemonicSize): New.
2378         (i386_opcode_modifier): Replace ignoresize/defaultsize with
2379         mnemonicsize.
2380         * i386-opc.tbl (IgnoreSize): New.
2381         (DefaultSize): Likewise.
2382         * i386-tbl.h: Regenerated.
2383
2384 2020-03-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
2385
2386         PR 25627
2387         * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
2388         instructions.
2389
2390 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
2391
2392         PR gas/25622
2393         * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
2394         vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
2395         * i386-tbl.h: Regenerated.
2396
2397 2020-02-26  Alan Modra  <amodra@gmail.com>
2398
2399         * aarch64-asm.c: Indent labels correctly.
2400         * aarch64-dis.c: Likewise.
2401         * aarch64-gen.c: Likewise.
2402         * aarch64-opc.c: Likewise.
2403         * alpha-dis.c: Likewise.
2404         * i386-dis.c: Likewise.
2405         * nds32-asm.c: Likewise.
2406         * nfp-dis.c: Likewise.
2407         * visium-dis.c: Likewise.
2408
2409 2020-02-25  Claudiu Zissulescu <claziss@gmail.com>
2410
2411         * arc-regs.h (int_vector_base): Make it available for all ARC
2412         CPUs.
2413
2414 2020-02-20  Nelson Chu  <nelson.chu@sifive.com>
2415
2416         * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
2417         changed.
2418
2419 2020-02-19  Nelson Chu  <nelson.chu@sifive.com>
2420
2421         * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
2422         c.mv/c.li if rs1 is zero.
2423
2424 2020-02-17  H.J. Lu  <hongjiu.lu@intel.com>
2425
2426         * i386-gen.c (cpu_flag_init): Replace CpuABM with
2427         CpuLZCNT|CpuPOPCNT.  Add CpuPOPCNT to CPU_SSE4_2_FLAGS.  Add
2428         CPU_POPCNT_FLAGS.
2429         (cpu_flags): Remove CpuABM.  Add CpuPOPCNT.
2430         * i386-opc.h (CpuABM): Removed.
2431         (CpuPOPCNT): New.
2432         (i386_cpu_flags): Remove cpuabm.  Add cpupopcnt.
2433         * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
2434         popcnt.  Remove CpuABM from lzcnt.
2435         * i386-init.h: Regenerated.
2436         * i386-tbl.h: Likewise.
2437
2438 2020-02-17  Jan Beulich  <jbeulich@suse.com>
2439
2440         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
2441         Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
2442         VexW1 instead of open-coding them.
2443         * i386-tbl.h: Re-generate.
2444
2445 2020-02-17  Jan Beulich  <jbeulich@suse.com>
2446
2447         * i386-opc.tbl (AddrPrefixOpReg): Define.
2448         (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
2449         umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
2450         templates. Drop NoRex64.
2451         * i386-tbl.h: Re-generate.
2452
2453 2020-02-17  Jan Beulich  <jbeulich@suse.com>
2454
2455         PR gas/6518
2456         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
2457         vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
2458         into Intel syntax instance (with Unpsecified) and AT&T one
2459         (without).
2460         (vcvtneps2bf16): Likewise, along with folding the two so far
2461         separate ones.
2462         * i386-tbl.h: Re-generate.
2463
2464 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
2465
2466         * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
2467         CPU_ANY_SSE4A_FLAGS.
2468
2469 2020-02-17  Alan Modra  <amodra@gmail.com>
2470
2471         * i386-gen.c (cpu_flag_init): Correct last change.
2472
2473 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
2474
2475         * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS.  Remove
2476         CPU_ANY_SSE4_FLAGS.
2477
2478 2020-02-14  H.J. Lu  <hongjiu.lu@intel.com>
2479
2480         * i386-opc.tbl (movsx): Remove Intel syntax comments.
2481         (movzx): Likewise.
2482
2483 2020-02-14  Jan Beulich  <jbeulich@suse.com>
2484
2485         PR gas/25438
2486         * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
2487         destination for Cpu64-only variant.
2488         (movzx): Fold patterns.
2489         * i386-tbl.h: Re-generate.
2490
2491 2020-02-13  Jan Beulich  <jbeulich@suse.com>
2492
2493         * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
2494         CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
2495         CPU_ANY_SSE4_FLAGS entry.
2496         * i386-init.h: Re-generate.
2497
2498 2020-02-12  Jan Beulich  <jbeulich@suse.com>
2499
2500         * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
2501         with Unspecified, making the present one AT&T syntax only.
2502         * i386-tbl.h: Re-generate.
2503
2504 2020-02-12  Jan Beulich  <jbeulich@suse.com>
2505
2506         * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
2507         * i386-tbl.h: Re-generate.
2508
2509 2020-02-12  Jan Beulich  <jbeulich@suse.com>
2510
2511         PR gas/24546
2512         * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
2513         * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
2514         Amd64 and Intel64 templates.
2515         (call, jmp): Likewise for far indirect variants. Dro
2516         Unspecified.
2517         * i386-tbl.h: Re-generate.
2518
2519 2020-02-11  Jan Beulich  <jbeulich@suse.com>
2520
2521         * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
2522         * i386-opc.h (ShortForm): Delete.
2523         (struct i386_opcode_modifier): Remove shortform field.
2524         * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
2525         fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
2526         fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
2527         ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
2528         Drop ShortForm.
2529         * i386-tbl.h: Re-generate.
2530
2531 2020-02-11  Jan Beulich  <jbeulich@suse.com>
2532
2533         * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
2534         fucompi): Drop ShortForm from operand-less templates.
2535         * i386-tbl.h: Re-generate.
2536
2537 2020-02-11  Alan Modra  <amodra@gmail.com>
2538
2539         * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
2540         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
2541         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
2542         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
2543         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
2544
2545 2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
2546
2547         * arm-dis.c (print_insn_cde): Define 'V' parse character.
2548         (cde_opcodes): Add VCX* instructions.
2549
2550 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
2551             Matthew Malcomson  <matthew.malcomson@arm.com>
2552
2553         * arm-dis.c (struct cdeopcode32): New.
2554         (CDE_OPCODE): New macro.
2555         (cde_opcodes): New disassembly table.
2556         (regnames): New option to table.
2557         (cde_coprocs): New global variable.
2558         (print_insn_cde): New
2559         (print_insn_thumb32): Use print_insn_cde.
2560         (parse_arm_disassembler_options): Parse coprocN args.
2561
2562 2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
2563
2564         PR gas/25516
2565         * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
2566         with ISA64.
2567         * i386-opc.h (AMD64): Removed.
2568         (Intel64): Likewose.
2569         (AMD64): New.
2570         (INTEL64): Likewise.
2571         (INTEL64ONLY): Likewise.
2572         (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
2573         * i386-opc.tbl (Amd64): New.
2574         (Intel64): Likewise.
2575         (Intel64Only): Likewise.
2576         Replace AMD64 with Amd64.  Update sysenter/sysenter with
2577         Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
2578         * i386-tbl.h: Regenerated.
2579
2580 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
2581
2582         PR 25469
2583         * z80-dis.c: Add support for GBZ80 opcodes.
2584
2585 2020-02-04  Alan Modra  <amodra@gmail.com>
2586
2587         * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
2588
2589 2020-02-03  Alan Modra  <amodra@gmail.com>
2590
2591         * m32c-ibld.c: Regenerate.
2592
2593 2020-02-01  Alan Modra  <amodra@gmail.com>
2594
2595         * frv-ibld.c: Regenerate.
2596
2597 2020-01-31  Jan Beulich  <jbeulich@suse.com>
2598
2599         * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
2600         (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
2601         (OP_E_memory): Replace xmm_mdq_mode case label by
2602         vex_scalar_w_dq_mode one.
2603         * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
2604
2605 2020-01-31  Jan Beulich  <jbeulich@suse.com>
2606
2607         * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
2608         (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
2609         vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
2610         (intel_operand_size): Drop vex_w_dq_mode case label.
2611
2612 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
2613
2614         * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
2615         Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
2616
2617 2020-01-30  Alan Modra  <amodra@gmail.com>
2618
2619         * m32c-ibld.c: Regenerate.
2620
2621 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
2622
2623         * bpf-opc.c: Regenerate.
2624
2625 2020-01-30  Jan Beulich  <jbeulich@suse.com>
2626
2627         * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
2628         (dis386): Use them to replace C2/C3 table entries.
2629         (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
2630         * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
2631         ones. Use Size64 instead of DefaultSize on Intel64 ones.
2632         * i386-tbl.h: Re-generate.
2633
2634 2020-01-30  Jan Beulich  <jbeulich@suse.com>
2635
2636         * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
2637         forms.
2638         (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
2639         DefaultSize.
2640         * i386-tbl.h: Re-generate.
2641
2642 2020-01-30  Alan Modra  <amodra@gmail.com>
2643
2644         * tic4x-dis.c (tic4x_dp): Make unsigned.
2645
2646 2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
2647             Jan Beulich  <jbeulich@suse.com>
2648
2649         PR binutils/25445
2650         * i386-dis.c (MOVSXD_Fixup): New function.
2651         (movsxd_mode): New enum.
2652         (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
2653         (intel_operand_size): Handle movsxd_mode.
2654         (OP_E_register): Likewise.
2655         (OP_G): Likewise.
2656         * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
2657         register on movsxd.  Add movsxd with 16-bit destination register
2658         for AMD64 and Intel64 ISAs.
2659         * i386-tbl.h: Regenerated.
2660
2661 2020-01-27  Tamar Christina  <tamar.christina@arm.com>
2662
2663         PR 25403
2664         * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
2665         * aarch64-asm-2.c: Regenerate
2666         * aarch64-dis-2.c: Likewise.
2667         * aarch64-opc-2.c: Likewise.
2668
2669 2020-01-21  Jan Beulich  <jbeulich@suse.com>
2670
2671         * i386-opc.tbl (sysret): Drop DefaultSize.
2672         * i386-tbl.h: Re-generate.
2673
2674 2020-01-21  Jan Beulich  <jbeulich@suse.com>
2675
2676         * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
2677         Dword.
2678         (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
2679         * i386-tbl.h: Re-generate.
2680
2681 2020-01-20  Nick Clifton  <nickc@redhat.com>
2682
2683         * po/de.po: Updated German translation.
2684         * po/pt_BR.po: Updated Brazilian Portuguese translation.
2685         * po/uk.po: Updated Ukranian translation.
2686
2687 2020-01-20  Alan Modra  <amodra@gmail.com>
2688
2689         * hppa-dis.c (fput_const): Remove useless cast.
2690
2691 2020-01-20  Alan Modra  <amodra@gmail.com>
2692
2693         * arm-dis.c (print_insn_arm): Wrap 'T' value.
2694
2695 2020-01-18  Nick Clifton  <nickc@redhat.com>
2696
2697         * configure: Regenerate.
2698         * po/opcodes.pot: Regenerate.
2699
2700 2020-01-18  Nick Clifton  <nickc@redhat.com>
2701
2702         Binutils 2.34 branch created.
2703
2704 2020-01-17  Christian Biesinger  <cbiesinger@google.com>
2705
2706         * opintl.h: Fix spelling error (seperate).
2707
2708 2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
2709
2710         * i386-opc.tbl: Add {vex} pseudo prefix.
2711         * i386-tbl.h: Regenerated.
2712
2713 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
2714
2715         PR 25376
2716         * arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
2717         (neon_opcodes): Likewise.
2718         (select_arm_features): Make sure we enable MVE bits when selecting
2719         armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
2720         any architecture.
2721
2722 2020-01-16  Jan Beulich  <jbeulich@suse.com>
2723
2724         * i386-opc.tbl: Drop stale comment from XOP section.
2725
2726 2020-01-16  Jan Beulich  <jbeulich@suse.com>
2727
2728         * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
2729         (extractps): Add VexWIG to SSE2AVX forms.
2730         * i386-tbl.h: Re-generate.
2731
2732 2020-01-16  Jan Beulich  <jbeulich@suse.com>
2733
2734         * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
2735         Size64 from and use VexW1 on SSE2AVX forms.
2736         (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
2737         VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
2738         * i386-tbl.h: Re-generate.
2739
2740 2020-01-15  Alan Modra  <amodra@gmail.com>
2741
2742         * tic4x-dis.c (tic4x_version): Make unsigned long.
2743         (optab, optab_special, registernames): New file scope vars.
2744         (tic4x_print_register): Set up registernames rather than
2745         malloc'd registertable.
2746         (tic4x_disassemble): Delete optable and optable_special.  Use
2747         optab and optab_special instead.  Throw away old optab,
2748         optab_special and registernames when info->mach changes.
2749
2750 2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>
2751
2752         PR 25377
2753         * z80-dis.c (suffix): Use .db instruction to generate double
2754         prefix.
2755
2756 2020-01-14  Alan Modra  <amodra@gmail.com>
2757
2758         * z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
2759         values to unsigned before shifting.
2760
2761 2020-01-13  Thomas Troeger  <tstroege@gmx.de>
2762
2763         * arm-dis.c (print_insn_arm): Fill in insn info fields for control
2764         flow instructions.
2765         (print_insn_thumb16, print_insn_thumb32): Likewise.
2766         (print_insn): Initialize the insn info.
2767         * i386-dis.c (print_insn): Initialize the insn info fields, and
2768         detect jumps.
2769
2770 2020-01-13  Claudiu Zissulescu <claziss@gmail.com>
2771
2772         * arc-opc.c (C_NE): Make it required.
2773
2774 2020-01-13  Claudiu Zissulescu <claziss@gmail.com>
2775
2776         * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
2777         reserved register name.
2778
2779 2020-01-13  Alan Modra  <amodra@gmail.com>
2780
2781         * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
2782         (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
2783
2784 2020-01-13  Alan Modra  <amodra@gmail.com>
2785
2786         * wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
2787         result of wasm_read_leb128 in a uint64_t and check that bits
2788         are not lost when copying to other locals.  Use uint32_t for
2789         most locals.  Use PRId64 when printing int64_t.
2790
2791 2020-01-13  Alan Modra  <amodra@gmail.com>
2792
2793         * score-dis.c: Formatting.
2794         * score7-dis.c: Formatting.
2795
2796 2020-01-13  Alan Modra  <amodra@gmail.com>
2797
2798         * score-dis.c (print_insn_score48): Use unsigned variables for
2799         unsigned values.  Don't left shift negative values.
2800         (print_insn_score32): Likewise.
2801         * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
2802
2803 2020-01-13  Alan Modra  <amodra@gmail.com>
2804
2805         * tic4x-dis.c (tic4x_print_register): Remove dead code.
2806
2807 2020-01-13  Alan Modra  <amodra@gmail.com>
2808
2809         * fr30-ibld.c: Regenerate.
2810
2811 2020-01-13  Alan Modra  <amodra@gmail.com>
2812
2813         * xgate-dis.c (print_insn): Don't left shift signed value.
2814         (ripBits): Formatting, use 1u.
2815
2816 2020-01-10  Alan Modra  <amodra@gmail.com>
2817
2818         * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
2819         * tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
2820
2821 2020-01-10  Alan Modra  <amodra@gmail.com>
2822
2823         * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
2824         and XRREG value earlier to avoid a shift with negative exponent.
2825         * m10200-dis.c (disassemble): Similarly.
2826
2827 2020-01-09  Nick Clifton  <nickc@redhat.com>
2828
2829         PR 25224
2830         * z80-dis.c (ld_ii_ii): Use correct cast.
2831
2832 2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
2833
2834         PR 25224
2835         * z80-dis.c (ld_ii_ii): Use character constant when checking
2836         opcode byte value.
2837
2838 2020-01-09  Jan Beulich  <jbeulich@suse.com>
2839
2840         * i386-dis.c (SEP_Fixup): New.
2841         (SEP): Define.
2842         (dis386_twobyte): Use it for sysenter/sysexit.
2843         (enum x86_64_isa): Change amd64 enumerator to value 1.
2844         (OP_J): Compare isa64 against intel64 instead of amd64.
2845         * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
2846         forms.
2847         * i386-tbl.h: Re-generate.
2848
2849 2020-01-08  Alan Modra  <amodra@gmail.com>
2850
2851         * z8k-dis.c: Include libiberty.h
2852         (instr_data_s): Make max_fetched unsigned.
2853         (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
2854         Don't exceed byte_info bounds.
2855         (output_instr): Make num_bytes unsigned.
2856         (unpack_instr): Likewise for nibl_count and loop.
2857         * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
2858         idx unsigned.
2859         * z8k-opc.h: Regenerate.
2860
2861 2020-01-07  Shahab Vahedi  <shahab@synopsys.com>
2862
2863         * arc-tbl.h (llock): Use 'LLOCK' as class.
2864         (llockd): Likewise.
2865         (scond): Use 'SCOND' as class.
2866         (scondd): Likewise.
2867         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
2868         (scondd): Likewise.
2869
2870 2020-01-06  Alan Modra  <amodra@gmail.com>
2871
2872         * m32c-ibld.c: Regenerate.
2873
2874 2020-01-06  Alan Modra  <amodra@gmail.com>
2875
2876         PR 25344
2877         * z80-dis.c (suffix): Don't use a local struct buffer copy.
2878         Peek at next byte to prevent recursion on repeated prefix bytes.
2879         Ensure uninitialised "mybuf" is not accessed.
2880         (print_insn_z80): Don't zero n_fetch and n_used here,..
2881         (print_insn_z80_buf): ..do it here instead.
2882
2883 2020-01-04  Alan Modra  <amodra@gmail.com>
2884
2885         * m32r-ibld.c: Regenerate.
2886
2887 2020-01-04  Alan Modra  <amodra@gmail.com>
2888
2889         * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
2890
2891 2020-01-04  Alan Modra  <amodra@gmail.com>
2892
2893         * crx-dis.c (match_opcode): Avoid shift left of signed value.
2894
2895 2020-01-04  Alan Modra  <amodra@gmail.com>
2896
2897         * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
2898
2899 2020-01-03  Jan Beulich  <jbeulich@suse.com>
2900
2901         * aarch64-tbl.h (aarch64_opcode_table): Use
2902         SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
2903
2904 2020-01-03  Jan Beulich  <jbeulich@suse.com>
2905
2906         * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
2907         forms of SUDOT and USDOT.
2908
2909 2020-01-03  Jan Beulich  <jbeulich@suse.com>
2910
2911         * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
2912         uzip{1,2}.
2913         * aarch64-dis-2.c: Re-generate.
2914
2915 2020-01-03  Jan Beulich  <jbeulich@suse.com>
2916
2917         * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
2918         FMMLA encoding.
2919         * aarch64-dis-2.c: Re-generate.
2920
2921 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
2922
2923         * z80-dis.c: Add support for eZ80 and Z80 instructions.
2924
2925 2020-01-01  Alan Modra  <amodra@gmail.com>
2926
2927         Update year range in copyright notice of all files.
2928
2929 For older changes see ChangeLog-2019
2930 \f
2931 Copyright (C) 2020 Free Software Foundation, Inc.
2932
2933 Copying and distribution of this file, with or without modification,
2934 are permitted in any medium without royalty provided the copyright
2935 notice and this notice are preserved.
2936
2937 Local Variables:
2938 mode: change-log
2939 left-margin: 8
2940 fill-column: 74
2941 version-control: never
2942 End: