1 2021-10-27 Maciej W. Rozycki <macro@embecosm.com>
3 * Makefile.am: Remove obsolete comment.
4 * configure.ac: Refer `libbfd.la' to link shared BFD library
6 * Makefile.in: Regenerate.
7 * configure: Regenerate.
9 2021-09-27 Nick Alcock <nick.alcock@oracle.com>
11 * configure: Regenerate.
13 2021-09-25 Peter Bergner <bergner@linux.ibm.com>
15 * ppc-opc.c (powerpc_opcodes) <mfppr, mfppr32, mtppr, mtppr32>: Enable
18 2021-09-20 Andrew Burgess <andrew.burgess@embecosm.com>
20 * riscv-dis.c (riscv_disassemble_insn): Print a .%dbyte opcode
21 before an unknown instruction, '%d' is replaced with the
24 2021-09-02 Nick Clifton <nickc@redhat.com>
27 * v850-opc.c (D16): Use BFD_RELOC_V850_LO16_SPLIT_OFFSET in place
30 2021-08-17 Shahab Vahedi <shahab@synopsys.com>
32 * arc-regs.h (DEF): Fix the register numbers.
34 2021-08-10 Nick Clifton <nickc@redhat.com>
36 * po/sr.po: Updated Serbian translation.
38 2021-07-26 Chenghua Xu <xuchenghua@loongson.cn>
40 * mips-dis.c (mips_arch_choices): Correct gs264e bfd_mach.
42 2021-06-07 Andreas Krebbel <krebbel@linux.ibm.com>
44 * s390-opc.txt: Add qpaci.
46 2021-07-03 Nick Clifton <nickc@redhat.com>
48 * configure: Regenerate.
49 * po/opcodes.pot: Regenerate.
51 2021-07-03 Nick Clifton <nickc@redhat.com>
53 * 2.37 release branch created.
55 2021-07-02 Alan Modra <amodra@gmail.com>
57 * nds32-dis.c (nds32_find_reg_keyword): Constify arg and return.
58 (nds32_parse_audio_ext, nds32_parse_opcode): Constify psys_reg.
59 (nds32_field_table, nds32_opcode_table, nds32_keyword_table),
60 (nds32_opcodes, nds32_operand_fields, nds32_keywords),
61 (nds32_keyword_gpr): Move declarations to..
62 * nds32-asm.h: ..here, constifying to match definitions.
64 2021-07-01 Mike Frysinger <vapier@gentoo.org>
66 * Makefile.am (GUILE): New variable.
68 * Makefile.in: Regenerate.
70 2021-07-01 Mike Frysinger <vapier@gentoo.org>
72 * mep-asm.c (macros): Mark static & const.
73 (lookup_macro): Change return & m to const.
74 (expand_macro): Change mac to const.
75 (expand_string): Change pmacro to const.
77 2021-07-01 Mike Frysinger <vapier@gentoo.org>
79 * nds32-asm.c (operand_fields): Rename to ...
80 (nds32_operand_fields): ... this.
81 (keyword_gpr): Rename to ...
82 (nds32_keyword_gpr): ... this.
83 (keyword_usr, keyword_dxr, keyword_sr, keyword_cp, keyword_cpr,
84 keyword_fsr, keyword_fdr, keyword_abdim, keyword_abm,
85 keyword_dpref_st, keyword_cctl_lv, keyword_standby_st,
86 keyword_msync_st, keyword_im5_i, keyword_im5_m, keyword_accumulator,
87 keyword_aridx, keyword_aridx2, keyword_aridxi, keyword_aridxi_mx):
89 (keywords): Rename to ...
90 (nds32_keywords): ... this.
91 * nds32-dis.c: Rename operand_fields to nds32_operand_fields,
92 keywords to nds32_keywords, and keyword_gpr to nds32_keyword_gpr.
94 2021-07-01 Mike Frysinger <vapier@gentoo.org>
96 * z80-dis.c (opc_ed): Make const.
97 (pref_ed): Make p const.
99 2021-07-01 Mike Frysinger <vapier@gentoo.org>
101 * microblaze-dis.c (get_field_special): Make op const.
102 (read_insn_microblaze): Make opr & op const. Rename opcodes to
104 (print_insn_microblaze): Make op & pop const.
105 (get_insn_microblaze): Make op const. Rename opcodes to
107 (microblaze_get_target_address): Likewise.
108 * microblaze-opc.h (struct op_code_struct): Make const.
109 Rename opcodes to microblaze_opcodes.
111 2021-07-01 Mike Frysinger <vapier@gentoo.org>
113 * aarch64-gen.c (aarch64_opcode_table): Add const.
114 * aarch64-tbl.h (aarch64_opcode_table): Likewise.
116 2021-06-22 Andrew Burgess <andrew.burgess@embecosm.com>
118 * cgen-dis.c (count_decodable_bits): Use __builtin_popcount when
121 2021-06-22 Alan Modra <amodra@gmail.com>
123 * pj-dis.c (print_insn_pj): Don't print trailing tab. Do
124 print separator for pcrel insns.
126 2021-06-19 Alan Modra <amodra@gmail.com>
128 * vax-dis.c (print_insn_vax): Avoid pointer overflow.
130 2021-06-19 Alan Modra <amodra@gmail.com>
132 * tic30-dis.c (get_register_operand): Don't ask strncpy to fill
135 2021-06-17 Alan Modra <amodra@gmail.com>
137 * ppc-opc.c (powerpc_opcodes): Move cell db*cyc to proper location
140 2021-06-03 Alan Modra <amodra@gmail.com>
143 * mcore-dis.c (print_insn_mcore): Correct loopt disassembly.
144 Use unsigned int for inst.
146 2021-06-02 Shahab Vahedi <shahab@synopsys.com>
148 * arc-dis.c (arc_option_arg_t): New enumeration.
149 (arc_options): New variable.
150 (disassembler_options_arc): New function.
151 (print_arc_disassembler_options): Reimplement in terms of
152 "disassembler_options_arc".
154 2021-05-29 Alan Modra <amodra@gmail.com>
156 * ppc-dis.c (lookup_powerpc): Test deprecated field when -Many.
157 Don't special case PPC_OPCODE_RAW.
158 (lookup_prefix): Likewise.
159 (lookup_vle, lookup_spe2): Similarly. Add dialect parameter and..
160 (print_insn_powerpc): ..update caller.
161 * ppc-opc.c (EXT): Define.
162 (powerpc_opcodes): Mark extended mnemonics with EXT.
163 (prefix_opcodes, vle_opcodes): Likewise.
164 (XISEL, XISEL_MASK): Add cr field and simplify.
165 (powerpc_opcodes): Use XISEL with extended isel mnemonics and sort
166 all isel variants to where the base mnemonic belongs. Sort dstt,
169 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
171 * mips-opc.c (mips_builtin_opcodes): Reorder legacy COP0, COP2,
172 COP3 opcode instructions.
174 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
176 * mips-opc.c (mips_builtin_opcodes): Update exclusion list for
177 "ldc2", "ldc3", "lwc0", "lwc2", "lwc3", "sdc2", "sdc3", "swc0",
178 "swc2", "swc3", "cfc0", "ctc0", "bc2f", "bc2fl", "bc2t",
179 "bc2tl", "cfc2", "ctc2", "dmfc2", "dmtc2", "mfc2", "mtc2",
180 "bc3f", "bc3fl", "bc3t", "bc3tl", "cfc3", "ctc3", "mfc3",
181 "mtc3", "bc0f", "bc0fl", "bc0t", "bc0tl", "rfe", "c2", "c3",
182 "cop2", and "cop3" entries.
184 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
186 * mips-opc.c (mips_builtin_opcodes): Remove "dmfc3" and "dmtc3"
187 entries and associated comments.
189 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
191 * mips-opc.c (mips_builtin_opcodes): Move the "rfe" entry ahead
194 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
196 * mips-dis.c (mips_cp1_names_mips): New variable.
197 (mips_arch_choices): Use it rather than `mips_cp1_names_numeric'
198 for "r3000", "r4000", "r4010", "vr4100", "vr4111", "vr4120",
199 "r4300", "r4400", "r4600", "r4650", "r5000", "vr5400", "vr5500",
200 "r5900", "r6000", "rm7000", "rm9000", "r8000", "r10000",
201 "r12000", "r14000", "r16000", "mips5", "loongson2e", and
204 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
206 * mips-dis.c (print_reg) <OP_REG_COPRO>: Move control register
207 handling code over to...
208 <OP_REG_CONTROL>: ... this new case.
209 * mips-opc.c (decode_mips_operand) <'g', 'y'>: New cases.
210 (mips_builtin_opcodes): Update "cfc1", "ctc1", "cttc1", "cttc2",
211 "cfc0", "ctc0", "cfc2", "ctc2", "cfc3", and "ctc3" entries
212 replacing the `G' operand code with `g'. Update "cftc1" and
213 "cftc2" entries replacing the `E' operand code with `y'.
214 * micromips-opc.c (decode_micromips_operand) <'g'>: New case.
215 (micromips_opcodes): Update "cfc1", "cfc2", "ctc1", and "ctc2"
216 entries replacing the `G' operand code with `g'.
218 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
220 * mips-dis.c (mips_cp0_names_r3900): New variable.
221 (mips_arch_choices): Use it rather than `mips_cp0_names_numeric'
224 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
226 * mips-opc.c (mips_builtin_opcodes): Switch "cttc2", "mttc2",
227 and "mtthc2" to using the `G' rather than `g' operand code for
228 the coprocessor control register referred.
230 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
232 * micromips-opc.c (micromips_opcodes): Swap the two "dmtc1"
233 entries with each other.
235 2021-05-27 Peter Bergner <bergner@linux.ibm.com>
237 * ppc-opc.c (powerpc_opcodes) <xxmr, xxlnot>: New extended mnemonics.
239 2021-05-25 Alan Modra <amodra@gmail.com>
241 * cris-desc.c: Regenerate.
242 * cris-desc.h: Regenerate.
243 * cris-opc.h: Regenerate.
244 * po/POTFILES.in: Regenerate.
246 2021-05-24 Mike Frysinger <vapier@gentoo.org>
248 * Makefile.am (HFILES): Add cris-desc.h & cris-opc.h.
249 (TARGET_LIBOPCODES_CFILES): Add cris-desc.c.
250 (CGEN_CPUS): Add cris.
252 (stamp-cris): New rule.
253 * cgen.sh: Handle desc action.
254 * configure.ac (bfd_cris_arch): Add cris-desc.lo.
255 * Makefile.in, configure: Regenerate.
257 2021-05-18 Job Noorman <mtvec@pm.me>
260 * riscv-dis.c (riscv_get_disassembler): Get elf attributes only for
263 2021-05-17 Alex Coplan <alex.coplan@arm.com>
265 * arm-dis.c (mve_opcodes): Fix disassembly of
266 MVE_VMOV2_GP_TO_VEC_LANE when idx == 1.
267 (is_mve_encoding_conflict): MVE vector loads should not match
269 (is_mve_unpredictable): It's not unpredictable to use the same
270 source register twice (for MVE_VMOV2_GP_TO_VEC_LANE).
272 2021-05-11 Nick Clifton <nickc@redhat.com>
275 * tic30-dis.c (print_insn_tic30): Prevent attempts to read beyond
276 the end of the code buffer.
278 2021-05-06 Stafford Horne <shorne@gmail.com>
281 * or1k-asm.c: Regenerate.
283 2021-05-01 Max Filippov <jcmvbkbc@gmail.com>
285 * xtensa-dis.c (print_insn_xtensa): Fill in info->insn_type and
286 info->insn_info_valid.
288 2021-04-26 Jan Beulich <jbeulich@suse.com>
290 * i386-opc.tbl (lea): Add Optimize.
291 * opcodes/i386-tbl.h: Re-generate.
293 2020-04-23 Max Filippov <jcmvbkbc@gmail.com>
295 * xtensa-dis.c (print_xtensa_operand): For PC-relative operand
296 of l32r fetch and display referenced literal value.
298 2021-04-23 Max Filippov <jcmvbkbc@gmail.com>
300 * xtensa-dis.c (print_insn_xtensa): Set info->bytes_per_chunk
301 to 4 for literal disassembly.
303 2021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
305 * aarch64-opc.c: Add new registers (RPAOS, RPALOS, PAALLOS, PAALL) support
306 for TLBI instruction.
308 2021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
310 * aarch64-opc.c: Add new register (CIPAPA, CIGDPAPA) support for
313 2021-04-19 Jan Beulich <jbeulich@suse.com>
315 * aarch64-asm.c (encode_asimd_fcvt): Add initializer for
317 (convert_mov_to_movewide): Add initializer for "value".
319 2021-04-16 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
321 * aarch64-opc.c: Add RME system registers.
323 2021-04-16 Lifang Xia <lifang_xia@c-sky.com>
325 * riscv-opc.c (riscv_opcodes): New insn alias for addi. Compress
326 "addi d,CV,z" to "c.mv d,CV".
328 2021-04-12 Alan Modra <amodra@gmail.com>
330 * configure.ac (--enable-checking): Add support.
331 * config.in: Regenerate.
332 * configure: Regenerate.
334 2021-04-09 Tejas Belagod <tejas.belagod@arm.com>
336 * aarch64-tbl.h (struct aarch64_opcode aarch64_opcode_table): Reclassify
337 LD64/ST64 instructions to lse_atomic instead of ldstexcl.
339 2021-04-09 Alan Modra <amodra@gmail.com>
341 * ppc-dis.c (struct dis_private): Add "special".
342 (POWERPC_DIALECT): Delete. Replace uses with..
343 (private_data): ..this. New inline function.
344 (disassemble_init_powerpc): Init "special" names.
345 (skip_optional_operands): Add is_pcrel arg, set when detecting R
346 field of prefix instructions.
347 (bsearch_reloc, print_got_plt): New functions.
348 (print_insn_powerpc): For pcrel instructions, print target address
349 and symbol if known, and decode plt and got loads too.
351 2021-04-08 Alan Modra <amodra@gmail.com>
354 * ppc-opc.c (powerpc_opcodes): Correct usprg typos, add mfpir.
356 2021-04-08 Alan Modra <amodra@gmail.com>
359 * ppc-opc.c (DCBT_EO): Move earlier.
360 (insert_thct, extract_thct, insert_thds, extract_thds): New functions.
361 (powerpc_operands): Add THCT and THDS entries.
362 (powerpc_opcodes): Add dcbtstct, dcbtstds, dcbna, dcbtct, dcbtds.
364 2021-04-06 Alan Modra <amodra@gmail.com>
366 * dis-buf.c (generic_symbol_at_address): Return symbol* NULL.
367 * s12z-dis.c (decode_possible_symbol): Use symbol returned from
368 symbol_at_address_func.
370 2021-04-05 Alan Modra <amodra@gmail.com>
372 * configure.ac: Don't check for limits.h, string.h, strings.h or
374 (AC_ISC_POSIX): Don't invoke.
375 * sysdep.h: Include stdlib.h and string.h unconditionally.
376 * i386-opc.h: Include limits.h unconditionally.
377 * wasm32-dis.c: Likewise.
378 * cgen-opc.c: Don't include alloca-conf.h.
379 * config.in: Regenerate.
380 * configure: Regenerate.
382 2021-04-01 Martin Liska <mliska@suse.cz>
384 * arm-dis.c (strneq): Remove strneq and use startswith.
385 * cr16-dis.c (print_insn_cr16): Likewise.
386 * score-dis.c (streq): Likewise.
388 * score7-dis.c (strneq): Likewise.
390 2021-04-01 Alan Modra <amodra@gmail.com>
393 * ppc-opc.c (powerpc_opcodes): Add mfummcr2 and mfmmcr2.
395 2021-03-31 Alan Modra <amodra@gmail.com>
397 * sysdep.h (POISON_BFD_BOOLEAN): Define.
398 * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h,
399 * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h,
400 * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c,
401 * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c,
402 * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c,
403 * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c,
404 * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c,
405 * microblaze-dis.h, * micromips-opc.c, * mips-dis.c,
406 * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c,
407 * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c,
408 * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c,
409 * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c,
410 * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false,
411 and TRUE with true throughout.
413 2021-03-31 Alan Modra <amodra@gmail.com>
415 * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h.
416 * aarch64-dis.h: Likewise.
417 * aarch64-opc.c: Likewise.
418 * avr-dis.c: Likewise.
419 * csky-dis.c: Likewise.
420 * nds32-asm.c: Likewise.
421 * nds32-dis.c: Likewise.
422 * nfp-dis.c: Likewise.
423 * riscv-dis.c: Likewise.
424 * s12z-dis.c: Likewise.
425 * wasm32-dis.c: Likewise.
427 2021-03-30 Jan Beulich <jbeulich@suse.com>
429 * i386-opc.c (cs, ds, ss, es, fs, gs): Delete.
430 (i386_seg_prefixes): New.
431 * i386-opc.h (cs, ds, ss, es, fs, gs): Delete.
432 (i386_seg_prefixes): Declare.
434 2021-03-30 Jan Beulich <jbeulich@suse.com>
436 * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Delete.
438 2021-03-30 Jan Beulich <jbeulich@suse.com>
440 * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Adjust values.
441 * i386-reg.tbl (st): Move down.
442 (st(0)): Delete. Extend comment.
443 * i386-tbl.h: Re-generate.
445 2021-03-29 Jan Beulich <jbeulich@suse.com>
447 * i386-opc.tbl (movq, movabs): Move next to mov counterparts.
448 (cmpsd): Move next to cmps.
449 (movsd): Move next to movs.
450 (cmpxchg16b): Move to separate section.
451 (fisttp, fisttpll): Likewise.
452 (monitor, mwait): Likewise.
453 * i386-tbl.h: Re-generate.
455 2021-03-29 Jan Beulich <jbeulich@suse.com>
457 * i386-opc.tbl (psadbw): Add <sse2:comm>.
459 * i386-tbl.h: Re-generate.
461 2021-03-29 Jan Beulich <jbeulich@suse.com>
463 * i386-opc.tbl (mmx, sse, sse2, sse3, ssse3, sse41, sse42, aes,
464 pclmul, gfni): New templates. Use them wherever possible. Move
465 SSE4.1 pextrw into respective section.
466 * i386-tbl.h: Re-generate.
468 2021-03-29 Jan Beulich <jbeulich@suse.com>
470 * i386-gen.c (output_i386_opcode): Widen type of "opcode". Use
471 strtoull(). Bump upper loop bound. Widen masks. Sanity check
473 * i386-opc.tbl (Prefix_0X66, Prefix_0XF2, Prefix_0XF3): Delete.
474 Convert all of their uses to representation in opcode.
476 2021-03-29 Jan Beulich <jbeulich@suse.com>
478 * i386-opc.h (struct insn_template): Shrink base_opcode to 16
479 bits. Shrink extension_opcode to 9 bits. Make it signed. Change
480 value of None. Shrink operands to 3 bits.
482 2021-03-29 Jan Beulich <jbeulich@suse.com>
484 * i386-gen.c (process_i386_opcode_modifier): New parameter
486 (output_i386_opcode): New local variable "space". Adjust
487 process_i386_opcode_modifier() invocation.
488 (process_i386_opcodes): Adjust process_i386_opcode_modifier()
490 * i386-tbl.h: Re-generate.
492 2021-03-29 Alan Modra <amodra@gmail.com>
494 * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
495 (fp_qualifier_p, get_data_pattern): Likewise.
496 (aarch64_get_operand_modifier_from_value): Likewise.
497 (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
498 (operand_variant_qualifier_p): Likewise.
499 (qualifier_value_in_range_constraint_p): Likewise.
500 (aarch64_get_qualifier_esize): Likewise.
501 (aarch64_get_qualifier_nelem): Likewise.
502 (aarch64_get_qualifier_standard_value): Likewise.
503 (get_lower_bound, get_upper_bound): Likewise.
504 (aarch64_find_best_match, match_operands_qualifier): Likewise.
505 (aarch64_print_operand): Likewise.
506 * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
507 (operand_need_sign_extension, operand_need_shift_by_two): Likewise.
508 (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
509 * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
510 * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
511 (print_insn_tic6x): Likewise.
513 2021-03-29 Alan Modra <amodra@gmail.com>
515 * arc-dis.c (extract_operand_value): Correct NULL cast.
516 * frv-opc.h: Regenerate.
518 2021-03-26 Jan Beulich <jbeulich@suse.com>
520 * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to
522 * i386-tbl.h: Re-generate.
524 2021-03-25 Abid Qadeer <abidh@codesourcery.com>
526 * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
527 immediate in br.n instruction.
529 2021-03-25 Jan Beulich <jbeulich@suse.com>
531 * i386-dis.c (XMGatherD, VexGatherD): New.
532 (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
533 (print_insn): Check masking for S/G insns.
534 (OP_E_memory): New local variable check_gather. Extend mandatory
535 SIB check. Check register conflicts for (EVEX-encoded) gathers.
536 Extend check for disallowed 16-bit addressing.
537 (OP_VEX): New local variables modrm_reg and sib_index. Convert
538 if()s to switch(). Check register conflicts for (VEX-encoded)
539 gathers. Drop no longer reachable cases.
540 * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
543 2021-03-25 Jan Beulich <jbeulich@suse.com>
545 * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
546 zeroing-masking without masking.
548 2021-03-25 Jan Beulich <jbeulich@suse.com>
550 * i386-opc.tbl (invlpgb): Fix multi-operand form.
551 (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
552 single-operand forms as deprecated.
553 * i386-tbl.h: Re-generate.
555 2021-03-25 Alan Modra <amodra@gmail.com>
558 * ppc-opc.c (XLOCB_MASK): Delete.
559 (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
561 (powerpc_opcodes): Accept a BH field on all extended forms of
562 bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
564 2021-03-24 Jan Beulich <jbeulich@suse.com>
566 * i386-gen.c (output_i386_opcode): Drop processing of
567 opcode_length. Calculate length from base_opcode. Adjust prefix
568 encoding determination.
569 (process_i386_opcodes): Drop output of fake opcode_length.
570 * i386-opc.h (struct insn_template): Drop opcode_length field.
571 * i386-opc.tbl: Drop opcode length field from all templates.
572 * i386-tbl.h: Re-generate.
574 2021-03-24 Jan Beulich <jbeulich@suse.com>
576 * i386-gen.c (process_i386_opcode_modifier): Return void. New
577 parameter "prefix". Drop local variable "regular_encoding".
578 Record prefix setting / check for consistency.
579 (output_i386_opcode): Parse opcode_length and base_opcode
580 earlier. Derive prefix encoding. Drop no longer applicable
581 consistency checking. Adjust process_i386_opcode_modifier()
583 (process_i386_opcodes): Adjust process_i386_opcode_modifier()
585 * i386-tbl.h: Re-generate.
587 2021-03-24 Jan Beulich <jbeulich@suse.com>
589 * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
591 * i386-opc.h (Prefix_*): Move #define-s.
592 * i386-opc.tbl: Move pseudo prefix enumerator values to
593 extension opcode field. Introduce pseudopfx template.
594 * i386-tbl.h: Re-generate.
596 2021-03-23 Jan Beulich <jbeulich@suse.com>
598 * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
600 * i386-tbl.h: Re-generate.
602 2021-03-23 Jan Beulich <jbeulich@suse.com>
604 * i386-opc.h (struct insn_template): Move cpu_flags field past
606 * i386-tbl.h: Re-generate.
608 2021-03-23 Jan Beulich <jbeulich@suse.com>
610 * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
611 * i386-opc.h (OpcodeSpace): New enumerator.
612 (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
613 (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
614 SPACE_XOP09, SPACE_XOP0A): ... respectively.
615 (struct i386_opcode_modifier): New field opcodespace. Shrink
617 i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
618 SpaceXOP09, SpaceXOP0A): Define. Use them to replace
620 * i386-tbl.h: Re-generate.
622 2021-03-22 Martin Liska <mliska@suse.cz>
624 * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
625 * arc-dis.c (parse_option): Likewise.
626 * arm-dis.c (parse_arm_disassembler_options): Likewise.
627 * cris-dis.c (print_with_operands): Likewise.
628 * h8300-dis.c (bfd_h8_disassemble): Likewise.
629 * i386-dis.c (print_insn): Likewise.
630 * ia64-gen.c (fetch_insn_class): Likewise.
631 (parse_resource_users): Likewise.
632 (in_iclass): Likewise.
633 (lookup_specifier): Likewise.
634 (insert_opcode_dependencies): Likewise.
635 * mips-dis.c (parse_mips_ase_option): Likewise.
636 (parse_mips_dis_option): Likewise.
637 * s390-dis.c (disassemble_init_s390): Likewise.
638 * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
640 2021-03-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
642 * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
644 2021-03-12 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
646 * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
647 icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
649 2021-03-12 Alan Modra <amodra@gmail.com>
651 * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
653 2021-03-11 Jan Beulich <jbeulich@suse.com>
655 * i386-dis.c (OP_XMM): Re-order checks.
657 2021-03-11 Jan Beulich <jbeulich@suse.com>
659 * i386-dis.c (putop): Drop need_vex check when also checking
661 (intel_operand_size, OP_E_memory): Drop vex.evex check when also
664 2021-03-11 Jan Beulich <jbeulich@suse.com>
666 * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
667 checks. Move case label past broadcast check.
669 2021-03-10 Jan Beulich <jbeulich@suse.com>
671 * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
672 vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
673 REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
674 EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
675 EVEX_W_0F38C7_M_0_L_2): Delete.
676 (REG_EVEX_0F38C7_M_0_L_2): New.
677 (intel_operand_size): Handle VEX and EVEX the same for
678 vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
679 vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
680 (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
681 vex_vsib_q_w_d_mode uses.
682 * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
683 0F38A1, and 0F38A3 entries.
684 * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
686 * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
687 * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
690 2021-03-10 Jan Beulich <jbeulich@suse.com>
692 * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
693 REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
694 MOD_VEX_0FXOP_09_12): Rename to ...
695 (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
696 REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
697 (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
698 RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
699 X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
700 X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
701 (reg_table): Adjust comments.
702 (x86_64_table): Move X86_64_0F24, X86_64_0F26,
703 X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
704 X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
705 (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
706 (vex_len_table): Adjust opcode 0A_12 entry.
707 (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
708 MOD_C5_32BIT, and MOD_XOP_09_12 entries.
709 (rm_table): Move hreset entry.
711 2021-03-10 Jan Beulich <jbeulich@suse.com>
713 * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
714 EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
715 EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
716 EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
717 EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
718 (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
719 (get_valid_dis386): Also handle 512-bit vector length when
720 vectoring into vex_len_table[].
721 * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
722 0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
724 * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
725 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
726 * i386-dis-evex-prefix.h: Adjust 0F7E entry.
727 * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
730 2021-03-10 Jan Beulich <jbeulich@suse.com>
732 * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
733 Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
734 EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
735 * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
737 * i386-dis-evex-len.h (evex_len_table): Likewise.
738 * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
740 2021-03-10 Jan Beulich <jbeulich@suse.com>
742 * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
743 MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
744 MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
745 MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
746 MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
747 MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
748 MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
749 MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
750 EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
751 EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
752 EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
753 EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
754 EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
755 EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
756 EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
757 EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
758 EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
759 EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
760 EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
761 EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
762 EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
763 EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
764 EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
765 EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
766 EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
767 EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
768 EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
769 EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
770 EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
771 EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
772 EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
773 EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
774 REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
775 REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
776 MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
777 MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
778 EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
779 EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
780 EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
781 EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
782 EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
783 EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
784 EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
785 EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
786 EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
787 EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
788 EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
789 EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
790 EVEX_W_0F3A43_L_n): New.
791 * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
792 0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
793 0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
794 * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
795 for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
796 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
797 0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
798 * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
799 0F385B, 0F38C6, and 0F38C7 entries.
800 * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
802 * i386-dis-evex-w.h: No longer link to evex_len_table[] for
803 opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
804 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
805 evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
807 2021-03-10 Jan Beulich <jbeulich@suse.com>
809 * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
810 MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
811 MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
812 MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
813 MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
814 MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
815 MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
816 MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
817 MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
818 MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
819 MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
820 MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
821 MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
822 MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
823 MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
824 MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
825 MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
826 MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
827 MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
828 MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
829 MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
830 MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
831 MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
832 MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
833 MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
834 PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
835 PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
836 PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
837 PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
838 PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
839 VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
840 VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
841 VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
842 VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
843 VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
844 VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
845 VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
846 VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
847 VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
848 VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
849 VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
850 VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
851 VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
852 VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
853 VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
854 VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
855 VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
856 VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
857 VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
858 VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
859 VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
860 VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
861 VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
862 VEX_W_0F99_P_2_LEN_0): Delete.
863 MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
864 MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
865 MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
866 MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
867 MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
868 PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
869 PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
870 PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
871 PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
872 PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
873 PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
874 PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
875 PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
876 PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
877 PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
878 PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
879 PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
880 PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
881 PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
882 VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
883 VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
884 VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
885 VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
886 VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
887 VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
888 VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
889 VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
890 (prefix_table): No longer link to vex_len_table[] for opcodes
891 0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
892 0F92, 0F93, 0F98, and 0F99.
893 (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
894 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
896 (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
897 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
899 (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
900 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
902 (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
903 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
906 2021-03-10 Jan Beulich <jbeulich@suse.com>
908 * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
909 Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
910 REG_VEX_0F73_M_0 respectively.
911 (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
912 MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
913 MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
914 MOD_VEX_0F73_REG_7): Delete.
915 (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
916 (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
917 PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
918 PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
919 PREFIX_VEX_0F3AF0_L_0 respectively.
920 (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
921 VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
922 VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
923 VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
924 (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
925 VEX_LEN_0F38F7): New.
926 (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
927 (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
928 0F72, and 0F73. No longer link to vex_len_table[] for opcode
930 (prefix_table): No longer link to vex_len_table[] for opcodes
931 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
932 (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
933 0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
934 0F38F6, 0F38F7, and 0F3AF0.
935 (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
936 prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
937 (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
940 2021-03-10 Jan Beulich <jbeulich@suse.com>
942 * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
943 REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
944 (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
945 MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
946 MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
947 (MOD_0F71, MOD_0F72, MOD_0F73): New.
948 (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
950 (reg_table): No longer link to mod_table[] for opcodes 0F71,
952 (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
955 2021-03-10 Jan Beulich <jbeulich@suse.com>
957 * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
958 MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
959 (reg_table): Don't link to mod_table[] where not needed. Add
960 PREFIX_IGNORED to nop entries.
961 (prefix_table): Replace PREFIX_OPCODE in nop entries.
962 (mod_table): Add nop entries next to prefetch ones. Drop
963 MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
964 MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
965 (rm_table): Add PREFIX_IGNORED to nop entries. Drop
966 PREFIX_OPCODE from endbr* entries.
967 (get_valid_dis386): Also consider entry's name when zapping
969 (print_insn): Handle PREFIX_IGNORED.
971 2021-03-09 Jan Beulich <jbeulich@suse.com>
973 * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
974 IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
976 * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
977 HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
978 (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
979 PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
980 (struct i386_opcode_modifier): Delete notrackprefixok,
981 islockable, hleprefixok, and repprefixok fields. Add prefixok
983 * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
984 HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
985 (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
986 not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
988 * opcodes/i386-tbl.h: Re-generate.
990 2021-03-09 Jan Beulich <jbeulich@suse.com>
992 * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
993 * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
995 * opcodes/i386-tbl.h: Re-generate.
997 2021-03-03 Jan Beulich <jbeulich@suse.com>
999 * i386-gen.c (output_i386_opcode): Don't get operand count. Look
1000 for {} instead of {0}. Don't look for '0'.
1001 * i386-opc.tbl: Drop operand count field. Drop redundant operand
1004 2021-02-19 Nelson Chu <nelson.chu@sifive.com>
1007 * riscv-dis.c (print_insn_args): Updated encoding macros.
1008 * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
1009 (match_c_addi16sp): Updated encoding macros.
1010 (match_c_lui): Likewise.
1011 (match_c_lui_with_hint): Likewise.
1012 (match_c_addi4spn): Likewise.
1013 (match_c_slli): Likewise.
1014 (match_slli_as_c_slli): Likewise.
1015 (match_c_slli64): Likewise.
1016 (match_srxi_as_c_srxi): Likewise.
1017 (riscv_insn_types): Added .insn css/cl/cs.
1019 2021-02-18 Nelson Chu <nelson.chu@sifive.com>
1021 * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
1022 (default_priv_spec): Updated type to riscv_spec_class.
1023 (parse_riscv_dis_option): Updated.
1024 * riscv-opc.c: Moved stuff and make the file tidy.
1026 2021-02-17 Alan Modra <amodra@gmail.com>
1028 * wasm32-dis.c: Include limits.h.
1029 (CHAR_BIT): Provide backup define.
1030 (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
1031 Correct signed overflow checking.
1033 2021-02-16 Jan Beulich <jbeulich@suse.com>
1035 * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
1036 * i386-tbl.h: Re-generate.
1038 2021-02-16 Jan Beulich <jbeulich@suse.com>
1040 * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
1042 * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
1044 2021-02-15 Andreas Krebbel <krebbel@linux.ibm.com>
1046 * s390-mkopc.c (main): Accept arch14 as cpu string.
1047 * s390-opc.txt: Add new arch14 instructions.
1049 2021-02-04 Nick Alcock <nick.alcock@oracle.com>
1051 * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
1053 * configure: Regenerated.
1055 2021-02-08 Mike Frysinger <vapier@gentoo.org>
1057 * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
1058 * tic54x-opc.c (regs): Rename to ...
1059 (tic54x_regs): ... this.
1060 (mmregs): Rename to ...
1061 (tic54x_mmregs): ... this.
1062 (condition_codes): Rename to ...
1063 (tic54x_condition_codes): ... this.
1064 (cc2_codes): Rename to ...
1065 (tic54x_cc2_codes): ... this.
1066 (cc3_codes): Rename to ...
1067 (tic54x_cc3_codes): ... this.
1068 (status_bits): Rename to ...
1069 (tic54x_status_bits): ... this.
1070 (misc_symbols): Rename to ...
1071 (tic54x_misc_symbols): ... this.
1073 2021-02-04 Nelson Chu <nelson.chu@sifive.com>
1075 * riscv-opc.c (MASK_RVB_IMM): Removed.
1076 (riscv_opcodes): Removed zb* instructions.
1077 (riscv_ext_version_table): Removed versions for zb*.
1079 2021-01-26 Alan Modra <amodra@gmail.com>
1081 * i386-gen.c (parse_template): Ensure entire template_instance
1084 2021-01-15 Nelson Chu <nelson.chu@sifive.com>
1086 * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
1087 (riscv_fpr_names_abi): Likewise.
1088 (riscv_opcodes): Likewise.
1089 (riscv_insn_types): Likewise.
1091 2021-01-15 Nelson Chu <nelson.chu@sifive.com>
1093 * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
1095 2021-01-15 Nelson Chu <nelson.chu@sifive.com>
1097 * riscv-dis.c: Comments tidy and improvement.
1098 * riscv-opc.c: Likewise.
1100 2021-01-13 Alan Modra <amodra@gmail.com>
1102 * Makefile.in: Regenerate.
1104 2021-01-12 H.J. Lu <hongjiu.lu@intel.com>
1107 * configure.ac: Use GNU_MAKE_JOBSERVER.
1108 * aclocal.m4: Regenerated.
1109 * configure: Likewise.
1111 2021-01-12 Nick Clifton <nickc@redhat.com>
1113 * po/sr.po: Updated Serbian translation.
1115 2021-01-11 H.J. Lu <hongjiu.lu@intel.com>
1118 * configure: Regenerated.
1120 2021-01-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
1122 * aarch64-asm-2.c: Regenerate.
1123 * aarch64-dis-2.c: Likewise.
1124 * aarch64-opc-2.c: Likewise.
1125 * aarch64-opc.c (aarch64_print_operand):
1126 Delete handling of AARCH64_OPND_CSRE_CSR.
1127 * aarch64-tbl.h (aarch64_feature_csre): Delete.
1129 (_CSRE_INSN): Likewise.
1130 (aarch64_opcode_table): Delete csr.
1132 2021-01-11 Nick Clifton <nickc@redhat.com>
1134 * po/de.po: Updated German translation.
1135 * po/fr.po: Updated French translation.
1136 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1137 * po/sv.po: Updated Swedish translation.
1138 * po/uk.po: Updated Ukranian translation.
1140 2021-01-09 H.J. Lu <hongjiu.lu@intel.com>
1142 * configure: Regenerated.
1144 2021-01-09 Nick Clifton <nickc@redhat.com>
1146 * configure: Regenerate.
1147 * po/opcodes.pot: Regenerate.
1149 2021-01-09 Nick Clifton <nickc@redhat.com>
1151 * 2.36 release branch crated.
1153 2021-01-08 Peter Bergner <bergner@linux.ibm.com>
1155 * ppc-opc.c (insert_dw, (extract_dw): New functions.
1156 (DW, (XRC_MASK): Define.
1157 (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
1159 2021-01-09 Alan Modra <amodra@gmail.com>
1161 * configure: Regenerate.
1163 2021-01-08 Nick Clifton <nickc@redhat.com>
1165 * po/sv.po: Updated Swedish translation.
1167 2021-01-08 Nick Clifton <nickc@redhat.com>
1170 * aarch64-dis.c (determine_disassembling_preference): Move call to
1171 aarch64_match_operands_constraint outside of the assertion.
1172 * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
1173 Replace with a return of FALSE.
1176 * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
1177 core system register.
1179 2021-01-07 Samuel Thibault <samuel.thibault@gnu.org>
1181 * configure: Regenerate.
1183 2021-01-07 Nick Clifton <nickc@redhat.com>
1185 * po/fr.po: Updated French translation.
1187 2021-01-07 Fredrik Noring <noring@nocrew.org>
1189 * m68k-opc.c (chkl): Change minimum architecture requirement to
1192 2021-01-07 Philipp Tomsich <prt@gnu.org>
1194 * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
1196 2021-01-07 Claire Xenia Wolf <claire@symbioticeda.com>
1197 Jim Wilson <jimw@sifive.com>
1198 Andrew Waterman <andrew@sifive.com>
1199 Maxim Blinov <maxim.blinov@embecosm.com>
1200 Kito Cheng <kito.cheng@sifive.com>
1201 Nelson Chu <nelson.chu@sifive.com>
1203 * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
1204 (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
1206 2021-01-01 Alan Modra <amodra@gmail.com>
1208 Update year range in copyright notice of all files.
1210 For older changes see ChangeLog-2020
1212 Copyright (C) 2021 Free Software Foundation, Inc.
1214 Copying and distribution of this file, with or without modification,
1215 are permitted in any medium without royalty provided the copyright
1216 notice and this notice are preserved.
1222 version-control: never