opcodes/ChangeLog

   1 2010-09-17  Tejas Belagod  <tejas.belagod@arm.com>
   2
   3         * arm_dis.c (coprocessor_opcodes): Add MRC entry for APSR_nzcv.
   4
   5 2010-09-14  Maciej W. Rozycki  <macro@codesourcery.com>
   6
   7         * mips-opc.c (mips_builtin_opcodes): Add "sync_acquire",
   8         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb".
   9
  10 2010-09-10  Pierre Muller  <muller@ics.u-strasbg.fr>
  11
  12         * src/opcodes/dlx-dis.c (print_insn_dlx): Use dlx_insn type for
  13         dlx_insn_type array.
  14
  15 2010-08-31  H.J. Lu  <hongjiu.lu@intel.com>
  16
  17         PR binutils/11960
  18         * i386-dis.c (sIv): New.
  19         (dis386): Replace Iq with sIv on "pushT".
  20         (reg_table): Replace T with {T|} on callT, JcallT, jmpT and JjmpT.
  21         (x86_64_table): Replace {T|}/{P|} with P.
  22         (putop): Add 'w' to 'T'/'P' if needed for Intel syntax.
  23         (OP_sI): Update v_mode.  Remove w_mode.
  24
  25 2010-08-27  Nathan Froyd  <froydnj@codesourcery.com>
  26
  27         * ppc-opc.c (powerpc_opcodes) [lswx,lswi,stswx,stswi]: Deprecate
  28         on E500 and E500MC.
  29
  30 2010-08-17  H.J. Lu  <hongjiu.lu@intel.com>
  31
  32         * i386-dis.c (reg_table): Replace Eb with Mb on prefetch and
  33         prefetchw.
  34
  35 2010-08-06  Quentin Neill <quentin.neill@amd.com>
  36
  37         * i386-gen.c (cpu_flag_init): Define CpuNop extension flag, add
  38         to processor flags for PENTIUMPRO processors and later.
  39         * i386-opc.h (enum): Add CpuNop.
  40         (i386_cpu_flags): Add cpunop bit.
  41         * i386-opc.tbl: Change nop cpu_flags.
  42         * i386-init.h: Regenerated.
  43         * i386-tbl.h: Likewise.
  44
  45 2010-08-06  Quentin Neill <quentin.neill@amd.com>
  46
  47         * i386-opc.h (enum): Fix typos in comments.
  48
  49 2010-08-06  Alan Modra  <amodra@gmail.com>
  50
  51         * disassemble.c: Formatting.
  52         (disassemble_init_for_target <ARCH_m32c>): Comment on endian.
  53
  54 2010-08-05  H.J. Lu  <hongjiu.lu@intel.com>
  55
  56         * i386-opc.tbl: Add Cpu186 to ud1/ud2/ud2a/ud2b.
  57         * i386-tbl.h: Regenerated.
  58
  59 2010-08-05  H.J. Lu  <hongjiu.lu@intel.com>
  60
  61         * i386-dis.c (dis386_twobyte): Replace ud2a/ud2b with ud2/ud1.
  62
  63         * i386-opc.tbl: Add ud1.  Remove Cpu686 from ud2/ud2a/ud2b.
  64         * i386-tbl.h: Regenerated.
  65
  66 2010-07-29  DJ Delorie  <dj@redhat.com>
  67
  68         * rx-decode.opc (SRR): New.
  69         (rx_decode_opcode): Use it for movbi and movbir.  Decode NOP2 (mov
  70         r0,r0) and NOP3 (max r0,r0) special cases.
  71         * rx-decode.c: Regenerate.
  72
  73 2010-07-28  H.J. Lu  <hongjiu.lu@intel.com>
  74
  75         * i386-dis.c: Add 0F to VEX opcode enums.
  76
  77 2010-07-27  DJ Delorie  <dj@redhat.com>
  78
  79         * rx-decode.opc (store_flags): Remove, replace with F_* macros.
  80         (rx_decode_opcode): Likewise.
  81         * rx-decode.c: Regenerate.
  82
  83 2010-07-23  Naveen.H.S  <naveen.S@kpitcummins.com>
  84             Ina Pandit  <ina.pandit@kpitcummins.com>
  85
  86         * v850-dis.c (v850_sreg_names): Updated structure for system
  87         registers.
  88         (float_cc_names): new structure for condition codes.
  89         (print_value): Update the function that prints value.
  90         (get_operand_value): New function to get the operand value.
  91         (disassemble): Updated to handle the disassembly of instructions.
  92         (print_insn_v850): Updated function to print instruction for different
  93         families.
  94         * opcodes/v850-opc.c (v850_msg_is_out_of_range, insert_i5div1,
  95         extract_i5div1, insert_i5div2, extract_i5div2, insert_i5div3,
  96         extract_i5div3, insert_d5_4, extract_d5_4, extract_d8_6,
  97         insert_d8_7, extract_d8_7, insert_v8, extract_v8, insert_u16_loop,
  98         extract_u16_loop, insert_d16_15, extract_d16_15, insert_d16_16,
  99         extract_d16_16, nsert_d17_16, extract_d17_16, insert_d22,
 100         extract_d22, insert_d23, extract_d23, insert_i9, extract_i9,
 101         insert_u9, extract_u9, extract_spe, insert_r4, extract_r4): New.
 102         (insert_d8_7, insert_d5_4, insert_i5div): Remove.
 103         (v850_operands): Update with the relocation name. Also update
 104         the instructions with specific set of processors.
 105
 106 2010-07-08 Tejas Belagod <tejas.belagod@arm.com>
 107
 108         * arm-dis.c (print_insn_arm): Add cases for printing more
 109         symbolic operands.
 110         (print_insn_thumb32): Likewise.
 111
 112 2010-07-06  Maciej W. Rozycki  <macro@codesourcery.com>
 113
 114         * mips-dis.c (print_insn_mips): Correct branch instruction type
 115         determination.
 116
 117 2010-07-06  Maciej W. Rozycki  <macro@codesourcery.com>
 118
 119         * mips-dis.c (print_mips16_insn_arg): Remove branch instruction
 120         type and delay slot determination.
 121         (print_insn_mips16): Extend branch instruction type and delay
 122         slot determination to cover all instructions.
 123         * mips16-opc.c (BR): Remove macro.
 124         (UBR, CBR): New macros.
 125         (mips16_opcodes): Update branch annotation for "b", "beqz",
 126         "bnez", "bteqz" and "btnez".  Add branch annotation for "jalrc"
 127         and "jrc".
 128
 129 2010-07-05  H.J. Lu  <hongjiu.lu@intel.com>
 130
 131         AVX Programming Reference (June, 2010)
 132         * i386-dis.c (mod_table): Replace rdrnd with rdrand.
 133         * i386-opc.tbl: Likewise.
 134         * i386-tbl.h: Regenerated.
 135
 136 2010-07-05  H.J. Lu  <hongjiu.lu@intel.com>
 137
 138         * i386-opc.h (CpuFSGSBase): Fix a typo in comments.
 139
 140 2010-07-03  Andreas Schwab  <schwab@linux-m68k.org>
 141
 142         * ppc-dis.c (powerpc_init_dialect): Cast PPC_OPCODE_xxx to
 143         ppc_cpu_t before inverting.
 144         (ppc_parse_cpu): Likewise.
 145         (print_insn_powerpc): Likewise.
 146
 147 2010-07-03  Alan Modra  <amodra@gmail.com>
 148
 149         * ppc-dis.c (ppc_opts, powerpc_init_dialect): Remove old opcode flags.
 150         * ppc-opc.c (PPC32, POWER32, COM32, CLASSIC): Delete.
 151         (PPC64, MFDEC2): Update.
 152         (NON32, NO371): Define.
 153         (powerpc_opcode): Update to not use old opcode flags, and avoid
 154         -m601 duplicates.
 155
 156 2010-07-03  DJ Delorie  <dj@delorie.com>
 157
 158         * m32c-ibld.c: Regenerate.
 159
 160 2010-07-03  Alan Modra  <amodra@gmail.com>
 161
 162         * ppc-opc.c (PWR2COM): Define.
 163         (PPCPWR2): Add PPC_OPCODE_COMMON.
 164         (powerpc_opcodes): Add "subc", "subco", "subco.", "fcir", "fcir.",
 165         "fcirz", "fcirz." to -mcom opcodes.  Remove "mfsri", "dclst",
 166         "rac" from -mcom.
 167
 168 2010-07-01  H.J. Lu  <hongjiu.lu@intel.com>
 169
 170         AVX Programming Reference (June, 2010)
 171         * i386-dis.c (PREFIX_0FAE_REG_0): New.
 172         (PREFIX_0FAE_REG_1): Likewise.
 173         (PREFIX_0FAE_REG_2): Likewise.
 174         (PREFIX_0FAE_REG_3): Likewise.
 175         (PREFIX_VEX_3813): Likewise.
 176         (PREFIX_VEX_3A1D): Likewise.
 177         (prefix_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
 178         PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3, PREFIX_VEX_3813 and
 179         PREFIX_VEX_3A1D.
 180         (vex_table): Add PREFIX_VEX_3813 and PREFIX_VEX_3A1D.
 181         (mod_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
 182         PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3 xsaveopt and rdrnd.
 183
 184         * i386-gen.c (cpu_flag_init): Add CPU_XSAVEOPT_FLAGS,
 185         CPU_FSGSBASE_FLAGS, CPU_RDRND_FLAGS and CPU_F16C_FLAGS.
 186         (cpu_flags): Add CpuXsaveopt, CpuFSGSBase, CpuRdRnd and CpuF16C.
 187
 188         * i386-opc.h (CpuXsaveopt): New.
 189         (CpuFSGSBase): Likewise.
 190         (CpuRdRnd): Likewise.
 191         (CpuF16C): Likewise.
 192         (i386_cpu_flags): Add cpuxsaveopt, cpufsgsbase, cpurdrnd and
 193         cpuf16c.
 194
 195         * i386-opc.tbl: Add xsaveopt, rdfsbase, rdgsbase, rdrnd,
 196         wrfsbase, wrgsbase, vcvtph2ps and vcvtps2ph.
 197         * i386-init.h: Regenerated.
 198         * i386-tbl.h: Likewise.
 199
 200 2010-07-01  Sebastian Andrzej Siewior  <bigeasy@linutronix.de>
 201
 202         * ppc-opc.c (powerpc_opcodes): Revert deprecation of mfocrf, mtcrf
 203         and mtocrf on EFS.
 204
 205 2010-06-29  Alan Modra  <amodra@gmail.com>
 206
 207         * maxq-dis.c: Delete file.
 208         * Makefile.am: Remove references to maxq.
 209         * configure.in: Likewise.
 210         * disassemble.c: Likewise.
 211         * Makefile.in: Regenerate.
 212         * configure: Regenerate.
 213         * po/POTFILES.in: Regenerate.
 214
 215 2010-06-29  Alan Modra  <amodra@gmail.com>
 216
 217         * mep-dis.c: Regenerate.
 218
 219 2010-06-28  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 220
 221         * arm-disc.c (parse_insn_neon):  Fix Neon alignment syntax.
 222
 223 2010-06-27  Alan Modra  <amodra@gmail.com>
 224
 225         * arc-dis.c (arc_sprintf): Delete set but unused variables.
 226         (decodeInstr): Likewise.
 227         * dlx-dis.c (print_insn_dlx): Likewise.
 228         * h8300-dis.c (bfd_h8_disassemble_init): Likewise.
 229         * maxq-dis.c (check_move, print_insn): Likewise.
 230         * mep-dis.c (mep_examine_ivc2_insns): Likewise.
 231         * msp430-dis.c (msp430_branchinstr): Likewise.
 232         * bfin-dis.c (_print_insn_bfin): Avoid set but unused warning.
 233         * cgen-asm.in (parse_insn_normal, _cgen_assemble_insn): Likewise.
 234         * sparc-dis.c (print_insn_sparc): Likewise.
 235         * fr30-asm.c: Regenerate.
 236         * frv-asm.c: Regenerate.
 237         * ip2k-asm.c: Regenerate.
 238         * iq2000-asm.c: Regenerate.
 239         * lm32-asm.c: Regenerate.
 240         * m32c-asm.c: Regenerate.
 241         * m32r-asm.c: Regenerate.
 242         * mep-asm.c: Regenerate.
 243         * mt-asm.c: Regenerate.
 244         * openrisc-asm.c: Regenerate.
 245         * xc16x-asm.c: Regenerate.
 246         * xstormy16-asm.c: Regenerate.
 247
 248 2010-06-16  Vincent Rivière  <vincent.riviere@freesbee.fr>
 249
 250         PR gas/11673
 251         * m68k-opc.c (m68k_opcodes): Remove move.l for isab and later.
 252
 253 2010-06-16  Vincent Rivière  <vincent.riviere@freesbee.fr>
 254
 255         PR binutils/11676
 256         * m68k-dis.c (print_insn_arg): Prefix float constants with #0e.
 257
 258 2010-06-14  Sebastian Andrzej Siewior  <bigeasy@linutronix.de>
 259
 260         * ppc-dis.c (ppc_opts):  Remove PPC_OPCODE_E500MC from e500 and
 261         e500x2.  Add PPC_OPCODE_E500 to e500 and e500x2
 262         * ppc-opc.c (powerpc_opcodes): Deprecate all opcodes on EFS which
 263         touch floating point regs and are enabled by COM, PPC or PPCCOM.
 264         Treat sync as msync on e500.  Treat eieio as mbar 1 on e500.
 265         Treat lwsync as msync on e500.
 266
 267 2010-06-07  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 268
 269         * arm-dis.c (thumb-opcodes): Add disassembly for movs.
 270
 271 2010-05-28  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 272
 273         * arm-dis.c (print_insn_neon):  Ensure disassembly of Neon
 274         constants is the same on 32-bit and 64-bit hosts.
 275
 276 2010-05-27  Jason Duerstock  <jason.duerstock+binutils@gmail.com>
 277
 278         * m68k-dis.c (print_insn_m68k): Emit undefined instructions as
 279         .short directives so that they can be reassembled.
 280
 281 2010-05-26  Catherine Moore <clm@codesourcery.com>
 282             David Ung  <davidu@mips.com>
 283
 284         * mips-opc.c: Change membership to I1 for instructions ssnop and
 285         ehb.
 286
 287 2010-05-26  H.J. Lu  <hongjiu.lu@intel.com>
 288
 289         * i386-dis.c (sib): New.
 290         (get_sib): Likewise.
 291         (print_insn): Call get_sib.
 292         OP_E_memory): Use sib.
 293
 294 2010-05-26  Catherine Moore  <clm@codesoourcery.com>
 295
 296         * mips-dis.c (mips_arch): Remove INSN_MIPS16.
 297         * mips-opc.c (I16): Remove.
 298         (mips_builtin_op): Reclassify jalx.
 299
 300 2010-05-19  Alan Modra  <amodra@gmail.com>
 301
 302         * ppc-opc.c (powerpc_opcodes): Enable divdeu, devweu, divde,
 303         divwe, divdeuo, divweuo, divdeo, divweo for A2.  Add icswepx.
 304
 305 2010-05-13  Alan Modra  <amodra@gmail.com>
 306
 307         * ppc-opc.c (powerpc_opcodes): Correct wclr encoding.
 308
 309 2010-05-11  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 310
 311         * arm-dis.c (thumb_opcodes): Update ldmia entry to use new %W
 312         format.
 313         (print_insn_thumb16): Add support for new %W format.
 314
 315 2010-05-07  Tristan Gingold  <gingold@adacore.com>
 316
 317         * Makefile.in: Regenerate with automake 1.11.1.
 318         * aclocal.m4: Ditto.
 319
 320 2010-05-05  Nick Clifton  <nickc@redhat.com>
 321
 322         * po/es.po: Updated Spanish translation.
 323
 324 2010-04-22  Nick Clifton  <nickc@redhat.com>
 325
 326         * po/opcodes.pot: Updated by the Translation project.
 327         * po/vi.po: Updated Vietnamese translation.
 328
 329 2010-04-16  H.J. Lu  <hongjiu.lu@intel.com>
 330
 331         * i386-dis.c (get_valid_dis386): Return bad_opcode on unknown
 332         bits in opcode.
 333
 334 2010-04-09  Nick Clifton  <nickc@redhat.com>
 335
 336         * i386-dis.c (print_insn): Remove unused variable op.
 337         (OP_sI): Remove unused variable mask.
 338
 339 2010-04-07  Alan Modra  <amodra@gmail.com>
 340
 341         * configure: Regenerate.
 342
 343 2010-04-06  Peter Bergner  <bergner@vnet.ibm.com>
 344
 345         * ppc-opc.c (RBOPT): New define.
 346         ("dccci"): Enable for PPCA2.  Make operands optional.
 347         ("iccci"): Likewise.  Do not deprecate for PPC476.
 348
 349 2010-04-02  Masaki Muranaka  <monaka@monami-software.com>
 350
 351         * cr16-opc.c (cr16_instruction): Fix typo in comment.
 352
 353 2010-03-25  Joseph Myers  <joseph@codesourcery.com>
 354
 355         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add tic6x-dis.c.
 356         * Makefile.in: Regenerate.
 357         * configure.in (bfd_tic6x_arch): New.
 358         * configure: Regenerate.
 359         * disassemble.c (ARCH_tic6x): Define if ARCH_all.
 360         (disassembler): Handle TI C6X.
 361         * tic6x-dis.c: New.
 362
 363 2010-03-24  Mike Frysinger  <vapier@gentoo.org>
 364
 365         * bfin-dis.c (decode_regs_hi): Change REG_LH2 typo to REG_MH2.
 366
 367 2010-03-23  Joseph Myers  <joseph@codesourcery.com>
 368
 369         * dis-buf.c (buffer_read_memory): Give error for reading just
 370         before the start of memory.
 371
 372 2010-03-22  Sebastian Pop  <sebastian.pop@amd.com>
 373             Quentin Neill <quentin.neill@amd.com>
 374
 375         * i386-dis.c (OP_LWP_I): Removed.
 376         (reg_table): Do not use OP_LWP_I, use Iq.
 377         (OP_LWPCB_E): Remove use of names16.
 378         (OP_LWP_E): Same.
 379         * i386-opc.tbl: Removed 16bit LWP insns.  32bit LWP insns
 380         should not set the Vex.length bit.
 381         * i386-tbl.h: Regenerated.
 382
 383 2010-02-25  Edmar Wienskoski  <edmar@freescale.com>
 384
 385         * ppc-dis.c (ppc_opts): Add PPC_OPCODE_E500MC for "e500mc64".
 386
 387 2010-02-24  Nick Clifton  <nickc@redhat.com>
 388
 389         PR binutils/6773
 390         * arm-dis.c (arm_opcodes): Replace <prefix>addsubx with
 391         <prefix>asx.  Replace <prefix>subaddx with <prefix>sax.
 392         (thumb32_opcodes): Likewise.
 393
 394 2010-02-15  Nick Clifton  <nickc@redhat.com>
 395
 396         * po/vi.po: Updated Vietnamese translation.
 397
 398 2010-02-12  Doug Evans  <dje@sebabeach.org>
 399
 400         * lm32-opinst.c: Regenerate.
 401
 402 2010-02-11  Doug Evans  <dje@sebabeach.org>
 403
 404         * cgen-dis.in (print_normal): Delete CGEN_PRINT_NORMAL.
 405         (print_address): Delete CGEN_PRINT_ADDRESS.
 406         * fr30-dis.c, * frv-dis.c, * ip2k-dis.c, * iq2000-dis.c,
 407         * lm32-dis.c, * m32c-dis.c, * m32r-desc.c, * m32r-desc.h,
 408         * m32r-dis.c, * mep-dis.c, * mt-dis.c, * openrisc-dis.c,
 409         * xc16x-dis.c, * xstormy16-dis.c: Regenerate.
 410
 411         * fr30-desc.c, * fr30-desc.h, * fr30-opc.c,
 412         * frv-desc.c, * frv-desc.h, * frv-opc.c,
 413         * ip2k-desc.c, * ip2k-desc.h, * ip2k-opc.c,
 414         * iq2000-desc.c, * iq2000-desc.h, * iq2000-opc.c,
 415         * lm32-desc.c, * lm32-desc.h, * lm32-opc.c, * lm32-opinst.c,
 416         * m32c-desc.c, * m32c-desc.h, * m32c-opc.c,
 417         * m32r-desc.c, * m32r-desc.h, * m32r-opc.c, * m32r-opinst.c,
 418         * mep-desc.c, * mep-desc.h, * mep-opc.c,
 419         * mt-desc.c, * mt-desc.h, * mt-opc.c,
 420         * openrisc-desc.c, * openrisc-desc.h, * openrisc-opc.c,
 421         * xc16x-desc.c, * xc16x-desc.h, * xc16x-opc.c,
 422         * xstormy16-desc.c, * xstormy16-desc.h, * xstormy16-opc.c: Regenerate.
 423
 424 2010-02-11  H.J. Lu  <hongjiu.lu@intel.com>
 425
 426         * i386-dis.c: Update copyright.
 427         * i386-gen.c: Likewise.
 428         * i386-opc.h: Likewise.
 429         * i386-opc.tbl: Likewise.
 430
 431 2010-02-10  Quentin Neill  <quentin.neill@amd.com>
 432             Sebastian Pop  <sebastian.pop@amd.com>
 433
 434         * i386-dis.c (OP_EX_VexImmW): Reintroduced
 435         function to handle 5th imm8 operand.
 436         (PREFIX_VEX_3A48): Added.
 437         (PREFIX_VEX_3A49): Added.
 438         (VEX_W_3A48_P_2): Added.
 439         (VEX_W_3A49_P_2): Added.
 440         (prefix table): Added entries for PREFIX_VEX_3A48
 441         and PREFIX_VEX_3A49.
 442         (vex table): Added entries for VEX_W_3A48_P_2 and
 443         and VEX_W_3A49_P_2.
 444         * i386-gen.c (operand_type_init): Added OPERAND_TYPE_VEC_IMM4
 445         for Vec_Imm4 operands.
 446         * i386-opc.h (enum): Added Vec_Imm4.
 447         (i386_operand_type): Added vec_imm4.
 448         * i386-opc.tbl: Add entries for vpermilp[ds].
 449         * i386-init.h: Regenerated.
 450         * i386-tbl.h: Regenerated.
 451
 452 2010-02-10  Richard Sandiford  <r.sandiford@uk.ibm.com>
 453
 454         * ppc-dis.c (ppc_opts): Add "pwr4", "pwr5", "pwr5x", "pwr6"
 455         and "pwr7".  Move "a2" into alphabetical order.
 456
 457 2010-02-08  Philipp Tomsich  <philipp.tomsich@theobroma-systems.com>
 458
 459         * ppc-dis.c (ppc_opts): Add titan entry.
 460         * ppc-opc.c (TITAN, MULHW): Define.
 461         (powerpc_opcodes): Support AppliedMicro Titan core (APM83xxx).
 462
 463 2010-02-03  Quentin Neill  <quentin.neill@amd.com>
 464
 465         * i386-gen.c (cpu_flag_init): Rename CPU_AMDFAM15_FLAGS
 466         to CPU_BDVER1_FLAGS
 467         * i386-init.h: Regenerated.
 468
 469 2010-02-03  Anthony Green  <green@moxielogic.com>
 470
 471         * moxie-opc.c (moxie_form1_opc_info): Move "nop" from 0x00 to
 472         0x0f, and make 0x00 an illegal instruction.
 473
 474 2010-01-29  Daniel Jacobowitz  <dan@codesourcery.com>
 475
 476         * opcodes/arm-dis.c (struct arm_private_data): New.
 477         (print_insn_coprocessor, print_insn_arm): Update to use struct
 478         arm_private_data.
 479         (is_mapping_symbol, get_map_sym_type): New functions.
 480         (get_sym_code_type): Check the symbol's section.  Do not check
 481         mapping symbols.
 482         (print_insn): Default to disassembling ARM mode code.  Check
 483         for mapping symbols separately from other symbols.  Use
 484         struct arm_private_data.
 485
 486 2010-01-28  H.J. Lu  <hongjiu.lu@intel.com>
 487
 488         * i386-dis.c (EXVexWdqScalar): New.
 489         (vex_scalar_w_dq_mode): Likewise.
 490         (prefix_table): Update entries for PREFIX_VEX_3899,
 491         PREFIX_VEX_389B, PREFIX_VEX_389D, PREFIX_VEX_389F,
 492         PREFIX_VEX_38A9, PREFIX_VEX_38AB, PREFIX_VEX_38AD,
 493         PREFIX_VEX_38AF, PREFIX_VEX_38B9, PREFIX_VEX_38BB,
 494         PREFIX_VEX_38BD and PREFIX_VEX_38BF.
 495         (intel_operand_size): Handle vex_scalar_w_dq_mode.
 496         (OP_EX): Likewise.
 497
 498 2010-01-27  H.J. Lu  <hongjiu.lu@intel.com>
 499
 500         * i386-dis.c (XMScalar): New.
 501         (EXdScalar): Likewise.
 502         (EXqScalar): Likewise.
 503         (EXqScalarS): Likewise.
 504         (VexScalar): Likewise.
 505         (EXdVexScalarS): Likewise.
 506         (EXqVexScalarS): Likewise.
 507         (XMVexScalar): Likewise.
 508         (scalar_mode): Likewise.
 509         (d_scalar_mode): Likewise.
 510         (d_scalar_swap_mode): Likewise.
 511         (q_scalar_mode): Likewise.
 512         (q_scalar_swap_mode): Likewise.
 513         (vex_scalar_mode): Likewise.
 514         (vex_len_table): Duplcate entries for VEX_LEN_10_P_1,
 515         VEX_LEN_10_P_3, VEX_LEN_11_P_1, VEX_LEN_11_P_3, VEX_LEN_2A_P_1,
 516         VEX_LEN_2A_P_3, VEX_LEN_2C_P_3, VEX_LEN_2D_P_1, VEX_LEN_2E_P_0,
 517         VEX_LEN_2E_P_2, VEX_LEN_2F_P_2, VEX_LEN_51_P_1, VEX_LEN_51_P_3,
 518         VEX_LEN_52_P_1, VEX_LEN_53_P_1, VEX_LEN_58_P_1, VEX_LEN_58_P_3,
 519         VEX_LEN_59_P_1, VEX_LEN_5A_P_1, VEX_LEN_5A_P_3, VEX_LEN_5C_P_1,
 520         VEX_LEN_5C_P_3, VEX_LEN_5D_P_1, VEX_LEN_5D_P_3, VEX_LEN_5E_P_1,
 521         VEX_LEN_5E_P_3, VEX_LEN_5F_P_1, VEX_LEN_5F_P_3, VEX_LEN_6E_P_2,
 522         VEX_LEN_7E_P_1, VEX_LEN_7E_P_2, VEX_LEN_D6_P_2, VEX_LEN_C2_P_1,
 523         VEX_LEN_C2_P_3, VEX_LEN_3A0A_P_2 and VEX_LEN_3A0B_P_2.
 524         (vex_w_table): Update entries for VEX_W_10_P_1, VEX_W_10_P_3,
 525         VEX_W_11_P_1, VEX_W_11_P_3, VEX_W_2E_P_0, VEX_W_2E_P_2,
 526         VEX_W_2F_P_0, VEX_W_2F_P_2, VEX_W_51_P_1, VEX_W_51_P_3,
 527         VEX_W_52_P_1, VEX_W_53_P_1, VEX_W_58_P_1, VEX_W_58_P_3,
 528         VEX_W_59_P_1, VEX_W_59_P_3, VEX_W_5A_P_1, VEX_W_5A_P_3,
 529         VEX_W_5C_P_1, VEX_W_5C_P_3, VEX_W_5D_P_1, VEX_W_5D_P_3,
 530         VEX_W_5E_P_1, VEX_W_5E_P_3, VEX_W_5F_P_1, VEX_W_5F_P_3,
 531         VEX_W_7E_P_1, VEX_W_D6_P_2  VEX_W_C2_P_1, VEX_W_C2_P_3,
 532         VEX_W_3A0A_P_2 and VEX_W_3A0B_P_2.
 533         (intel_operand_size): Handle d_scalar_mode, d_scalar_swap_mode,
 534         q_scalar_mode, q_scalar_swap_mode.
 535         (OP_XMM): Handle scalar_mode.
 536         (OP_EX): Handle d_scalar_mode, d_scalar_swap_mode, q_scalar_mode
 537         and q_scalar_swap_mode.
 538         (OP_VEX): Handle vex_scalar_mode.
 539
 540 2010-01-24  H.J. Lu  <hongjiu.lu@intel.com>
 541
 542         * i386-dis.c (prefix_table): Remove trailing { Bad_Opcode }.
 543
 544 2010-01-24  H.J. Lu  <hongjiu.lu@intel.com>
 545
 546         * i386-dis.c (vex_len_table): Remove trailing { Bad_Opcode }.
 547
 548 2010-01-24  H.J. Lu  <hongjiu.lu@intel.com>
 549
 550         * i386-dis.c (prefix_table): Remove trailing { Bad_Opcode }.
 551
 552 2010-01-24  H.J. Lu  <hongjiu.lu@intel.com>
 553
 554         * i386-dis.c (Bad_Opcode): New.
 555         (bad_opcode): Likewise.
 556         (dis386): Replace { "(bad)", { XX } } with { Bad_Opcode }.
 557         (dis386_twobyte): Likewise.
 558         (reg_table): Likewise.
 559         (prefix_table): Likewise.
 560         (x86_64_table): Likewise.
 561         (vex_len_table): Likewise.
 562         (vex_w_table): Likewise.
 563         (mod_table): Likewise.
 564         (rm_table): Likewise.
 565         (float_reg): Likewise.
 566         (reg_table): Remove trailing "(bad)" entries.
 567         (prefix_table): Likewise.
 568         (x86_64_table): Likewise.
 569         (vex_len_table): Likewise.
 570         (vex_w_table): Likewise.
 571         (mod_table): Likewise.
 572         (rm_table): Likewise.
 573         (get_valid_dis386): Handle bytemode 0.
 574
 575 2010-01-23  H.J. Lu  <hongjiu.lu@intel.com>
 576
 577         * i386-opc.h (VEXScalar): New.
 578
 579         * i386-opc.tbl: Replace "Vex" with "Vex=3" on AVX scalar
 580         instructions.
 581         * i386-tbl.h: Regenerated.
 582
 583 2010-01-21  H.J. Lu  <hongjiu.lu@intel.com>
 584
 585         * i386-dis.c (mod_table): Use FXSAVE on xsave and xrstor.
 586
 587         * i386-opc.tbl: Add xsave64 and xrstor64.
 588         * i386-tbl.h: Regenerated.
 589
 590 2010-01-20  Nick Clifton  <nickc@redhat.com>
 591
 592         PR 11170
 593         * arm-dis.c (print_arm_address): Do not ignore negative bit in PC
 594         based post-indexed addressing.
 595
 596 2010-01-15  Sebastian Pop  <sebastian.pop@amd.com>
 597
 598         * i386-opc.tbl: Support all the possible aliases for VPCOM* insns.
 599         * i386-tbl.h: Regenerated.
 600
 601 2010-01-14  H.J. Lu  <hongjiu.lu@intel.com>
 602
 603         * i386-opc.h (VexVVVV): Replace VEX.DNS with VEX.NDS in
 604         comments.
 605
 606 2010-01-14  H.J. Lu  <hongjiu.lu@intel.com>
 607
 608         * i386-dis.c (names_mm): New.
 609         (intel_names_mm): Likewise.
 610         (att_names_mm): Likewise.
 611         (names_xmm): Likewise.
 612         (intel_names_xmm): Likewise.
 613         (att_names_xmm): Likewise.
 614         (names_ymm): Likewise.
 615         (intel_names_ymm): Likewise.
 616         (att_names_ymm): Likewise.
 617         (print_insn): Set names_mm, names_xmm and names_ymm.
 618         (OP_MMX): Use names_mm, names_xmm and names_ymm.
 619         (OP_XMM): Likewise.
 620         (OP_EM): Likewise.
 621         (OP_EMC): Likewise.
 622         (OP_MXC): Likewise.
 623         (OP_EX): Likewise.
 624         (XMM_Fixup): Likewise.
 625         (OP_VEX): Likewise.
 626         (OP_EX_VexReg): Likewise.
 627         (OP_Vex_2src): Likewise.
 628         (OP_Vex_2src_1): Likewise.
 629         (OP_Vex_2src_2): Likewise.
 630         (OP_REG_VexI4): Likewise.
 631
 632 2010-01-13  H.J. Lu  <hongjiu.lu@intel.com>
 633
 634         * i386-dis.c (print_insn): Update comments.
 635
 636 2010-01-12  H.J. Lu  <hongjiu.lu@intel.com>
 637
 638         * i386-dis.c (rex_original): Removed.
 639         (ckprefix): Remove rex_original.
 640         (print_insn): Update comments.
 641
 642 2010-01-09  Ralf Wildenhues  <Ralf.Wildenhues@gmx.de>
 643
 644         * Makefile.in: Regenerate.
 645         * configure: Regenerate.
 646
 647 2010-01-07  Doug Evans  <dje@sebabeach.org>
 648
 649         * cgen-ibld.in (insert_normal, extract_normal): Minor cleanup.
 650         * fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c,
 651         * lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c,
 652         * mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c,
 653         * xstormy16-ibld.c: Regenerate.
 654
 655 2010-01-06  Quentin Neill  <quentin.neill@amd.com>
 656
 657         * i386-gen.c (cpu_flag_init): Add new CPU_AMDFAM15_FLAGS.
 658         * i386-init.h: Regenerated.
 659
 660 2010-01-06  Daniel Gutson  <dgutson@codesourcery.com>
 661
 662         * arm-dis.c (print_insn): Fixed search for next symbol and data
 663         dumping condition, and the initial mapping symbol state.
 664
 665 2010-01-05  Doug Evans  <dje@sebabeach.org>
 666
 667         * cgen-ibld.in: #include "cgen/basic-modes.h".
 668         * fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c,
 669         * lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c,
 670         * mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c,
 671         * xstormy16-ibld.c: Regenerate.
 672
 673 2010-01-04  Nick Clifton  <nickc@redhat.com>
 674
 675         PR 11123
 676         * arm-dis.c (print_insn_coprocessor): Initialise value.
 677
 678 2010-01-04  Edmar Wienskoski  <edmar@freescale.com>
 679
 680         * ppc-dis.c (ppc_opts): Add entry for "e500mc64".
 681
 682 2010-01-02  Doug Evans  <dje@sebabeach.org>
 683
 684         * cgen-asm.in: Update copyright year.
 685         * cgen-dis.in: Update copyright year.
 686         * cgen-ibld.in: Update copyright year.
 687         * fr30-asm.c, * fr30-desc.c, * fr30-desc.h, * fr30-dis.c,
 688         * fr30-ibld.c, * fr30-opc.c, * fr30-opc.h, * frv-asm.c, * frv-desc.c,
 689         * frv-desc.h, * frv-dis.c, * frv-ibld.c, * frv-opc.c, * frv-opc.h,
 690         * ip2k-asm.c, * ip2k-desc.c, * ip2k-desc.h, * ip2k-dis.c,
 691         * ip2k-ibld.c, * ip2k-opc.c, * ip2k-opc.h, * iq2000-asm.c,
 692         * iq2000-desc.c, * iq2000-desc.h, * iq2000-dis.c, * iq2000-ibld.c,
 693         * iq2000-opc.c, * iq2000-opc.h, * lm32-asm.c, * lm32-desc.c,
 694         * lm32-desc.h, * lm32-dis.c, * lm32-ibld.c, * lm32-opc.c, * lm32-opc.h,
 695         * lm32-opinst.c, * m32c-asm.c, * m32c-desc.c, * m32c-desc.h,
 696         * m32c-dis.c, * m32c-ibld.c, * m32c-opc.c, * m32c-opc.h, * m32r-asm.c,
 697         * m32r-desc.c, * m32r-desc.h, * m32r-dis.c, * m32r-ibld.c,
 698         * m32r-opc.c, * m32r-opc.h, * m32r-opinst.c, * mep-asm.c, * mep-desc.c,
 699         * mep-desc.h, * mep-dis.c, * mep-ibld.c, * mep-opc.c, * mep-opc.h,
 700         * mt-asm.c, * mt-desc.c, * mt-desc.h, * mt-dis.c, * mt-ibld.c,
 701         * mt-opc.c, * mt-opc.h, * openrisc-asm.c, * openrisc-desc.c,
 702         * openrisc-desc.h, * openrisc-dis.c, * openrisc-ibld.c,
 703         * openrisc-opc.c, * openrisc-opc.h, * xc16x-asm.c, * xc16x-desc.c,
 704         * xc16x-desc.h, * xc16x-dis.c, * xc16x-ibld.c, * xc16x-opc.c,
 705         * xc16x-opc.h, * xstormy16-asm.c, * xstormy16-desc.c,
 706         * xstormy16-desc.h, * xstormy16-dis.c, * xstormy16-ibld.c,
 707         * xstormy16-opc.c, * xstormy16-opc.h: Regenerate.
 708
 709 For older changes see ChangeLog-2009
 710 \f
 711 Local Variables:
 712 mode: change-log
 713 left-margin: 8
 714 fill-column: 74
 715 version-control: never
 716 End: