opcodes/ChangeLog

   1 2021-06-07  Andreas Krebbel  <krebbel@linux.ibm.com>
   2
   3         * s390-opc.txt: Add qpaci.
   4
   5 2021-07-03  Nick Clifton  <nickc@redhat.com>
   6
   7         * configure: Regenerate.
   8         * po/opcodes.pot: Regenerate.
   9
  10 2021-07-03  Nick Clifton  <nickc@redhat.com>
  11
  12         * 2.37 release branch created.
  13
  14 2021-07-02  Alan Modra  <amodra@gmail.com>
  15
  16         * nds32-dis.c (nds32_find_reg_keyword): Constify arg and return.
  17         (nds32_parse_audio_ext, nds32_parse_opcode): Constify psys_reg.
  18         (nds32_field_table, nds32_opcode_table, nds32_keyword_table),
  19         (nds32_opcodes, nds32_operand_fields, nds32_keywords),
  20         (nds32_keyword_gpr): Move declarations to..
  21         * nds32-asm.h: ..here, constifying to match definitions.
  22
  23 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
  24
  25         * Makefile.am (GUILE): New variable.
  26         (CGEN): Use $(GUILE).
  27         * Makefile.in: Regenerate.
  28
  29 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
  30
  31         * mep-asm.c (macros): Mark static & const.
  32         (lookup_macro): Change return & m to const.
  33         (expand_macro): Change mac to const.
  34         (expand_string): Change pmacro to const.
  35
  36 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
  37
  38         * nds32-asm.c (operand_fields): Rename to ...
  39         (nds32_operand_fields): ... this.
  40         (keyword_gpr): Rename to ...
  41         (nds32_keyword_gpr): ... this.
  42         (keyword_usr, keyword_dxr, keyword_sr, keyword_cp, keyword_cpr,
  43         keyword_fsr, keyword_fdr, keyword_abdim, keyword_abm,
  44         keyword_dpref_st, keyword_cctl_lv, keyword_standby_st,
  45         keyword_msync_st, keyword_im5_i, keyword_im5_m, keyword_accumulator,
  46         keyword_aridx, keyword_aridx2, keyword_aridxi, keyword_aridxi_mx):
  47         Mark static.
  48         (keywords): Rename to ...
  49         (nds32_keywords): ... this.
  50         * nds32-dis.c: Rename operand_fields to nds32_operand_fields,
  51         keywords to nds32_keywords, and keyword_gpr to nds32_keyword_gpr.
  52
  53 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
  54
  55         * z80-dis.c (opc_ed): Make const.
  56         (pref_ed): Make p const.
  57
  58 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
  59
  60         * microblaze-dis.c (get_field_special): Make op const.
  61         (read_insn_microblaze): Make opr & op const.  Rename opcodes to
  62         microblaze_opcodes.
  63         (print_insn_microblaze): Make op & pop const.
  64         (get_insn_microblaze): Make op const.  Rename opcodes to
  65         microblaze_opcodes.
  66         (microblaze_get_target_address): Likewise.
  67         * microblaze-opc.h (struct op_code_struct): Make const.
  68         Rename opcodes to microblaze_opcodes.
  69
  70 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
  71
  72         * aarch64-gen.c (aarch64_opcode_table): Add const.
  73         * aarch64-tbl.h (aarch64_opcode_table): Likewise.
  74
  75 2021-06-22  Andrew Burgess  <andrew.burgess@embecosm.com>
  76
  77         * cgen-dis.c (count_decodable_bits): Use __builtin_popcount when
  78         available.
  79
  80 2021-06-22  Alan Modra  <amodra@gmail.com>
  81
  82         * pj-dis.c (print_insn_pj): Don't print trailing tab.  Do
  83         print separator for pcrel insns.
  84
  85 2021-06-19  Alan Modra  <amodra@gmail.com>
  86
  87         * vax-dis.c (print_insn_vax): Avoid pointer overflow.
  88
  89 2021-06-19  Alan Modra  <amodra@gmail.com>
  90
  91         * tic30-dis.c (get_register_operand): Don't ask strncpy to fill
  92         entire buffer.
  93
  94 2021-06-17  Alan Modra  <amodra@gmail.com>
  95
  96         * ppc-opc.c (powerpc_opcodes): Move cell db*cyc to proper location
  97         in table.
  98
  99 2021-06-03  Alan Modra  <amodra@gmail.com>
 100
 101         PR 1202
 102         * mcore-dis.c (print_insn_mcore): Correct loopt disassembly.
 103         Use unsigned int for inst.
 104
 105 2021-06-02  Shahab Vahedi  <shahab@synopsys.com>
 106
 107         * arc-dis.c (arc_option_arg_t): New enumeration.
 108         (arc_options): New variable.
 109         (disassembler_options_arc): New function.
 110         (print_arc_disassembler_options): Reimplement in terms of
 111         "disassembler_options_arc".
 112
 113 2021-05-29  Alan Modra  <amodra@gmail.com>
 114
 115         * ppc-dis.c (lookup_powerpc): Test deprecated field when -Many.
 116         Don't special case PPC_OPCODE_RAW.
 117         (lookup_prefix): Likewise.
 118         (lookup_vle, lookup_spe2): Similarly.  Add dialect parameter and..
 119         (print_insn_powerpc): ..update caller.
 120         * ppc-opc.c (EXT): Define.
 121         (powerpc_opcodes): Mark extended mnemonics with EXT.
 122         (prefix_opcodes, vle_opcodes): Likewise.
 123         (XISEL, XISEL_MASK): Add cr field and simplify.
 124         (powerpc_opcodes): Use XISEL with extended isel mnemonics and sort
 125         all isel variants to where the base mnemonic belongs.  Sort dstt,
 126         dststt and dssall.
 127
 128 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 129
 130         * mips-opc.c (mips_builtin_opcodes): Reorder legacy COP0, COP2,
 131         COP3 opcode instructions.
 132
 133 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 134
 135         * mips-opc.c (mips_builtin_opcodes): Update exclusion list for
 136         "ldc2", "ldc3", "lwc0", "lwc2", "lwc3", "sdc2", "sdc3", "swc0",
 137         "swc2", "swc3", "cfc0", "ctc0", "bc2f", "bc2fl", "bc2t",
 138         "bc2tl", "cfc2", "ctc2", "dmfc2", "dmtc2", "mfc2", "mtc2",
 139         "bc3f", "bc3fl", "bc3t", "bc3tl", "cfc3", "ctc3", "mfc3",
 140         "mtc3", "bc0f", "bc0fl", "bc0t", "bc0tl", "rfe", "c2", "c3",
 141         "cop2", and "cop3" entries.
 142
 143 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 144
 145         * mips-opc.c (mips_builtin_opcodes): Remove "dmfc3" and "dmtc3"
 146         entries and associated comments.
 147
 148 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 149
 150         * mips-opc.c (mips_builtin_opcodes): Move the "rfe" entry ahead
 151         of "c0".
 152
 153 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 154
 155         * mips-dis.c (mips_cp1_names_mips): New variable.
 156         (mips_arch_choices): Use it rather than `mips_cp1_names_numeric'
 157         for "r3000", "r4000", "r4010", "vr4100", "vr4111", "vr4120",
 158         "r4300", "r4400", "r4600", "r4650", "r5000", "vr5400", "vr5500",
 159         "r5900", "r6000", "rm7000", "rm9000", "r8000", "r10000",
 160         "r12000", "r14000", "r16000", "mips5", "loongson2e", and
 161         "loongson2f".
 162
 163 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 164
 165         * mips-dis.c (print_reg) <OP_REG_COPRO>: Move control register
 166         handling code over to...
 167         <OP_REG_CONTROL>: ... this new case.
 168         * mips-opc.c (decode_mips_operand) <'g', 'y'>: New cases.
 169         (mips_builtin_opcodes): Update "cfc1", "ctc1", "cttc1", "cttc2",
 170         "cfc0", "ctc0", "cfc2", "ctc2", "cfc3", and "ctc3" entries
 171         replacing the `G' operand code with `g'.  Update "cftc1" and
 172         "cftc2" entries replacing the `E' operand code with `y'.
 173         * micromips-opc.c (decode_micromips_operand) <'g'>: New case.
 174         (micromips_opcodes): Update "cfc1", "cfc2", "ctc1", and "ctc2"
 175         entries replacing the `G' operand code with `g'.
 176
 177 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 178
 179         * mips-dis.c (mips_cp0_names_r3900): New variable.
 180         (mips_arch_choices): Use it rather than `mips_cp0_names_numeric'
 181         for "r3900".
 182
 183 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 184
 185         * mips-opc.c (mips_builtin_opcodes): Switch "cttc2", "mttc2",
 186         and "mtthc2" to using the `G' rather than `g' operand code for
 187         the coprocessor control register referred.
 188
 189 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 190
 191         * micromips-opc.c (micromips_opcodes): Swap the two "dmtc1"
 192         entries with each other.
 193
 194 2021-05-27  Peter Bergner  <bergner@linux.ibm.com>
 195
 196         * ppc-opc.c (powerpc_opcodes) <xxmr, xxlnot>: New extended mnemonics.
 197
 198 2021-05-25  Alan Modra  <amodra@gmail.com>
 199
 200         * cris-desc.c: Regenerate.
 201         * cris-desc.h: Regenerate.
 202         * cris-opc.h: Regenerate.
 203         * po/POTFILES.in: Regenerate.
 204
 205 2021-05-24  Mike Frysinger  <vapier@gentoo.org>
 206
 207         * Makefile.am (HFILES): Add cris-desc.h & cris-opc.h.
 208         (TARGET_LIBOPCODES_CFILES): Add cris-desc.c.
 209         (CGEN_CPUS): Add cris.
 210         (CRIS_DEPS): Define.
 211         (stamp-cris): New rule.
 212         * cgen.sh: Handle desc action.
 213         * configure.ac (bfd_cris_arch): Add cris-desc.lo.
 214         * Makefile.in, configure: Regenerate.
 215
 216 2021-05-18  Job Noorman  <mtvec@pm.me>
 217
 218         PR 27814
 219         * riscv-dis.c (riscv_get_disassembler): Get elf attributes only for
 220         the elf objects.
 221
 222 2021-05-17  Alex Coplan  <alex.coplan@arm.com>
 223
 224         * arm-dis.c (mve_opcodes): Fix disassembly of
 225         MVE_VMOV2_GP_TO_VEC_LANE when idx == 1.
 226         (is_mve_encoding_conflict): MVE vector loads should not match
 227         when P = W = 0.
 228         (is_mve_unpredictable): It's not unpredictable to use the same
 229         source register twice (for MVE_VMOV2_GP_TO_VEC_LANE).
 230
 231 2021-05-11  Nick Clifton  <nickc@redhat.com>
 232
 233         PR 27840
 234         * tic30-dis.c (print_insn_tic30): Prevent attempts to read beyond
 235         the end of the code buffer.
 236
 237 2021-05-06  Stafford Horne  <shorne@gmail.com>
 238
 239         PR 21464
 240         * or1k-asm.c: Regenerate.
 241
 242 2021-05-01  Max Filippov  <jcmvbkbc@gmail.com>
 243
 244         * xtensa-dis.c (print_insn_xtensa): Fill in info->insn_type and
 245         info->insn_info_valid.
 246
 247 2021-04-26  Jan Beulich  <jbeulich@suse.com>
 248
 249         * i386-opc.tbl (lea): Add Optimize.
 250         * opcodes/i386-tbl.h: Re-generate.
 251
 252 2020-04-23  Max Filippov  <jcmvbkbc@gmail.com>
 253
 254         * xtensa-dis.c (print_xtensa_operand): For PC-relative operand
 255         of l32r fetch and display referenced literal value.
 256
 257 2021-04-23  Max Filippov  <jcmvbkbc@gmail.com>
 258
 259         * xtensa-dis.c (print_insn_xtensa): Set info->bytes_per_chunk
 260         to 4 for literal disassembly.
 261
 262 2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 263
 264         * aarch64-opc.c: Add new registers (RPAOS, RPALOS, PAALLOS, PAALL) support
 265         for TLBI instruction.
 266
 267 2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 268
 269         * aarch64-opc.c: Add new register (CIPAPA, CIGDPAPA) support for
 270         DC instruction.
 271
 272 2021-04-19  Jan Beulich  <jbeulich@suse.com>
 273
 274         * aarch64-asm.c (encode_asimd_fcvt): Add initializer for
 275         "qualifier".
 276         (convert_mov_to_movewide): Add initializer for "value".
 277
 278 2021-04-16  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 279
 280         * aarch64-opc.c: Add RME system registers.
 281
 282 2021-04-16  Lifang Xia <lifang_xia@c-sky.com>
 283
 284         * riscv-opc.c (riscv_opcodes): New insn alias for addi. Compress
 285         "addi d,CV,z" to "c.mv d,CV".
 286
 287 2021-04-12  Alan Modra  <amodra@gmail.com>
 288
 289         * configure.ac (--enable-checking): Add support.
 290         * config.in: Regenerate.
 291         * configure: Regenerate.
 292
 293 2021-04-09  Tejas Belagod  <tejas.belagod@arm.com>
 294
 295         * aarch64-tbl.h (struct aarch64_opcode aarch64_opcode_table): Reclassify
 296         LD64/ST64 instructions to lse_atomic instead of ldstexcl.
 297
 298 2021-04-09  Alan Modra  <amodra@gmail.com>
 299
 300         * ppc-dis.c (struct dis_private): Add "special".
 301         (POWERPC_DIALECT): Delete.  Replace uses with..
 302         (private_data): ..this.  New inline function.
 303         (disassemble_init_powerpc): Init "special" names.
 304         (skip_optional_operands): Add is_pcrel arg, set when detecting R
 305         field of prefix instructions.
 306         (bsearch_reloc, print_got_plt): New functions.
 307         (print_insn_powerpc): For pcrel instructions, print target address
 308         and symbol if known, and decode plt and got loads too.
 309
 310 2021-04-08  Alan Modra  <amodra@gmail.com>
 311
 312         PR 27684
 313         * ppc-opc.c (powerpc_opcodes): Correct usprg typos, add mfpir.
 314
 315 2021-04-08  Alan Modra  <amodra@gmail.com>
 316
 317         PR 27676
 318         * ppc-opc.c (DCBT_EO): Move earlier.
 319         (insert_thct, extract_thct, insert_thds, extract_thds): New functions.
 320         (powerpc_operands): Add THCT and THDS entries.
 321         (powerpc_opcodes): Add dcbtstct, dcbtstds, dcbna, dcbtct, dcbtds.
 322
 323 2021-04-06  Alan Modra  <amodra@gmail.com>
 324
 325         * dis-buf.c (generic_symbol_at_address): Return symbol* NULL.
 326         * s12z-dis.c (decode_possible_symbol): Use symbol returned from
 327         symbol_at_address_func.
 328
 329 2021-04-05  Alan Modra  <amodra@gmail.com>
 330
 331         * configure.ac: Don't check for limits.h, string.h, strings.h or
 332         stdlib.h.
 333         (AC_ISC_POSIX): Don't invoke.
 334         * sysdep.h: Include stdlib.h and string.h unconditionally.
 335         * i386-opc.h: Include limits.h unconditionally.
 336         * wasm32-dis.c: Likewise.
 337         * cgen-opc.c: Don't include alloca-conf.h.
 338         * config.in: Regenerate.
 339         * configure: Regenerate.
 340
 341 2021-04-01  Martin Liska  <mliska@suse.cz>
 342
 343         * arm-dis.c (strneq): Remove strneq and use startswith.
 344         * cr16-dis.c (print_insn_cr16): Likewise.
 345         * score-dis.c (streq): Likewise.
 346         (strneq): Likewise.
 347         * score7-dis.c (strneq): Likewise.
 348
 349 2021-04-01  Alan Modra  <amodra@gmail.com>
 350
 351         PR 27675
 352         * ppc-opc.c (powerpc_opcodes): Add mfummcr2 and mfmmcr2.
 353
 354 2021-03-31  Alan Modra  <amodra@gmail.com>
 355
 356         * sysdep.h (POISON_BFD_BOOLEAN): Define.
 357         * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h,
 358         * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h,
 359         * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c,
 360         * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c,
 361         * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c,
 362         * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c,
 363         * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c,
 364         * microblaze-dis.h, * micromips-opc.c, * mips-dis.c,
 365         * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c,
 366         * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c,
 367         * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c,
 368         * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c,
 369         * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false,
 370         and TRUE with true throughout.
 371
 372 2021-03-31  Alan Modra  <amodra@gmail.com>
 373
 374         * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h.
 375         * aarch64-dis.h: Likewise.
 376         * aarch64-opc.c: Likewise.
 377         * avr-dis.c: Likewise.
 378         * csky-dis.c: Likewise.
 379         * nds32-asm.c: Likewise.
 380         * nds32-dis.c: Likewise.
 381         * nfp-dis.c: Likewise.
 382         * riscv-dis.c: Likewise.
 383         * s12z-dis.c: Likewise.
 384         * wasm32-dis.c: Likewise.
 385
 386 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 387
 388         * i386-opc.c (cs, ds, ss, es, fs, gs): Delete.
 389         (i386_seg_prefixes): New.
 390         * i386-opc.h (cs, ds, ss, es, fs, gs): Delete.
 391         (i386_seg_prefixes): Declare.
 392
 393 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 394
 395         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Delete.
 396
 397 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 398
 399         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Adjust values.
 400         * i386-reg.tbl (st): Move down.
 401         (st(0)): Delete. Extend comment.
 402         * i386-tbl.h: Re-generate.
 403
 404 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 405
 406         * i386-opc.tbl (movq, movabs): Move next to mov counterparts.
 407         (cmpsd): Move next to cmps.
 408         (movsd): Move next to movs.
 409         (cmpxchg16b): Move to separate section.
 410         (fisttp, fisttpll): Likewise.
 411         (monitor, mwait): Likewise.
 412         * i386-tbl.h: Re-generate.
 413
 414 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 415
 416         * i386-opc.tbl (psadbw): Add <sse2:comm>.
 417         (vpsadbw): Add C.
 418         * i386-tbl.h: Re-generate.
 419
 420 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 421
 422         * i386-opc.tbl (mmx, sse, sse2, sse3, ssse3, sse41, sse42, aes,
 423         pclmul, gfni): New templates. Use them wherever possible. Move
 424         SSE4.1 pextrw into respective section.
 425         * i386-tbl.h: Re-generate.
 426
 427 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 428
 429         * i386-gen.c (output_i386_opcode): Widen type of "opcode". Use
 430         strtoull(). Bump upper loop bound. Widen masks. Sanity check
 431         "length".
 432         * i386-opc.tbl (Prefix_0X66, Prefix_0XF2, Prefix_0XF3): Delete.
 433         Convert all of their uses to representation in opcode.
 434
 435 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 436
 437         * i386-opc.h (struct insn_template): Shrink base_opcode to 16
 438         bits. Shrink extension_opcode to 9 bits. Make it signed. Change
 439         value of None. Shrink operands to 3 bits.
 440
 441 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 442
 443         * i386-gen.c (process_i386_opcode_modifier): New parameter
 444         "space".
 445         (output_i386_opcode): New local variable "space". Adjust
 446         process_i386_opcode_modifier() invocation.
 447         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 448         invocation.
 449         * i386-tbl.h: Re-generate.
 450
 451 2021-03-29  Alan Modra  <amodra@gmail.com>
 452
 453         * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
 454         (fp_qualifier_p, get_data_pattern): Likewise.
 455         (aarch64_get_operand_modifier_from_value): Likewise.
 456         (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
 457         (operand_variant_qualifier_p): Likewise.
 458         (qualifier_value_in_range_constraint_p): Likewise.
 459         (aarch64_get_qualifier_esize): Likewise.
 460         (aarch64_get_qualifier_nelem): Likewise.
 461         (aarch64_get_qualifier_standard_value): Likewise.
 462         (get_lower_bound, get_upper_bound): Likewise.
 463         (aarch64_find_best_match, match_operands_qualifier): Likewise.
 464         (aarch64_print_operand): Likewise.
 465         * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
 466         (operand_need_sign_extension, operand_need_shift_by_two): Likewise.
 467         (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
 468         * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
 469         * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
 470         (print_insn_tic6x): Likewise.
 471
 472 2021-03-29  Alan Modra  <amodra@gmail.com>
 473
 474         * arc-dis.c (extract_operand_value): Correct NULL cast.
 475         * frv-opc.h: Regenerate.
 476
 477 2021-03-26  Jan Beulich  <jbeulich@suse.com>
 478
 479         * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to
 480         MMX form.
 481         * i386-tbl.h: Re-generate.
 482
 483 2021-03-25  Abid Qadeer  <abidh@codesourcery.com>
 484
 485         * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
 486         immediate in br.n instruction.
 487
 488 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 489
 490         * i386-dis.c (XMGatherD, VexGatherD): New.
 491         (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
 492         (print_insn): Check masking for S/G insns.
 493         (OP_E_memory): New local variable check_gather. Extend mandatory
 494         SIB check. Check register conflicts for (EVEX-encoded) gathers.
 495         Extend check for disallowed 16-bit addressing.
 496         (OP_VEX): New local variables modrm_reg and sib_index. Convert
 497         if()s to switch(). Check register conflicts for (VEX-encoded)
 498         gathers. Drop no longer reachable cases.
 499         * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
 500         vgatherdp*.
 501
 502 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 503
 504         * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
 505         zeroing-masking without masking.
 506
 507 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 508
 509         * i386-opc.tbl (invlpgb): Fix multi-operand form.
 510         (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
 511         single-operand forms as deprecated.
 512         * i386-tbl.h: Re-generate.
 513
 514 2021-03-25  Alan Modra  <amodra@gmail.com>
 515
 516         PR 27647
 517         * ppc-opc.c (XLOCB_MASK): Delete.
 518         (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
 519         XLBH_MASK.
 520         (powerpc_opcodes): Accept a BH field on all extended forms of
 521         bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
 522
 523 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 524
 525         * i386-gen.c (output_i386_opcode): Drop processing of
 526         opcode_length. Calculate length from base_opcode. Adjust prefix
 527         encoding determination.
 528         (process_i386_opcodes): Drop output of fake opcode_length.
 529         * i386-opc.h (struct insn_template): Drop opcode_length field.
 530         * i386-opc.tbl: Drop opcode length field from all templates.
 531         * i386-tbl.h: Re-generate.
 532
 533 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 534
 535         * i386-gen.c (process_i386_opcode_modifier): Return void. New
 536         parameter "prefix". Drop local variable "regular_encoding".
 537         Record prefix setting / check for consistency.
 538         (output_i386_opcode): Parse opcode_length and base_opcode
 539         earlier. Derive prefix encoding. Drop no longer applicable
 540         consistency checking. Adjust process_i386_opcode_modifier()
 541         invocation.
 542         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 543         invocation.
 544         * i386-tbl.h: Re-generate.
 545
 546 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 547
 548         * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
 549         check.
 550         * i386-opc.h (Prefix_*): Move #define-s.
 551         * i386-opc.tbl: Move pseudo prefix enumerator values to
 552         extension opcode field. Introduce pseudopfx template.
 553         * i386-tbl.h: Re-generate.
 554
 555 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 556
 557         * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
 558         comment.
 559         * i386-tbl.h: Re-generate.
 560
 561 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 562
 563         * i386-opc.h (struct insn_template): Move cpu_flags field past
 564         opcode_modifier one.
 565         * i386-tbl.h: Re-generate.
 566
 567 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 568
 569         * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
 570         * i386-opc.h (OpcodeSpace): New enumerator.
 571         (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
 572         (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
 573         SPACE_XOP09, SPACE_XOP0A): ... respectively.
 574         (struct i386_opcode_modifier): New field opcodespace. Shrink
 575         opcodeprefix field.
 576         i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
 577         SpaceXOP09, SpaceXOP0A): Define. Use them to replace
 578         OpcodePrefix uses.
 579         * i386-tbl.h: Re-generate.
 580
 581 2021-03-22  Martin Liska  <mliska@suse.cz>
 582
 583         * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
 584         * arc-dis.c (parse_option): Likewise.
 585         * arm-dis.c (parse_arm_disassembler_options): Likewise.
 586         * cris-dis.c (print_with_operands): Likewise.
 587         * h8300-dis.c (bfd_h8_disassemble): Likewise.
 588         * i386-dis.c (print_insn): Likewise.
 589         * ia64-gen.c (fetch_insn_class): Likewise.
 590         (parse_resource_users): Likewise.
 591         (in_iclass): Likewise.
 592         (lookup_specifier): Likewise.
 593         (insert_opcode_dependencies): Likewise.
 594         * mips-dis.c (parse_mips_ase_option): Likewise.
 595         (parse_mips_dis_option): Likewise.
 596         * s390-dis.c (disassemble_init_s390): Likewise.
 597         * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
 598
 599 2021-03-16  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
 600
 601         * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
 602
 603 2021-03-12  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 604
 605         * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
 606         icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
 607
 608 2021-03-12  Alan Modra  <amodra@gmail.com>
 609
 610         * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
 611
 612 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 613
 614         * i386-dis.c (OP_XMM): Re-order checks.
 615
 616 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 617
 618         * i386-dis.c (putop): Drop need_vex check when also checking
 619         vex.evex.
 620         (intel_operand_size, OP_E_memory): Drop vex.evex check when also
 621         checking vex.b.
 622
 623 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 624
 625         * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
 626         checks. Move case label past broadcast check.
 627
 628 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 629
 630         * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
 631         vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
 632         REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
 633         EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
 634         EVEX_W_0F38C7_M_0_L_2): Delete.
 635         (REG_EVEX_0F38C7_M_0_L_2): New.
 636         (intel_operand_size): Handle VEX and EVEX the same for
 637         vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
 638         vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
 639         (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
 640         vex_vsib_q_w_d_mode uses.
 641         * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
 642         0F38A1, and 0F38A3 entries.
 643         * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
 644         entry.
 645         * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
 646         * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
 647         0F38A3 entries.
 648
 649 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 650
 651         * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
 652         REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
 653         MOD_VEX_0FXOP_09_12): Rename to ...
 654         (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
 655         REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
 656         (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
 657         RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
 658         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 659         X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
 660         (reg_table): Adjust comments.
 661         (x86_64_table): Move X86_64_0F24, X86_64_0F26,
 662         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 663         X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
 664         (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
 665         (vex_len_table): Adjust opcode 0A_12 entry.
 666         (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
 667         MOD_C5_32BIT, and MOD_XOP_09_12 entries.
 668         (rm_table): Move hreset entry.
 669
 670 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 671
 672         * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
 673         EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
 674         EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
 675         EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
 676         EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
 677         (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
 678         (get_valid_dis386): Also handle 512-bit vector length when
 679         vectoring into vex_len_table[].
 680         * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
 681         0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
 682         entries.
 683         * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
 684         0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
 685         * i386-dis-evex-prefix.h: Adjust 0F7E entry.
 686         * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
 687         entries.
 688
 689 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 690
 691         * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
 692         Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
 693         EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
 694         * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
 695         entries.
 696         * i386-dis-evex-len.h (evex_len_table): Likewise.
 697         * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
 698
 699 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 700
 701         * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
 702         MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
 703         MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
 704         MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
 705         MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
 706         MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
 707         MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
 708         MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
 709         EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
 710         EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
 711         EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
 712         EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
 713         EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
 714         EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
 715         EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
 716         EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
 717         EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
 718         EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
 719         EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
 720         EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
 721         EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
 722         EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
 723         EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
 724         EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
 725         EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
 726         EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
 727         EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
 728         EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
 729         EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
 730         EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
 731         EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
 732         EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
 733         REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
 734         REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
 735         MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
 736         MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
 737         EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
 738         EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
 739         EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
 740         EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
 741         EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
 742         EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
 743         EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
 744         EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
 745         EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
 746         EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
 747         EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
 748         EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
 749         EVEX_W_0F3A43_L_n): New.
 750         * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
 751         0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
 752         0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
 753         * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
 754         for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
 755         0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
 756         0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
 757         * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
 758         0F385B, 0F38C6, and 0F38C7 entries.
 759         * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
 760         0F38C6 and 0F38C7.
 761         * i386-dis-evex-w.h: No longer link to evex_len_table[] for
 762         opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
 763         0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
 764         evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
 765
 766 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 767
 768         * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
 769         MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
 770         MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
 771         MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
 772         MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
 773         MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
 774         MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
 775         MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
 776         MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
 777         MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
 778         MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
 779         MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
 780         MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
 781         MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
 782         MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
 783         MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
 784         MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
 785         MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
 786         MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
 787         MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
 788         MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
 789         MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
 790         MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
 791         MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
 792         MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
 793         PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
 794         PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
 795         PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
 796         PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
 797         PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
 798         VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
 799         VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
 800         VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
 801         VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
 802         VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
 803         VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
 804         VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
 805         VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
 806         VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
 807         VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
 808         VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
 809         VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
 810         VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
 811         VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
 812         VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
 813         VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
 814         VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
 815         VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
 816         VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
 817         VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
 818         VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
 819         VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
 820         VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
 821         VEX_W_0F99_P_2_LEN_0): Delete.
 822         MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
 823         MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
 824         MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
 825         MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
 826         MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
 827         PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
 828         PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
 829         PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
 830         PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
 831         PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
 832         PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
 833         PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
 834         PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
 835         PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
 836         PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
 837         PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
 838         PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
 839         PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
 840         PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
 841         VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
 842         VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
 843         VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
 844         VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
 845         VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
 846         VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
 847         VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
 848         VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
 849         (prefix_table): No longer link to vex_len_table[] for opcodes
 850         0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
 851         0F92, 0F93, 0F98, and 0F99.
 852         (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
 853         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 854         0F98, and 0F99.
 855         (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
 856         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 857         0F98, and 0F99.
 858         (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
 859         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 860         0F98, and 0F99.
 861         (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
 862         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 863         0F98, and 0F99.
 864
 865 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 866
 867         * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
 868         Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
 869         REG_VEX_0F73_M_0 respectively.
 870         (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
 871         MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
 872         MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
 873         MOD_VEX_0F73_REG_7): Delete.
 874         (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
 875         (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
 876         PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
 877         PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
 878         PREFIX_VEX_0F3AF0_L_0 respectively.
 879         (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
 880         VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
 881         VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
 882         VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
 883         (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
 884         VEX_LEN_0F38F7): New.
 885         (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
 886         (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
 887         0F72, and 0F73. No longer link to vex_len_table[] for opcode
 888         0F38F3.
 889         (prefix_table): No longer link to vex_len_table[] for opcodes
 890         0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 891         (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
 892         0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
 893         0F38F6, 0F38F7, and 0F3AF0.
 894         (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
 895         prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 896         (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
 897         0F73.
 898
 899 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 900
 901         * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
 902         REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
 903         (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
 904         MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
 905         MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
 906         (MOD_0F71, MOD_0F72, MOD_0F73): New.
 907         (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
 908         73.
 909         (reg_table): No longer link to mod_table[] for opcodes 0F71,
 910         0F72, and 0F73.
 911         (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
 912         0F73.
 913
 914 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 915
 916         * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
 917         MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
 918         (reg_table): Don't link to mod_table[] where not needed. Add
 919         PREFIX_IGNORED to nop entries.
 920         (prefix_table): Replace PREFIX_OPCODE in nop entries.
 921         (mod_table): Add nop entries next to prefetch ones. Drop
 922         MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
 923         MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
 924         (rm_table): Add PREFIX_IGNORED to nop entries. Drop
 925         PREFIX_OPCODE from endbr* entries.
 926         (get_valid_dis386): Also consider entry's name when zapping
 927         vindex.
 928         (print_insn): Handle PREFIX_IGNORED.
 929
 930 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 931
 932         * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
 933         IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
 934         element.
 935         * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
 936         HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
 937         (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
 938         PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
 939         (struct i386_opcode_modifier): Delete notrackprefixok,
 940         islockable, hleprefixok, and repprefixok fields. Add prefixok
 941         field.
 942         * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
 943         HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
 944         (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
 945         not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
 946         Replace HLEPrefixOk.
 947         * opcodes/i386-tbl.h: Re-generate.
 948
 949 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 950
 951         * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
 952         * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
 953         64-bit form.
 954         * opcodes/i386-tbl.h: Re-generate.
 955
 956 2021-03-03  Jan Beulich  <jbeulich@suse.com>
 957
 958         * i386-gen.c (output_i386_opcode): Don't get operand count. Look
 959         for {} instead of {0}. Don't look for '0'.
 960         * i386-opc.tbl: Drop operand count field. Drop redundant operand
 961         size specifiers.
 962
 963 2021-02-19  Nelson Chu  <nelson.chu@sifive.com>
 964
 965         PR 27158
 966         * riscv-dis.c (print_insn_args): Updated encoding macros.
 967         * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
 968         (match_c_addi16sp): Updated encoding macros.
 969         (match_c_lui): Likewise.
 970         (match_c_lui_with_hint): Likewise.
 971         (match_c_addi4spn): Likewise.
 972         (match_c_slli): Likewise.
 973         (match_slli_as_c_slli): Likewise.
 974         (match_c_slli64): Likewise.
 975         (match_srxi_as_c_srxi): Likewise.
 976         (riscv_insn_types): Added .insn css/cl/cs.
 977
 978 2021-02-18  Nelson Chu  <nelson.chu@sifive.com>
 979
 980         * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
 981         (default_priv_spec): Updated type to riscv_spec_class.
 982         (parse_riscv_dis_option): Updated.
 983         * riscv-opc.c: Moved stuff and make the file tidy.
 984
 985 2021-02-17  Alan Modra  <amodra@gmail.com>
 986
 987         * wasm32-dis.c: Include limits.h.
 988         (CHAR_BIT): Provide backup define.
 989         (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
 990         Correct signed overflow checking.
 991
 992 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 993
 994         * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
 995         * i386-tbl.h: Re-generate.
 996
 997 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 998
 999         * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
1000         Oword.
1001         * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
1002
1003 2021-02-15  Andreas Krebbel  <krebbel@linux.ibm.com>
1004
1005         * s390-mkopc.c (main): Accept arch14 as cpu string.
1006         * s390-opc.txt: Add new arch14 instructions.
1007
1008 2021-02-04  Nick Alcock  <nick.alcock@oracle.com>
1009
1010         * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
1011         favour of LIBINTL.
1012         * configure: Regenerated.
1013
1014 2021-02-08  Mike Frysinger  <vapier@gentoo.org>
1015
1016         * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
1017         * tic54x-opc.c (regs): Rename to ...
1018         (tic54x_regs): ... this.
1019         (mmregs): Rename to ...
1020         (tic54x_mmregs): ... this.
1021         (condition_codes): Rename to ...
1022         (tic54x_condition_codes): ... this.
1023         (cc2_codes): Rename to ...
1024         (tic54x_cc2_codes): ... this.
1025         (cc3_codes): Rename to ...
1026         (tic54x_cc3_codes): ... this.
1027         (status_bits): Rename to ...
1028         (tic54x_status_bits): ... this.
1029         (misc_symbols): Rename to ...
1030         (tic54x_misc_symbols): ... this.
1031
1032 2021-02-04  Nelson Chu  <nelson.chu@sifive.com>
1033
1034         * riscv-opc.c (MASK_RVB_IMM): Removed.
1035         (riscv_opcodes): Removed zb* instructions.
1036         (riscv_ext_version_table): Removed versions for zb*.
1037
1038 2021-01-26  Alan Modra  <amodra@gmail.com>
1039
1040         * i386-gen.c (parse_template): Ensure entire template_instance
1041         is initialised.
1042
1043 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
1044
1045         * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
1046         (riscv_fpr_names_abi): Likewise.
1047         (riscv_opcodes): Likewise.
1048         (riscv_insn_types): Likewise.
1049
1050 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
1051
1052         * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
1053
1054 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
1055
1056         * riscv-dis.c: Comments tidy and improvement.
1057         * riscv-opc.c: Likewise.
1058
1059 2021-01-13  Alan Modra  <amodra@gmail.com>
1060
1061         * Makefile.in: Regenerate.
1062
1063 2021-01-12  H.J. Lu  <hongjiu.lu@intel.com>
1064
1065         PR binutils/26792
1066         * configure.ac: Use GNU_MAKE_JOBSERVER.
1067         * aclocal.m4: Regenerated.
1068         * configure: Likewise.
1069
1070 2021-01-12  Nick Clifton  <nickc@redhat.com>
1071
1072         * po/sr.po: Updated Serbian translation.
1073
1074 2021-01-11  H.J. Lu  <hongjiu.lu@intel.com>
1075
1076         PR ld/27173
1077         * configure: Regenerated.
1078
1079 2021-01-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
1080
1081         * aarch64-asm-2.c: Regenerate.
1082         * aarch64-dis-2.c: Likewise.
1083         * aarch64-opc-2.c: Likewise.
1084         * aarch64-opc.c (aarch64_print_operand):
1085         Delete handling of AARCH64_OPND_CSRE_CSR.
1086         * aarch64-tbl.h (aarch64_feature_csre): Delete.
1087         (CSRE): Likewise.
1088         (_CSRE_INSN): Likewise.
1089         (aarch64_opcode_table): Delete csr.
1090
1091 2021-01-11  Nick Clifton  <nickc@redhat.com>
1092
1093         * po/de.po: Updated German translation.
1094         * po/fr.po: Updated French translation.
1095         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1096         * po/sv.po: Updated Swedish translation.
1097         * po/uk.po: Updated Ukranian translation.
1098
1099 2021-01-09  H.J. Lu  <hongjiu.lu@intel.com>
1100
1101         * configure: Regenerated.
1102
1103 2021-01-09  Nick Clifton  <nickc@redhat.com>
1104
1105         * configure: Regenerate.
1106         * po/opcodes.pot: Regenerate.
1107
1108 2021-01-09  Nick Clifton  <nickc@redhat.com>
1109
1110         * 2.36 release branch crated.
1111
1112 2021-01-08  Peter Bergner  <bergner@linux.ibm.com>
1113
1114         * ppc-opc.c (insert_dw, (extract_dw): New functions.
1115         (DW, (XRC_MASK): Define.
1116         (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
1117
1118 2021-01-09  Alan Modra  <amodra@gmail.com>
1119
1120         * configure: Regenerate.
1121
1122 2021-01-08  Nick Clifton  <nickc@redhat.com>
1123
1124         * po/sv.po: Updated Swedish translation.
1125
1126 2021-01-08  Nick Clifton  <nickc@redhat.com>
1127
1128         PR 27129
1129         * aarch64-dis.c (determine_disassembling_preference): Move call to
1130         aarch64_match_operands_constraint outside of the assertion.
1131         * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
1132         Replace with a return of FALSE.
1133
1134         PR 27139
1135         * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
1136         core system register.
1137
1138 2021-01-07  Samuel Thibault  <samuel.thibault@gnu.org>
1139
1140         * configure: Regenerate.
1141
1142 2021-01-07  Nick Clifton  <nickc@redhat.com>
1143
1144         * po/fr.po: Updated French translation.
1145
1146 2021-01-07  Fredrik Noring  <noring@nocrew.org>
1147
1148         * m68k-opc.c (chkl): Change minimum architecture requirement to
1149         m68020.
1150
1151 2021-01-07  Philipp Tomsich  <prt@gnu.org>
1152
1153         * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
1154
1155 2021-01-07  Claire Xenia Wolf  <claire@symbioticeda.com>
1156             Jim Wilson  <jimw@sifive.com>
1157             Andrew Waterman  <andrew@sifive.com>
1158             Maxim Blinov  <maxim.blinov@embecosm.com>
1159             Kito Cheng  <kito.cheng@sifive.com>
1160             Nelson Chu  <nelson.chu@sifive.com>
1161
1162         * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
1163         (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
1164
1165 2021-01-01  Alan Modra  <amodra@gmail.com>
1166
1167         Update year range in copyright notice of all files.
1168
1169 For older changes see ChangeLog-2020
1170 \f
1171 Copyright (C) 2021 Free Software Foundation, Inc.
1172
1173 Copying and distribution of this file, with or without modification,
1174 are permitted in any medium without royalty provided the copyright
1175 notice and this notice are preserved.
1176
1177 Local Variables:
1178 mode: change-log
1179 left-margin: 8
1180 fill-column: 74
1181 version-control: never
1182 End: