opcodes/ChangeLog

   1 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
   2
   3         * bfin-dis.c (decode_pseudoDEBUG_0): Add space after OUTC.
   4         (decode_pseudoOChar_0): New function.
   5         (_print_insn_bfin): Remove #if 0 and call new decode_pseudoOChar_0.
   6
   7 2010-09-22  Robin Getz  <robin.getz@analog.com>
   8
   9         * bfin-dis.c (decode_dsp32shift_0): Decode sub opcodes 2/2 as
  10         LSHIFT instead of SHIFT.
  11
  12 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
  13
  14         * bfin-dis.c (constant_formats): Constify the whole structure.
  15         (fmtconst): Add const to return value.
  16         (reg_names): Mark const.
  17         (decode_multfunc): Mark s0/s1 as const.
  18         (decode_macfunc): Mark a/sop as const.
  19
  20 2010-09-17  Tejas Belagod  <tejas.belagod@arm.com>
  21
  22         * arm_dis.c (coprocessor_opcodes): Add MRC entry for APSR_nzcv.
  23
  24 2010-09-14  Maciej W. Rozycki  <macro@codesourcery.com>
  25
  26         * mips-opc.c (mips_builtin_opcodes): Add "sync_acquire",
  27         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb".
  28
  29 2010-09-10  Pierre Muller  <muller@ics.u-strasbg.fr>
  30
  31         * src/opcodes/dlx-dis.c (print_insn_dlx): Use dlx_insn type for
  32         dlx_insn_type array.
  33
  34 2010-08-31  H.J. Lu  <hongjiu.lu@intel.com>
  35
  36         PR binutils/11960
  37         * i386-dis.c (sIv): New.
  38         (dis386): Replace Iq with sIv on "pushT".
  39         (reg_table): Replace T with {T|} on callT, JcallT, jmpT and JjmpT.
  40         (x86_64_table): Replace {T|}/{P|} with P.
  41         (putop): Add 'w' to 'T'/'P' if needed for Intel syntax.
  42         (OP_sI): Update v_mode.  Remove w_mode.
  43
  44 2010-08-27  Nathan Froyd  <froydnj@codesourcery.com>
  45
  46         * ppc-opc.c (powerpc_opcodes) [lswx,lswi,stswx,stswi]: Deprecate
  47         on E500 and E500MC.
  48
  49 2010-08-17  H.J. Lu  <hongjiu.lu@intel.com>
  50
  51         * i386-dis.c (reg_table): Replace Eb with Mb on prefetch and
  52         prefetchw.
  53
  54 2010-08-06  Quentin Neill <quentin.neill@amd.com>
  55
  56         * i386-gen.c (cpu_flag_init): Define CpuNop extension flag, add
  57         to processor flags for PENTIUMPRO processors and later.
  58         * i386-opc.h (enum): Add CpuNop.
  59         (i386_cpu_flags): Add cpunop bit.
  60         * i386-opc.tbl: Change nop cpu_flags.
  61         * i386-init.h: Regenerated.
  62         * i386-tbl.h: Likewise.
  63
  64 2010-08-06  Quentin Neill <quentin.neill@amd.com>
  65
  66         * i386-opc.h (enum): Fix typos in comments.
  67
  68 2010-08-06  Alan Modra  <amodra@gmail.com>
  69
  70         * disassemble.c: Formatting.
  71         (disassemble_init_for_target <ARCH_m32c>): Comment on endian.
  72
  73 2010-08-05  H.J. Lu  <hongjiu.lu@intel.com>
  74
  75         * i386-opc.tbl: Add Cpu186 to ud1/ud2/ud2a/ud2b.
  76         * i386-tbl.h: Regenerated.
  77
  78 2010-08-05  H.J. Lu  <hongjiu.lu@intel.com>
  79
  80         * i386-dis.c (dis386_twobyte): Replace ud2a/ud2b with ud2/ud1.
  81
  82         * i386-opc.tbl: Add ud1.  Remove Cpu686 from ud2/ud2a/ud2b.
  83         * i386-tbl.h: Regenerated.
  84
  85 2010-07-29  DJ Delorie  <dj@redhat.com>
  86
  87         * rx-decode.opc (SRR): New.
  88         (rx_decode_opcode): Use it for movbi and movbir.  Decode NOP2 (mov
  89         r0,r0) and NOP3 (max r0,r0) special cases.
  90         * rx-decode.c: Regenerate.
  91
  92 2010-07-28  H.J. Lu  <hongjiu.lu@intel.com>
  93
  94         * i386-dis.c: Add 0F to VEX opcode enums.
  95
  96 2010-07-27  DJ Delorie  <dj@redhat.com>
  97
  98         * rx-decode.opc (store_flags): Remove, replace with F_* macros.
  99         (rx_decode_opcode): Likewise.
 100         * rx-decode.c: Regenerate.
 101
 102 2010-07-23  Naveen.H.S  <naveen.S@kpitcummins.com>
 103             Ina Pandit  <ina.pandit@kpitcummins.com>
 104
 105         * v850-dis.c (v850_sreg_names): Updated structure for system
 106         registers.
 107         (float_cc_names): new structure for condition codes.
 108         (print_value): Update the function that prints value.
 109         (get_operand_value): New function to get the operand value.
 110         (disassemble): Updated to handle the disassembly of instructions.
 111         (print_insn_v850): Updated function to print instruction for different
 112         families.
 113         * opcodes/v850-opc.c (v850_msg_is_out_of_range, insert_i5div1,
 114         extract_i5div1, insert_i5div2, extract_i5div2, insert_i5div3,
 115         extract_i5div3, insert_d5_4, extract_d5_4, extract_d8_6,
 116         insert_d8_7, extract_d8_7, insert_v8, extract_v8, insert_u16_loop,
 117         extract_u16_loop, insert_d16_15, extract_d16_15, insert_d16_16,
 118         extract_d16_16, nsert_d17_16, extract_d17_16, insert_d22,
 119         extract_d22, insert_d23, extract_d23, insert_i9, extract_i9,
 120         insert_u9, extract_u9, extract_spe, insert_r4, extract_r4): New.
 121         (insert_d8_7, insert_d5_4, insert_i5div): Remove.
 122         (v850_operands): Update with the relocation name. Also update
 123         the instructions with specific set of processors.
 124
 125 2010-07-08 Tejas Belagod <tejas.belagod@arm.com>
 126
 127         * arm-dis.c (print_insn_arm): Add cases for printing more
 128         symbolic operands.
 129         (print_insn_thumb32): Likewise.
 130
 131 2010-07-06  Maciej W. Rozycki  <macro@codesourcery.com>
 132
 133         * mips-dis.c (print_insn_mips): Correct branch instruction type
 134         determination.
 135
 136 2010-07-06  Maciej W. Rozycki  <macro@codesourcery.com>
 137
 138         * mips-dis.c (print_mips16_insn_arg): Remove branch instruction
 139         type and delay slot determination.
 140         (print_insn_mips16): Extend branch instruction type and delay
 141         slot determination to cover all instructions.
 142         * mips16-opc.c (BR): Remove macro.
 143         (UBR, CBR): New macros.
 144         (mips16_opcodes): Update branch annotation for "b", "beqz",
 145         "bnez", "bteqz" and "btnez".  Add branch annotation for "jalrc"
 146         and "jrc".
 147
 148 2010-07-05  H.J. Lu  <hongjiu.lu@intel.com>
 149
 150         AVX Programming Reference (June, 2010)
 151         * i386-dis.c (mod_table): Replace rdrnd with rdrand.
 152         * i386-opc.tbl: Likewise.
 153         * i386-tbl.h: Regenerated.
 154
 155 2010-07-05  H.J. Lu  <hongjiu.lu@intel.com>
 156
 157         * i386-opc.h (CpuFSGSBase): Fix a typo in comments.
 158
 159 2010-07-03  Andreas Schwab  <schwab@linux-m68k.org>
 160
 161         * ppc-dis.c (powerpc_init_dialect): Cast PPC_OPCODE_xxx to
 162         ppc_cpu_t before inverting.
 163         (ppc_parse_cpu): Likewise.
 164         (print_insn_powerpc): Likewise.
 165
 166 2010-07-03  Alan Modra  <amodra@gmail.com>
 167
 168         * ppc-dis.c (ppc_opts, powerpc_init_dialect): Remove old opcode flags.
 169         * ppc-opc.c (PPC32, POWER32, COM32, CLASSIC): Delete.
 170         (PPC64, MFDEC2): Update.
 171         (NON32, NO371): Define.
 172         (powerpc_opcode): Update to not use old opcode flags, and avoid
 173         -m601 duplicates.
 174
 175 2010-07-03  DJ Delorie  <dj@delorie.com>
 176
 177         * m32c-ibld.c: Regenerate.
 178
 179 2010-07-03  Alan Modra  <amodra@gmail.com>
 180
 181         * ppc-opc.c (PWR2COM): Define.
 182         (PPCPWR2): Add PPC_OPCODE_COMMON.
 183         (powerpc_opcodes): Add "subc", "subco", "subco.", "fcir", "fcir.",
 184         "fcirz", "fcirz." to -mcom opcodes.  Remove "mfsri", "dclst",
 185         "rac" from -mcom.
 186
 187 2010-07-01  H.J. Lu  <hongjiu.lu@intel.com>
 188
 189         AVX Programming Reference (June, 2010)
 190         * i386-dis.c (PREFIX_0FAE_REG_0): New.
 191         (PREFIX_0FAE_REG_1): Likewise.
 192         (PREFIX_0FAE_REG_2): Likewise.
 193         (PREFIX_0FAE_REG_3): Likewise.
 194         (PREFIX_VEX_3813): Likewise.
 195         (PREFIX_VEX_3A1D): Likewise.
 196         (prefix_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
 197         PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3, PREFIX_VEX_3813 and
 198         PREFIX_VEX_3A1D.
 199         (vex_table): Add PREFIX_VEX_3813 and PREFIX_VEX_3A1D.
 200         (mod_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
 201         PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3 xsaveopt and rdrnd.
 202
 203         * i386-gen.c (cpu_flag_init): Add CPU_XSAVEOPT_FLAGS,
 204         CPU_FSGSBASE_FLAGS, CPU_RDRND_FLAGS and CPU_F16C_FLAGS.
 205         (cpu_flags): Add CpuXsaveopt, CpuFSGSBase, CpuRdRnd and CpuF16C.
 206
 207         * i386-opc.h (CpuXsaveopt): New.
 208         (CpuFSGSBase): Likewise.
 209         (CpuRdRnd): Likewise.
 210         (CpuF16C): Likewise.
 211         (i386_cpu_flags): Add cpuxsaveopt, cpufsgsbase, cpurdrnd and
 212         cpuf16c.
 213
 214         * i386-opc.tbl: Add xsaveopt, rdfsbase, rdgsbase, rdrnd,
 215         wrfsbase, wrgsbase, vcvtph2ps and vcvtps2ph.
 216         * i386-init.h: Regenerated.
 217         * i386-tbl.h: Likewise.
 218
 219 2010-07-01  Sebastian Andrzej Siewior  <bigeasy@linutronix.de>
 220
 221         * ppc-opc.c (powerpc_opcodes): Revert deprecation of mfocrf, mtcrf
 222         and mtocrf on EFS.
 223
 224 2010-06-29  Alan Modra  <amodra@gmail.com>
 225
 226         * maxq-dis.c: Delete file.
 227         * Makefile.am: Remove references to maxq.
 228         * configure.in: Likewise.
 229         * disassemble.c: Likewise.
 230         * Makefile.in: Regenerate.
 231         * configure: Regenerate.
 232         * po/POTFILES.in: Regenerate.
 233
 234 2010-06-29  Alan Modra  <amodra@gmail.com>
 235
 236         * mep-dis.c: Regenerate.
 237
 238 2010-06-28  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 239
 240         * arm-disc.c (parse_insn_neon):  Fix Neon alignment syntax.
 241
 242 2010-06-27  Alan Modra  <amodra@gmail.com>
 243
 244         * arc-dis.c (arc_sprintf): Delete set but unused variables.
 245         (decodeInstr): Likewise.
 246         * dlx-dis.c (print_insn_dlx): Likewise.
 247         * h8300-dis.c (bfd_h8_disassemble_init): Likewise.
 248         * maxq-dis.c (check_move, print_insn): Likewise.
 249         * mep-dis.c (mep_examine_ivc2_insns): Likewise.
 250         * msp430-dis.c (msp430_branchinstr): Likewise.
 251         * bfin-dis.c (_print_insn_bfin): Avoid set but unused warning.
 252         * cgen-asm.in (parse_insn_normal, _cgen_assemble_insn): Likewise.
 253         * sparc-dis.c (print_insn_sparc): Likewise.
 254         * fr30-asm.c: Regenerate.
 255         * frv-asm.c: Regenerate.
 256         * ip2k-asm.c: Regenerate.
 257         * iq2000-asm.c: Regenerate.
 258         * lm32-asm.c: Regenerate.
 259         * m32c-asm.c: Regenerate.
 260         * m32r-asm.c: Regenerate.
 261         * mep-asm.c: Regenerate.
 262         * mt-asm.c: Regenerate.
 263         * openrisc-asm.c: Regenerate.
 264         * xc16x-asm.c: Regenerate.
 265         * xstormy16-asm.c: Regenerate.
 266
 267 2010-06-16  Vincent Rivière  <vincent.riviere@freesbee.fr>
 268
 269         PR gas/11673
 270         * m68k-opc.c (m68k_opcodes): Remove move.l for isab and later.
 271
 272 2010-06-16  Vincent Rivière  <vincent.riviere@freesbee.fr>
 273
 274         PR binutils/11676
 275         * m68k-dis.c (print_insn_arg): Prefix float constants with #0e.
 276
 277 2010-06-14  Sebastian Andrzej Siewior  <bigeasy@linutronix.de>
 278
 279         * ppc-dis.c (ppc_opts):  Remove PPC_OPCODE_E500MC from e500 and
 280         e500x2.  Add PPC_OPCODE_E500 to e500 and e500x2
 281         * ppc-opc.c (powerpc_opcodes): Deprecate all opcodes on EFS which
 282         touch floating point regs and are enabled by COM, PPC or PPCCOM.
 283         Treat sync as msync on e500.  Treat eieio as mbar 1 on e500.
 284         Treat lwsync as msync on e500.
 285
 286 2010-06-07  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 287
 288         * arm-dis.c (thumb-opcodes): Add disassembly for movs.
 289
 290 2010-05-28  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 291
 292         * arm-dis.c (print_insn_neon):  Ensure disassembly of Neon
 293         constants is the same on 32-bit and 64-bit hosts.
 294
 295 2010-05-27  Jason Duerstock  <jason.duerstock+binutils@gmail.com>
 296
 297         * m68k-dis.c (print_insn_m68k): Emit undefined instructions as
 298         .short directives so that they can be reassembled.
 299
 300 2010-05-26  Catherine Moore <clm@codesourcery.com>
 301             David Ung  <davidu@mips.com>
 302
 303         * mips-opc.c: Change membership to I1 for instructions ssnop and
 304         ehb.
 305
 306 2010-05-26  H.J. Lu  <hongjiu.lu@intel.com>
 307
 308         * i386-dis.c (sib): New.
 309         (get_sib): Likewise.
 310         (print_insn): Call get_sib.
 311         OP_E_memory): Use sib.
 312
 313 2010-05-26  Catherine Moore  <clm@codesoourcery.com>
 314
 315         * mips-dis.c (mips_arch): Remove INSN_MIPS16.
 316         * mips-opc.c (I16): Remove.
 317         (mips_builtin_op): Reclassify jalx.
 318
 319 2010-05-19  Alan Modra  <amodra@gmail.com>
 320
 321         * ppc-opc.c (powerpc_opcodes): Enable divdeu, devweu, divde,
 322         divwe, divdeuo, divweuo, divdeo, divweo for A2.  Add icswepx.
 323
 324 2010-05-13  Alan Modra  <amodra@gmail.com>
 325
 326         * ppc-opc.c (powerpc_opcodes): Correct wclr encoding.
 327
 328 2010-05-11  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 329
 330         * arm-dis.c (thumb_opcodes): Update ldmia entry to use new %W
 331         format.
 332         (print_insn_thumb16): Add support for new %W format.
 333
 334 2010-05-07  Tristan Gingold  <gingold@adacore.com>
 335
 336         * Makefile.in: Regenerate with automake 1.11.1.
 337         * aclocal.m4: Ditto.
 338
 339 2010-05-05  Nick Clifton  <nickc@redhat.com>
 340
 341         * po/es.po: Updated Spanish translation.
 342
 343 2010-04-22  Nick Clifton  <nickc@redhat.com>
 344
 345         * po/opcodes.pot: Updated by the Translation project.
 346         * po/vi.po: Updated Vietnamese translation.
 347
 348 2010-04-16  H.J. Lu  <hongjiu.lu@intel.com>
 349
 350         * i386-dis.c (get_valid_dis386): Return bad_opcode on unknown
 351         bits in opcode.
 352
 353 2010-04-09  Nick Clifton  <nickc@redhat.com>
 354
 355         * i386-dis.c (print_insn): Remove unused variable op.
 356         (OP_sI): Remove unused variable mask.
 357
 358 2010-04-07  Alan Modra  <amodra@gmail.com>
 359
 360         * configure: Regenerate.
 361
 362 2010-04-06  Peter Bergner  <bergner@vnet.ibm.com>
 363
 364         * ppc-opc.c (RBOPT): New define.
 365         ("dccci"): Enable for PPCA2.  Make operands optional.
 366         ("iccci"): Likewise.  Do not deprecate for PPC476.
 367
 368 2010-04-02  Masaki Muranaka  <monaka@monami-software.com>
 369
 370         * cr16-opc.c (cr16_instruction): Fix typo in comment.
 371
 372 2010-03-25  Joseph Myers  <joseph@codesourcery.com>
 373
 374         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add tic6x-dis.c.
 375         * Makefile.in: Regenerate.
 376         * configure.in (bfd_tic6x_arch): New.
 377         * configure: Regenerate.
 378         * disassemble.c (ARCH_tic6x): Define if ARCH_all.
 379         (disassembler): Handle TI C6X.
 380         * tic6x-dis.c: New.
 381
 382 2010-03-24  Mike Frysinger  <vapier@gentoo.org>
 383
 384         * bfin-dis.c (decode_regs_hi): Change REG_LH2 typo to REG_MH2.
 385
 386 2010-03-23  Joseph Myers  <joseph@codesourcery.com>
 387
 388         * dis-buf.c (buffer_read_memory): Give error for reading just
 389         before the start of memory.
 390
 391 2010-03-22  Sebastian Pop  <sebastian.pop@amd.com>
 392             Quentin Neill <quentin.neill@amd.com>
 393
 394         * i386-dis.c (OP_LWP_I): Removed.
 395         (reg_table): Do not use OP_LWP_I, use Iq.
 396         (OP_LWPCB_E): Remove use of names16.
 397         (OP_LWP_E): Same.
 398         * i386-opc.tbl: Removed 16bit LWP insns.  32bit LWP insns
 399         should not set the Vex.length bit.
 400         * i386-tbl.h: Regenerated.
 401
 402 2010-02-25  Edmar Wienskoski  <edmar@freescale.com>
 403
 404         * ppc-dis.c (ppc_opts): Add PPC_OPCODE_E500MC for "e500mc64".
 405
 406 2010-02-24  Nick Clifton  <nickc@redhat.com>
 407
 408         PR binutils/6773
 409         * arm-dis.c (arm_opcodes): Replace <prefix>addsubx with
 410         <prefix>asx.  Replace <prefix>subaddx with <prefix>sax.
 411         (thumb32_opcodes): Likewise.
 412
 413 2010-02-15  Nick Clifton  <nickc@redhat.com>
 414
 415         * po/vi.po: Updated Vietnamese translation.
 416
 417 2010-02-12  Doug Evans  <dje@sebabeach.org>
 418
 419         * lm32-opinst.c: Regenerate.
 420
 421 2010-02-11  Doug Evans  <dje@sebabeach.org>
 422
 423         * cgen-dis.in (print_normal): Delete CGEN_PRINT_NORMAL.
 424         (print_address): Delete CGEN_PRINT_ADDRESS.
 425         * fr30-dis.c, * frv-dis.c, * ip2k-dis.c, * iq2000-dis.c,
 426         * lm32-dis.c, * m32c-dis.c, * m32r-desc.c, * m32r-desc.h,
 427         * m32r-dis.c, * mep-dis.c, * mt-dis.c, * openrisc-dis.c,
 428         * xc16x-dis.c, * xstormy16-dis.c: Regenerate.
 429
 430         * fr30-desc.c, * fr30-desc.h, * fr30-opc.c,
 431         * frv-desc.c, * frv-desc.h, * frv-opc.c,
 432         * ip2k-desc.c, * ip2k-desc.h, * ip2k-opc.c,
 433         * iq2000-desc.c, * iq2000-desc.h, * iq2000-opc.c,
 434         * lm32-desc.c, * lm32-desc.h, * lm32-opc.c, * lm32-opinst.c,
 435         * m32c-desc.c, * m32c-desc.h, * m32c-opc.c,
 436         * m32r-desc.c, * m32r-desc.h, * m32r-opc.c, * m32r-opinst.c,
 437         * mep-desc.c, * mep-desc.h, * mep-opc.c,
 438         * mt-desc.c, * mt-desc.h, * mt-opc.c,
 439         * openrisc-desc.c, * openrisc-desc.h, * openrisc-opc.c,
 440         * xc16x-desc.c, * xc16x-desc.h, * xc16x-opc.c,
 441         * xstormy16-desc.c, * xstormy16-desc.h, * xstormy16-opc.c: Regenerate.
 442
 443 2010-02-11  H.J. Lu  <hongjiu.lu@intel.com>
 444
 445         * i386-dis.c: Update copyright.
 446         * i386-gen.c: Likewise.
 447         * i386-opc.h: Likewise.
 448         * i386-opc.tbl: Likewise.
 449
 450 2010-02-10  Quentin Neill  <quentin.neill@amd.com>
 451             Sebastian Pop  <sebastian.pop@amd.com>
 452
 453         * i386-dis.c (OP_EX_VexImmW): Reintroduced
 454         function to handle 5th imm8 operand.
 455         (PREFIX_VEX_3A48): Added.
 456         (PREFIX_VEX_3A49): Added.
 457         (VEX_W_3A48_P_2): Added.
 458         (VEX_W_3A49_P_2): Added.
 459         (prefix table): Added entries for PREFIX_VEX_3A48
 460         and PREFIX_VEX_3A49.
 461         (vex table): Added entries for VEX_W_3A48_P_2 and
 462         and VEX_W_3A49_P_2.
 463         * i386-gen.c (operand_type_init): Added OPERAND_TYPE_VEC_IMM4
 464         for Vec_Imm4 operands.
 465         * i386-opc.h (enum): Added Vec_Imm4.
 466         (i386_operand_type): Added vec_imm4.
 467         * i386-opc.tbl: Add entries for vpermilp[ds].
 468         * i386-init.h: Regenerated.
 469         * i386-tbl.h: Regenerated.
 470
 471 2010-02-10  Richard Sandiford  <r.sandiford@uk.ibm.com>
 472
 473         * ppc-dis.c (ppc_opts): Add "pwr4", "pwr5", "pwr5x", "pwr6"
 474         and "pwr7".  Move "a2" into alphabetical order.
 475
 476 2010-02-08  Philipp Tomsich  <philipp.tomsich@theobroma-systems.com>
 477
 478         * ppc-dis.c (ppc_opts): Add titan entry.
 479         * ppc-opc.c (TITAN, MULHW): Define.
 480         (powerpc_opcodes): Support AppliedMicro Titan core (APM83xxx).
 481
 482 2010-02-03  Quentin Neill  <quentin.neill@amd.com>
 483
 484         * i386-gen.c (cpu_flag_init): Rename CPU_AMDFAM15_FLAGS
 485         to CPU_BDVER1_FLAGS
 486         * i386-init.h: Regenerated.
 487
 488 2010-02-03  Anthony Green  <green@moxielogic.com>
 489
 490         * moxie-opc.c (moxie_form1_opc_info): Move "nop" from 0x00 to
 491         0x0f, and make 0x00 an illegal instruction.
 492
 493 2010-01-29  Daniel Jacobowitz  <dan@codesourcery.com>
 494
 495         * opcodes/arm-dis.c (struct arm_private_data): New.
 496         (print_insn_coprocessor, print_insn_arm): Update to use struct
 497         arm_private_data.
 498         (is_mapping_symbol, get_map_sym_type): New functions.
 499         (get_sym_code_type): Check the symbol's section.  Do not check
 500         mapping symbols.
 501         (print_insn): Default to disassembling ARM mode code.  Check
 502         for mapping symbols separately from other symbols.  Use
 503         struct arm_private_data.
 504
 505 2010-01-28  H.J. Lu  <hongjiu.lu@intel.com>
 506
 507         * i386-dis.c (EXVexWdqScalar): New.
 508         (vex_scalar_w_dq_mode): Likewise.
 509         (prefix_table): Update entries for PREFIX_VEX_3899,
 510         PREFIX_VEX_389B, PREFIX_VEX_389D, PREFIX_VEX_389F,
 511         PREFIX_VEX_38A9, PREFIX_VEX_38AB, PREFIX_VEX_38AD,
 512         PREFIX_VEX_38AF, PREFIX_VEX_38B9, PREFIX_VEX_38BB,
 513         PREFIX_VEX_38BD and PREFIX_VEX_38BF.
 514         (intel_operand_size): Handle vex_scalar_w_dq_mode.
 515         (OP_EX): Likewise.
 516
 517 2010-01-27  H.J. Lu  <hongjiu.lu@intel.com>
 518
 519         * i386-dis.c (XMScalar): New.
 520         (EXdScalar): Likewise.
 521         (EXqScalar): Likewise.
 522         (EXqScalarS): Likewise.
 523         (VexScalar): Likewise.
 524         (EXdVexScalarS): Likewise.
 525         (EXqVexScalarS): Likewise.
 526         (XMVexScalar): Likewise.
 527         (scalar_mode): Likewise.
 528         (d_scalar_mode): Likewise.
 529         (d_scalar_swap_mode): Likewise.
 530         (q_scalar_mode): Likewise.
 531         (q_scalar_swap_mode): Likewise.
 532         (vex_scalar_mode): Likewise.
 533         (vex_len_table): Duplcate entries for VEX_LEN_10_P_1,
 534         VEX_LEN_10_P_3, VEX_LEN_11_P_1, VEX_LEN_11_P_3, VEX_LEN_2A_P_1,
 535         VEX_LEN_2A_P_3, VEX_LEN_2C_P_3, VEX_LEN_2D_P_1, VEX_LEN_2E_P_0,
 536         VEX_LEN_2E_P_2, VEX_LEN_2F_P_2, VEX_LEN_51_P_1, VEX_LEN_51_P_3,
 537         VEX_LEN_52_P_1, VEX_LEN_53_P_1, VEX_LEN_58_P_1, VEX_LEN_58_P_3,
 538         VEX_LEN_59_P_1, VEX_LEN_5A_P_1, VEX_LEN_5A_P_3, VEX_LEN_5C_P_1,
 539         VEX_LEN_5C_P_3, VEX_LEN_5D_P_1, VEX_LEN_5D_P_3, VEX_LEN_5E_P_1,
 540         VEX_LEN_5E_P_3, VEX_LEN_5F_P_1, VEX_LEN_5F_P_3, VEX_LEN_6E_P_2,
 541         VEX_LEN_7E_P_1, VEX_LEN_7E_P_2, VEX_LEN_D6_P_2, VEX_LEN_C2_P_1,
 542         VEX_LEN_C2_P_3, VEX_LEN_3A0A_P_2 and VEX_LEN_3A0B_P_2.
 543         (vex_w_table): Update entries for VEX_W_10_P_1, VEX_W_10_P_3,
 544         VEX_W_11_P_1, VEX_W_11_P_3, VEX_W_2E_P_0, VEX_W_2E_P_2,
 545         VEX_W_2F_P_0, VEX_W_2F_P_2, VEX_W_51_P_1, VEX_W_51_P_3,
 546         VEX_W_52_P_1, VEX_W_53_P_1, VEX_W_58_P_1, VEX_W_58_P_3,
 547         VEX_W_59_P_1, VEX_W_59_P_3, VEX_W_5A_P_1, VEX_W_5A_P_3,
 548         VEX_W_5C_P_1, VEX_W_5C_P_3, VEX_W_5D_P_1, VEX_W_5D_P_3,
 549         VEX_W_5E_P_1, VEX_W_5E_P_3, VEX_W_5F_P_1, VEX_W_5F_P_3,
 550         VEX_W_7E_P_1, VEX_W_D6_P_2  VEX_W_C2_P_1, VEX_W_C2_P_3,
 551         VEX_W_3A0A_P_2 and VEX_W_3A0B_P_2.
 552         (intel_operand_size): Handle d_scalar_mode, d_scalar_swap_mode,
 553         q_scalar_mode, q_scalar_swap_mode.
 554         (OP_XMM): Handle scalar_mode.
 555         (OP_EX): Handle d_scalar_mode, d_scalar_swap_mode, q_scalar_mode
 556         and q_scalar_swap_mode.
 557         (OP_VEX): Handle vex_scalar_mode.
 558
 559 2010-01-24  H.J. Lu  <hongjiu.lu@intel.com>
 560
 561         * i386-dis.c (prefix_table): Remove trailing { Bad_Opcode }.
 562
 563 2010-01-24  H.J. Lu  <hongjiu.lu@intel.com>
 564
 565         * i386-dis.c (vex_len_table): Remove trailing { Bad_Opcode }.
 566
 567 2010-01-24  H.J. Lu  <hongjiu.lu@intel.com>
 568
 569         * i386-dis.c (prefix_table): Remove trailing { Bad_Opcode }.
 570
 571 2010-01-24  H.J. Lu  <hongjiu.lu@intel.com>
 572
 573         * i386-dis.c (Bad_Opcode): New.
 574         (bad_opcode): Likewise.
 575         (dis386): Replace { "(bad)", { XX } } with { Bad_Opcode }.
 576         (dis386_twobyte): Likewise.
 577         (reg_table): Likewise.
 578         (prefix_table): Likewise.
 579         (x86_64_table): Likewise.
 580         (vex_len_table): Likewise.
 581         (vex_w_table): Likewise.
 582         (mod_table): Likewise.
 583         (rm_table): Likewise.
 584         (float_reg): Likewise.
 585         (reg_table): Remove trailing "(bad)" entries.
 586         (prefix_table): Likewise.
 587         (x86_64_table): Likewise.
 588         (vex_len_table): Likewise.
 589         (vex_w_table): Likewise.
 590         (mod_table): Likewise.
 591         (rm_table): Likewise.
 592         (get_valid_dis386): Handle bytemode 0.
 593
 594 2010-01-23  H.J. Lu  <hongjiu.lu@intel.com>
 595
 596         * i386-opc.h (VEXScalar): New.
 597
 598         * i386-opc.tbl: Replace "Vex" with "Vex=3" on AVX scalar
 599         instructions.
 600         * i386-tbl.h: Regenerated.
 601
 602 2010-01-21  H.J. Lu  <hongjiu.lu@intel.com>
 603
 604         * i386-dis.c (mod_table): Use FXSAVE on xsave and xrstor.
 605
 606         * i386-opc.tbl: Add xsave64 and xrstor64.
 607         * i386-tbl.h: Regenerated.
 608
 609 2010-01-20  Nick Clifton  <nickc@redhat.com>
 610
 611         PR 11170
 612         * arm-dis.c (print_arm_address): Do not ignore negative bit in PC
 613         based post-indexed addressing.
 614
 615 2010-01-15  Sebastian Pop  <sebastian.pop@amd.com>
 616
 617         * i386-opc.tbl: Support all the possible aliases for VPCOM* insns.
 618         * i386-tbl.h: Regenerated.
 619
 620 2010-01-14  H.J. Lu  <hongjiu.lu@intel.com>
 621
 622         * i386-opc.h (VexVVVV): Replace VEX.DNS with VEX.NDS in
 623         comments.
 624
 625 2010-01-14  H.J. Lu  <hongjiu.lu@intel.com>
 626
 627         * i386-dis.c (names_mm): New.
 628         (intel_names_mm): Likewise.
 629         (att_names_mm): Likewise.
 630         (names_xmm): Likewise.
 631         (intel_names_xmm): Likewise.
 632         (att_names_xmm): Likewise.
 633         (names_ymm): Likewise.
 634         (intel_names_ymm): Likewise.
 635         (att_names_ymm): Likewise.
 636         (print_insn): Set names_mm, names_xmm and names_ymm.
 637         (OP_MMX): Use names_mm, names_xmm and names_ymm.
 638         (OP_XMM): Likewise.
 639         (OP_EM): Likewise.
 640         (OP_EMC): Likewise.
 641         (OP_MXC): Likewise.
 642         (OP_EX): Likewise.
 643         (XMM_Fixup): Likewise.
 644         (OP_VEX): Likewise.
 645         (OP_EX_VexReg): Likewise.
 646         (OP_Vex_2src): Likewise.
 647         (OP_Vex_2src_1): Likewise.
 648         (OP_Vex_2src_2): Likewise.
 649         (OP_REG_VexI4): Likewise.
 650
 651 2010-01-13  H.J. Lu  <hongjiu.lu@intel.com>
 652
 653         * i386-dis.c (print_insn): Update comments.
 654
 655 2010-01-12  H.J. Lu  <hongjiu.lu@intel.com>
 656
 657         * i386-dis.c (rex_original): Removed.
 658         (ckprefix): Remove rex_original.
 659         (print_insn): Update comments.
 660
 661 2010-01-09  Ralf Wildenhues  <Ralf.Wildenhues@gmx.de>
 662
 663         * Makefile.in: Regenerate.
 664         * configure: Regenerate.
 665
 666 2010-01-07  Doug Evans  <dje@sebabeach.org>
 667
 668         * cgen-ibld.in (insert_normal, extract_normal): Minor cleanup.
 669         * fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c,
 670         * lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c,
 671         * mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c,
 672         * xstormy16-ibld.c: Regenerate.
 673
 674 2010-01-06  Quentin Neill  <quentin.neill@amd.com>
 675
 676         * i386-gen.c (cpu_flag_init): Add new CPU_AMDFAM15_FLAGS.
 677         * i386-init.h: Regenerated.
 678
 679 2010-01-06  Daniel Gutson  <dgutson@codesourcery.com>
 680
 681         * arm-dis.c (print_insn): Fixed search for next symbol and data
 682         dumping condition, and the initial mapping symbol state.
 683
 684 2010-01-05  Doug Evans  <dje@sebabeach.org>
 685
 686         * cgen-ibld.in: #include "cgen/basic-modes.h".
 687         * fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c,
 688         * lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c,
 689         * mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c,
 690         * xstormy16-ibld.c: Regenerate.
 691
 692 2010-01-04  Nick Clifton  <nickc@redhat.com>
 693
 694         PR 11123
 695         * arm-dis.c (print_insn_coprocessor): Initialise value.
 696
 697 2010-01-04  Edmar Wienskoski  <edmar@freescale.com>
 698
 699         * ppc-dis.c (ppc_opts): Add entry for "e500mc64".
 700
 701 2010-01-02  Doug Evans  <dje@sebabeach.org>
 702
 703         * cgen-asm.in: Update copyright year.
 704         * cgen-dis.in: Update copyright year.
 705         * cgen-ibld.in: Update copyright year.
 706         * fr30-asm.c, * fr30-desc.c, * fr30-desc.h, * fr30-dis.c,
 707         * fr30-ibld.c, * fr30-opc.c, * fr30-opc.h, * frv-asm.c, * frv-desc.c,
 708         * frv-desc.h, * frv-dis.c, * frv-ibld.c, * frv-opc.c, * frv-opc.h,
 709         * ip2k-asm.c, * ip2k-desc.c, * ip2k-desc.h, * ip2k-dis.c,
 710         * ip2k-ibld.c, * ip2k-opc.c, * ip2k-opc.h, * iq2000-asm.c,
 711         * iq2000-desc.c, * iq2000-desc.h, * iq2000-dis.c, * iq2000-ibld.c,
 712         * iq2000-opc.c, * iq2000-opc.h, * lm32-asm.c, * lm32-desc.c,
 713         * lm32-desc.h, * lm32-dis.c, * lm32-ibld.c, * lm32-opc.c, * lm32-opc.h,
 714         * lm32-opinst.c, * m32c-asm.c, * m32c-desc.c, * m32c-desc.h,
 715         * m32c-dis.c, * m32c-ibld.c, * m32c-opc.c, * m32c-opc.h, * m32r-asm.c,
 716         * m32r-desc.c, * m32r-desc.h, * m32r-dis.c, * m32r-ibld.c,
 717         * m32r-opc.c, * m32r-opc.h, * m32r-opinst.c, * mep-asm.c, * mep-desc.c,
 718         * mep-desc.h, * mep-dis.c, * mep-ibld.c, * mep-opc.c, * mep-opc.h,
 719         * mt-asm.c, * mt-desc.c, * mt-desc.h, * mt-dis.c, * mt-ibld.c,
 720         * mt-opc.c, * mt-opc.h, * openrisc-asm.c, * openrisc-desc.c,
 721         * openrisc-desc.h, * openrisc-dis.c, * openrisc-ibld.c,
 722         * openrisc-opc.c, * openrisc-opc.h, * xc16x-asm.c, * xc16x-desc.c,
 723         * xc16x-desc.h, * xc16x-dis.c, * xc16x-ibld.c, * xc16x-opc.c,
 724         * xc16x-opc.h, * xstormy16-asm.c, * xstormy16-desc.c,
 725         * xstormy16-desc.h, * xstormy16-dis.c, * xstormy16-ibld.c,
 726         * xstormy16-opc.c, * xstormy16-opc.h: Regenerate.
 727
 728 For older changes see ChangeLog-2009
 729 \f
 730 Local Variables:
 731 mode: change-log
 732 left-margin: 8
 733 fill-column: 74
 734 version-control: never
 735 End: