opcodes/ChangeLog

   1 2016-12-12  Yao Qi  <yao.qi@linaro.org>
   2
   3         * rx-dis.c: Include <setjmp.h>
   4         (struct private): New.
   5         (rx_get_byte): Check return value of read_memory_func, and
   6         call memory_error_func and OPCODES_SIGLONGJMP on error.
   7         (print_insn_rx): Call OPCODES_SIGSETJMP.
   8
   9 2016-12-12  Yao Qi  <yao.qi@linaro.org>
  10
  11         * rl78-dis.c: Include <setjmp.h>.
  12         (struct private): New.
  13         (rl78_get_byte): Check return value of read_memory_func, and
  14         call memory_error_func and OPCODES_SIGLONGJMP on error.
  15         (print_insn_rl78_common): Call OPCODES_SIGJMP.
  16
  17 2016-12-09  Maciej W. Rozycki  <macro@imgtec.com>
  18
  19         * mips16-opc.c (decode_mips16_operand) <'>'>: Remove cases.
  20
  21 2016-12-09  Maciej W. Rozycki  <macro@imgtec.com>
  22
  23         * mips16-opc.c (decode_mips16_operand) <'e'>: Use HINT rather
  24         than UINT.
  25
  26 2016-12-09  Maciej W. Rozycki  <macro@imgtec.com>
  27
  28         * mips-dis.c (print_insn_mips16): Use a tab rather than a space
  29         to separate `extend' and its uninterpreted argument output.
  30         Separate hexadecimal halves of undecoded extended instructions
  31         output.
  32
  33 2016-12-08  Maciej W. Rozycki  <macro@imgtec.com>
  34
  35         * mips-dis.c (print_mips16_insn_arg): Remove extraneous
  36         indentation space across.
  37
  38 2016-12-08  Maciej W. Rozycki  <macro@imgtec.com>
  39
  40         * mips-dis.c (print_mips16_insn_arg): Avoid delay-slot
  41         adjustment for PC-relative operations following MIPS16e compact
  42         jumps or undefined RR/J(AL)R(C) encodings.
  43
  44 2016-12-08  Maciej W. Rozycki  <macro@imgtec.com>
  45
  46         * aarch64-asm.c (aarch64_ins_reglane): Rename `index' local
  47         variable to `reglane_index'.
  48
  49 2016-12-08  Luis Machado  <lgustavo@codesourcery.com>
  50
  51         * ppc-dis.c (get_powerpc_dialect): Check NULL info->section.
  52
  53 2016-12-07  Maciej W. Rozycki  <macro@imgtec.com>
  54
  55         * mips-dis.c (print_mips16_insn_arg): Fix comment typo.
  56
  57 2016-12-07  Maciej W. Rozycki  <macro@imgtec.com>
  58
  59         * mips16-opc.c (mips16_opcodes): Update comment naming structure
  60         members.
  61
  62 2016-12-07  Maciej W. Rozycki  <macro@imgtec.com>
  63
  64         * mips-dis.c (print_mips_disassembler_options): Reformat output.
  65
  66 2016-12-05  Szabolcs Nagy  <szabolcs.nagy@arm.com>
  67
  68         * arm-dis.c (coprocessor_opcodes): Add vcmla and vcadd.
  69         (print_insn_coprocessor): Add 'V' format for neon D or Q regs.
  70
  71 2016-12-05  Szabolcs Nagy  <szabolcs.nagy@arm.com>
  72
  73         * arm-dis.c (coprocessor_opcodes): Add vjcvt.
  74
  75 2016-12-01  Nick Clifton  <nickc@redhat.com>
  76
  77         PR binutils/20893
  78         * i386-dis.c (OP_VEX): Replace call to abort with a append of bad
  79         opcode designator.
  80
  81 2016-11-29  Claudiu Zissulescu  <claziss@synopsys.com>
  82
  83         * arc-opc.c (insert_ra_chk): New function.
  84         (insert_rb_chk): Likewise.
  85         (insert_rad): Update text error message.
  86         (insert_rcd): Likewise.
  87         (insert_rhv2): Likewise.
  88         (insert_r0): Likewise.
  89         (insert_r1): Likewise.
  90         (insert_r2): Likewise.
  91         (insert_r3): Likewise.
  92         (insert_sp): Likewise.
  93         (insert_gp): Likewise.
  94         (insert_pcl): Likewise.
  95         (insert_blink): Likewise.
  96         (insert_ilink1): Likewise.
  97         (insert_ilink2): Likewise.
  98         (insert_ras): Likewise.
  99         (insert_rbs): Likewise.
 100         (insert_rcs): Likewise.
 101         (insert_simm3s): Likewise.
 102         (insert_rrange): Likewise.
 103         (insert_fpel): Likewise.
 104         (insert_blinkel): Likewise.
 105         (insert_pcel): Likewise.
 106         (insert_nps_3bit_dst): Likewise.
 107         (insert_nps_3bit_dst_short): Likewise.
 108         (insert_nps_3bit_src2_short): Likewise.
 109         (insert_nps_bitop_size_2b): Likewise.
 110         (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Likewise.
 111         (RA_CHK): Define.
 112         (RB): Adjust.
 113         (RB_CHK): Define.
 114         (RC): Adjust.
 115         * arc-dis.c (print_insn_arc): Add LOAD and STORE class.
 116         * arc-tbl.h (div, divu): All instructions are DIVREM class.
 117         Change first insn argument to check for LP_COUNT usage.
 118         (rem): Likewise.
 119         (ld, ldd): All instructions are LOAD class.  Change first insn
 120         argument to check for LP_COUNT usage.
 121         (st, std): All instructions are STORE class.
 122         (mac, mpy, dmac, mul, dmpy): All instructions are MPY class.
 123         Change first insn argument to check for LP_COUNT usage.
 124         (mov): All instructions are MOVE class.  Change first insn
 125         argument to check for LP_COUNT usage.
 126
 127 2016-11-29  Claudiu Zissulescu  <claziss@synopsys.com>
 128
 129         * arc-dis.c (is_compatible_p): Remove function.
 130         (skip_this_opcode): Don't add any decoding class to decode list.
 131         Remove warning.
 132         (find_format_from_table): Go through all opcodes, and warn if we
 133         use a guessed mnemonic.
 134
 135 2016-11-28  Ramiro Polla  <ramiro@hex-rays.com>
 136             Amit Pawar  <amit.pawar@amd.com>
 137
 138         PR binutils/20637
 139         * i386-dis.c (get_valid_dis386): Ignore REX_B for 32-bit XOP
 140         instructions.
 141
 142 2016-11-22  Ambrogino Modigliani  <ambrogino.modigliani@gmail.com>
 143
 144         * configure: Regenerate.
 145
 146 2016-11-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
 147
 148         * sparc-opc.c (HWS_V8): Definition moved from
 149         gas/config/tc-sparc.c.
 150         (HWS_V9): Likewise.
 151         (HWS_VA): Likewise.
 152         (HWS_VB): Likewise.
 153         (HWS_VC): Likewise.
 154         (HWS_VD): Likewise.
 155         (HWS_VE): Likewise.
 156         (HWS_VV): Likewise.
 157         (HWS_VM): Likewise.
 158         (HWS2_VM): Likewise.
 159         (sparc_opcode_archs): Initialize hwcaps and hwcaps2 fields of
 160         existing entries.
 161
 162 2016-11-22  Claudiu Zissulescu  <claziss@synopsys.com>
 163
 164         * arc-tbl.h: Reorder conditional flags with delay flags for 'b'
 165         instructions.
 166
 167 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 168
 169         * aarch64-tbl.h (QL_V3SAMEHSD_ROT, QL_ELEMENT_ROT): Define.
 170         (aarch64_feature_simd_v8_3, SIMD_V8_3): Define.
 171         (aarch64_opcode_table): Add fcmla and fcadd.
 172         (AARCH64_OPERANDS): Add IMM_ROT{1,2,3}.
 173         * aarch64-asm.h (aarch64_ins_imm_rotate): Declare.
 174         * aarch64-asm.c (aarch64_ins_imm_rotate): Define.
 175         * aarch64-dis.h (aarch64_ext_imm_rotate): Declare.
 176         * aarch64-dis.c (aarch64_ext_imm_rotate): Define.
 177         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_rotate{1,2,3}.
 178         * aarch64-opc.c (fields): Add FLD_rotate{1,2,3}.
 179         (operand_general_constraint_met_p): Rotate and index range check.
 180         (aarch64_print_operand): Handle rotate operand.
 181         * aarch64-asm-2.c: Regenerate.
 182         * aarch64-dis-2.c: Likewise.
 183         * aarch64-opc-2.c: Likewise.
 184
 185 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 186
 187         * aarch64-tbl.h (arch64_opcode_table): Add ldaprb, ldaprh, ldapr.
 188         * aarch64-asm-2.c: Regenerate.
 189         * aarch64-dis-2.c: Regenerate.
 190         * aarch64-opc-2.c: Regenerate.
 191
 192 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 193
 194         * aarch64-tbl.h (arch64_opcode_table): Add fjcvtzs.
 195         (QL_FP2INT_W_D, aarch64_feature_fp_v8_3, FP_V8_3): Define.
 196         * aarch64-asm-2.c: Regenerate.
 197         * aarch64-dis-2.c: Regenerate.
 198         * aarch64-opc-2.c: Regenerate.
 199
 200 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 201
 202         * aarch64-tbl.h (QL_X1NIL): New.
 203         (arch64_opcode_table): Add ldraa, ldrab.
 204         (AARCH64_OPERANDS): Add "ADDR_SIMM10".
 205         * aarch64-asm.h (aarch64_ins_addr_simm10): Declare.
 206         * aarch64-asm.c (aarch64_ins_addr_simm10): Define.
 207         * aarch64-dis.h (aarch64_ext_addr_simm10): Declare.
 208         * aarch64-dis.c (aarch64_ext_addr_simm10): Define.
 209         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_S_simm10.
 210         * aarch64-opc.c (fields): Add data for FLD_S_simm10.
 211         (operand_general_constraint_met_p): Handle AARCH64_OPND_ADDR_SIMM10.
 212         (aarch64_print_operand): Likewise.
 213         * aarch64-asm-2.c: Regenerate.
 214         * aarch64-dis-2.c: Regenerate.
 215         * aarch64-opc-2.c: Regenerate.
 216
 217 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 218
 219         * aarch64-tbl.h (arch64_opcode_table): Add braa, brab, blraa, blrab, braaz,
 220         brabz, blraaz, blrabz, retaa, retab, eretaa, eretab.
 221         * aarch64-asm-2.c: Regenerate.
 222         * aarch64-dis-2.c: Regenerate.
 223         * aarch64-opc-2.c: Regenerate.
 224
 225 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 226
 227         * aarch64-tbl.h (arch64_opcode_table): Add pacga.
 228         (AARCH64_OPERANDS): Add Rm_SP.
 229         * aarch64-opc.c (aarch64_print_operand): Handle AARCH64_OPND_Rm_SP.
 230         * aarch64-asm-2.c: Regenerate.
 231         * aarch64-dis-2.c: Regenerate.
 232         * aarch64-opc-2.c: Regenerate.
 233
 234 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 235
 236         * aarch64-tbl.h (arch64_opcode_table): Add pacia, pacib, pacda, pacdb, autia,
 237         autib, autda, autdb, paciza, pacizb, pacdza, pacdzb, autiza, autizb, autdza,
 238         autdzb, xpaci, xpacd.
 239         * aarch64-asm-2.c: Regenerate.
 240         * aarch64-dis-2.c: Regenerate.
 241         * aarch64-opc-2.c: Regenerate.
 242
 243 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 244
 245         * aarch64-opc.c (aarch64_sys_regs): Add apiakeylo_el1, apiakeyhi_el1,
 246         apibkeylo_el1, apibkeyhi_el1, apdakeylo_el1, apdakeyhi_el1,
 247         apdbkeylo_el1, apdbkeyhi_el1, apgakeylo_el1 and apgakeyhi_el1.
 248         (aarch64_sys_reg_supported_p): Add feature test for new registers.
 249
 250 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 251
 252         * aarch64-tbl.h (aarch64_feature_v8_3, ARMV8_3, V8_3_INSN): New.
 253         (arch64_opcode_table): Add xpaclri, pacia1716, pacib1716, autia1716,
 254         autib1716, paciaz, paciasp, pacibz, pacibsp, autiaz, autiasp, autibz,
 255         autibsp.
 256         * aarch64-asm-2.c: Regenerate.
 257         * aarch64-dis-2.c: Regenerate.
 258
 259 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 260
 261         * aarch64-gen.c (find_alias_opcode): Increase max_num_aliases to 32.
 262
 263 2016-11-09  H.J. Lu  <hongjiu.lu@intel.com>
 264
 265         PR binutils/20799
 266         * i386-dis-evex.h (evex_table): Replace EdqwS with Edqw.
 267         * i386-dis.c (EdqwS): Removed.
 268         (dqw_swap_mode): Likewise.
 269         (intel_operand_size): Don't check dqw_swap_mode.
 270         (OP_E_register): Likewise.
 271         (OP_E_memory): Likewise.
 272         (OP_G): Likewise.
 273         (OP_EX): Likewise.
 274         * i386-opc.tbl: Remove "S" from EVEX vpextrw.
 275         * i386-tbl.h: Regerated.
 276
 277 2016-11-09  H.J. Lu  <hongjiu.lu@intel.com>
 278
 279         * i386-opc.tbl: Merge AVX512F vmovq.
 280         * i386-tbl.h: Regerated.
 281
 282 2016-11-08  H.J. Lu  <hongjiu.lu@intel.com>
 283
 284         PR binutils/20701
 285         * i386-dis.c (THREE_BYTE_0F7A): Removed.
 286         (dis386_twobyte): Don't use THREE_BYTE_0F7A.
 287         (three_byte_table): Remove THREE_BYTE_0F7A.
 288
 289 2016-11-07  H.J. Lu  <hongjiu.lu@intel.com>
 290
 291         PR binutils/20775
 292         * i386-dis.c (FGRPd9_2): Replace 0 with 1.
 293         (FGRPd9_4): Replace 1 with 2.
 294         (FGRPd9_5): Replace 2 with 3.
 295         (FGRPd9_6): Replace 3 with 4.
 296         (FGRPd9_7): Replace 4 with 5.
 297         (FGRPda_5): Replace 5 with 6.
 298         (FGRPdb_4): Replace 6 with 7.
 299         (FGRPde_3): Replace 7 with 8.
 300         (FGRPdf_4): Replace 8 with 9.
 301         (fgrps): Add an entry for Bad_Opcode.
 302
 303 2016-11-04  Andrew Burgess  <andrew.burgess@embecosm.com>
 304
 305         * arc-opc.c (arc_flag_operands): Add F_DI14.
 306         (arc_flag_classes): Add C_DI14.
 307         * arc-nps400-tbl.h: Add new exc instructions.
 308
 309 2016-11-03  Graham Markall  <graham.markall@embecosm.com>
 310
 311         * arc-dis.c (arc_insn_length): Return length 8 for instructions with
 312         major opcode 0xa.
 313         * arc-nps-400-tbl.h: Add dcmac instruction.
 314         * arc-opc.c (arc_operands): Added operands for dcmac instruction.
 315         (insert_nps_rbdouble_64): Added.
 316         (extract_nps_rbdouble_64): Added.
 317         (insert_nps_proto_size): Added.
 318         (extract_nps_proto_size): Added.
 319
 320 2016-11-03  Andrew Burgess  <andrew.burgess@embecosm.com>
 321
 322         * arc-dis.c (struct arc_operand_iterator): Remove all fields
 323         relating to long instruction processing, add new limm field.
 324         (OPCODE): Rename to...
 325         (OPCODE_32BIT_INSN): ...this.
 326         (OPCODE_AC): Delete.
 327         (skip_this_opcode): Handle different instruction lengths, update
 328         macro name.
 329         (special_flag_p): Update parameter type.
 330         (find_format_from_table): Update for more instruction lengths.
 331         (find_format_long_instructions): Delete.
 332         (find_format): Update for more instruction lengths.
 333         (arc_insn_length): Likewise.
 334         (extract_operand_value): Update for more instruction lengths.
 335         (operand_iterator_next): Remove code relating to long
 336         instructions.
 337         (arc_opcode_to_insn_type): New function.
 338         (print_insn_arc):Update for more instructions lengths.
 339         * arc-ext.c (extInstruction_t): Change argument type.
 340         * arc-ext.h (extInstruction_t): Change argument type.
 341         * arc-fxi.h: Change type unsigned to unsigned long long
 342         extensively throughout.
 343         * arc-nps400-tbl.h: Add long instructions taken from
 344         arc_long_opcodes table in arc-opc.c.
 345         * arc-opc.c: Update parameter types on insert/extract handlers.
 346         (arc_long_opcodes): Delete.
 347         (arc_num_long_opcodes): Delete.
 348         (arc_opcode_len): Update for more instruction lengths.
 349
 350 2016-11-03  Graham Markall  <graham.markall@embecosm.com>
 351
 352         * arc-dis.c (print_insn_arc): Swap highbyte and lowbyte.
 353
 354 2016-11-03  Graham Markall  <graham.markall@embecosm.com>
 355
 356         * arc-dis.c (find_format_from_table): Replace use of ARC_SHORT
 357         with arc_opcode_len.
 358         (find_format_long_instructions): Likewise.
 359         * arc-opc.c (arc_opcode_len): New function.
 360
 361 2016-11-03  Andrew Burgess  <andrew.burgess@embecosm.com>
 362
 363         * arc-nps400-tbl.h: Fix some instruction masks.
 364
 365 2016-11-03  H.J. Lu  <hongjiu.lu@intel.com>
 366
 367         * i386-dis.c (REG_82): Removed.
 368         (X86_64_82_REG_0): Likewise.
 369         (X86_64_82_REG_1): Likewise.
 370         (X86_64_82_REG_2): Likewise.
 371         (X86_64_82_REG_3): Likewise.
 372         (X86_64_82_REG_4): Likewise.
 373         (X86_64_82_REG_5): Likewise.
 374         (X86_64_82_REG_6): Likewise.
 375         (X86_64_82_REG_7): Likewise.
 376         (X86_64_82): New.
 377         (dis386): Use X86_64_82 instead of REG_82.
 378         (reg_table): Remove REG_82.
 379         (x86_64_table): Add X86_64_82.  Remove X86_64_82_REG_0,
 380         X86_64_82_REG_1, X86_64_82_REG_2, X86_64_82_REG_3,
 381         X86_64_82_REG_4, X86_64_82_REG_5, X86_64_82_REG_6 and
 382         X86_64_82_REG_7.
 383
 384 2016-11-03  H.J. Lu  <hongjiu.lu@intel.com>
 385
 386         PR binutils/20754
 387         * i386-dis.c (REG_82): New.
 388         (X86_64_82_REG_0): Likewise.
 389         (X86_64_82_REG_1): Likewise.
 390         (X86_64_82_REG_2): Likewise.
 391         (X86_64_82_REG_3): Likewise.
 392         (X86_64_82_REG_4): Likewise.
 393         (X86_64_82_REG_5): Likewise.
 394         (X86_64_82_REG_6): Likewise.
 395         (X86_64_82_REG_7): Likewise.
 396         (dis386): Use REG_82.
 397         (reg_table): Add REG_82.
 398         (x86_64_table): Add X86_64_82_REG_0, X86_64_82_REG_1,
 399         X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4,
 400         X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7.
 401
 402 2016-11-03  H.J. Lu  <hongjiu.lu@intel.com>
 403
 404         * i386-dis.c (REG_82): Renamed to ...
 405         (REG_83): This.
 406         (dis386): Updated.
 407         (reg_table): Likewise.
 408
 409 2016-11-02  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 410
 411         * i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853.
 412         * i386-dis-evex.h (evex_table): Updated.
 413         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS,
 414         CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 415         (cpu_flags): Add CpuAVX512_4VNNIW.
 416         * i386-opc.h (enum): (AVX512_4VNNIW): New.
 417         (i386_cpu_flags): Add cpuavx512_4vnniw.
 418         * i386-opc.tbl: Add Intel AVX512_4VNNIW instructions.
 419         * i386-init.h: Regenerate.
 420         * i386-tbl.h: Ditto.
 421
 422 2016-11-02  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 423
 424         * i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,
 425         PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.
 426         * i386-dis-evex.h (evex_table): Updated.
 427         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,
 428         CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 429         (cpu_flags): Add CpuAVX512_4FMAPS.
 430         (opcode_modifiers): Add ImplicitQuadGroup modifier.
 431         * i386-opc.h (AVX512_4FMAP): New.
 432         (i386_cpu_flags): Add cpuavx512_4fmaps.
 433         (ImplicitQuadGroup): New.
 434         (i386_opcode_modifier): Add implicitquadgroup.
 435         * i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.
 436         * i386-init.h: Regenerate.
 437         * i386-tbl.h: Ditto.
 438
 439 2016-11-01  Palmer Dabbelt  <palmer@dabbelt.com>
 440             Andrew Waterman <andrew@sifive.com>
 441
 442         Add support for RISC-V architecture.
 443         * configure.ac: Add entry for bfd_riscv_arch.
 444         * configure: Regenerate.
 445         * disassemble.c (disassembler): Add support for riscv.
 446         (disassembler_usage): Likewise.
 447         * riscv-dis.c: New file.
 448         * riscv-opc.c: New file.
 449
 450 2016-10-21  H.J. Lu  <hongjiu.lu@intel.com>
 451
 452         * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
 453         (prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
 454         (rm_table): Update the RM_0FAE_REG_7 entry.
 455         * i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
 456         (cpu_flags): Remove CpuPCOMMIT.
 457         * i386-opc.h (CpuPCOMMIT): Removed.
 458         (i386_cpu_flags): Remove cpupcommit.
 459         * i386-opc.tbl: Remove pcommit.
 460         * i386-init.h: Regenerated.
 461         * i386-tbl.h: Likewise.
 462
 463 2016-10-20  H.J. Lu  <hongjiu.lu@intel.com>
 464
 465         PR binutis/20705
 466         * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
 467         the highest bit in VEX.vvvv for the 3-byte VEX prefix in
 468         32-bit mode.  Don't check vex.register_specifier in 32-bit
 469         mode.
 470         (OP_VEX): Check for invalid mask registers.
 471
 472 2016-10-18  H.J. Lu  <hongjiu.lu@intel.com>
 473
 474         PR binutis/20699
 475         * i386-dis.c (OP_E_memory): Check addr32flag in stead of
 476         sizeflag.
 477
 478 2016-10-18  H.J. Lu  <hongjiu.lu@intel.com>
 479
 480         PR binutis/20704
 481         * i386-dis.c (three_byte_table): Remove the remaining SSE5 support.
 482
 483 2016-10-18  Maciej W. Rozycki  <macro@imgtec.com>
 484
 485         * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'
 486         local variable to `index_regno'.
 487
 488 2016-10-17  Cupertino Miranda  <cmiranda@synopsys.com>
 489
 490         * arc-tbl.h: Removed any "inv.+" instructions from the table.
 491
 492 2016-10-14  Claudiu Zissulescu  <claziss@synopsys.com>
 493
 494         * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
 495         usage on ISA basis.
 496
 497 2016-10-11  Jiong Wang  <jiong.wang@arm.com>
 498
 499         PR target/20666
 500         * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
 501
 502 2016-10-07  Jiong Wang  <jiong.wang@arm.com>
 503
 504         PR target/20667
 505         * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
 506         available.
 507
 508 2016-10-07  Alan Modra  <amodra@gmail.com>
 509
 510         * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
 511
 512 2016-10-06  Alan Modra  <amodra@gmail.com>
 513
 514         * aarch64-opc.c: Spell fall through comments consistently.
 515         * i386-dis.c: Likewise.
 516         * aarch64-dis.c: Add missing fall through comments.
 517         * aarch64-opc.c: Likewise.
 518         * arc-dis.c: Likewise.
 519         * arm-dis.c: Likewise.
 520         * i386-dis.c: Likewise.
 521         * m68k-dis.c: Likewise.
 522         * mep-asm.c: Likewise.
 523         * ns32k-dis.c: Likewise.
 524         * sh-dis.c: Likewise.
 525         * tic4x-dis.c: Likewise.
 526         * tic6x-dis.c: Likewise.
 527         * vax-dis.c: Likewise.
 528
 529 2016-10-06  Alan Modra  <amodra@gmail.com>
 530
 531         * arc-ext.c (create_map): Add missing break.
 532         * msp430-decode.opc (encode_as): Likewise.
 533         * msp430-decode.c: Regenerate.
 534
 535 2016-10-06  Alan Modra  <amodra@gmail.com>
 536
 537         * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
 538         * crx-dis.c (print_insn_crx): Likewise.
 539
 540 2016-09-30  H.J. Lu  <hongjiu.lu@intel.com>
 541
 542         PR binutils/20657
 543         * i386-dis.c (putop): Don't assign alt twice.
 544
 545 2016-09-29  Jiong Wang  <jiong.wang@arm.com>
 546
 547         PR target/20553
 548         * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
 549
 550 2016-09-29  Alan Modra  <amodra@gmail.com>
 551
 552         * ppc-opc.c (L): Make compulsory.
 553         (LOPT): New, optional form of L.
 554         (HTM_R): Define as LOPT.
 555         (L0, L1): Delete.
 556         (L32OPT): New, optional for 32-bit L.
 557         (L2OPT): New, 2-bit L for dcbf.
 558         (SVC_LEC): Update.
 559         (L2): Define.
 560         (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
 561         (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
 562         <dcbf>: Use L2OPT.
 563         <tlbiel, tlbie>: Use LOPT.
 564         <wclr, wclrall>: Use L2.
 565
 566 2016-09-26  Vlad Zakharov  <vzakhar@synopsys.com>
 567
 568         * Makefile.in: Regenerate.
 569         * configure: Likewise.
 570
 571 2016-09-26  Claudiu Zissulescu  <claziss@synopsys.com>
 572
 573         * arc-ext-tbl.h (EXTINSN2OPF): Define.
 574         (EXTINSN2OP): Use EXTINSN2OPF.
 575         (bspeekm, bspop, modapp): New extension instructions.
 576         * arc-opc.c (F_DNZ_ND): Define.
 577         (F_DNZ_D): Likewise.
 578         (F_SIZEB1): Changed.
 579         (C_DNZ_D): Define.
 580         (C_HARD): Changed.
 581         * arc-tbl.h (dbnz): New instruction.
 582         (prealloc): Allow it for ARC EM.
 583         (xbfu): Likewise.
 584
 585 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 586
 587         * aarch64-opc.c (print_immediate_offset_address): Print spaces
 588         after commas in addresses.
 589         (aarch64_print_operand): Likewise.
 590
 591 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 592
 593         * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
 594         rather than "should be" or "expected to be" in error messages.
 595
 596 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 597
 598         * aarch64-dis.c (remove_dot_suffix): New function, split out from...
 599         (print_mnemonic_name): ...here.
 600         (print_comment): New function.
 601         (print_aarch64_insn): Call it.
 602         * aarch64-opc.c (aarch64_conds): Add SVE names.
 603         (aarch64_print_operand): Print alternative condition names in
 604         a comment.
 605
 606 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 607
 608         * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
 609         (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
 610         (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
 611         (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
 612         (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
 613         (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
 614         (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
 615         (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
 616         (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
 617         (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
 618         (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
 619         (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
 620         (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
 621         (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
 622         (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
 623         (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
 624         (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
 625         (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
 626         (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
 627         (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
 628         (OP_SVE_XWU, OP_SVE_XXU): New macros.
 629         (aarch64_feature_sve): New variable.
 630         (SVE): New macro.
 631         (_SVE_INSN): Likewise.
 632         (aarch64_opcode_table): Add SVE instructions.
 633         * aarch64-opc.h (extract_fields): Declare.
 634         * aarch64-opc-2.c: Regenerate.
 635         * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
 636         * aarch64-asm-2.c: Regenerate.
 637         * aarch64-dis.c (extract_fields): Make global.
 638         (do_misc_decoding): Handle the new SVE aarch64_ops.
 639         * aarch64-dis-2.c: Regenerate.
 640
 641 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 642
 643         * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
 644         (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
 645         aarch64_field_kinds.
 646         * aarch64-opc.c (fields): Add corresponding entries.
 647         * aarch64-asm.c (aarch64_get_variant): New function.
 648         (aarch64_encode_variant_using_iclass): Likewise.
 649         (aarch64_opcode_encode): Call it.
 650         * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
 651         (aarch64_opcode_decode): Call it.
 652
 653 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 654
 655         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
 656         and FP register operands.
 657         * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
 658         (FLD_SVE_Vn): New aarch64_field_kinds.
 659         * aarch64-opc.c (fields): Add corresponding entries.
 660         (aarch64_print_operand): Handle the new SVE core and FP register
 661         operands.
 662         * aarch64-opc-2.c: Regenerate.
 663         * aarch64-asm-2.c: Likewise.
 664         * aarch64-dis-2.c: Likewise.
 665
 666 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 667
 668         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
 669         immediate operands.
 670         * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
 671         * aarch64-opc.c (fields): Add corresponding entry.
 672         (operand_general_constraint_met_p): Handle the new SVE FP immediate
 673         operands.
 674         (aarch64_print_operand): Likewise.
 675         * aarch64-opc-2.c: Regenerate.
 676         * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
 677         (ins_sve_float_zero_one): New inserters.
 678         * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
 679         (aarch64_ins_sve_float_half_two): Likewise.
 680         (aarch64_ins_sve_float_zero_one): Likewise.
 681         * aarch64-asm-2.c: Regenerate.
 682         * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
 683         (ext_sve_float_zero_one): New extractors.
 684         * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
 685         (aarch64_ext_sve_float_half_two): Likewise.
 686         (aarch64_ext_sve_float_zero_one): Likewise.
 687         * aarch64-dis-2.c: Regenerate.
 688
 689 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 690
 691         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
 692         integer immediate operands.
 693         * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
 694         (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
 695         (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
 696         * aarch64-opc.c (fields): Add corresponding entries.
 697         (operand_general_constraint_met_p): Handle the new SVE integer
 698         immediate operands.
 699         (aarch64_print_operand): Likewise.
 700         (aarch64_sve_dupm_mov_immediate_p): New function.
 701         * aarch64-opc-2.c: Regenerate.
 702         * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
 703         (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
 704         * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
 705         (aarch64_ins_limm): ...here.
 706         (aarch64_ins_inv_limm): New function.
 707         (aarch64_ins_sve_aimm): Likewise.
 708         (aarch64_ins_sve_asimm): Likewise.
 709         (aarch64_ins_sve_limm_mov): Likewise.
 710         (aarch64_ins_sve_shlimm): Likewise.
 711         (aarch64_ins_sve_shrimm): Likewise.
 712         * aarch64-asm-2.c: Regenerate.
 713         * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
 714         (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
 715         * aarch64-dis.c (decode_limm): New function, split out from...
 716         (aarch64_ext_limm): ...here.
 717         (aarch64_ext_inv_limm): New function.
 718         (decode_sve_aimm): Likewise.
 719         (aarch64_ext_sve_aimm): Likewise.
 720         (aarch64_ext_sve_asimm): Likewise.
 721         (aarch64_ext_sve_limm_mov): Likewise.
 722         (aarch64_top_bit): Likewise.
 723         (aarch64_ext_sve_shlimm): Likewise.
 724         (aarch64_ext_sve_shrimm): Likewise.
 725         * aarch64-dis-2.c: Regenerate.
 726
 727 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 728
 729         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
 730         operands.
 731         * aarch64-opc.c (aarch64_operand_modifiers): Initialize
 732         the AARCH64_MOD_MUL_VL entry.
 733         (value_aligned_p): Cope with non-power-of-two alignments.
 734         (operand_general_constraint_met_p): Handle the new MUL VL addresses.
 735         (print_immediate_offset_address): Likewise.
 736         (aarch64_print_operand): Likewise.
 737         * aarch64-opc-2.c: Regenerate.
 738         * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
 739         (ins_sve_addr_ri_s9xvl): New inserters.
 740         * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
 741         (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
 742         (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
 743         * aarch64-asm-2.c: Regenerate.
 744         * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
 745         (ext_sve_addr_ri_s9xvl): New extractors.
 746         * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
 747         (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
 748         (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
 749         (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
 750         * aarch64-dis-2.c: Regenerate.
 751
 752 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 753
 754         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
 755         address operands.
 756         * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
 757         (FLD_SVE_xs_22): New aarch64_field_kinds.
 758         (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
 759         (get_operand_specific_data): New function.
 760         * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
 761         FLD_SVE_xs_14 and FLD_SVE_xs_22.
 762         (operand_general_constraint_met_p): Handle the new SVE address
 763         operands.
 764         (sve_reg): New array.
 765         (get_addr_sve_reg_name): New function.
 766         (aarch64_print_operand): Handle the new SVE address operands.
 767         * aarch64-opc-2.c: Regenerate.
 768         * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
 769         (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
 770         (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
 771         * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
 772         (aarch64_ins_sve_addr_rr_lsl): Likewise.
 773         (aarch64_ins_sve_addr_rz_xtw): Likewise.
 774         (aarch64_ins_sve_addr_zi_u5): Likewise.
 775         (aarch64_ins_sve_addr_zz): Likewise.
 776         (aarch64_ins_sve_addr_zz_lsl): Likewise.
 777         (aarch64_ins_sve_addr_zz_sxtw): Likewise.
 778         (aarch64_ins_sve_addr_zz_uxtw): Likewise.
 779         * aarch64-asm-2.c: Regenerate.
 780         * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
 781         (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
 782         (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
 783         * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
 784         (aarch64_ext_sve_addr_ri_u6): Likewise.
 785         (aarch64_ext_sve_addr_rr_lsl): Likewise.
 786         (aarch64_ext_sve_addr_rz_xtw): Likewise.
 787         (aarch64_ext_sve_addr_zi_u5): Likewise.
 788         (aarch64_ext_sve_addr_zz): Likewise.
 789         (aarch64_ext_sve_addr_zz_lsl): Likewise.
 790         (aarch64_ext_sve_addr_zz_sxtw): Likewise.
 791         (aarch64_ext_sve_addr_zz_uxtw): Likewise.
 792         * aarch64-dis-2.c: Regenerate.
 793
 794 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 795
 796         * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
 797         AARCH64_OPND_SVE_PATTERN_SCALED.
 798         * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
 799         * aarch64-opc.c (fields): Add a corresponding entry.
 800         (set_multiplier_out_of_range_error): New function.
 801         (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
 802         (operand_general_constraint_met_p): Handle
 803         AARCH64_OPND_SVE_PATTERN_SCALED.
 804         (print_register_offset_address): Use PRIi64 to print the
 805         shift amount.
 806         (aarch64_print_operand): Likewise.  Handle
 807         AARCH64_OPND_SVE_PATTERN_SCALED.
 808         * aarch64-opc-2.c: Regenerate.
 809         * aarch64-asm.h (ins_sve_scale): New inserter.
 810         * aarch64-asm.c (aarch64_ins_sve_scale): New function.
 811         * aarch64-asm-2.c: Regenerate.
 812         * aarch64-dis.h (ext_sve_scale): New inserter.
 813         * aarch64-dis.c (aarch64_ext_sve_scale): New function.
 814         * aarch64-dis-2.c: Regenerate.
 815
 816 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 817
 818         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
 819         AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
 820         * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
 821         (FLD_SVE_prfop): Likewise.
 822         * aarch64-opc.c: Include libiberty.h.
 823         (aarch64_sve_pattern_array): New variable.
 824         (aarch64_sve_prfop_array): Likewise.
 825         (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
 826         (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
 827         AARCH64_OPND_SVE_PRFOP.
 828         * aarch64-asm-2.c: Regenerate.
 829         * aarch64-dis-2.c: Likewise.
 830         * aarch64-opc-2.c: Likewise.
 831
 832 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 833
 834         * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
 835         AARCH64_OPND_QLF_P_[ZM].
 836         (aarch64_print_operand): Print /z and /m where appropriate.
 837
 838 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 839
 840         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
 841         * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
 842         (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
 843         (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
 844         (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
 845         * aarch64-opc.c (fields): Add corresponding entries here.
 846         (operand_general_constraint_met_p): Check that SVE register lists
 847         have the correct length.  Check the ranges of SVE index registers.
 848         Check for cases where p8-p15 are used in 3-bit predicate fields.
 849         (aarch64_print_operand): Handle the new SVE operands.
 850         * aarch64-opc-2.c: Regenerate.
 851         * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
 852         * aarch64-asm.c (aarch64_ins_sve_index): New function.
 853         (aarch64_ins_sve_reglist): Likewise.
 854         * aarch64-asm-2.c: Regenerate.
 855         * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
 856         * aarch64-dis.c (aarch64_ext_sve_index): New function.
 857         (aarch64_ext_sve_reglist): Likewise.
 858         * aarch64-dis-2.c: Regenerate.
 859
 860 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 861
 862         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
 863         (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
 864         (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
 865         * aarch64-opc.c (aarch64_match_operands_constraint): Check for
 866         tied operands.
 867
 868 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 869
 870         * aarch64-opc.c (get_offset_int_reg_name): New function.
 871         (print_immediate_offset_address): Likewise.
 872         (print_register_offset_address): Take the base and offset
 873         registers as parameters.
 874         (aarch64_print_operand): Update caller accordingly.  Use
 875         print_immediate_offset_address.
 876
 877 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 878
 879         * aarch64-opc.c (BANK): New macro.
 880         (R32, R64): Take a register number as argument
 881         (int_reg): Use BANK.
 882
 883 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 884
 885         * aarch64-opc.c (print_register_list): Add a prefix parameter.
 886         (aarch64_print_operand): Update accordingly.
 887
 888 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 889
 890         * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
 891         for FPIMM.
 892         * aarch64-asm.h (ins_fpimm): New inserter.
 893         * aarch64-asm.c (aarch64_ins_fpimm): New function.
 894         * aarch64-asm-2.c: Regenerate.
 895         * aarch64-dis.h (ext_fpimm): New extractor.
 896         * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
 897         (aarch64_ext_fpimm): New function.
 898         * aarch64-dis-2.c: Regenerate.
 899
 900 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 901
 902         * aarch64-asm.c: Include libiberty.h.
 903         (insert_fields): New function.
 904         (aarch64_ins_imm): Use it.
 905         * aarch64-dis.c (extract_fields): New function.
 906         (aarch64_ext_imm): Use it.
 907
 908 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 909
 910         * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
 911         with an esize parameter.
 912         (operand_general_constraint_met_p): Update accordingly.
 913         Fix misindented code.
 914         * aarch64-asm.c (aarch64_ins_limm): Update call to
 915         aarch64_logical_immediate_p.
 916
 917 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 918
 919         * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
 920
 921 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 922
 923         * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
 924
 925 2016-09-15  Claudiu Zissulescu  <claziss@synopsys.com>
 926
 927         * arc-dis.c (find_format): Walk the linked list pointed by einsn.
 928
 929 2016-09-14  Peter Bergner <bergner@vnet.ibm.com>
 930
 931         * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
 932         <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
 933         xor3>: Delete mnemonics.
 934         <cp_abort>: Rename mnemonic from ...
 935         <cpabort>: ...to this.
 936         <setb>: Change to a X form instruction.
 937         <sync>: Change to 1 operand form.
 938         <copy>: Delete mnemonic.
 939         <copy_first>: Rename mnemonic from ...
 940         <copy>: ...to this.
 941         <paste, paste.>: Delete mnemonics.
 942         <paste_last>: Rename mnemonic from ...
 943         <paste.>: ...to this.
 944
 945 2016-09-14  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 946
 947         * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
 948
 949 2016-09-12  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 950
 951         * s390-mkopc.c (main): Support alternate arch strings.
 952
 953 2016-09-12  Patrick Steuer  <steuer@linux.vnet.ibm.com>
 954
 955         * s390-opc.txt: Fix kmctr instruction type.
 956
 957 2016-09-07  H.J. Lu  <hongjiu.lu@intel.com>
 958
 959         * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
 960         * i386-init.h: Regenerated.
 961
 962 2016-08-30  Cupertino Miranda  <cmiranda@synopsys.com>
 963
 964         * opcodes/arc-dis.c (print_insn_arc): Changed.
 965
 966 2016-08-26  Jose E. Marchesi  <jose.marchesi@oracle.com>
 967
 968         * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
 969         camellia_fl.
 970
 971 2016-08-26  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 972
 973         * arm-dis.c (psr_name): Use hex as case labels.  Add detection for
 974         MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
 975         FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
 976
 977 2016-08-24  H.J. Lu  <hongjiu.lu@intel.com>
 978
 979         * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
 980         (PREFIX_MOD_3_0FAE_REG_4): Likewise.
 981         (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
 982         PREFIX_MOD_3_0FAE_REG_4.
 983         (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
 984         PREFIX_MOD_3_0FAE_REG_4.
 985         * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
 986         (cpu_flags): Add CpuPTWRITE.
 987         * i386-opc.h (CpuPTWRITE): New.
 988         (i386_cpu_flags): Add cpuptwrite.
 989         * i386-opc.tbl: Add ptwrite instruction.
 990         * i386-init.h: Regenerated.
 991         * i386-tbl.h: Likewise.
 992
 993 2016-08-24  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 994
 995         * arc-dis.h: Wrap around in extern "C".
 996
 997 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 998
 999         * aarch64-tbl.h (V8_2_INSN): New macro.
1000         (aarch64_opcode_table): Use it.
1001
1002 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
1003
1004         * aarch64-tbl.h (aarch64_opcode_table): Make more use of
1005         CORE_INSN, __FP_INSN and SIMD_INSN.
1006
1007 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
1008
1009         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
1010         (aarch64_opcode_table): Update uses accordingly.
1011
1012 2016-07-25  Andrew Jenner  <andrew@codesourcery.com>
1013         Kwok Cheung Yeung  <kcy@codesourcery.com>
1014
1015         opcodes/
1016         * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
1017         'e_cmplwi' to 'e_cmpli' instead.
1018         (OPVUPRT, OPVUPRT_MASK): Define.
1019         (powerpc_opcodes): Add E200Z4 insns.
1020         (vle_opcodes): Add context save/restore insns.
1021
1022 2016-07-27  Maciej W. Rozycki  <macro@imgtec.com>
1023
1024         * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
1025         "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
1026         "j".
1027
1028 2016-07-27  Graham Markall  <graham.markall@embecosm.com>
1029
1030         * arc-nps400-tbl.h: Change block comments to GNU format.
1031         * arc-dis.c: Add new globals addrtypenames,
1032         addrtypenames_max, and addtypeunknown.
1033         (get_addrtype): New function.
1034         (print_insn_arc): Print colons and address types when
1035         required.
1036         * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
1037         define insert and extract functions for all address types.
1038         (arc_operands): Add operands for colon and all address
1039         types.
1040         * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
1041         * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
1042         insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
1043         * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
1044         * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
1045         insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
1046
1047 2016-07-21  H.J. Lu  <hongjiu.lu@intel.com>
1048
1049         * configure: Regenerated.
1050
1051 2016-07-20  Claudiu Zissulescu  <claziss@synopsys.com>
1052
1053         * arc-dis.c (skipclass): New structure.
1054         (decodelist): New variable.
1055         (is_compatible_p): New function.
1056         (new_element): Likewise.
1057         (skip_class_p): Likewise.
1058         (find_format_from_table): Use skip_class_p function.
1059         (find_format): Decode first the extension instructions.
1060         (print_insn_arc): Select either ARCEM or ARCHS based on elf
1061         e_flags.
1062         (parse_option): New function.
1063         (parse_disassembler_options): Likewise.
1064         (print_arc_disassembler_options): Likewise.
1065         (print_insn_arc): Use parse_disassembler_options function.  Proper
1066         select ARCv2 cpu variant.
1067         * disassemble.c (disassembler_usage): Add ARC disassembler
1068         options.
1069
1070 2016-07-13  Maciej W. Rozycki  <macro@imgtec.com>
1071
1072         * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
1073         annotation from the "nal" entry and reorder it beyond "bltzal".
1074
1075 2016-07-12  Jose E. Marchesi  <jose.marchesi@oracle.com>
1076
1077         * sparc-opc.c (ldtxa): New macro.
1078         (sparc_opcodes): Use the macro defined above to add entries for
1079         the LDTXA instructions.
1080         (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
1081         instruction.
1082
1083 2016-07-07  James Bowman  <james.bowman@ftdichip.com>
1084
1085         * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
1086         and "jmpc".
1087
1088 2016-07-01  Jan Beulich  <jbeulich@suse.com>
1089
1090         * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
1091         (movzb): Adjust to cover all permitted suffixes.
1092         (movzw): New.
1093         * i386-tbl.h: Re-generate.
1094
1095 2016-07-01  Jan Beulich  <jbeulich@suse.com>
1096
1097         * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
1098         (lgdt): Remove Tbyte from non-64-bit variant.
1099         (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
1100         xsaves64, xsavec64): Remove Disp16.
1101         (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
1102         Remove Disp32S from non-64-bit variants. Remove Disp16 from
1103         64-bit variants.
1104         (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
1105         vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
1106         vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
1107         64-bit variants.
1108         * i386-tbl.h: Re-generate.
1109
1110 2016-07-01  Jan Beulich  <jbeulich@suse.com>
1111
1112         * i386-opc.tbl (xlat): Remove RepPrefixOk.
1113         * i386-tbl.h: Re-generate.
1114
1115 2016-06-30  Yao Qi  <yao.qi@linaro.org>
1116
1117         * arm-dis.c (print_insn): Fix typo in comment.
1118
1119 2016-06-28  Richard Sandiford  <richard.sandiford@arm.com>
1120
1121         * aarch64-opc.c (operand_general_constraint_met_p): Check the
1122         range of ldst_elemlist operands.
1123         (print_register_list): Use PRIi64 to print the index.
1124         (aarch64_print_operand): Likewise.
1125
1126 2016-06-25  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1127
1128         * mcore-opc.h: Remove sentinal.
1129         * mcore-dis.c (print_insn_mcore): Adjust.
1130
1131 2016-06-23  Graham Markall  <graham.markall@embecosm.com>
1132
1133         * arc-opc.c: Correct description of availability of NPS400
1134         features.
1135
1136 2016-06-22  Peter Bergner <bergner@vnet.ibm.com>
1137
1138         * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
1139         (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
1140         mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
1141         xor3>: New mnemonics.
1142         <setb>: Change to a VX form instruction.
1143         (insert_sh6): Add support for rldixor.
1144         (extract_sh6): Likewise.
1145
1146 2016-06-22  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1147
1148         * arc-ext.h: Wrap in extern C.
1149
1150 2016-06-21  Graham Markall  <graham.markall@embecosm.com>
1151
1152         * arc-dis.c (arc_insn_length): Add comment on instruction length.
1153         Use same method for determining instruction length on ARC700 and
1154         NPS-400.
1155         (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
1156         * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
1157         with the NPS400 subclass.
1158         * arc-opc.c: Likewise.
1159
1160 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
1161
1162         * sparc-opc.c (rdasr): New macro.
1163         (wrasr): Likewise.
1164         (rdpr): Likewise.
1165         (wrpr): Likewise.
1166         (rdhpr): Likewise.
1167         (wrhpr): Likewise.
1168         (sparc_opcodes): Use the macros above to fix and expand the
1169         definition of read/write instructions from/to
1170         asr/privileged/hyperprivileged instructions.
1171         * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
1172         %hva_mask_nz.  Prefer softint_set and softint_clear over
1173         set_softint and clear_softint.
1174         (print_insn_sparc): Support %ver in Rd.
1175
1176 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
1177
1178         * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
1179         architecture according to the hardware capabilities they require.
1180
1181 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
1182
1183         * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
1184         (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
1185         bfd_mach_sparc_v9{c,d,e,v,m}.
1186         * sparc-opc.c (MASK_V9C): Define.
1187         (MASK_V9D): Likewise.
1188         (MASK_V9E): Likewise.
1189         (MASK_V9V): Likewise.
1190         (MASK_V9M): Likewise.
1191         (v6): Add MASK_V9{C,D,E,V,M}.
1192         (v6notlet): Likewise.
1193         (v7): Likewise.
1194         (v8): Likewise.
1195         (v9): Likewise.
1196         (v9andleon): Likewise.
1197         (v9a): Likewise.
1198         (v9b): Likewise.
1199         (v9c): Define.
1200         (v9d): Likewise.
1201         (v9e): Likewise.
1202         (v9v): Likewise.
1203         (v9m): Likewise.
1204         (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
1205
1206 2016-06-15  Nick Clifton  <nickc@redhat.com>
1207
1208         * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
1209         constants to match expected behaviour.
1210         (nds32_parse_opcode): Likewise.  Also for whitespace.
1211
1212 2016-06-15  Andrew Burgess  <andrew.burgess@embecosm.com>
1213
1214         * arc-opc.c (extract_rhv1): Extract value from insn.
1215
1216 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
1217
1218         * arc-nps400-tbl.h: Add ldbit instruction.
1219         * arc-opc.c: Add flag classes required for ldbit.
1220
1221 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
1222
1223         * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
1224         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1225         support the above instructions.
1226
1227 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
1228
1229         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
1230         imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
1231         csma, cbba, zncv, and hofs.
1232         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1233         support the above instructions.
1234
1235 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1236
1237         * arc-nps400-tbl.h: Add andab and orab instructions.
1238
1239 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1240
1241         * arc-nps400-tbl.h: Add addl-like instructions.
1242
1243 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1244
1245         * arc-nps400-tbl.h: Add mxb and imxb instructions.
1246
1247 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1248
1249         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
1250         instructions.
1251
1252 2016-06-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
1253
1254         * s390-dis.c (option_use_insn_len_bits_p): New file scope
1255         variable.
1256         (init_disasm): Handle new command line option "insnlength".
1257         (print_s390_disassembler_options): Mention new option in help
1258         output.
1259         (print_insn_s390): Use the encoded insn length when dumping
1260         unknown instructions.
1261
1262 2016-06-03  Pitchumani Sivanupandi  <pitchumani.s@atmel.com>
1263
1264         * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
1265          to the address and set as symbol address for LDS/ STS immediate operands.
1266
1267 2016-06-07  Alan Modra  <amodra@gmail.com>
1268
1269         * ppc-dis.c (ppc_opts): Delete extraneous parentheses.  Default
1270         cpu for "vle" to e500.
1271         * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
1272         (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
1273         (PPCNONE): Delete, substitute throughout.
1274         (powerpc_opcodes): Remove PPCVLE from "flags".  Add to "deprecated"
1275         except for major opcode 4 and 31.
1276         (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
1277
1278 2016-06-07  Matthew Wahab  <matthew.wahab@arm.com>
1279
1280         * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
1281         ARM_EXT_RAS in relevant entries.
1282
1283 2016-06-03  Peter Bergner <bergner@vnet.ibm.com>
1284
1285         PR binutils/20196
1286         * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
1287         opcodes for E6500.
1288
1289 2016-06-03  H.J. Lu  <hongjiu.lu@intel.com>
1290
1291         PR binutis/18386
1292         * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
1293         (indir_v_mode): New.
1294         Add comments for '&'.
1295         (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
1296         (putop): Handle '&'.
1297         (intel_operand_size): Handle indir_v_mode.
1298         (OP_E_register): Likewise.
1299         * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64.  Add
1300         64-bit indirect call/jmp for AMD64.
1301         * i386-tbl.h: Regenerated
1302
1303 2016-06-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1304
1305         * arc-dis.c (struct arc_operand_iterator): New structure.
1306         (find_format_from_table): All the old content from find_format,
1307         with some minor adjustments, and parameter renaming.
1308         (find_format_long_instructions): New function.
1309         (find_format): Rewritten.
1310         (arc_insn_length): Add LSB parameter.
1311         (extract_operand_value): New function.
1312         (operand_iterator_next): New function.
1313         (print_insn_arc): Use new functions to find opcode, and iterator
1314         over operands.
1315         * arc-opc.c (insert_nps_3bit_dst_short): New function.
1316         (extract_nps_3bit_dst_short): New function.
1317         (insert_nps_3bit_src2_short): New function.
1318         (extract_nps_3bit_src2_short): New function.
1319         (insert_nps_bitop1_size): New function.
1320         (extract_nps_bitop1_size): New function.
1321         (insert_nps_bitop2_size): New function.
1322         (extract_nps_bitop2_size): New function.
1323         (insert_nps_bitop_mod4_msb): New function.
1324         (extract_nps_bitop_mod4_msb): New function.
1325         (insert_nps_bitop_mod4_lsb): New function.
1326         (extract_nps_bitop_mod4_lsb): New function.
1327         (insert_nps_bitop_dst_pos3_pos4): New function.
1328         (extract_nps_bitop_dst_pos3_pos4): New function.
1329         (insert_nps_bitop_ins_ext): New function.
1330         (extract_nps_bitop_ins_ext): New function.
1331         (arc_operands): Add new operands.
1332         (arc_long_opcodes): New global array.
1333         (arc_num_long_opcodes): New global.
1334         * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
1335
1336 2016-06-01  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1337
1338         * nds32-asm.h: Add extern "C".
1339         * sh-opc.h: Likewise.
1340
1341 2016-06-01  Graham Markall  <graham.markall@embecosm.com>
1342
1343         * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
1344         0,b,limm to the rflt instruction.
1345
1346 2016-05-31  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1347
1348         * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
1349         constant.
1350
1351 2016-05-29  H.J. Lu  <hongjiu.lu@intel.com>
1352
1353         PR gas/20145
1354         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
1355         CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
1356         CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
1357         CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
1358         CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
1359         * i386-init.h: Regenerated.
1360
1361 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
1362
1363         PR gas/20145
1364         * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS.  Remove
1365         CpuMMX from CPU_SSE_FLAGS.  Remove AVX and AVX512 bits from
1366         CPU_ANY_SSE_FLAGS.  Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
1367         Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
1368         CpuXSAVEC.  Add CPU_AVX_FLAGS to CpuF16C.  Remove CpuMMX from
1369         CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
1370         CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
1371         Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS.   Add CPU_ANY_287_FLAGS,
1372         CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
1373         CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
1374         CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS.  Enable CpuRegMMX
1375         for MMX.  Enable CpuRegXMM for SSE, AVX and AVX512.  Enable
1376         CpuRegYMM for AVX and AVX512VL,  Enable CpuRegZMM and
1377         CpuRegMask for AVX512.
1378         (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
1379         and CpuRegMask.
1380         (set_bitfield_from_cpu_flag_init): New function.
1381         (set_bitfield): Remove const on f.  Call
1382         set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
1383         * i386-opc.h (CpuRegMMX): New.
1384         (CpuRegXMM): Likewise.
1385         (CpuRegYMM): Likewise.
1386         (CpuRegZMM): Likewise.
1387         (CpuRegMask): Likewise.
1388         (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
1389         and cpuregmask.
1390         * i386-init.h: Regenerated.
1391         * i386-tbl.h: Likewise.
1392
1393 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
1394
1395         PR gas/20154
1396         * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
1397         (opcode_modifiers): Add AMD64 and Intel64.
1398         (main): Properly verify CpuMax.
1399         * i386-opc.h (CpuAMD64): Removed.
1400         (CpuIntel64): Likewise.
1401         (CpuMax): Set to CpuNo64.
1402         (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
1403         (AMD64): New.
1404         (Intel64): Likewise.
1405         (i386_opcode_modifier): Add amd64 and intel64.
1406         (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
1407         on call and jmp.
1408         * i386-init.h: Regenerated.
1409         * i386-tbl.h: Likewise.
1410
1411 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
1412
1413         PR gas/20154
1414         * i386-gen.c (main): Fail if CpuMax is incorrect.
1415         * i386-opc.h (CpuMax): Set to CpuIntel64.
1416         * i386-tbl.h: Regenerated.
1417
1418 2016-05-27  Nick Clifton  <nickc@redhat.com>
1419
1420         PR target/20150
1421         * msp430-dis.c (msp430dis_read_two_bytes): New function.
1422         (msp430dis_opcode_unsigned): New function.
1423         (msp430dis_opcode_signed): New function.
1424         (msp430_singleoperand): Use the new opcode reading functions.
1425         Only disassenmble bytes if they were successfully read.
1426         (msp430_doubleoperand): Likewise.
1427         (msp430_branchinstr): Likewise.
1428         (msp430x_callx_instr): Likewise.
1429         (print_insn_msp430): Check that it is safe to read bytes before
1430         attempting disassembly.  Use the new opcode reading functions.
1431
1432 2016-05-26  Peter Bergner <bergner@vnet.ibm.com>
1433
1434         * ppc-opc.c (CY): New define.  Document it.
1435         (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
1436
1437 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1438
1439         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
1440         CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
1441         and CPU_AVX512VBMI_FLAGS.  Add CpuAVX512DQ, CpuAVX512BW,
1442         CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
1443         CPU_ANY_AVX_FLAGS.
1444         * i386-init.h: Regenerated.
1445
1446 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1447
1448         PR gas/20141
1449         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
1450         CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
1451         * i386-init.h: Regenerated.
1452
1453 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1454
1455         * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
1456         CPU_ANY_X87_FLAGS.  Add CPU_ANY_MMX_FLAGS.
1457         * i386-init.h: Regenerated.
1458
1459 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
1460
1461         * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
1462         information.
1463         (print_insn_arc): Set insn_type information.
1464         * arc-opc.c (C_CC): Add F_CLASS_COND.
1465         * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
1466         (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
1467         (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
1468         (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
1469         (brne, brne_s, jeq_s, jne_s): Likewise.
1470
1471 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
1472
1473         * arc-tbl.h (neg): New instruction variant.
1474
1475 2016-05-23  Cupertino Miranda  <cmiranda@synopsys.com>
1476
1477         * arc-dis.c (find_format, find_format, get_auxreg)
1478         (print_insn_arc): Changed.
1479         * arc-ext.h (INSERT_XOP): Likewise.
1480
1481 2016-05-23  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1482
1483         * tic54x-dis.c (sprint_mmr): Adjust.
1484         * tic54x-opc.c: Likewise.
1485
1486 2016-05-19  Alan Modra  <amodra@gmail.com>
1487
1488         * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
1489
1490 2016-05-19  Alan Modra  <amodra@gmail.com>
1491
1492         * ppc-opc.c: Formatting.
1493         (NSISIGNOPT): Define.
1494         (powerpc_opcodes <subis>): Use NSISIGNOPT.
1495
1496 2016-05-18  Maciej W. Rozycki  <macro@imgtec.com>
1497
1498         * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
1499         replacing references to `micromips_ase' throughout.
1500         (_print_insn_mips): Don't use file-level microMIPS annotation to
1501         determine the disassembly mode with the symbol table.
1502
1503 2016-05-13  Peter Bergner <bergner@vnet.ibm.com>
1504
1505         * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
1506
1507 2016-05-11  Andrew Bennett  <andrew.bennett@imgtec.com>
1508
1509         * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
1510         mips64r6.
1511         * mips-opc.c (D34): New macro.
1512         (mips_builtin_opcodes): Define bposge32c for DSPr3.
1513
1514 2016-05-10  Alexander Fomin  <alexander.fomin@intel.com>
1515
1516         * i386-dis.c (prefix_table): Add RDPID instruction.
1517         * i386-gen.c (cpu_flag_init): Add RDPID flag.
1518         (cpu_flags): Add RDPID bitfield.
1519         * i386-opc.h (enum): Add RDPID element.
1520         (i386_cpu_flags): Add RDPID field.
1521         * i386-opc.tbl: Add RDPID instruction.
1522         * i386-init.h: Regenerate.
1523         * i386-tbl.h: Regenerate.
1524
1525 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1526
1527         * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
1528         branch type of a symbol.
1529         (print_insn): Likewise.
1530
1531 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1532
1533         * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1534         Mainline Security Extensions instructions.
1535         (thumb_opcodes): Add entries for narrow ARMv8-M Security
1536         Extensions instructions.
1537         (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1538         instructions.
1539         (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1540         special registers.
1541
1542 2016-05-09  Jose E. Marchesi  <jose.marchesi@oracle.com>
1543
1544         * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1545
1546 2016-05-03  Claudiu Zissulescu  <claziss@synopsys.com>
1547
1548         * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1549         (arcExtMap_genOpcode): Likewise.
1550         * arc-opc.c (arg_32bit_rc): Define new variable.
1551         (arg_32bit_u6): Likewise.
1552         (arg_32bit_limm): Likewise.
1553
1554 2016-05-03  Szabolcs Nagy  <szabolcs.nagy@arm.com>
1555
1556         * aarch64-gen.c (VERIFIER): Define.
1557         * aarch64-opc.c (VERIFIER): Define.
1558         (verify_ldpsw): Use static linkage.
1559         * aarch64-opc.h (verify_ldpsw): Remove.
1560         * aarch64-tbl.h: Use VERIFIER for verifiers.
1561
1562 2016-04-28  Nick Clifton  <nickc@redhat.com>
1563
1564         PR target/19722
1565         * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1566         * aarch64-opc.c (verify_ldpsw): New function.
1567         * aarch64-opc.h (verify_ldpsw): New prototype.
1568         * aarch64-tbl.h: Add initialiser for verifier field.
1569         (LDPSW): Set verifier to verify_ldpsw.
1570
1571 2016-04-23  H.J. Lu  <hongjiu.lu@intel.com>
1572
1573         PR binutils/19983
1574         PR binutils/19984
1575         * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1576         smaller than address size.
1577
1578 2016-04-20  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1579
1580         * alpha-dis.c: Regenerate.
1581         * crx-dis.c: Likewise.
1582         * disassemble.c: Likewise.
1583         * epiphany-opc.c: Likewise.
1584         * fr30-opc.c: Likewise.
1585         * frv-opc.c: Likewise.
1586         * ip2k-opc.c: Likewise.
1587         * iq2000-opc.c: Likewise.
1588         * lm32-opc.c: Likewise.
1589         * lm32-opinst.c: Likewise.
1590         * m32c-opc.c: Likewise.
1591         * m32r-opc.c: Likewise.
1592         * m32r-opinst.c: Likewise.
1593         * mep-opc.c: Likewise.
1594         * mt-opc.c: Likewise.
1595         * or1k-opc.c: Likewise.
1596         * or1k-opinst.c: Likewise.
1597         * tic80-opc.c: Likewise.
1598         * xc16x-opc.c: Likewise.
1599         * xstormy16-opc.c: Likewise.
1600
1601 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
1602
1603         * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1604         fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1605         calcsd, and calcxd instructions.
1606         * arc-opc.c (insert_nps_bitop_size): Delete.
1607         (extract_nps_bitop_size): Delete.
1608         (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1609         (extract_nps_qcmp_m3): Define.
1610         (extract_nps_qcmp_m2): Define.
1611         (extract_nps_qcmp_m1): Define.
1612         (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1613         (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1614         (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1615         NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1616         NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1617         NPS_QCMP_M3.
1618
1619 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
1620
1621         * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1622
1623 2016-04-15  H.J. Lu  <hongjiu.lu@intel.com>
1624
1625         * Makefile.in: Regenerated with automake 1.11.6.
1626         * aclocal.m4: Likewise.
1627
1628 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
1629
1630         * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1631         instructions.
1632         * arc-opc.c (insert_nps_cmem_uimm16): New function.
1633         (extract_nps_cmem_uimm16): New function.
1634         (arc_operands): Add NPS_XLDST_UIMM16 operand.
1635
1636 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
1637
1638         * arc-dis.c (arc_insn_length): New function.
1639         (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1640         (find_format): Change insnLen parameter to unsigned.
1641
1642 2016-04-13  Nick Clifton  <nickc@redhat.com>
1643
1644         PR target/19937
1645         * v850-opc.c (v850_opcodes): Correct masks for long versions of
1646         the LD.B and LD.BU instructions.
1647
1648 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1649
1650         * arc-dis.c (find_format): Check for extension flags.
1651         (print_flags): New function.
1652         (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1653         .extAuxRegister.
1654         * arc-ext.c (arcExtMap_coreRegName): Use
1655         LAST_EXTENSION_CORE_REGISTER.
1656         (arcExtMap_coreReadWrite): Likewise.
1657         (dump_ARC_extmap): Update printing.
1658         * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1659         (arc_aux_regs): Add cpu field.
1660         * arc-regs.h: Add cpu field, lower case name aux registers.
1661
1662 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1663
1664         * arc-tbl.h: Add rtsc, sleep with no arguments.
1665
1666 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1667
1668         * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1669         Initialize.
1670         (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1671         (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1672         (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1673         (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1674         (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1675         (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1676         (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1677         (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1678         (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1679         (arc_opcode arc_opcodes): Null terminate the array.
1680         (arc_num_opcodes): Remove.
1681         * arc-ext.h (INSERT_XOP): Define.
1682         (extInstruction_t): Likewise.
1683         (arcExtMap_instName): Delete.
1684         (arcExtMap_insn): New function.
1685         (arcExtMap_genOpcode): Likewise.
1686         * arc-ext.c (ExtInstruction): Remove.
1687         (create_map): Zero initialize instruction fields.
1688         (arcExtMap_instName): Remove.
1689         (arcExtMap_insn): New function.
1690         (dump_ARC_extmap): More info while debuging.
1691         (arcExtMap_genOpcode): New function.
1692         * arc-dis.c (find_format): New function.
1693         (print_insn_arc): Use find_format.
1694         (arc_get_disassembler): Enable dump_ARC_extmap only when
1695         debugging.
1696
1697 2016-04-11  Maciej W. Rozycki  <macro@imgtec.com>
1698
1699         * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1700         instruction bits out.
1701
1702 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
1703
1704         * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1705         * arc-opc.c (arc_flag_operands): Add new flags.
1706         (arc_flag_classes): Add new classes.
1707
1708 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
1709
1710         * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1711
1712 2016-04-05  Andrew Burgess  <andrew.burgess@embecosm.com>
1713
1714         * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1715         encode1, rflt, crc16, and crc32 instructions.
1716         * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1717         (arc_flag_classes): Add C_NPS_R.
1718         (insert_nps_bitop_size_2b): New function.
1719         (extract_nps_bitop_size_2b): Likewise.
1720         (insert_nps_bitop_uimm8): Likewise.
1721         (extract_nps_bitop_uimm8): Likewise.
1722         (arc_operands): Add new operand entries.
1723
1724 2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>
1725
1726         * arc-regs.h: Add a new subclass field.  Add double assist
1727         accumulator register values.
1728         * arc-tbl.h: Use DPA subclass to mark the double assist
1729         instructions.  Use DPX/SPX subclas to mark the FPX instructions.
1730         * arc-opc.c (RSP): Define instead of SP.
1731         (arc_aux_regs): Add the subclass field.
1732
1733 2016-04-05  Jiong Wang  <jiong.wang@arm.com>
1734
1735         * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1736
1737 2016-03-31  Andrew Burgess  <andrew.burgess@embecosm.com>
1738
1739         * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1740         NPS_R_SRC1.
1741
1742 2016-03-30  Andrew Burgess  <andrew.burgess@embecosm.com>
1743
1744         * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1745         issues.  No functional changes.
1746
1747 2016-03-30  Claudiu Zissulescu  <claziss@synopsys.com>
1748
1749         * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1750         (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1751         (RTT): Remove duplicate.
1752         (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1753         (PCT_CONFIG*): Remove.
1754         (D1L, D1H, D2H, D2L): Define.
1755
1756 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1757
1758         * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
1759
1760 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1761
1762         * arc-tbl.h (invld07): Remove.
1763         * arc-ext-tbl.h: New file.
1764         * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1765         * arc-opc.c (arc_opcodes): Add ext-tbl include.
1766
1767 2016-03-24  Jan Kratochvil  <jan.kratochvil@redhat.com>
1768
1769         Fix -Wstack-usage warnings.
1770         * aarch64-dis.c (print_operands): Substitute size.
1771         * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1772
1773 2016-03-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
1774
1775         * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1776         to get a proper diagnostic when an invalid ASR register is used.
1777
1778 2016-03-22  Nick Clifton  <nickc@redhat.com>
1779
1780         * configure: Regenerate.
1781
1782 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1783
1784         * arc-nps400-tbl.h: New file.
1785         * arc-opc.c: Add top level comment.
1786         (insert_nps_3bit_dst): New function.
1787         (extract_nps_3bit_dst): New function.
1788         (insert_nps_3bit_src2): New function.
1789         (extract_nps_3bit_src2): New function.
1790         (insert_nps_bitop_size): New function.
1791         (extract_nps_bitop_size): New function.
1792         (arc_flag_operands): Add nps400 entries.
1793         (arc_flag_classes): Add nps400 entries.
1794         (arc_operands): Add nps400 entries.
1795         (arc_opcodes): Add nps400 include.
1796
1797 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1798
1799         * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1800         the new class enum values.
1801
1802 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1803
1804         * arc-dis.c (print_insn_arc): Handle nps400.
1805
1806 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1807
1808         * arc-opc.c (BASE): Delete.
1809
1810 2016-03-18  Nick Clifton  <nickc@redhat.com>
1811
1812         PR target/19721
1813         * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1814         of MOV insn that aliases an ORR insn.
1815
1816 2016-03-16  Jiong Wang  <jiong.wang@arm.com>
1817
1818         * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1819
1820 2016-03-07  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1821
1822         * mcore-opc.h: Add const qualifiers.
1823         * microblaze-opc.h (struct op_code_struct): Likewise.
1824         * sh-opc.h: Likewise.
1825         * tic4x-dis.c (tic4x_print_indirect): Likewise.
1826         (tic4x_print_op): Likewise.
1827
1828 2016-03-02  Alan Modra  <amodra@gmail.com>
1829
1830         * or1k-desc.h: Regenerate.
1831         * fr30-ibld.c: Regenerate.
1832         * rl78-decode.c: Regenerate.
1833
1834 2016-03-01  Nick Clifton  <nickc@redhat.com>
1835
1836         PR target/19747
1837         * rl78-dis.c (print_insn_rl78_common): Fix typo.
1838
1839 2016-02-24  Renlin Li  <renlin.li@arm.com>
1840
1841         * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1842         (print_insn_coprocessor): Support fp16 instructions.
1843
1844 2016-02-24  Renlin Li  <renlin.li@arm.com>
1845
1846         * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1847         vminnm, vrint(mpna).
1848
1849 2016-02-24  Renlin Li  <renlin.li@arm.com>
1850
1851         * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1852         cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1853
1854 2016-02-15  H.J. Lu  <hongjiu.lu@intel.com>
1855
1856         * i386-dis.c (print_insn): Parenthesize expression to prevent
1857         truncated addresses.
1858         (OP_J): Likewise.
1859
1860 2016-02-10  Claudiu Zissulescu  <claziss@synopsys.com>
1861             Janek van Oirschot  <jvanoirs@synopsys.com>
1862
1863         * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1864         variable.
1865
1866 2016-02-04  Nick Clifton  <nickc@redhat.com>
1867
1868         PR target/19561
1869         * msp430-dis.c (print_insn_msp430): Add a special case for
1870         decoding an RRC instruction with the ZC bit set in the extension
1871         word.
1872
1873 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1874
1875         * cgen-ibld.in (insert_normal): Rework calculation of shift.
1876         * epiphany-ibld.c: Regenerate.
1877         * fr30-ibld.c: Regenerate.
1878         * frv-ibld.c: Regenerate.
1879         * ip2k-ibld.c: Regenerate.
1880         * iq2000-ibld.c: Regenerate.
1881         * lm32-ibld.c: Regenerate.
1882         * m32c-ibld.c: Regenerate.
1883         * m32r-ibld.c: Regenerate.
1884         * mep-ibld.c: Regenerate.
1885         * mt-ibld.c: Regenerate.
1886         * or1k-ibld.c: Regenerate.
1887         * xc16x-ibld.c: Regenerate.
1888         * xstormy16-ibld.c: Regenerate.
1889
1890 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1891
1892         * epiphany-dis.c: Regenerated from latest cpu files.
1893
1894 2016-02-01  Michael McConville  <mmcco@mykolab.com>
1895
1896         * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1897         test bit.
1898
1899 2016-01-25  Renlin Li  <renlin.li@arm.com>
1900
1901         * arm-dis.c (mapping_symbol_for_insn): New function.
1902         (find_ifthen_state): Call mapping_symbol_for_insn().
1903
1904 2016-01-20  Matthew Wahab  <matthew.wahab@arm.com>
1905
1906         * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1907         of MSR UAO immediate operand.
1908
1909 2016-01-18  Maciej W. Rozycki  <macro@imgtec.com>
1910
1911         * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1912         instruction support.
1913
1914 2016-01-17  Alan Modra  <amodra@gmail.com>
1915
1916         * configure: Regenerate.
1917
1918 2016-01-14  Nick Clifton  <nickc@redhat.com>
1919
1920         * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1921         instructions that can support stack pointer operations.
1922         * rl78-decode.c: Regenerate.
1923         * rl78-dis.c: Fix display of stack pointer in MOVW based
1924         instructions.
1925
1926 2016-01-14  Matthew Wahab  <matthew.wahab@arm.com>
1927
1928         * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1929         testing for RAS support.  Add checks for erxfr_el1, erxctlr_el1,
1930         erxtatus_el1 and erxaddr_el1.
1931
1932 2016-01-12  Matthew Wahab  <matthew.wahab@arm.com>
1933
1934         * arm-dis.c (arm_opcodes): Add "esb".
1935         (thumb_opcodes): Likewise.
1936
1937 2016-01-11  Peter Bergner <bergner@vnet.ibm.com>
1938
1939         * ppc-opc.c <xscmpnedp>: Delete.
1940         <xvcmpnedp>: Likewise.
1941         <xvcmpnedp.>: Likewise.
1942         <xvcmpnesp>: Likewise.
1943         <xvcmpnesp.>: Likewise.
1944
1945 2016-01-08  Andreas Schwab  <schwab@linux-m68k.org>
1946
1947         PR gas/13050
1948         * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1949         addition to ISA_A.
1950
1951 2016-01-01  Alan Modra  <amodra@gmail.com>
1952
1953         Update year range in copyright notice of all files.
1954
1955 For older changes see ChangeLog-2015
1956 \f
1957 Copyright (C) 2016 Free Software Foundation, Inc.
1958
1959 Copying and distribution of this file, with or without modification,
1960 are permitted in any medium without royalty provided the copyright
1961 notice and this notice are preserved.
1962
1963 Local Variables:
1964 mode: change-log
1965 left-margin: 8
1966 fill-column: 74
1967 version-control: never
1968 End: