opcodes/ChangeLog

   1 2015-07-23  Alan Modra  <amodra@gmail.com>
   2
   3         PR 18708
   4         * i386-dis.c (get64): Avoid signed integer overflow.
   5
   6 2015-07-22  Alexander Fomin  <alexander.fomin@intel.com>
   7
   8         PR binutils/18631
   9         * i386-dis-evex.h (EVEX_W_0F78_P_2): Replace "EXxmmq" with
  10         "EXEvexHalfBcstXmmq" for the second operand.
  11         (EVEX_W_0F79_P_2): Likewise.
  12         (EVEX_W_0F7A_P_2): Likewise.
  13         (EVEX_W_0F7B_P_2): Likewise.
  14
  15 2015-07-16  Alessandro Marzocchi  <alessandro.marzocchi@gmail.com>
  16
  17         * arm-dis.c (print_insn_coprocessor): Added support for quarter
  18         float bitfield format.
  19         (coprocessor_opcodes): Changed VFP vmov reg,immediate to use new
  20         quarter float bitfield format.
  21
  22 2015-07-14  H.J. Lu  <hongjiu.lu@intel.com>
  23
  24         * configure: Regenerated.
  25
  26 2015-07-03  Alan Modra  <amodra@gmail.com>
  27
  28         * ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
  29         * ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries.  Add
  30         PPC_OPCODE_7450 to 7450 entry.  Add PPC_OPCODE_750 to 750cl entry.
  31
  32 2015-07-01  Sandra Loosemore  <sandra@codesourcery.com>
  33             Cesar Philippidis  <cesar@codesourcery.com>
  34
  35         * nios2-dis.c (nios2_extract_opcode): New.
  36         (nios2_disassembler_state): New.
  37         (nios2_find_opcode_hash): Use mach parameter to select correct
  38         disassembler state.
  39         (nios2_print_insn_arg): Extend to support new R2 argument letters
  40         and formats.
  41         (print_insn_nios2): Check for 16-bit instruction at end of memory.
  42         * nios2-opc.c (nios2_builtin_regs): Add R2 register attributes.
  43         (NIOS2_NUM_OPCODES): Rename to...
  44         (NIOS2_NUM_R1_OPCODES): This.
  45         (nios2_r2_opcodes): New.
  46         (NIOS2_NUM_R2_OPCODES): New.
  47         (nios2_num_r2_opcodes): New.
  48         (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New.
  49         (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New.
  50         (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New.
  51         (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New.
  52         (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): New.
  53
  54 2015-06-30  Amit Pawar  <Amit.Pawar@amd.com>
  55
  56         * i386-dis.c (OP_Mwaitx): New.
  57         (rm_table): Add monitorx/mwaitx.
  58         * i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS
  59         and CPU_ZNVER1_FLAGS.  Add CPU_MWAITX_FLAGS.
  60         (operand_type_init): Add CpuMWAITX.
  61         * i386-opc.h (CpuMWAITX): New.
  62         (i386_cpu_flags): Add cpumwaitx.
  63         * i386-opc.tbl: Add monitorx and mwaitx.
  64         * i386-init.h: Regenerated.
  65         * i386-tbl.h: Likewise.
  66
  67 2015-06-22  Peter Bergner  <bergner@vnet.ibm.com>
  68
  69         * ppc-opc.c (insert_ls): Test for invalid LS operands.
  70         (insert_esync): New function.
  71         (LS, WC): Use insert_ls.
  72         (ESYNC): Use insert_esync.
  73
  74 2015-06-22  Nick Clifton  <nickc@redhat.com>
  75
  76         * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
  77         requested region lies beyond it.
  78         * bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
  79         looking for 32-bit insns.
  80         * mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
  81         data.
  82         * sh-dis.c (print_insn_sh): Likewise.
  83         * tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
  84         blocks of instructions.
  85         * vax-dis.c (print_insn_vax): Check that the requested address
  86         does not clash with the stop_vma.
  87
  88 2015-06-19  Peter Bergner  <bergner@vnet.ibm.com>
  89
  90         * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
  91         * ppc-opc.c (FXM4): Add non-zero optional value.
  92         (TBR): Likewise.
  93         (SXL): Likewise.
  94         (insert_fxm): Handle new default operand value.
  95         (extract_fxm): Likewise.
  96         (insert_tbr): Likewise.
  97         (extract_tbr): Likewise.
  98
  99 2015-06-16  Matthew Wahab  <matthew.wahab@arm.com>
 100
 101         * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
 102
 103 2015-06-16  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 104
 105         * arm-dis.c (print_insn_coprocessor): Avoid negative shift.
 106
 107 2015-06-12  Peter Bergner  <bergner@vnet.ibm.com>
 108
 109         * ppc-opc.c: Add comment accidentally removed by old commit.
 110         (MTMSRD_L): Delete.
 111
 112 2015-06-04  Peter Bergner  <bergner@vnet.ibm.com>
 113
 114         * ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.
 115
 116 2015-06-04  Nick Clifton  <nickc@redhat.com>
 117
 118         PR 18474
 119         * msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
 120
 121 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 122
 123         * arm-dis.c (arm_opcodes): Add "setpan".
 124         (thumb_opcodes): Add "setpan".
 125
 126 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 127
 128         * arm-dis.c (select_arm_features): Rework to avoid used of redefined
 129         macros.
 130
 131 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 132
 133         * aarch64-tbl.h (aarch64_feature_rdma): New.
 134         (RDMA): New.
 135         (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
 136         * aarch64-asm-2.c: Regenerate.
 137         * aarch64-dis-2.c: Regenerate.
 138         * aarch64-opc-2.c: Regenerate.
 139
 140 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 141
 142         * aarch64-tbl.h (aarch64_feature_lor): New.
 143         (LOR): New.
 144         (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
 145         "stllrb", "stllrh".
 146         * aarch64-asm-2.c: Regenerate.
 147         * aarch64-dis-2.c: Regenerate.
 148         * aarch64-opc-2.c: Regenerate.
 149
 150 2015-06-01  Matthew Wahab  <matthew.wahab@arm.com>
 151
 152         * aarch64-opc.c (F_ARCHEXT): New.
 153         (aarch64_sys_regs): Add "pan".
 154         (aarch64_sys_reg_supported_p): New.
 155         (aarch64_pstatefields): Add "pan".
 156         (aarch64_pstatefield_supported_p): New.
 157
 158 2015-06-01  Jan Beulich  <jbeulich@suse.com>
 159
 160         * i386-tbl.h: Regenerate.
 161
 162 2015-06-01  Jan Beulich  <jbeulich@suse.com>
 163
 164         * i386-dis.c (print_insn): Swap rounding mode specifier and
 165         general purpose register in Intel mode.
 166
 167 2015-06-01  Jan Beulich  <jbeulich@suse.com>
 168
 169         * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
 170         * i386-tbl.h: Regenerate.
 171
 172 2015-05-18  H.J. Lu  <hongjiu.lu@intel.com>
 173
 174         * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
 175         * i386-init.h: Regenerated.
 176
 177 2015-05-15  H.J. Lu  <hongjiu.lu@intel.com>
 178
 179         PR binutis/18386
 180         * i386-dis.c: Add comments for '@'.
 181         (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
 182         (enum x86_64_isa): New.
 183         (isa64): Likewise.
 184         (print_i386_disassembler_options): Add amd64 and intel64.
 185         (print_insn): Handle amd64 and intel64.
 186         (putop): Handle '@'.
 187         (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
 188         * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
 189         * i386-opc.h (AMD64): New.
 190         (CpuIntel64): Likewise.
 191         (i386_cpu_flags): Add cpuamd64 and cpuintel64.
 192         * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
 193         Mark direct call/jmp without Disp16|Disp32 as Intel64.
 194         * i386-init.h: Regenerated.
 195         * i386-tbl.h: Likewise.
 196
 197 2015-05-14  Peter Bergner  <bergner@vnet.ibm.com>
 198
 199         * ppc-opc.c (IH) New define.
 200         (powerpc_opcodes) <wait>: Do not enable for POWER7.
 201         <tlbie>: Add RS operand for POWER7.
 202         <slbia>: Add IH operand for POWER6.
 203
 204 2015-05-11  H.J. Lu  <hongjiu.lu@intel.com>
 205
 206         * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
 207         direct branch.
 208         (jmp): Likewise.
 209         * i386-tbl.h: Regenerated.
 210
 211 2015-05-11  H.J. Lu  <hongjiu.lu@intel.com>
 212
 213         * configure.ac: Support bfd_iamcu_arch.
 214         * disassemble.c (disassembler): Support bfd_iamcu_arch.
 215         * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
 216         CPU_IAMCU_COMPAT_FLAGS.
 217         (cpu_flags): Add CpuIAMCU.
 218         * i386-opc.h (CpuIAMCU): New.
 219         (i386_cpu_flags): Add cpuiamcu.
 220         * configure: Regenerated.
 221         * i386-init.h: Likewise.
 222         * i386-tbl.h: Likewise.
 223
 224 2015-05-08  H.J. Lu  <hongjiu.lu@intel.com>
 225
 226         PR binutis/18386
 227         * i386-dis.c (X86_64_E8): New.
 228         (X86_64_E9): Likewise.
 229         Update comments on 'T', 'U', 'V'.  Add comments for '^'.
 230         (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
 231         (x86_64_table): Add X86_64_E8 and X86_64_E9.
 232         (mod_table): Replace {T|} with ^ on Jcall/Jmp.
 233         (putop): Handle '^'.
 234         (OP_J): Ignore the operand size prefix in 64-bit.  Don't check
 235         REX_W.
 236
 237 2015-04-30  DJ Delorie  <dj@redhat.com>
 238
 239         * disassemble.c (disassembler): Choose suitable disassembler based
 240         on E_ABI.
 241         * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter.  Use
 242         it to decode mul/div insns.
 243         * rl78-decode.c: Regenerate.
 244         * rl78-dis.c (print_insn_rl78): Rename to...
 245         (print_insn_rl78_common): ...this, take ISA parameter.
 246         (print_insn_rl78): New.
 247         (print_insn_rl78_g10): New.
 248         (print_insn_rl78_g13): New.
 249         (print_insn_rl78_g14): New.
 250         (rl78_get_disassembler): New.
 251
 252 2015-04-29  Nick Clifton  <nickc@redhat.com>
 253
 254         * po/fr.po: Updated French translation.
 255
 256 2015-04-27  Peter Bergner  <bergner@vnet.ibm.com>
 257
 258         * ppc-opc.c (DCBT_EO): New define.
 259         (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
 260         <lharx>: Likewise.
 261         <stbcx.>: Likewise.
 262         <sthcx.>: Likewise.
 263         <waitrsv>: Do not enable for POWER7 and later.
 264         <waitimpl>: Likewise.
 265         <dcbt>: Default to the two operand form of the instruction for all
 266         "old" cpus.  For "new" cpus, use the operand ordering that matches
 267         whether the cpu is server or embedded.
 268         <dcbtst>: Likewise.
 269
 270 2015-04-27  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 271
 272         * s390-opc.c: New instruction type VV0UU2.
 273         * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
 274         and WFC.
 275
 276 2015-04-23  Jan Beulich  <jbeulich@suse.com>
 277
 278         * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
 279         * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
 280         vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
 281         (vfpclasspd, vfpclassps): Add %XZ.
 282
 283 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 284
 285         * i386-dis.c (PREFIX_UD_SHIFT): Removed.
 286         (PREFIX_UD_REPZ): Likewise.
 287         (PREFIX_UD_REPNZ): Likewise.
 288         (PREFIX_UD_DATA): Likewise.
 289         (PREFIX_UD_ADDR): Likewise.
 290         (PREFIX_UD_LOCK): Likewise.
 291
 292 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 293
 294         * i386-dis.c (prefix_requirement): Removed.
 295         (print_insn): Don't set prefix_requirement.  Check
 296         dp->prefix_requirement instead of prefix_requirement.
 297
 298 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 299
 300         PR binutils/17898
 301         * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
 302         (PREFIX_MOD_0_0FC7_REG_6): This.
 303         (PREFIX_MOD_3_0FC7_REG_6): New.
 304         (PREFIX_MOD_3_0FC7_REG_7): Likewise.
 305         (prefix_table): Replace PREFIX_0FC7_REG_6 with
 306         PREFIX_MOD_0_0FC7_REG_6.  Add PREFIX_MOD_3_0FC7_REG_6 and
 307         PREFIX_MOD_3_0FC7_REG_7.
 308         (mod_table): Replace PREFIX_0FC7_REG_6 with
 309         PREFIX_MOD_0_0FC7_REG_6.  Use PREFIX_MOD_3_0FC7_REG_6 and
 310         PREFIX_MOD_3_0FC7_REG_7.
 311
 312 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 313
 314         * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
 315         (PREFIX_MANDATORY_REPNZ): Likewise.
 316         (PREFIX_MANDATORY_DATA): Likewise.
 317         (PREFIX_MANDATORY_ADDR): Likewise.
 318         (PREFIX_MANDATORY_LOCK): Likewise.
 319         (PREFIX_MANDATORY): Likewise.
 320         (PREFIX_UD_SHIFT): Set to 8
 321         (PREFIX_UD_REPZ): Updated.
 322         (PREFIX_UD_REPNZ): Likewise.
 323         (PREFIX_UD_DATA): Likewise.
 324         (PREFIX_UD_ADDR): Likewise.
 325         (PREFIX_UD_LOCK): Likewise.
 326         (PREFIX_IGNORED_SHIFT): New.
 327         (PREFIX_IGNORED_REPZ): Likewise.
 328         (PREFIX_IGNORED_REPNZ): Likewise.
 329         (PREFIX_IGNORED_DATA): Likewise.
 330         (PREFIX_IGNORED_ADDR): Likewise.
 331         (PREFIX_IGNORED_LOCK): Likewise.
 332         (PREFIX_OPCODE): Likewise.
 333         (PREFIX_IGNORED): Likewise.
 334         (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
 335         (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
 336         (three_byte_table): Likewise.
 337         (mod_table): Likewise.
 338         (mandatory_prefix): Renamed to ...
 339         (prefix_requirement): This.
 340         (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
 341         Update PREFIX_90 entry.
 342         (get_valid_dis386): Check prefix_requirement to see if a prefix
 343         should be ignored.
 344         (print_insn): Replace mandatory_prefix with prefix_requirement.
 345
 346 2015-04-15  Renlin Li  <renlin.li@arm.com>
 347
 348         * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
 349         use it for ssat and ssat16.
 350         (print_insn_thumb32): Add handle case for 'D' control code.
 351
 352 2015-04-06  Ilya Tocar  <ilya.tocar@intel.com>
 353             H.J. Lu  <hongjiu.lu@intel.com>
 354
 355         * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
 356         * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
 357         PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
 358         PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
 359         PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
 360         (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
 361         Fill prefix_requirement field.
 362         (struct dis386): Add prefix_requirement field.
 363         (dis386): Fill prefix_requirement field.
 364         (dis386_twobyte): Ditto.
 365         (twobyte_has_mandatory_prefix_: Remove.
 366         (reg_table): Fill prefix_requirement field.
 367         (prefix_table): Ditto.
 368         (x86_64_table): Ditto.
 369         (three_byte_table): Ditto.
 370         (xop_table): Ditto.
 371         (vex_table): Ditto.
 372         (vex_len_table): Ditto.
 373         (vex_w_table): Ditto.
 374         (mod_table): Ditto.
 375         (bad_opcode): Ditto.
 376         (print_insn): Use prefix_requirement.
 377         (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
 378         FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
 379         (float_reg): Ditto.
 380
 381 2015-03-30  Mike Frysinger  <vapier@gentoo.org>
 382
 383         * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
 384
 385 2015-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 386
 387         * Makefile.in: Regenerated.
 388
 389 2015-03-25  Anton Blanchard  <anton@samba.org>
 390
 391         * ppc-dis.c (disassemble_init_powerpc): Only initialise
 392         powerpc_opcd_indices and vle_opcd_indices once.
 393
 394 2015-03-25  Anton Blanchard  <anton@samba.org>
 395
 396         * ppc-opc.c (powerpc_opcodes): Add slbfee.
 397
 398 2015-03-24  Terry Guo  <terry.guo@arm.com>
 399
 400         * arm-dis.c (opcode32): Updated to use new arm feature struct.
 401         (opcode16): Likewise.
 402         (coprocessor_opcodes): Replace bit with feature struct.
 403         (neon_opcodes): Likewise.
 404         (arm_opcodes): Likewise.
 405         (thumb_opcodes): Likewise.
 406         (thumb32_opcodes): Likewise.
 407         (print_insn_coprocessor): Likewise.
 408         (print_insn_arm): Likewise.
 409         (select_arm_features): Follow new feature struct.
 410
 411 2015-03-17  Ganesh Gopalasubramanian  <Ganesh.Gopalasubramanian@amd.com>
 412
 413         * i386-dis.c (rm_table): Add clzero.
 414         * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
 415         Add CPU_CLZERO_FLAGS.
 416         (cpu_flags): Add CpuCLZERO.
 417         * i386-opc.h: Add CpuCLZERO.
 418         * i386-opc.tbl: Add clzero.
 419         * i386-init.h: Re-generated.
 420         * i386-tbl.h: Re-generated.
 421
 422 2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>
 423
 424         * mips-opc.c (decode_mips_operand): Fix constraint issues
 425         with u and y operands.
 426
 427 2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>
 428
 429         * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
 430
 431 2015-03-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 432
 433         * s390-opc.c: Add new IBM z13 instructions.
 434         * s390-opc.txt: Likewise.
 435
 436 2015-03-10  Renlin Li  <renlin.li@arm.com>
 437
 438         * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
 439         stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
 440         related alias.
 441         * aarch64-asm-2.c: Regenerate.
 442         * aarch64-dis-2.c: Likewise.
 443         * aarch64-opc-2.c: Likewise.
 444
 445 2015-03-03  Jiong Wang  <jiong.wang@arm.com>
 446
 447         * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
 448
 449 2015-02-25  Oleg Endo  <olegendo@gcc.gnu.org>
 450
 451         * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
 452         arch_sh_up.
 453         (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
 454         arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
 455
 456 2015-02-23  Vinay  <Vinay.G@kpit.com>
 457
 458         * rl78-decode.opc (MOV): Added space between two operands for
 459         'mov' instruction in index addressing mode.
 460         * rl78-decode.c: Regenerate.
 461
 462 2015-02-19  Pedro Alves  <palves@redhat.com>
 463
 464         * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
 465
 466 2015-02-10  Pedro Alves  <palves@redhat.com>
 467             Tom Tromey  <tromey@redhat.com>
 468
 469         * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
 470         microblaze_and, microblaze_xor.
 471         * microblaze-opc.h (opcodes): Adjust.
 472
 473 2015-01-28  James Bowman  <james.bowman@ftdichip.com>
 474
 475         * Makefile.am: Add FT32 files.
 476         * configure.ac: Handle FT32.
 477         * disassemble.c (disassembler): Call print_insn_ft32.
 478         * ft32-dis.c: New file.
 479         * ft32-opc.c: New file.
 480         * Makefile.in: Regenerate.
 481         * configure: Regenerate.
 482         * po/POTFILES.in: Regenerate.
 483
 484 2015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
 485
 486         * nds32-asm.c (keyword_sr): Add new system registers.
 487
 488 2015-01-16  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 489
 490         * s390-dis.c (s390_extract_operand): Support vector register
 491         operands.
 492         (s390_print_insn_with_opcode): Support new operands types and add
 493         new handling of optional operands.
 494         * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
 495         and include opcode/s390.h instead.
 496         (struct op_struct): New field `flags'.
 497         (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
 498         (dumpTable): Dump flags.
 499         (main): Parse flags from the s390-opc.txt file.  Add z13 as cpu
 500         string.
 501         * s390-opc.c: Add new operands types, instruction formats, and
 502         instruction masks.
 503         (s390_opformats): Add new formats for .insn.
 504         * s390-opc.txt: Add new instructions.
 505
 506 2015-01-01  Alan Modra  <amodra@gmail.com>
 507
 508         Update year range in copyright notice of all files.
 509
 510 For older changes see ChangeLog-2014
 511 \f
 512 Copyright (C) 2015 Free Software Foundation, Inc.
 513
 514 Copying and distribution of this file, with or without modification,
 515 are permitted in any medium without royalty provided the copyright
 516 notice and this notice are preserved.
 517
 518 Local Variables:
 519 mode: change-log
 520 left-margin: 8
 521 fill-column: 74
 522 version-control: never
 523 End: