opcodes/ChangeLog

   1 2016-05-29  H.J. Lu  <hongjiu.lu@intel.com>
   2
   3         PR gas/20145
   4         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
   5         CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
   6         CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
   7         CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
   8         CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
   9         * i386-init.h: Regenerated.
  10
  11 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
  12
  13         PR gas/20145
  14         * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS.  Remove
  15         CpuMMX from CPU_SSE_FLAGS.  Remove AVX and AVX512 bits from
  16         CPU_ANY_SSE_FLAGS.  Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
  17         Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
  18         CpuXSAVEC.  Add CPU_AVX_FLAGS to CpuF16C.  Remove CpuMMX from
  19         CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
  20         CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
  21         Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS.   Add CPU_ANY_287_FLAGS,
  22         CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
  23         CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
  24         CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS.  Enable CpuRegMMX
  25         for MMX.  Enable CpuRegXMM for SSE, AVX and AVX512.  Enable
  26         CpuRegYMM for AVX and AVX512VL,  Enable CpuRegZMM and
  27         CpuRegMask for AVX512.
  28         (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
  29         and CpuRegMask.
  30         (set_bitfield_from_cpu_flag_init): New function.
  31         (set_bitfield): Remove const on f.  Call
  32         set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
  33         * i386-opc.h (CpuRegMMX): New.
  34         (CpuRegXMM): Likewise.
  35         (CpuRegYMM): Likewise.
  36         (CpuRegZMM): Likewise.
  37         (CpuRegMask): Likewise.
  38         (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
  39         and cpuregmask.
  40         * i386-init.h: Regenerated.
  41         * i386-tbl.h: Likewise.
  42
  43 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
  44
  45         PR gas/20154
  46         * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
  47         (opcode_modifiers): Add AMD64 and Intel64.
  48         (main): Properly verify CpuMax.
  49         * i386-opc.h (CpuAMD64): Removed.
  50         (CpuIntel64): Likewise.
  51         (CpuMax): Set to CpuNo64.
  52         (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
  53         (AMD64): New.
  54         (Intel64): Likewise.
  55         (i386_opcode_modifier): Add amd64 and intel64.
  56         (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
  57         on call and jmp.
  58         * i386-init.h: Regenerated.
  59         * i386-tbl.h: Likewise.
  60
  61 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
  62
  63         PR gas/20154
  64         * i386-gen.c (main): Fail if CpuMax is incorrect.
  65         * i386-opc.h (CpuMax): Set to CpuIntel64.
  66         * i386-tbl.h: Regenerated.
  67
  68 2016-05-27  Nick Clifton  <nickc@redhat.com>
  69
  70         PR target/20150
  71         * msp430-dis.c (msp430dis_read_two_bytes): New function.
  72         (msp430dis_opcode_unsigned): New function.
  73         (msp430dis_opcode_signed): New function.
  74         (msp430_singleoperand): Use the new opcode reading functions.
  75         Only disassenmble bytes if they were successfully read.
  76         (msp430_doubleoperand): Likewise.
  77         (msp430_branchinstr): Likewise.
  78         (msp430x_callx_instr): Likewise.
  79         (print_insn_msp430): Check that it is safe to read bytes before
  80         attempting disassembly.  Use the new opcode reading functions.
  81
  82 2016-05-26  Peter Bergner <bergner@vnet.ibm.com>
  83
  84         * ppc-opc.c (CY): New define.  Document it.
  85         (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
  86
  87 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
  88
  89         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
  90         CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
  91         and CPU_AVX512VBMI_FLAGS.  Add CpuAVX512DQ, CpuAVX512BW,
  92         CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
  93         CPU_ANY_AVX_FLAGS.
  94         * i386-init.h: Regenerated.
  95
  96 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
  97
  98         PR gas/20141
  99         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
 100         CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
 101         * i386-init.h: Regenerated.
 102
 103 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 104
 105         * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
 106         CPU_ANY_X87_FLAGS.  Add CPU_ANY_MMX_FLAGS.
 107         * i386-init.h: Regenerated.
 108
 109 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
 110
 111         * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
 112         information.
 113         (print_insn_arc): Set insn_type information.
 114         * arc-opc.c (C_CC): Add F_CLASS_COND.
 115         * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
 116         (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
 117         (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
 118         (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
 119         (brne, brne_s, jeq_s, jne_s): Likewise.
 120
 121 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
 122
 123         * arc-tbl.h (neg): New instruction variant.
 124
 125 2016-05-23  Cupertino Miranda  <cmiranda@synopsys.com>
 126
 127         * arc-dis.c (find_format, find_format, get_auxreg)
 128         (print_insn_arc): Changed.
 129         * arc-ext.h (INSERT_XOP): Likewise.
 130
 131 2016-05-23  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 132
 133         * tic54x-dis.c (sprint_mmr): Adjust.
 134         * tic54x-opc.c: Likewise.
 135
 136 2016-05-19  Alan Modra  <amodra@gmail.com>
 137
 138         * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
 139
 140 2016-05-19  Alan Modra  <amodra@gmail.com>
 141
 142         * ppc-opc.c: Formatting.
 143         (NSISIGNOPT): Define.
 144         (powerpc_opcodes <subis>): Use NSISIGNOPT.
 145
 146 2016-05-18  Maciej W. Rozycki  <macro@imgtec.com>
 147
 148         * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
 149         replacing references to `micromips_ase' throughout.
 150         (_print_insn_mips): Don't use file-level microMIPS annotation to
 151         determine the disassembly mode with the symbol table.
 152
 153 2016-05-13  Peter Bergner <bergner@vnet.ibm.com>
 154
 155         * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
 156
 157 2016-05-11  Andrew Bennett  <andrew.bennett@imgtec.com>
 158
 159         * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
 160         mips64r6.
 161         * mips-opc.c (D34): New macro.
 162         (mips_builtin_opcodes): Define bposge32c for DSPr3.
 163
 164 2016-05-10  Alexander Fomin  <alexander.fomin@intel.com>
 165
 166         * i386-dis.c (prefix_table): Add RDPID instruction.
 167         * i386-gen.c (cpu_flag_init): Add RDPID flag.
 168         (cpu_flags): Add RDPID bitfield.
 169         * i386-opc.h (enum): Add RDPID element.
 170         (i386_cpu_flags): Add RDPID field.
 171         * i386-opc.tbl: Add RDPID instruction.
 172         * i386-init.h: Regenerate.
 173         * i386-tbl.h: Regenerate.
 174
 175 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 176
 177         * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
 178         branch type of a symbol.
 179         (print_insn): Likewise.
 180
 181 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 182
 183         * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
 184         Mainline Security Extensions instructions.
 185         (thumb_opcodes): Add entries for narrow ARMv8-M Security
 186         Extensions instructions.
 187         (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
 188         instructions.
 189         (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
 190         special registers.
 191
 192 2016-05-09  Jose E. Marchesi  <jose.marchesi@oracle.com>
 193
 194         * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
 195
 196 2016-05-03  Claudiu Zissulescu  <claziss@synopsys.com>
 197
 198         * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
 199         (arcExtMap_genOpcode): Likewise.
 200         * arc-opc.c (arg_32bit_rc): Define new variable.
 201         (arg_32bit_u6): Likewise.
 202         (arg_32bit_limm): Likewise.
 203
 204 2016-05-03  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 205
 206         * aarch64-gen.c (VERIFIER): Define.
 207         * aarch64-opc.c (VERIFIER): Define.
 208         (verify_ldpsw): Use static linkage.
 209         * aarch64-opc.h (verify_ldpsw): Remove.
 210         * aarch64-tbl.h: Use VERIFIER for verifiers.
 211
 212 2016-04-28  Nick Clifton  <nickc@redhat.com>
 213
 214         PR target/19722
 215         * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
 216         * aarch64-opc.c (verify_ldpsw): New function.
 217         * aarch64-opc.h (verify_ldpsw): New prototype.
 218         * aarch64-tbl.h: Add initialiser for verifier field.
 219         (LDPSW): Set verifier to verify_ldpsw.
 220
 221 2016-04-23  H.J. Lu  <hongjiu.lu@intel.com>
 222
 223         PR binutils/19983
 224         PR binutils/19984
 225         * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
 226         smaller than address size.
 227
 228 2016-04-20  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 229
 230         * alpha-dis.c: Regenerate.
 231         * crx-dis.c: Likewise.
 232         * disassemble.c: Likewise.
 233         * epiphany-opc.c: Likewise.
 234         * fr30-opc.c: Likewise.
 235         * frv-opc.c: Likewise.
 236         * ip2k-opc.c: Likewise.
 237         * iq2000-opc.c: Likewise.
 238         * lm32-opc.c: Likewise.
 239         * lm32-opinst.c: Likewise.
 240         * m32c-opc.c: Likewise.
 241         * m32r-opc.c: Likewise.
 242         * m32r-opinst.c: Likewise.
 243         * mep-opc.c: Likewise.
 244         * mt-opc.c: Likewise.
 245         * or1k-opc.c: Likewise.
 246         * or1k-opinst.c: Likewise.
 247         * tic80-opc.c: Likewise.
 248         * xc16x-opc.c: Likewise.
 249         * xstormy16-opc.c: Likewise.
 250
 251 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
 252
 253         * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
 254         fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
 255         calcsd, and calcxd instructions.
 256         * arc-opc.c (insert_nps_bitop_size): Delete.
 257         (extract_nps_bitop_size): Delete.
 258         (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
 259         (extract_nps_qcmp_m3): Define.
 260         (extract_nps_qcmp_m2): Define.
 261         (extract_nps_qcmp_m1): Define.
 262         (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
 263         (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
 264         (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
 265         NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
 266         NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
 267         NPS_QCMP_M3.
 268
 269 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
 270
 271         * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
 272
 273 2016-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 274
 275         * Makefile.in: Regenerated with automake 1.11.6.
 276         * aclocal.m4: Likewise.
 277
 278 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
 279
 280         * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
 281         instructions.
 282         * arc-opc.c (insert_nps_cmem_uimm16): New function.
 283         (extract_nps_cmem_uimm16): New function.
 284         (arc_operands): Add NPS_XLDST_UIMM16 operand.
 285
 286 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
 287
 288         * arc-dis.c (arc_insn_length): New function.
 289         (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
 290         (find_format): Change insnLen parameter to unsigned.
 291
 292 2016-04-13  Nick Clifton  <nickc@redhat.com>
 293
 294         PR target/19937
 295         * v850-opc.c (v850_opcodes): Correct masks for long versions of
 296         the LD.B and LD.BU instructions.
 297
 298 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 299
 300         * arc-dis.c (find_format): Check for extension flags.
 301         (print_flags): New function.
 302         (print_insn_arc): Update for .extCondCode, .extCoreRegister and
 303         .extAuxRegister.
 304         * arc-ext.c (arcExtMap_coreRegName): Use
 305         LAST_EXTENSION_CORE_REGISTER.
 306         (arcExtMap_coreReadWrite): Likewise.
 307         (dump_ARC_extmap): Update printing.
 308         * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
 309         (arc_aux_regs): Add cpu field.
 310         * arc-regs.h: Add cpu field, lower case name aux registers.
 311
 312 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 313
 314         * arc-tbl.h: Add rtsc, sleep with no arguments.
 315
 316 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 317
 318         * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
 319         Initialize.
 320         (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
 321         (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
 322         (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
 323         (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
 324         (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
 325         (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
 326         (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
 327         (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
 328         (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
 329         (arc_opcode arc_opcodes): Null terminate the array.
 330         (arc_num_opcodes): Remove.
 331         * arc-ext.h (INSERT_XOP): Define.
 332         (extInstruction_t): Likewise.
 333         (arcExtMap_instName): Delete.
 334         (arcExtMap_insn): New function.
 335         (arcExtMap_genOpcode): Likewise.
 336         * arc-ext.c (ExtInstruction): Remove.
 337         (create_map): Zero initialize instruction fields.
 338         (arcExtMap_instName): Remove.
 339         (arcExtMap_insn): New function.
 340         (dump_ARC_extmap): More info while debuging.
 341         (arcExtMap_genOpcode): New function.
 342         * arc-dis.c (find_format): New function.
 343         (print_insn_arc): Use find_format.
 344         (arc_get_disassembler): Enable dump_ARC_extmap only when
 345         debugging.
 346
 347 2016-04-11  Maciej W. Rozycki  <macro@imgtec.com>
 348
 349         * mips-dis.c (print_mips16_insn_arg): Mask unused extended
 350         instruction bits out.
 351
 352 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
 353
 354         * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
 355         * arc-opc.c (arc_flag_operands): Add new flags.
 356         (arc_flag_classes): Add new classes.
 357
 358 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
 359
 360         * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
 361
 362 2016-04-05  Andrew Burgess  <andrew.burgess@embecosm.com>
 363
 364         * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
 365         encode1, rflt, crc16, and crc32 instructions.
 366         * arc-opc.c (arc_flag_operands): Add F_NPS_R.
 367         (arc_flag_classes): Add C_NPS_R.
 368         (insert_nps_bitop_size_2b): New function.
 369         (extract_nps_bitop_size_2b): Likewise.
 370         (insert_nps_bitop_uimm8): Likewise.
 371         (extract_nps_bitop_uimm8): Likewise.
 372         (arc_operands): Add new operand entries.
 373
 374 2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>
 375
 376         * arc-regs.h: Add a new subclass field.  Add double assist
 377         accumulator register values.
 378         * arc-tbl.h: Use DPA subclass to mark the double assist
 379         instructions.  Use DPX/SPX subclas to mark the FPX instructions.
 380         * arc-opc.c (RSP): Define instead of SP.
 381         (arc_aux_regs): Add the subclass field.
 382
 383 2016-04-05  Jiong Wang  <jiong.wang@arm.com>
 384
 385         * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
 386
 387 2016-03-31  Andrew Burgess  <andrew.burgess@embecosm.com>
 388
 389         * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
 390         NPS_R_SRC1.
 391
 392 2016-03-30  Andrew Burgess  <andrew.burgess@embecosm.com>
 393
 394         * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
 395         issues.  No functional changes.
 396
 397 2016-03-30  Claudiu Zissulescu  <claziss@synopsys.com>
 398
 399         * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
 400         (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
 401         (RTT): Remove duplicate.
 402         (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
 403         (PCT_CONFIG*): Remove.
 404         (D1L, D1H, D2H, D2L): Define.
 405
 406 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
 407
 408         * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
 409
 410 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
 411
 412         * arc-tbl.h (invld07): Remove.
 413         * arc-ext-tbl.h: New file.
 414         * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
 415         * arc-opc.c (arc_opcodes): Add ext-tbl include.
 416
 417 2016-03-24  Jan Kratochvil  <jan.kratochvil@redhat.com>
 418
 419         Fix -Wstack-usage warnings.
 420         * aarch64-dis.c (print_operands): Substitute size.
 421         * aarch64-opc.c (print_register_offset_address): Substitute tblen.
 422
 423 2016-03-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
 424
 425         * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
 426         to get a proper diagnostic when an invalid ASR register is used.
 427
 428 2016-03-22  Nick Clifton  <nickc@redhat.com>
 429
 430         * configure: Regenerate.
 431
 432 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 433
 434         * arc-nps400-tbl.h: New file.
 435         * arc-opc.c: Add top level comment.
 436         (insert_nps_3bit_dst): New function.
 437         (extract_nps_3bit_dst): New function.
 438         (insert_nps_3bit_src2): New function.
 439         (extract_nps_3bit_src2): New function.
 440         (insert_nps_bitop_size): New function.
 441         (extract_nps_bitop_size): New function.
 442         (arc_flag_operands): Add nps400 entries.
 443         (arc_flag_classes): Add nps400 entries.
 444         (arc_operands): Add nps400 entries.
 445         (arc_opcodes): Add nps400 include.
 446
 447 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 448
 449         * arc-opc.c (arc_flag_classes): Convert all flag classes to use
 450         the new class enum values.
 451
 452 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 453
 454         * arc-dis.c (print_insn_arc): Handle nps400.
 455
 456 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 457
 458         * arc-opc.c (BASE): Delete.
 459
 460 2016-03-18  Nick Clifton  <nickc@redhat.com>
 461
 462         PR target/19721
 463         * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
 464         of MOV insn that aliases an ORR insn.
 465
 466 2016-03-16  Jiong Wang  <jiong.wang@arm.com>
 467
 468         * arm-dis.c (neon_opcodes): Support new FP16 instructions.
 469
 470 2016-03-07  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 471
 472         * mcore-opc.h: Add const qualifiers.
 473         * microblaze-opc.h (struct op_code_struct): Likewise.
 474         * sh-opc.h: Likewise.
 475         * tic4x-dis.c (tic4x_print_indirect): Likewise.
 476         (tic4x_print_op): Likewise.
 477
 478 2016-03-02  Alan Modra  <amodra@gmail.com>
 479
 480         * or1k-desc.h: Regenerate.
 481         * fr30-ibld.c: Regenerate.
 482         * rl78-decode.c: Regenerate.
 483
 484 2016-03-01  Nick Clifton  <nickc@redhat.com>
 485
 486         PR target/19747
 487         * rl78-dis.c (print_insn_rl78_common): Fix typo.
 488
 489 2016-02-24  Renlin Li  <renlin.li@arm.com>
 490
 491         * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
 492         (print_insn_coprocessor): Support fp16 instructions.
 493
 494 2016-02-24  Renlin Li  <renlin.li@arm.com>
 495
 496         * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
 497         vminnm, vrint(mpna).
 498
 499 2016-02-24  Renlin Li  <renlin.li@arm.com>
 500
 501         * arm-dis.c (print_insn_coprocessor): Check co-processor number for
 502         cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
 503
 504 2016-02-15  H.J. Lu  <hongjiu.lu@intel.com>
 505
 506         * i386-dis.c (print_insn): Parenthesize expression to prevent
 507         truncated addresses.
 508         (OP_J): Likewise.
 509
 510 2016-02-10  Claudiu Zissulescu  <claziss@synopsys.com>
 511             Janek van Oirschot  <jvanoirs@synopsys.com>
 512
 513         * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
 514         variable.
 515
 516 2016-02-04  Nick Clifton  <nickc@redhat.com>
 517
 518         PR target/19561
 519         * msp430-dis.c (print_insn_msp430): Add a special case for
 520         decoding an RRC instruction with the ZC bit set in the extension
 521         word.
 522
 523 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
 524
 525         * cgen-ibld.in (insert_normal): Rework calculation of shift.
 526         * epiphany-ibld.c: Regenerate.
 527         * fr30-ibld.c: Regenerate.
 528         * frv-ibld.c: Regenerate.
 529         * ip2k-ibld.c: Regenerate.
 530         * iq2000-ibld.c: Regenerate.
 531         * lm32-ibld.c: Regenerate.
 532         * m32c-ibld.c: Regenerate.
 533         * m32r-ibld.c: Regenerate.
 534         * mep-ibld.c: Regenerate.
 535         * mt-ibld.c: Regenerate.
 536         * or1k-ibld.c: Regenerate.
 537         * xc16x-ibld.c: Regenerate.
 538         * xstormy16-ibld.c: Regenerate.
 539
 540 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
 541
 542         * epiphany-dis.c: Regenerated from latest cpu files.
 543
 544 2016-02-01  Michael McConville  <mmcco@mykolab.com>
 545
 546         * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
 547         test bit.
 548
 549 2016-01-25  Renlin Li  <renlin.li@arm.com>
 550
 551         * arm-dis.c (mapping_symbol_for_insn): New function.
 552         (find_ifthen_state): Call mapping_symbol_for_insn().
 553
 554 2016-01-20  Matthew Wahab  <matthew.wahab@arm.com>
 555
 556         * aarch64-opc.c (operand_general_constraint_met_p): Check validity
 557         of MSR UAO immediate operand.
 558
 559 2016-01-18  Maciej W. Rozycki  <macro@imgtec.com>
 560
 561         * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
 562         instruction support.
 563
 564 2016-01-17  Alan Modra  <amodra@gmail.com>
 565
 566         * configure: Regenerate.
 567
 568 2016-01-14  Nick Clifton  <nickc@redhat.com>
 569
 570         * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
 571         instructions that can support stack pointer operations.
 572         * rl78-decode.c: Regenerate.
 573         * rl78-dis.c: Fix display of stack pointer in MOVW based
 574         instructions.
 575
 576 2016-01-14  Matthew Wahab  <matthew.wahab@arm.com>
 577
 578         * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
 579         testing for RAS support.  Add checks for erxfr_el1, erxctlr_el1,
 580         erxtatus_el1 and erxaddr_el1.
 581
 582 2016-01-12  Matthew Wahab  <matthew.wahab@arm.com>
 583
 584         * arm-dis.c (arm_opcodes): Add "esb".
 585         (thumb_opcodes): Likewise.
 586
 587 2016-01-11  Peter Bergner <bergner@vnet.ibm.com>
 588
 589         * ppc-opc.c <xscmpnedp>: Delete.
 590         <xvcmpnedp>: Likewise.
 591         <xvcmpnedp.>: Likewise.
 592         <xvcmpnesp>: Likewise.
 593         <xvcmpnesp.>: Likewise.
 594
 595 2016-01-08  Andreas Schwab  <schwab@linux-m68k.org>
 596
 597         PR gas/13050
 598         * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
 599         addition to ISA_A.
 600
 601 2016-01-01  Alan Modra  <amodra@gmail.com>
 602
 603         Update year range in copyright notice of all files.
 604
 605 For older changes see ChangeLog-2015
 606 \f
 607 Copyright (C) 2016 Free Software Foundation, Inc.
 608
 609 Copying and distribution of this file, with or without modification,
 610 are permitted in any medium without royalty provided the copyright
 611 notice and this notice are preserved.
 612
 613 Local Variables:
 614 mode: change-log
 615 left-margin: 8
 616 fill-column: 74
 617 version-control: never
 618 End: