opcodes/ChangeLog

   1 2013-10-10  Sean Keys <skeys@ipdatasys.com>
   2
   3         * xgate-opc.c (xgate_opcode): Remove short_hand field from opcode
   4         table.
   5         * xgate-dis.c (print_insn): Refactor to work with table change.
   6
   7 2013-10-10  Roland McGrath  <mcgrathr@google.com>
   8
   9         * i386-dis.c (oappend_maybe_intel): New function.
  10         (OP_ST, OP_STi, append_seg, OP_I, OP_I64, OP_sI, OP_ESreg): Use it.
  11         (OP_C, OP_T, CMP_Fixup, OP_EX_VexImmW): Likewise.
  12         (VCMP_Fixup, VPCMP_Fixup, PCLMUL_Fixup): Likewise.
  13
  14         * cr16-opc.c (REG): Cast NAME to 'reg' enum type to suppress
  15         possible compiler warnings when the union's initializer is
  16         actually meant for the 'preg' enum typed member.
  17         * crx-opc.c (REG): Likewise.
  18
  19         * v850-dis.c (v850_cacheop_codes, v850_prefop_codes):
  20         Remove duplicate const qualifier.
  21
  22 2013-10-08  Jan Beulich <jbeulich@suse.com>
  23
  24         * i386-opc.tbl (invlpg): Use Anysize instead of Unspecified.
  25         (clflush): Use Anysize instead of Byte|Unspecified.
  26         (prefetch*): Likewise.
  27         * i386-tbl.h: Re-generate.
  28
  29 2013-10-07  Chao-ying Fu  <Chao-ying.Fu@imgtec.com>
  30
  31         * micromips-opc.c (micromips_opcodes): Fix dmfgc0 and dmtgc0.
  32
  33 2013-09-30  H.J. Lu  <hongjiu.lu@intel.com>
  34
  35         * i386-opc.tbl: Add Size64 to movq/vmovq with Reg64 operand.
  36         * i386-init.h: Regenerated.
  37
  38 2013-09-30  Saravanan Ekanathan <saravanan.ekanathan@amd.com>
  39
  40         * i386-gen.c (cpu_flag_init): Add CPU_BDVER4_FLAGS.
  41         * i386-init.h: Regenerated.
  42
  43 2013-09-20  Alan Modra  <amodra@gmail.com>
  44
  45         * configure: Regenerate.
  46
  47 2013-09-17  Richard Sandiford  <rsandifo@linux.vnet.ibm.com>
  48
  49         * s390-opc.txt (clih): Make the immediate unsigned.
  50
  51 2013-09-04  Roland McGrath  <mcgrathr@google.com>
  52
  53         PR gas/15914
  54         * arm-dis.c (arm_opcodes): Add udf.
  55         (thumb_opcodes): Use "udf" mnemonic rather than UNDEFINED_INSTRUCTION.
  56         (thumb32_opcodes): Add udf.w.
  57         (print_insn_thumb32): Handle %H as the thumb32_opcodes comment says.
  58
  59 2013-09-02  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
  60
  61         * s390-opc.txt: Fix description for fiebra, fidbra, and fixbra.
  62         For the load fp integer instructions only the suppression flag was
  63         new with z196 version.
  64
  65 2013-08-28  Nick Clifton  <nickc@redhat.com>
  66
  67         * aarch64-opc.c (aarch64_logical_immediate_p): Return FALSE if the
  68         immediate is not suitable for the 32-bit ABI.
  69
  70 2013-08-23  Maciej W. Rozycki  <macro@codesourcery.com>
  71
  72         * micromips-opc.c (micromips_opcodes): Use RD_4 for "alnv.ps",
  73         replacing NODS.
  74
  75 2013-08-23  Yuri Chornoivan  <yurchor@ukr.net>
  76
  77         PR binutils/15834
  78         * aarch64-asm.c: Fix typos.
  79         * aarch64-dis.c: Likewise.
  80         * msp430-dis.c: Likewise.
  81
  82 2013-08-19  Richard Sandiford  <rdsandiford@googlemail.com>
  83
  84         * micromips-opc.c (micromips_opcodes): Replace "dext" and "dins"
  85         macro entries with "dextm", "dextu", "dinsm" and "dinsu" aliases.
  86         Use +H rather than +C for the real "dext".
  87         * mips-opc.c (mips_builtin_opcodes): Likewise.
  88
  89 2013-08-19  Richard Sandiford  <rdsandiford@googlemail.com>
  90
  91         * mips-formats.h (OPTIONAL_REG, OPTIONAL_MAPPED_REG): New macros.
  92         * micromips-opc.c (decode_micromips_operand): Use OPTIONAL_REG
  93         and OPTIONAL_MAPPED_REG.
  94         * mips-opc.c (decode_mips_operand): Likewise.
  95         * mips16-opc.c (decode_mips16_operand): Likewise.
  96         * mips-dis.c (print_insn_arg): Handle OP_OPTIONAL_REG.
  97
  98 2013-08-19  H.J. Lu  <hongjiu.lu@intel.com>
  99
 100         * i386-dis.c (PREFIX_EVEX_0F3A3E): Removed.
 101         (PREFIX_EVEX_0F3A3F): Likewise.
 102         * i386-dis-evex.h (evex_table): Updated.
 103
 104 2013-08-06  Jürgen Urban  <JuergenUrban@gmx.de>
 105
 106         * mips-opc.c (mips_builtin_opcodes): Add a suffixless version of
 107         VCLIPW.
 108
 109 2013-08-05  Eric Botcazou  <ebotcazou@adacore.com>
 110             Konrad Eisele  <konrad@gaisler.com>
 111
 112         * sparc-dis.c (compute_arch_mask): Set SPARC_OPCODE_ARCH_LEON bit for
 113         bfd_mach_sparc.
 114         * sparc-opc.c (MASK_LEON): Define.
 115         (v6, v6notlet, v7, v8, v6notv9): Add MASK_LEON.
 116         (letandleon): New macro.
 117         (v9andleon): Likewise.
 118         (sparc_opc): Add leon.
 119         (umac): Enable for letandleon.
 120         (smac): Likewise.
 121         (casa): Enable for v9andleon.
 122         (cas): Likewise.
 123         (casl): Likewise.
 124
 125 2013-08-04  Jürgen Urban  <JuergenUrban@gmx.de>
 126             Richard Sandiford  <rdsandiford@googlemail.com>
 127
 128         * mips-dis.c (print_reg): Handle OP_REG_VI, OP_REG_VF, OP_REG_R5900_I,
 129         OP_REG_R5900_Q, OP_REG_R5900_R and OP_REG_R5900_ACC.
 130         (print_vu0_channel): New function.
 131         (print_insn_arg): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX.
 132         (print_insn_args): Handle '#'.
 133         (print_insn_mips): Handle INSN2_VU0_CHANNEL_SUFFIX.
 134         * mips-opc.c (mips_vu0_channel_mask): New constant.
 135         (decode_mips_operand): Handle new VU0 operand types.
 136         (VU0, VU0CH): New macros.
 137         (mips_builtin_opcodes): Add VU0 opcodes.  Use "+7" rather than "E"
 138         for LQC2 and SQC2.  Use "+9" rather than "G" for EE CFC2 and CTC2.
 139         Use "+6" rather than "G" for QMFC2 and QMTC2.
 140
 141 2013-08-03  Richard Sandiford  <rdsandiford@googlemail.com>
 142
 143         * mips-formats.h (PCREL): Reorder parameters and update the definition
 144         to match new mips_pcrel_operand layout.
 145         (JUMP, JALX, BRANCH): Update accordingly.
 146         * mips16-opc.c (decode_mips16_operand): Likewise.
 147
 148 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 149
 150         * micromips-opc.c (WR_s): Delete.
 151
 152 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 153
 154         * mips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2, UDI):
 155         New macros.
 156         (WR_d, WR_t, WR_D, WR_T, WR_S, RD_s, RD_b, RD_t, RD_S, RD_T, RD_R)
 157         (WR_z, WR_Z, RD_z, RD_Z, RD_d): Delete.
 158         (mips_builtin_opcodes): Use the new position-based read-write flags
 159         instead of field-based ones.  Use UDI for "udi..." instructions.
 160         * mips16-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
 161         New macros.
 162         (WR_x, WR_y, WR_z, WR_Y, RD_x, RD_y, RD_Z, RD_X): Delete.
 163         (RD_T, WR_T, WR_31): Redefine using generic INSN_* flags.
 164         (WR_SP, RD_16): New macros.
 165         (RD_SP): Redefine as an INSN2_* flag.
 166         (MOD_SP): Redefine in terms of RD_SP and WR_SP.
 167         (mips16_opcodes): Use the new position-based read-write flags
 168         instead of field-based ones.  Use RD_16 for "nop".  Move RD_SP to
 169         pinfo2 field.
 170         * micromips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
 171         New macros.
 172         (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf, RD_mg, WR_mh, RD_mj)
 173         (WR_mj, RD_ml, RD_mmn, RD_mp, WR_mp, RD_mq, RD_gp, WR_d, WR_t, WR_D)
 174         (WR_T, WR_S, RD_s, RD_b, RD_t, RD_T, RD_S, RD_R, RD_D): Delete.
 175         (RD_sp, WR_sp): Redefine to INSN2_READ_SP and INSN2_WRITE_SP.
 176         (micromips_opcodes): Use the new position-based read-write flags
 177         instead of field-based ones.
 178         * mips-dis.c (print_insn_arg): Use mips_decode_reg_operand.
 179         (print_insn_mips, print_insn_micromips): Use INSN_WRITE_1 instead
 180         of field-based flags.
 181
 182 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 183
 184         * mips16-opc.c (UBR, CBR, RD_31, RD_PC): Redefine as INSN2_* flags.
 185         (WR_SP): Replace with...
 186         (MOD_SP): ...this.
 187         (mips16_opcodes): Update accordingly.
 188         * mips-dis.c (print_insn_mips16): Likewise.
 189
 190 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 191
 192         * mips16-opc.c (mips16_opcodes): Reformat.
 193
 194 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 195
 196         * mips-opc.c (mips_builtin_opcodes): Remove WR_* and RD_* flags
 197         for operands that are hard-coded to $0.
 198         * micromips-opc.c (micromips_opcodes): Likewise.
 199
 200 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 201
 202         * mips-opc.c (mips_builtin_opcodes): Use WR_31 rather than WR_d
 203         for the single-operand forms of JALR and JALR.HB.
 204         * micromips-opc.c (micromips_opcodes): Likewise JALR, JALRS, JALR.HB
 205         and JALRS.HB.
 206
 207 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 208
 209         * mips-opc.c (mips_builtin_opcodes): Add FP_D to VR5400 vector
 210         instructions.  Fix them to use WR_MACC instead of WR_CC and
 211         add missing RD_MACCs.
 212
 213 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 214
 215         * mips-dis.c (print_mips16_insn_arg): Include ISA bit in base address.
 216
 217 2013-07-29  Peter Bergner <bergner@vnet.ibm.com>
 218
 219         * ppc-dis.c (powerpc_init_dialect): Use ppc_parse_cpu() to set dialect.
 220
 221 2013-07-26  Sergey Guriev  <sergey.s.guriev@intel.com>
 222             Alexander Ivchenko  <alexander.ivchenko@intel.com>
 223             Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
 224             Sergey Lega  <sergey.s.lega@intel.com>
 225             Anna Tikhonova  <anna.tikhonova@intel.com>
 226             Ilya Tocar  <ilya.tocar@intel.com>
 227             Andrey Turetskiy  <andrey.turetskiy@intel.com>
 228             Ilya Verbin  <ilya.verbin@intel.com>
 229             Kirill Yukhin  <kirill.yukhin@intel.com>
 230             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 231
 232         * i386-dis-evex.h: New.
 233         * i386-dis.c (OP_Rounding): New.
 234         (VPCMP_Fixup): New.
 235         (OP_Mask): New.
 236         (Rdq): New.
 237         (XMxmmq): New.
 238         (EXdScalarS): New.
 239         (EXymm): New.
 240         (EXEvexHalfBcstXmmq): New.
 241         (EXxmm_mdq): New.
 242         (EXEvexXGscat): New.
 243         (EXEvexXNoBcst): New.
 244         (VPCMP): New.
 245         (EXxEVexR): New.
 246         (EXxEVexS): New.
 247         (XMask): New.
 248         (MaskG): New.
 249         (MaskE): New.
 250         (MaskR): New.
 251         (MaskVex): New.
 252         (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode,
 253         evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode,
 254         evex_rounding_mode, evex_sae_mode, mask_mode.
 255         (USE_EVEX_TABLE): New.
 256         (EVEX_TABLE): New.
 257         (EVEX enum): New.
 258         (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6,
 259         REG_EVEX_0F38C7.
 260         (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3,
 261         MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3,
 262         MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1,
 263         MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
 264         MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,  MOD_EVEX_0F38C7_REG_5,
 265         MOD_EVEX_0F38C7_REG_6.
 266         (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
 267         PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B,
 268         PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
 269         PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32,
 270         PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11,
 271         PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14,
 272         PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17,
 273         PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A,
 274         PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
 275         PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51,
 276         PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A,
 277         PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D,
 278         PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62,
 279         PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C,
 280         PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F,
 281         PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
 282         PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
 283         PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
 284         PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78,
 285         PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B,
 286         PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2,
 287         PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3,
 288         PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB,
 289         PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7,
 290         PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2,
 291         PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB,
 292         PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D,
 293         PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813,
 294         PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816,
 295         PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A,
 296         PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F,
 297         PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823,
 298         PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827,
 299         PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A,
 300         PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831,
 301         PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834,
 302         PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
 303         PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B,
 304         PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840,
 305         PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844,
 306         PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847,
 307         PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E,
 308         PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859,
 309         PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864,
 310         PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877,
 311         PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F,
 312         PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
 313         PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891,
 314         PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896,
 315         PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899,
 316         PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C,
 317         PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F,
 318         PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2,
 319         PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7,
 320         PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA,
 321         PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD,
 322         PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6,
 323         PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9,
 324         PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC,
 325         PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF,
 326         PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1,
 327         PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5,
 328         PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1,
 329         PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5,
 330         PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA,
 331         PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD,
 332         PREFIX_EVEX_0F3A00,  PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03,
 333         PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08,
 334         PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B,
 335         PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19,
 336         PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D,
 337         PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21,
 338         PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26,
 339         PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39,
 340         PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E,
 341         PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54,
 342         PREFIX_EVEX_0F3A55.
 343         (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0,
 344         VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0,
 345         VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0,
 346         VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0,
 347         VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1,
 348         VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1,
 349         VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1,
 350         VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0,
 351         VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0,
 352         VEX_W_0F3A32_P_2_LEN_0.
 353         (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0,
 354         EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0,
 355         EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0,
 356         EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0,
 357         EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1,
 358         EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
 359         EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0,
 360         EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1,
 361         EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
 362         EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2,
 363         EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
 364         EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2,
 365         EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3,
 366         EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3,
 367         EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3,
 368         EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3,
 369         EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0,
 370         EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0,
 371         EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0,
 372         EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0,
 373         EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2,
 374         EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2,
 375         EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2,
 376         EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2,
 377         EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0,
 378         EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1,
 379         EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1,
 380         EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2,
 381         EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2,
 382         EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1,
 383         EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2,
 384         EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2,
 385         EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2,
 386         EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1,
 387         EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1,
 388         EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2,
 389         EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
 390         EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1,
 391         EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2,
 392         EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1,
 393         EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1,
 394         EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1,
 395         EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1,
 396         EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2,
 397         EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2,
 398         EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
 399         EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2,
 400         EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
 401         EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
 402         EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2,
 403         EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
 404         EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2,
 405         EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2,
 406         EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2.
 407         (struct vex): Add fields evex, r, v, mask_register_specifier,
 408         zeroing, ll, b.
 409         (intel_names_xmm): Add upper 16 registers.
 410         (att_names_xmm): Ditto.
 411         (intel_names_ymm): Ditto.
 412         (att_names_ymm): Ditto.
 413         (names_zmm): New.
 414         (intel_names_zmm): Ditto.
 415         (att_names_zmm): Ditto.
 416         (names_mask): Ditto.
 417         (intel_names_mask): Ditto.
 418         (att_names_mask): Ditto.
 419         (names_rounding): Ditto.
 420         (names_broadcast): Ditto.
 421         (x86_64_table): Add escape to evex-table.
 422         (reg_table): Include reg_table evex-entries from
 423         i386-dis-evex.h.  Fix prefetchwt1 instruction.
 424         (prefix_table): Add entries for new instructions.
 425         (vex_table): Ditto.
 426         (vex_len_table): Ditto.
 427         (vex_w_table): Ditto.
 428         (mod_table): Ditto.
 429         (get_valid_dis386): Properly handle new instructions.
 430         (print_insn): Handle zmm and mask registers, print mask operand.
 431         (intel_operand_size): Support EVEX, new modes and sizes.
 432         (OP_E_register): Handle new modes.
 433         (OP_E_memory): Ditto.
 434         (OP_G): Ditto.
 435         (OP_XMM): Ditto.
 436         (OP_EX): Ditto.
 437         (OP_VEX): Ditto.
 438         * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and
 439         CPU_ANY_AVX_FLAGS.  Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS,
 440         CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
 441         (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER,
 442         CpuAVX512PF and CpuVREX.
 443         (operand_type_init): Add OPERAND_TYPE_REGZMM,
 444         OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8.
 445         (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast,
 446         StaticRounding, SAE, Disp8MemShift, NoDefMask.
 447         (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword.
 448         * i386-init.h: Regenerate.
 449         * i386-opc.h (CpuAVX512F): New.
 450         (CpuAVX512CD): New.
 451         (CpuAVX512ER): New.
 452         (CpuAVX512PF): New.
 453         (CpuVREX): New.
 454         (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er,
 455         cpuavx512pf and cpuvrex fields.
 456         (VecSIB): Add VecSIB512.
 457         (EVex): New.
 458         (Masking): New.
 459         (VecESize): New.
 460         (Broadcast): New.
 461         (StaticRounding): New.
 462         (SAE): New.
 463         (Disp8MemShift): New.
 464         (NoDefMask): New.
 465         (i386_opcode_modifier): Add evex, masking, vecesize, broadcast,
 466         staticrounding, sae, disp8memshift and nodefmask.
 467         (RegZMM): New.
 468         (Zmmword): Ditto.
 469         (Vec_Disp8): Ditto.
 470         (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8
 471         fields.
 472         (RegVRex): New.
 473         * i386-opc.tbl: Add AVX512 instructions.
 474         * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM
 475         registers, mask registers.
 476         * i386-tbl.h: Regenerate.
 477
 478 2013-07-25  Aaro Koskinen  <aaro.koskinen@iki.fi>
 479
 480         PR gas/15220
 481         * mips-opc.c (mips_builtin_opcodes): Fix wrong opcodes for
 482         Loongson 2F madd.ps, msub.ps, nmadd.ps and nmsub.ps.
 483
 484 2013-07-25  Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 485
 486         * i386-dis.c (PREFIX enum): Add PREFIX_0F38C8, PREFIX_0F38C9,
 487         PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC, PREFIX_0F38CD,
 488         PREFIX_0F3ACC.
 489         (prefix_table): Updated.
 490         (three_byte_table): Likewise.
 491         * i386-gen.c (cpu_flag_init): Add CPU_SHA_FLAGS.
 492         (cpu_flags): Add CpuSHA.
 493         (i386_cpu_flags): Add cpusha.
 494         * i386-init.h: Regenerate.
 495         * i386-opc.h (CpuSHA): New.
 496         (CpuUnused): Restored.
 497         (i386_cpu_flags): Add cpusha.
 498         * i386-opc.tbl: Add SHA instructions.
 499         * i386-tbl.h: Regenerate.
 500
 501 2013-07-24  Anna Tikhonova  <anna.tikhonova@intel.com>
 502             Kirill Yukhin  <kirill.yukhin@intel.com>
 503             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 504
 505         * i386-dis.c (BND_Fixup): New.
 506         (Ebnd): New.
 507         (Ev_bnd): New.
 508         (Gbnd): New.
 509         (BND): New.
 510         (v_bnd_mode): New.
 511         (bnd_mode): New.
 512         (MOD enum): Add MOD_0F1A_PREFIX_0, MOD_0F1B_PREFIX_0,
 513         MOD_0F1B_PREFIX_1.
 514         (PREFIX enum): Add PREFIX_0F1A, PREFIX_0F1B.
 515         (dis tables): Replace XX with BND for near branch and call
 516         instructions.
 517         (prefix_table): Add new entries.
 518         (mod_table): Likewise.
 519         (names_bnd): New.
 520         (intel_names_bnd): New.
 521         (att_names_bnd): New.
 522         (BND_PREFIX): New.
 523         (prefix_name): Handle BND_PREFIX.
 524         (print_insn): Initialize names_bnd.
 525         (intel_operand_size): Handle new modes.
 526         (OP_E_register): Likewise.
 527         (OP_E_memory): Likewise.
 528         (OP_G): Likewise.
 529         * i386-gen.c (cpu_flag_init): Add CpuMPX.
 530         (cpu_flags): Add CpuMPX.
 531         (operand_type_init): Add RegBND.
 532         (opcode_modifiers): Add BNDPrefixOk.
 533         (operand_types): Add RegBND.
 534         * i386-init.h: Regenerate.
 535         * i386-opc.h (CpuMPX): New.
 536         (CpuUnused): Comment out.
 537         (i386_cpu_flags): Add cpumpx.
 538         (BNDPrefixOk): New.
 539         (i386_opcode_modifier): Add bndprefixok.
 540         (RegBND): New.
 541         (i386_operand_type): Add regbnd.
 542         * i386-opc.tbl: Add BNDPrefixOk to near jumps, calls and rets.
 543         Add MPX instructions and bnd prefix.
 544         * i386-reg.tbl: Add bnd0-bnd3 registers.
 545         * i386-tbl.h: Regenerate.
 546
 547 2013-07-17  Richard Sandiford  <rdsandiford@googlemail.com>
 548
 549         * mips-formats.h (MAPPED_INT, MAPPED_REG, REG_PAIR): Add
 550         ATTRIBUTE_UNUSED.
 551
 552 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 553
 554         * Makefile.am (mips-opc.lo, micromips-opc.lo, mips16-opc.lo): Remove
 555         special rules.
 556         * Makefile.in: Regenerate.
 557         * mips-opc.c, micromips-opc.c, mips16-opc.c: Explicitly initialize
 558         all fields.  Reformat.
 559
 560 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 561
 562         * mips16-opc.c: Include mips-formats.h.
 563         (reg_0_map, reg_29_map, reg_31_map, reg_m16_map, reg32r_map): New
 564         static arrays.
 565         (decode_mips16_operand): New function.
 566         * mips-dis.c (mips16_to_32_reg_map, mips16_reg_names): Delete.
 567         (print_insn_arg): Handle OP_ENTRY_EXIT list.
 568         Abort for OP_SAVE_RESTORE_LIST.
 569         (print_mips16_insn_arg): Change interface.  Use mips_operand
 570         structures.  Delete GET_OP_S.  Move GET_OP definition to...
 571         (print_insn_mips16): ...here.  Call init_print_arg_state.
 572         Update the call to print_mips16_insn_arg.
 573
 574 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 575
 576         * mips-formats.h: New file.
 577         * mips-opc.c: Include mips-formats.h.
 578         (reg_0_map): New static array.
 579         (decode_mips_operand): New function.
 580         * micromips-opc.c: Remove <stdio.h> include.  Include mips-formats.h.
 581         (reg_0_map, reg_28_map, reg_29_map, reg_31_map, reg_m16_map)
 582         (reg_mn_map, reg_q_map, reg_h_map1, reg_h_map2, int_b_map)
 583         (int_c_map): New static arrays.
 584         (decode_micromips_operand): New function.
 585         * mips-dis.c (micromips_to_32_reg_b_map, micromips_to_32_reg_c_map)
 586         (micromips_to_32_reg_d_map, micromips_to_32_reg_e_map)
 587         (micromips_to_32_reg_f_map, micromips_to_32_reg_g_map)
 588         (micromips_to_32_reg_h_map1, micromips_to_32_reg_h_map2)
 589         (micromips_to_32_reg_l_map, micromips_to_32_reg_m_map)
 590         (micromips_to_32_reg_n_map, micromips_to_32_reg_q_map)
 591         (micromips_imm_b_map, micromips_imm_c_map): Delete.
 592         (print_reg): New function.
 593         (mips_print_arg_state): New structure.
 594         (init_print_arg_state, print_insn_arg): New functions.
 595         (print_insn_args): Change interface and use mips_operand structures.
 596         Delete GET_OP_S.  Move GET_OP definition to...
 597         (print_insn_mips): ...here.  Update the call to print_insn_args.
 598         (print_insn_micromips): Use print_insn_args.
 599
 600 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 601
 602         * mips16-opc.c (mips16_opcodes): Use "I" for immediate operands
 603         in macros.
 604
 605 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 606
 607         * mips-opc.c (mips_builtin_opcodes): Use "S,T" rather than "V,T" for
 608         ADDA.S, MULA.S and SUBA.S.
 609
 610 2013-07-08  H.J. Lu  <hongjiu.lu@intel.com>
 611
 612         PR gas/13572
 613         * i386-opc.tbl: Replace Xmmword with Qword on cvttps2pi.
 614         * i386-tbl.h: Regenerated.
 615
 616 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 617
 618         * mips-opc.c (mips_builtin_opcodes): Remove o(b) macros.  Move LD
 619         and SD A(B) macros up.
 620         * micromips-opc.c (micromips_opcodes): Likewise.
 621
 622 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 623
 624         * mips16-opc.c: Add entries for argumentless "entry" and "exit"
 625         instructions.
 626
 627 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 628
 629         * mips-opc.c (mips_builtin_opcodes): Use "Q" for the INSN_5400
 630         MDMX-like instructions.
 631         * mips-dis.c (print_insn_arg): Use "$f" rather than "$v" when
 632         printing "Q" operands for INSN_5400 instructions.
 633
 634 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 635
 636         * mips-opc.c (mips_builtin_opcodes): Use "+s" for "cins32" and
 637         "+S" for "cins".
 638         * mips-dis.c (print_mips_arg): Update "+s" and "+S" comments.
 639         Combine cases.
 640
 641 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 642
 643         * mips-opc.c (mips_builtin_opcodes): Use "+i" rather than "a" for
 644         "jalx".
 645         * mips16-opc.c (mips16_opcodes): Likewise.
 646         * micromips-opc.c (micromips_opcodes): Likewise.
 647         * mips-dis.c (print_insn_args, print_mips16_insn_arg)
 648         (print_insn_mips16): Handle "+i".
 649         (print_insn_micromips): Likewise.  Conditionally preserve the
 650         ISA bit for "a" but not for "+i".
 651
 652 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 653
 654         * micromips-opc.c (WR_mhi): Rename to..
 655         (WR_mh): ...this.
 656         (micromips_opcodes): Update "movep" entry accordingly.  Replace
 657         "mh,mi" with "mh".
 658         * mips-dis.c (micromips_to_32_reg_h_map): Rename to...
 659         (micromips_to_32_reg_h_map1): ...this.
 660         (micromips_to_32_reg_i_map): Rename to...
 661         (micromips_to_32_reg_h_map2): ...this.
 662         (print_micromips_insn): Remove "mi" case.  Print both registers
 663         in the pair for "mh".
 664
 665 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 666
 667         * mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries.
 668         * micromips-opc.c (micromips_opcodes): Likewise.
 669         * mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D"
 670         and "+T" handling.  Check for a "0" suffix when deciding whether to
 671         use coprocessor 0 names.  In that case, also check for ",H" selectors.
 672
 673 2013-07-05  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 674
 675         * s390-opc.c (J12_12, J24_24): New macros.
 676         (INSTR_MII_UPI): Rename to INSTR_MII_UPP.
 677         (MASK_MII_UPI): Rename to MASK_MII_UPP.
 678         * s390-opc.txt: Rename MII_UPI to MII_UPP for bprp instruction.
 679
 680 2013-07-04  Alan Modra  <amodra@gmail.com>
 681
 682         * ppc-opc.c (powerpc_opcodes): Add tdui, twui, tdu, twu, tui, tu.
 683
 684 2013-06-26  Nick Clifton  <nickc@redhat.com>
 685
 686         * rx-decode.opc (rx_decode_opcode): Check sd field as well as ss
 687         field when checking for type 2 nop.
 688         * rx-decode.c: Regenerate.
 689
 690 2013-06-25  Maciej W. Rozycki  <macro@codesourcery.com>
 691
 692         * micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc"
 693         and "movep" macros.
 694
 695 2013-06-24  Maciej W. Rozycki  <macro@codesourcery.com>
 696
 697         * mips-dis.c (is_mips16_plt_tail): New function.
 698         (print_insn_mips16): Handle MIPS16 PLT entry's GOT slot address
 699         word.
 700         (is_compressed_mode_p): Handle MIPS16/microMIPS PLT entries.
 701
 702 2013-06-21  DJ Delorie  <dj@redhat.com>
 703
 704         * msp430-decode.opc: New.
 705         * msp430-decode.c: New/generated.
 706         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add msp430-decode.c.
 707         (MAINTAINER_CLEANFILES): Likewise.
 708         Add rule to build msp430-decode.c frommsp430decode.opc
 709         using the opc2c program.
 710         * Makefile.in: Regenerate.
 711         * configure.in: Add msp430-decode.lo to msp430 architecture files.
 712         * configure: Regenerate.
 713
 714 2013-06-20  Yufeng Zhang  <yufeng.zhang@arm.com>
 715
 716         * aarch64-dis.c (EMBEDDED_ENV): Remove the check on it.
 717         (SYMTAB_AVAILABLE): Removed.
 718         (#include "elf/aarch64.h): Ditto.
 719
 720 2013-06-17  Catherine Moore  <clm@codesourcery.com>
 721             Maciej W. Rozycki  <macro@codesourcery.com>
 722             Chao-Ying Fu  <fu@mips.com>
 723
 724         * micromips-opc.c (EVA): Define.
 725         (TLBINV): Define.
 726         (micromips_opcodes): Add EVA opcodes.
 727         * mips-dis.c (mips_arch_choices): Update for ASE_EVA.
 728         (print_insn_args): Handle EVA offsets.
 729         (print_insn_micromips): Likewise.
 730         * mips-opc.c (EVA): Define.
 731         (TLBINV): Define.
 732         (mips_builtin_opcodes): Add EVA opcodes.
 733
 734 2013-06-17  Alan Modra  <amodra@gmail.com>
 735
 736         * Makefile.am (mips-opc.lo): Add rules to create automatic
 737         dependency files.  Pass archdefs.
 738         (micromips-opc.lo, mips16-opc.lo): Likewise.
 739         * Makefile.in: Regenerate.
 740
 741 2013-06-14  DJ Delorie  <dj@redhat.com>
 742
 743         * rx-decode.opc (rx_decode_opcode): Bit operations on
 744         registers are 32-bit operations, not 8-bit operations.
 745         * rx-decode.c: Regenerate.
 746
 747 2013-06-13  Chao-ying Fu  <Chao-ying.Fu@imgtec.com>
 748
 749         * micromips-opc.c (IVIRT): New define.
 750         (IVIRT64): New define.
 751         (micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
 752         tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions.
 753
 754         * mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0,
 755         dmtgc0 to print cp0 names.
 756
 757 2013-06-09  Sandra Loosemore  <sandra@codesourcery.com>
 758
 759         * nios2-opc.c (nios2_builtin_opcodes): Give "trap" a type-"b"
 760         argument.
 761
 762 2013-06-08  Catherine Moore  <clm@codesourcery.com>
 763             Richard Sandiford  <rdsandiford@googlemail.com>
 764
 765         * micromips-opc.c (D32, D33, MC): Update definitions.
 766         (micromips_opcodes):  Initialize ase field.
 767         * mips-dis.c (mips_arch_choice): Add ase field.
 768         (mips_arch_choices): Initialize ase field.
 769         (set_default_mips_dis_options): Declare and setup mips_ase.
 770         * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
 771         MT32, MC): Update definitions.
 772         (mips_builtin_opcodes): Initialize ase field.
 773
 774 2013-05-24  Richard Sandiford  <rsandifo@linux.vnet.ibm.com>
 775
 776         * s390-opc.txt (flogr): Require a register pair destination.
 777
 778 2013-05-23  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 779
 780         * s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU
 781         instruction format.
 782
 783 2013-05-22  Jürgen Urban  <JuergenUrban@gmx.de>
 784
 785         * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
 786
 787 2013-05-20  Peter Bergner <bergner@vnet.ibm.com>
 788
 789         * ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
 790         * ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
 791         XLS_MASK, PPCVSX2): New defines.
 792         (powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
 793         fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
 794         mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
 795         mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
 796         mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
 797         vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
 798         vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
 799         vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
 800         vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
 801         vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
 802         vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
 803         vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
 804         vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
 805         vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
 806         xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
 807         xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
 808         xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
 809         xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
 810         <lxvx, stxvx>: New extended mnemonics.
 811
 812 2013-05-17  Alan Modra  <amodra@gmail.com>
 813
 814         * ia64-raw.tbl: Replace non-ASCII char.
 815         * ia64-waw.tbl: Likewise.
 816         * ia64-asmtab.c: Regenerate.
 817
 818 2013-05-15  Saravanan Ekanathan <saravanan.ekanathan@amd.com>
 819
 820         * i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
 821         * i386-init.h: Regenerated.
 822
 823 2013-05-13  Yufeng Zhang  <yufeng.zhang@arm.com>
 824
 825         * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
 826         * aarch64-opc.c (operand_general_constraint_met_p): Relax the range
 827         check from [0, 255] to [-128, 255].
 828
 829 2013-05-09  Andrew Pinski  <apinski@cavium.com>
 830
 831         * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
 832         Add INSN_VIRT and INSN_VIRT64 to mips64r2.
 833         (parse_mips_dis_option): Handle the virt option.
 834         (print_insn_args): Handle "+J".
 835         (print_mips_disassembler_options): Print out message about virt64.
 836         * mips-opc.c (IVIRT): New define.
 837         (IVIRT64): New define.
 838         (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
 839         tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
 840         Move rfe to the bottom as it conflicts with tlbgp.
 841
 842 2013-05-09  Alan Modra  <amodra@gmail.com>
 843
 844         * ppc-opc.c (extract_vlesi): Properly sign extend.
 845         (extract_vlensi): Likewise.  Comment reason for setting invalid.
 846
 847 2013-05-02  Nick Clifton  <nickc@redhat.com>
 848
 849         * msp430-dis.c: Add support for MSP430X instructions.
 850
 851 2013-04-24  Sandra Loosemore  <sandra@codesourcery.com>
 852
 853         * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
 854         to "eccinj".
 855
 856 2013-04-17  Wei-chen Wang  <cole945@gmail.com>
 857
 858         PR binutils/15369
 859         * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
 860         of CGEN_CPU_ENDIAN.
 861         (hash_insns_list): Likewise.
 862
 863 2013-04-10  Jan Kratochvil  <jan.kratochvil@redhat.com>
 864
 865         * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
 866         warning workaround.
 867
 868 2013-04-08  Jan Beulich <jbeulich@suse.com>
 869
 870         * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
 871         * i386-tbl.h: Re-generate.
 872
 873 2013-04-06  David S. Miller  <davem@davemloft.net>
 874
 875         * sparc-dis.c (compare_opcodes): When encountering multiple aliases
 876         of an opcode, prefer the one with F_PREFERRED set.
 877         * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
 878         lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
 879         ops.  Make 64-bit VIS logical ops have "d" suffix in their names,
 880         mark existing mnenomics as aliases.  Add "cc" suffix to edge
 881         instructions generating condition codes, mark existing mnenomics
 882         as aliases.  Add "fp" prefix to VIS compare instructions, mark
 883         existing mnenomics as aliases.
 884
 885 2013-04-03  Nick Clifton  <nickc@redhat.com>
 886
 887         * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
 888         destination address by subtracting the operand from the current
 889         address.
 890         * v850-opc.c (insert_u16_loop): Disallow negative offsets.  Store
 891         a positive value in the insn.
 892         (extract_u16_loop): Do not negate the returned value.
 893         (D16_LOOP): Add V850_INVERSE_PCREL flag.
 894
 895         (ceilf.sw): Remove duplicate entry.
 896         (cvtf.hs): New entry.
 897         (cvtf.sh): Likewise.
 898         (fmaf.s): Likewise.
 899         (fmsf.s): Likewise.
 900         (fnmaf.s): Likewise.
 901         (fnmsf.s): Likewise.
 902         (maddf.s): Restrict to E3V5 architectures.
 903         (msubf.s): Likewise.
 904         (nmaddf.s): Likewise.
 905         (nmsubf.s): Likewise.
 906
 907 2013-03-27  H.J. Lu  <hongjiu.lu@intel.com>
 908
 909         * i386-dis.c (get_sib): Add the sizeflag argument.  Properly
 910         check address mode.
 911         (print_insn): Pass sizeflag to get_sib.
 912
 913 2013-03-27  Alexis Deruelle  <alexis.deruelle@gmail.com>
 914
 915         PR binutils/15068
 916         * tic6x-dis.c: Add support for displaying 16-bit insns.
 917
 918 2013-03-20  Alexis Deruelle  <alexis.deruelle@gmail.com>
 919
 920         PR gas/15095
 921         * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
 922         individual msb and lsb halves in src1 & src2 fields.  Discard the
 923         src1 (lsb) value and only use src2 (msb), discarding bit 0, to
 924         follow what Ti SDK does in that case as any value in the src1
 925         field yields the same output with SDK disassembler.
 926
 927 2013-03-12  Michael Eager <eager@eagercon.com>
 928
 929         * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
 930
 931 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
 932
 933         * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
 934
 935 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
 936
 937         * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
 938
 939 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
 940
 941         * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
 942
 943 2013-03-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 944
 945         * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
 946         (thumb32_opcodes): Likewise.
 947         (print_insn_thumb32): Handle 'S' control char.
 948
 949 2013-03-08  Yann Sionneau  <yann.sionneau@gmail.com>
 950
 951         * lm32-desc.c: Regenerate.
 952
 953 2013-03-01  H.J. Lu  <hongjiu.lu@intel.com>
 954
 955         * i386-reg.tbl (riz): Add RegRex64.
 956         * i386-tbl.h: Regenerated.
 957
 958 2013-02-28  Yufeng Zhang  <yufeng.zhang@arm.com>
 959
 960         * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
 961         (aarch64_feature_crc): New static.
 962         (CRC): New macro.
 963         (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
 964         crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
 965         * aarch64-asm-2.c: Re-generate.
 966         * aarch64-dis-2.c: Ditto.
 967         * aarch64-opc-2.c: Ditto.
 968
 969 2013-02-27  Alan Modra  <amodra@gmail.com>
 970
 971         * rl78-decode.opc (rl78_decode_opcode): Fix typo.
 972         * rl78-decode.c: Regenerate.
 973
 974 2013-02-25  Kaushik Phatak  <Kaushik.Phatak@kpitcummins.com>
 975
 976         * rl78-decode.opc: Fix encoding of DIVWU insn.
 977         * rl78-decode.c: Regenerate.
 978
 979 2013-02-19  H.J. Lu  <hongjiu.lu@intel.com>
 980
 981         PR gas/15159
 982         * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
 983
 984         * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
 985         (cpu_flags): Add CpuSMAP.
 986
 987         * i386-opc.h (CpuSMAP): New.
 988         (i386_cpu_flags): Add cpusmap.
 989
 990         * i386-opc.tbl: Add clac and stac.
 991
 992         * i386-init.h: Regenerated.
 993         * i386-tbl.h: Likewise.
 994
 995 2013-02-15  Markos Chandras  <markos.chandras@imgtec.com>
 996
 997         * metag-dis.c: Initialize outf->bytes_per_chunk to 4
 998         which also makes the disassembler output be in little
 999         endian like it should be.
1000
1001 2013-02-14  Yufeng Zhang  <yufeng.zhang@arm.com>
1002
1003         * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
1004         fields to NULL.
1005         (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
1006
1007 2013-02-13  Maciej W. Rozycki  <macro@codesourcery.com>
1008
1009         * mips-dis.c (is_compressed_mode_p): Only match symbols from the
1010         section disassembled.
1011
1012 2013-02-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
1013
1014         * arm-dis.c: Update strht pattern.
1015
1016 2013-02-09  Jürgen Urban  <JuergenUrban@gmx.de>
1017
1018         * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
1019         single-float.  Disable ll, lld, sc and scd for EE.  Disable the
1020         trunc.w.s macro for EE.
1021
1022 2013-02-06  Sandra Loosemore  <sandra@codesourcery.com>
1023             Andrew Jenner <andrew@codesourcery.com>
1024
1025         Based on patches from Altera Corporation.
1026
1027         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
1028         nios2-opc.c.
1029         * Makefile.in: Regenerated.
1030         * configure.in: Add case for bfd_nios2_arch.
1031         * configure: Regenerated.
1032         * disassemble.c (ARCH_nios2): Define.
1033         (disassembler): Add case for bfd_arch_nios2.
1034         * nios2-dis.c: New file.
1035         * nios2-opc.c: New file.
1036
1037 2013-02-04  Alan Modra  <amodra@gmail.com>
1038
1039         * po/POTFILES.in: Regenerate.
1040         * rl78-decode.c: Regenerate.
1041         * rx-decode.c: Regenerate.
1042
1043 2013-01-30  Yufeng Zhang  <yufeng.zhang@arm.com>
1044
1045         * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
1046         ushll2 with F_HAS_ALIAS.  Add entries for sxtl, sxtl2, uxtl and uxtl2.
1047         * aarch64-asm.c (convert_xtl_to_shll): New function.
1048         (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
1049         calling convert_xtl_to_shll.
1050         * aarch64-dis.c (convert_shll_to_xtl): New function.
1051         (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
1052         calling convert_shll_to_xtl.
1053         * aarch64-gen.c: Update copyright year.
1054         * aarch64-asm-2.c: Re-generate.
1055         * aarch64-dis-2.c: Re-generate.
1056         * aarch64-opc-2.c: Re-generate.
1057
1058 2013-01-24  Nick Clifton  <nickc@redhat.com>
1059
1060         * v850-dis.c: Add support for e3v5 architecture.
1061         * v850-opc.c: Likewise.
1062
1063 2013-01-17  Yufeng Zhang  <yufeng.zhang@arm.com>
1064
1065         * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
1066         * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
1067         * aarch64-opc.c (operand_general_constraint_met_p): For
1068         AARCH64_MOD_LSL, move the range check on the shift amount before the
1069         alignment check; change to call set_sft_amount_out_of_range_error
1070         instead of set_imm_out_of_range_error.
1071         * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
1072         (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
1073         8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
1074         SIMD_IMM_SFT.
1075
1076 2013-01-16  H.J. Lu  <hongjiu.lu@intel.com>
1077
1078         * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
1079
1080         * i386-init.h: Regenerated.
1081         * i386-tbl.h: Likewise.
1082
1083 2013-01-15  Nick Clifton  <nickc@redhat.com>
1084
1085         * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
1086         values.
1087         * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
1088
1089 2013-01-14  Will Newton <will.newton@imgtec.com>
1090
1091         * metag-dis.c (REG_WIDTH): Increase to 64.
1092
1093 2013-01-10  Peter Bergner <bergner@vnet.ibm.com>
1094
1095         * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
1096         * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
1097         XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
1098         (SH6): Update.
1099         <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
1100         "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
1101         "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
1102         <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
1103
1104 2013-01-10  Will Newton <will.newton@imgtec.com>
1105
1106         * Makefile.am: Add Meta.
1107         * configure.in: Add Meta.
1108         * disassemble.c: Add Meta support.
1109         * metag-dis.c: New file.
1110         * Makefile.in: Regenerate.
1111         * configure: Regenerate.
1112
1113 2013-01-07  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
1114
1115         * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
1116         (match_opcode): Rename to cr16_match_opcode.
1117
1118 2013-01-04  Juergen Urban <JuergenUrban@gmx.de>
1119
1120         * mips-dis.c: Add names for CP0 registers of r5900.
1121         * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
1122         instructions sq and lq.
1123         Add support for MIPS r5900 CPU.
1124         Add support for 128 bit MMI (Multimedia Instructions).
1125         Add support for EE instructions (Emotion Engine).
1126         Disable unsupported floating point instructions (64 bit and
1127         undefined compare operations).
1128         Enable instructions of MIPS ISA IV which are supported by r5900.
1129         Disable 64 bit co processor instructions.
1130         Disable 64 bit multiplication and division instructions.
1131         Disable instructions for co-processor 2 and 3, because these are
1132         not supported (preparation for later VU0 support (Vector Unit)).
1133         Disable cvt.w.s because this behaves like trunc.w.s and the
1134         correct execution can't be ensured on r5900.
1135         Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
1136         will confuse less developers and compilers.
1137
1138 2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>
1139
1140         * aarch64-opc.c (aarch64_print_operand): Change to print
1141         AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
1142         in comment.
1143         * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
1144         from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
1145         OP_MOV_IMM_WIDE.
1146
1147 2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>
1148
1149         * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
1150         PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
1151
1152 2013-01-02  H.J. Lu  <hongjiu.lu@intel.com>
1153
1154         * i386-gen.c (process_copyright): Update copyright year to 2013.
1155
1156 2013-01-02  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
1157
1158         * cr16-dis.c (match_opcode,make_instruction): Remove static
1159         declaration.
1160         (dwordU,wordU): Moved typedefs to opcode/cr16.h
1161         (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
1162
1163 For older changes see ChangeLog-2012
1164 \f
1165 Copyright (C) 2013 Free Software Foundation, Inc.
1166
1167 Copying and distribution of this file, with or without modification,
1168 are permitted in any medium without royalty provided the copyright
1169 notice and this notice are preserved.
1170
1171 Local Variables:
1172 mode: change-log
1173 left-margin: 8
1174 fill-column: 74
1175 version-control: never
1176 End: