1 2020-09-28 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
3 * aarch64-opc.c: Added ETMv4 system registers TRCACATRn, TRCACVRn,
4 TRCAUTHSTATUS, TRCAUXCTLR, TRCBBCTLR, TRCCCCTLR, TRCCIDCCTLR0, TRCCIDCCTLR1,
5 TRCCIDCVRn, TRCCIDR0, TRCCIDR1, TRCCIDR2, TRCCIDR3, TRCCLAIMCLR, TRCCLAIMSET,
6 TRCCNTCTLRn, TRCCNTRLDVRn, TRCCNTVRn, TRCCONFIGR, TRCDEVAFF0, TRCDEVAFF1,
7 TRCDEVARCH, TRCDEVID, TRCDEVTYPE, TRCDVCMRn, TRCDVCVRn, TRCEVENTCTL0R,
8 TRCEVENTCTL1R, TRCEXTINSELR, TRCIDR0, TRCIDR1, TRCIDR2, TRCIDR3, TRCIDR4,
9 TRCIDR5, TRCIDR6, TRCIDR7, TRCIDR8, TRCIDR9, TRCIDR10, TRCIDR11, TRCIDR12,
10 TRCIDR13, TRCIMSPEC0, TRCIMSPECn, TRCITCTRL, TRCLAR WOTRCLSR, TRCOSLAR
11 WOTRCOSLSR, TRCPDCR, TRCPDSR, TRCPIDR0, TRCPIDR1, TRCPIDR2, TRCPIDR3,
12 TRCPIDR4, TRCPIDR[5,6,7], TRCPRGCTLR, TRCP,CSELR, TRCQCTLR, TRCRSCTLRn,
13 TRCSEQEVRn, TRCSEQRSTEVR, TRCSEQSTR, TRCSSCCRn, TRCSSCSRn, TRCSSPCICRn,
14 TRCSTALLCTLR, TRCSTATR, TRCSYNCPR, TRCTRACEIDR, TRCTSCTLR, TRCVDARCCTLR,
15 TRCVDCTLR, TRCVDSACCTLR, TRCVICTLR, TRCVIIECTLR, TRCVIPCSSCTLR, TRCVISSCTLR,
16 TRCVMIDCCTLR0, TRCVMIDCCTLR1 and TRCVMIDCVRn.
18 2020-09-28 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
20 * aarch64-opc.c: Add ETE system registers TRCEXTINSELR<0-3> and TRCRSR.
22 2020-09-28 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
24 * aarch64-opc.c: Add TRBE system registers TRBIDR_EL1 , TRBBASER_EL1 ,
25 TRBLIMITR_EL1 , TRBMAR_EL1 , TRBPTR_EL1, TRBSR_EL1 and TRBTRG_EL1.
27 2020-09-26 Alan Modra <amodra@gmail.com>
29 * csky-opc.h: Formatting.
30 (GENERAL_REG_BANK): Correct spelling. Update use throughout file.
31 (get_register_name): Mask arch with CSKY_ARCH_MASK for shift,
33 (get_register_number): Likewise.
34 * csky-dis.c (get_gr_name, get_cr_name): Don't mask mach_flag.
36 2020-09-24 Lili Cui <lili.cui@intel.com>
39 * i386-dis.c (enum): Put MOD_VEX_0F38* together.
41 2020-09-24 Andrew Burgess <andrew.burgess@embecosm.com>
43 * csky-dis.c (csky_output_operand): Enclose body of if in curly
46 2020-09-24 Lili Cui <lili.cui@intel.com>
48 * i386-dis.c (enum): Add PREFIX_0F01_REG_1_RM_5,
49 PREFIX_0F01_REG_1_RM_6, PREFIX_0F01_REG_1_RM_7,
50 X86_64_0F01_REG_1_RM_5_P_2, X86_64_0F01_REG_1_RM_6_P_2,
51 X86_64_0F01_REG_1_RM_7_P_2.
52 (prefix_table): Likewise.
53 (x86_64_table): Likewise.
55 * i386-gen.c (cpu_flag_init): Add CPU_TDX_FLAGS
56 and CPU_ANY_TDX_FLAGS.
57 (cpu_flags): Add CpuTDX.
58 * i386-opc.h (enum): Add CpuTDX.
59 (i386_cpu_flags): Add cputdx.
60 * i386-opc.tbl: Add TDX insns.
61 * i386-init.h: Regenerate.
62 * i386-tbl.h: Likewise.
64 2020-09-17 Cooper Qu <<cooper.qu@linux.alibaba.com>>
66 * csky-dis.c (using_abi): New.
67 (parse_csky_dis_options): New function.
68 (get_gr_name): New function.
69 (get_cr_name): New function.
70 (csky_output_operand): Use get_gr_name and get_cr_name to
71 disassemble and add handle of OPRND_TYPE_IMM5b_LS.
72 (print_insn_csky): Parse disassembler options.
73 * csky-opc.h (OPRND_TYPE_IMM5b_LS): New enum.
74 (GENARAL_REG_BANK): Define.
75 (REG_SUPPORT_ALL): Define.
76 (REG_SUPPORT_ALL): New.
78 (REG_SUPPORT_A): Define.
79 (REG_SUPPORT_B): Define.
80 (REG_SUPPORT_C): Define.
81 (REG_SUPPORT_D): Define.
82 (REG_SUPPORT_E): Define.
83 (csky_abiv1_general_regs): New.
84 (csky_abiv1_control_regs): New.
85 (csky_abiv2_general_regs): New.
86 (csky_abiv2_control_regs): New.
87 (get_register_name): New function.
88 (get_register_number): New function.
89 (csky_get_general_reg_name): New function.
90 (csky_get_general_regno): New function.
91 (csky_get_control_reg_name): New function.
92 (csky_get_control_regno): New function.
93 (csky_v2_opcodes): Prefer two oprerans format for bclri and
94 bseti, strengthen the operands legality check of addc, zext
97 2020-09-23 Lili Cui <lili.cui@intel.com>
99 * i386-dis.c (enum): Add REG_0F38D8_PREFIX_1,
100 MOD_0F38FA_PREFIX_1, MOD_0F38FB_PREFIX_1,
101 MOD_0F38DC_PREFIX_1, MOD_0F38DD_PREFIX_1,
102 MOD_0F38DE_PREFIX_1, MOD_0F38DF_PREFIX_1,
103 PREFIX_0F38D8, PREFIX_0F38FA, PREFIX_0F38FB.
104 (reg_table): New instructions (see prefixes above).
105 (prefix_table): Likewise.
106 (three_byte_table): Likewise.
107 (mod_table): Likewise
108 * i386-gen.c (cpu_flag_init): Add CPU_KL_FLAGS, CPU_WIDE_KL_FLAGS,
109 CPU_ANY_KL_FLAGS and CPU_ANY_WIDE_KL_FLAGS.
110 (cpu_flags): Likewise.
111 (operand_type_init): Likewise.
112 * i386-opc.h (enum): Add CpuKL and CpuWide_KL.
113 (i386_cpu_flags): Add cpukl and cpuwide_kl.
114 * i386-opc.tbl: Add KL and WIDE_KL insns.
115 * i386-init.h: Regenerate.
116 * i386-tbl.h: Likewise.
118 2020-09-21 Alan Modra <amodra@gmail.com>
120 * rx-dis.c (flag_names): Add missing comma.
121 (register_names, flag_names, double_register_names),
122 (double_register_high_names, double_register_low_names),
123 (double_control_register_names, double_condition_names): Remove
126 2020-09-18 David Faust <david.faust@oracle.com>
128 * bpf-desc.c: Regenerate.
129 * bpf-desc.h: Likewise.
130 * bpf-opc.c: Likewise.
131 * bpf-opc.h: Likewise.
133 2020-09-16 Andrew Burgess <andrew.burgess@embecosm.com>
135 * csky-dis.c (csky_get_disassembler): Don't return NULL when there
138 2020-09-16 Alan Modra <amodra@gmail.com>
140 * ppc-dis.c (ppc_symbol_is_valid): Adjust elf_symbol_from invocation.
142 2020-09-10 Nick Clifton <nickc@redhat.com>
144 * ppc-dis.c (ppc_symbol_is_valid): New function. Returns false
145 for hidden, local, no-type symbols.
146 (disassemble_init_powerpc): Point the symbol_is_valid field in the
147 info structure at the new function.
149 2020-09-10 Cooper Qu <cooper.qu@linux.alibaba.com>
151 * csky-opc.h (csky_v2_opcodes): Add L2Cache instructions.
152 * testsuite/gas/csky/cskyv2_ck860.d : Adjust to icache.iva
155 2020-09-10 Nick Clifton <nickc@redhat.com>
157 * csky-dis.c (csky_output_operand): Coerce the immediate values to
158 long before printing.
160 2020-09-10 Alan Modra <amodra@gmail.com>
162 * csky-dis.c (csky_output_operand): Don't sprintf str to itself.
164 2020-09-07 Cooper Qu <cooper.qu@linux.alibaba.com>
166 * csky-opc.h (csky_v2_opcodes): Change mvtc and mulsw's
169 2020-09-07 Cooper Qu <cooper.qu@linux.alibaba.com>
171 * csky-dis.c (csky_output_operand): Add handlers for
172 OPRND_TYPE_HFLOAT_FMOVI, OPRND_TYPE_SFLOAT_FMOVI and
173 OPRND_TYPE_DFLOAT_FMOVI. Refine OPRND_TYPE_FREGLIST_DASH
174 to support FPUV3 instructions.
175 * csky-opc.h (enum operand_type): New enum OPRND_TYPE_IMM9b,
176 OPRND_TYPE_HFLOAT_FMOVI, OPRND_TYPE_SFLOAT_FMOVI and
177 OPRND_TYPE_DFLOAT_FMOVI.
178 (OPRND_MASK_4_5, OPRND_MASK_6, OPRND_MASK_6_7, OPRND_MASK_6_8,
179 OPRND_MASK_7, OPRND_MASK_7_8, OPRND_MASK_17_24,
180 OPRND_MASK_20, OPRND_MASK_20_21, OPRND_MASK_20_22,
181 OPRND_MASK_20_23, OPRND_MASK_20_24, OPRND_MASK_20_25,
182 OPRND_MASK_0_3or5_8, OPRND_MASK_0_3or6_7, OPRND_MASK_0_3or25,
183 OPRND_MASK_0_4or21_24, OPRND_MASK_5or20_21,
184 OPRND_MASK_5or20_22, OPRND_MASK_5or20_23, OPRND_MASK_5or20_24,
185 OPRND_MASK_5or20_25, OPRND_MASK_8_9or21_25,
186 OPRND_MASK_8_9or16_25, OPRND_MASK_4_6or20, OPRND_MASK_5_7or20,
187 OPRND_MASK_4_5or20or25, OPRND_MASK_4_6or20or25,
188 OPRND_MASK_4_7or20or25, OPRND_MASK_6_9or17_24,
189 OPRND_MASK_6_7or20, OPRND_MASK_6or20, OPRND_MASK_7or20,
190 OPRND_MASK_5or8_9or16_25, OPRND_MASK_5or8_9or20_25): Define.
191 (csky_v2_opcodes): Add FPUV3 instructions.
193 2020-09-08 Alex Coplan <alex.coplan@arm.com>
195 * aarch64-dis.c (print_operands): Pass CPU features to
196 aarch64_print_operand().
197 * aarch64-opc.c (aarch64_print_operand): Use CPU features to determine
198 preferred disassembly of system registers.
199 (SR_RNG): Refactor to use new SR_FEAT2 macro.
205 (SR_EXPAND_ELx): New.
206 (SR_EXPAND_EL12): New.
207 (aarch64_sys_regs): Specify which registers are only on
208 A-profile, add R-profile system registers.
212 (aarch64_sys_ins_reg_supported_p): Reject EL3 registers for
215 2020-09-08 Alex Coplan <alex.coplan@arm.com>
217 * aarch64-tbl.h (aarch64_feature_v8_r): New.
220 (aarch64_opcode_table): Add dfb.
221 * aarch64-opc-2.c: Regenerate.
222 * aarch64-asm-2.c: Regenerate.
223 * aarch64-dis-2.c: Regenerate.
225 2020-09-08 Alex Coplan <alex.coplan@arm.com>
227 * aarch64-dis.c (arch_variant): New.
228 (determine_disassembling_preference): Disassemble according to
230 (select_aarch64_variant): New.
231 (print_insn_aarch64): Set feature set.
233 2020-09-02 Alan Modra <amodra@gmail.com>
235 * v850-opc.c (insert_i5div1, insert_i5div2, insert_i5div3),
236 (insert_d5_4, insert_d8_6, insert_d8_7, insert_v8, insert_d9),
237 (insert_u16_loop, insert_d16_15, insert_d16_16, insert_d17_16),
238 (insert_d22, insert_d23, insert_d23_align1, insert_i9, insert_u9),
239 (insert_spe, insert_r4, insert_POS, insert_WIDTH, insert_SELID),
240 (insert_VECTOR8, insert_VECTOR5, insert_CACHEOP, insert_PREFOP),
241 (nsert_IMM10U, insert_SRSEL1, insert_SRSEL2): Use unsigned long
242 for value parameter and update code to suit.
243 (extract_d9, extract_d16_15, extract_d16_16, extract_d17_16),
244 (extract_d22, extract_d23, extract_i9): Use unsigned long variables.
246 2020-09-02 Alan Modra <amodra@gmail.com>
248 * i386-dis.c (OP_E_memory): Don't cast to signed type when
250 (get32, get32s): Use unsigned types in shift expressions.
252 2020-09-02 Alan Modra <amodra@gmail.com>
254 * csky-dis.c (print_insn_csky): Use unsigned type for "given".
256 2020-09-02 Alan Modra <amodra@gmail.com>
258 * crx-dis.c: Whitespace.
259 (print_arg): Use unsigned type for longdisp and mask variables,
260 and for left shift constant.
262 2020-09-02 Alan Modra <amodra@gmail.com>
264 * cgen-ibld.in (insert_normal, extract_normal): Use 1UL in left shift.
265 * bpf-ibld.c: Regenerate.
266 * epiphany-ibld.c: Regenerate.
267 * fr30-ibld.c: Regenerate.
268 * frv-ibld.c: Regenerate.
269 * ip2k-ibld.c: Regenerate.
270 * iq2000-ibld.c: Regenerate.
271 * lm32-ibld.c: Regenerate.
272 * m32c-ibld.c: Regenerate.
273 * m32r-ibld.c: Regenerate.
274 * mep-ibld.c: Regenerate.
275 * mt-ibld.c: Regenerate.
276 * or1k-ibld.c: Regenerate.
277 * xc16x-ibld.c: Regenerate.
278 * xstormy16-ibld.c: Regenerate.
280 2020-09-02 Alan Modra <amodra@gmail.com>
282 * bfin-dis.c (MASKBITS): Use SIGNBIT.
284 2020-09-02 Cooper Qu <cooper.qu@linux.alibaba.com>
286 * csky-opc.h (csky_v2_opcodes): Move divul and divsl
287 to CSKYV2_ISA_3E3R3 instruction set.
289 2020-09-02 Cooper Qu <cooper.qu@linux.alibaba.com>
291 * csky-opc.h (csky_v2_opcodes): Fix Encode of mulsws.
293 2020-09-01 Alan Modra <amodra@gmail.com>
295 * mep-ibld.c: Regenerate.
297 2020-08-31 Cooper Qu <cooper.qu@linux.alibaba.com>
299 * csky-dis.c (csky_output_operand): Assign dis_info.value for
302 2020-08-30 Alan Modra <amodra@gmail.com>
304 * cr16-dis.c: Formatting.
305 (parameter): Delete struct typedef. Use dwordU instead
307 (make_argument <arg_idxr>): Simplify detection of cbitb, sbitb
309 (make_argument <arg_cr>): Extract 20-bit field not 16-bit.
311 2020-08-29 Alan Modra <amodra@gmail.com>
314 * csky-opc.h (MAX_OPRND_NUM): Define to 5.
315 (union csky_operand): Use MAX_OPRND_NUM to size oprnds array.
317 2020-08-28 Alan Modra <amodra@gmail.com>
321 * cgen-ibld.in (insert_1): Use 1UL in forming mask.
322 (extract_normal): Likewise.
323 (insert_normal): Likewise, and move past zero length test.
324 (put_insn_int_value): Handle mask for zero length, use 1UL.
325 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
326 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
327 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
328 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
330 2020-08-28 Cooper Qu <cooper.qu@linux.alibaba.com>
332 * csky-dis.c (CSKY_DEFAULT_ISA): Define.
333 (csky_dis_info): Add member isa.
334 (csky_find_inst_info): Skip instructions that do not belong to
336 (csky_get_disassembler): Get infomation from attribute section.
337 (print_insn_csky): Set defualt ISA flag.
338 * csky.h (CSKY_ISA_VDSP_2): Rename from CSKY_ISA_VDSP_V2.
339 * csky-opc.h (struct csky_opcode): Change isa_flag16 and
340 isa_flag32'type to unsigned 64 bits.
342 2020-08-26 Jose E. Marchesi <jemarch@gnu.org>
344 * disassemble.c (enum epbf_isa_attr): Add ISA_XBPFBE, ISA_EBPFMAX.
346 2020-08-26 David Faust <david.faust@oracle.com>
348 * bpf-desc.c: Regenerate.
349 * bpf-desc.h: Likewise.
350 * bpf-opc.c: Likewise.
351 * bpf-opc.h: Likewise.
352 * disassemble.c (disassemble_init_for_target): Set bits for xBPF
353 ISA when appropriate.
355 2020-08-25 Alan Modra <amodra@gmail.com>
358 * vax-dis.c (parse_disassembler_options): Always add at least one
359 to entry_addr_total_slots.
361 2020-08-24 Cooper Qu <cooper.qu@linux.alibaba.com>
363 * csky-dis.c (csky_find_inst_info): Skip CK860's instructions
364 in other CPUs to speed up disassembling.
365 * csky-opc.h (csky_v2_opcodes): Add CK860's instructions,
366 Change plsli.u16 to plsli.16, change sync's operand format.
368 2020-08-21 Cooper Qu <cooper.qu@linux.alibaba.com>
370 * csky-opc.h (csky_v2_opcodes): Add instruction bnezad.
372 2020-08-21 Nick Clifton <nickc@redhat.com>
374 * aarch64-dis.c (get_sym_code_type): Return FALSE for non-ELF
377 2020-08-21 Cooper Qu <cooper.qu@linux.alibaba.com>
379 * csky-opc.h (csky_v2_opcodes): Add two operands form for bloop.
381 2020-08-19 Alan Modra <amodra@gmail.com>
383 * ppc-opc.c (powerpc_opcodes): Replace OBF with BF for vcmpsq,
386 2020-08-18 Peter Bergner <bergner@linux.ibm.com>
388 * ppc-opc.c (powerpc_opcodes) <xvcvbf16sp>: Rename from this...
389 <xvcvbf16spn>: ...to this.
391 2020-08-12 Alex Coplan <alex.coplan@arm.com>
393 * aarch64-opc.c (aarch64_sys_regs): Add MPAM registers.
395 2020-08-12 Nick Clifton <nickc@redhat.com>
397 * po/sr.po: Updated Serbian translation.
399 2020-08-11 Alan Modra <amodra@gmail.com>
401 * ppc-opc.c (powerpc_opcodes): Move cctpl, cctpm and cctph.
403 2020-08-10 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
405 * aarch64-opc.c (aarch64_print_operand):
406 (aarch64_sys_reg_deprecated_p): Functions paramaters changed.
407 (aarch64_sys_reg_supported_p): Function removed.
408 (aarch64_sys_ins_reg_supported_p): Functions paramaters changed.
409 (aarch64_sys_ins_reg_supported_p): Merged aarch64_sys_reg_supported_p
412 2020-08-10 Alan Modra <amodra@gmail.com>
414 * ppc-opc.c (powerpc_opcodes): Add many mtspr and mfspr extended
417 2020-08-10 Alan Modra <amodra@gmail.com>
419 * ppc-opc.c (powerpc_opcodes): Add exser, msgsndu, msgclru.
420 Enable icbt for power5, miso for power8.
422 2020-08-10 Alan Modra <amodra@gmail.com>
424 * ppc-opc.c (powerpc_opcodes): Prioritise mtfprd and mtvrd over
425 mtvsrd, and similarly for mfvsrd.
427 2020-08-04 Christian Groessler <chris@groessler.org>
428 Tadashi G. Takaoka <tadashi.g.takaoka@gmail.com>
430 * z8kgen.c (opt): Fix "sout imm16,rs" and "soutb imm16,rbs"
431 opcodes (special "out" to absolute address).
432 * z8k-opc.h: Regenerate.
434 2020-07-30 H.J. Lu <hongjiu.lu@intel.com>
437 * i386-opc.h (Prefix_Disp8): New.
438 (Prefix_Disp16): Likewise.
439 (Prefix_Disp32): Likewise.
440 (Prefix_Load): Likewise.
441 (Prefix_Store): Likewise.
442 (Prefix_VEX): Likewise.
443 (Prefix_VEX3): Likewise.
444 (Prefix_EVEX): Likewise.
445 (Prefix_REX): Likewise.
446 (Prefix_NoOptimize): Likewise.
447 * i386-opc.tbl: Use Prefix_XXX on pseudo prefixes. Add {disp16}.
448 * i386-tbl.h: Regenerated.
450 2020-07-29 Andreas Arnez <arnez@linux.ibm.com>
452 * s390-mkopc.c (insertExpandedMnemonic): Handle unreachable
453 default case with abort() instead of printing an error message and
454 continuing, to avoid a maybe-uninitialized warning.
456 2020-07-24 Nick Clifton <nickc@redhat.com>
458 * po/de.po: Updated German translation.
460 2020-07-21 Jan Beulich <jbeulich@suse.com>
462 * i386-dis.c (OP_E_memory): Revert previous change.
464 2020-07-15 H.J. Lu <hongjiu.lu@intel.com>
467 * i386-dis.c (OP_E_memory): Don't display eiz with no scale
468 without base nor index registers.
470 2020-07-15 Jan Beulich <jbeulich@suse.com>
472 * i386-dis.c (putop): Move 'V' and 'W' handling.
474 2020-07-15 Jan Beulich <jbeulich@suse.com>
476 * i386-dis.c (dis386): Adjust 'V' description. Use P-based
477 construct for push/pop of register.
478 (putop): Honor cond when handling 'P'. Drop handling of plain
481 2020-07-15 Jan Beulich <jbeulich@suse.com>
483 * i386-dis.c (dis386): Adjust 'P', 'T', 'U', and '@'
484 description. Drop '&' description. Use P for push of immediate,
485 pushf/popf, enter, and leave. Use %LP for lret/retf.
486 (dis386_twobyte): Use P for push/pop of fs/gs.
487 (reg_table): Use P for push/pop. Use @ for near call/jmp.
488 (x86_64_table): Use P for far call/jmp.
489 (putop): Drop handling of 'U' and '&'. Move and adjust handling
490 of '@'. Adjust handling of 'P' and 'T'. Drop case_P and case_Q
492 (OP_J): Drop marking of REX_W as used for v_mode (ISA-dependent)
493 and dqw_mode (unconditional).
495 2020-07-14 H.J. Lu <hongjiu.lu@intel.com>
498 * i386-dis.c (OP_E_memory): Without base nor index registers,
499 32-bit displacement to 64 bits.
501 2020-07-14 Claudiu Zissulescu <claziss@gmail.com>
503 * arc-dis.c (print_insn_arc): Detect and emit a warning when a
504 faulty double register pair is detected.
506 2020-07-14 Jan Beulich <jbeulich@suse.com>
508 * i386-dis.c (OP_D): Print dr<N> instead of db<N> in Intel mode.
510 2020-07-14 Jan Beulich <jbeulich@suse.com>
512 * i386-dis.c (OP_R, Rm): Delete.
513 (MOD_0F24, MOD_0F26): Rename to ...
514 (X86_64_0F24, X86_64_0F26): ... respectively.
515 (dis386): Update 'L' and 'Z' comments.
516 (dis386_twobyte): Replace Rm by Em. Change opcode 0F24 and 0F26
518 (mod_table): Move opcode 0F24 and 0F26 entries ...
519 (x86_64_table): ... here.
520 (putop): Drop handling of 'L'. Set modrm.mod to 3 for 'Z'. Move
523 2020-07-14 Jan Beulich <jbeulich@suse.com>
525 * i386-dis.c (Rd, Rdq, MaskR): Delete.
526 (MOD_EVEX_0F3828_P_1, MOD_EVEX_0F382A_P_1_W_1,
527 MOD_EVEX_0F3838_P_1, MOD_EVEX_0F383A_P_1_W_0,
528 MOD_EVEX_0F387A_W_0, MOD_EVEX_0F387B_W_0,
529 MOD_EVEX_0F387C): New enumerators.
530 (reg_table): Use Edq for rdssp.
531 (prefix_table): Use Edq for incssp.
532 (mod_table): Use Rm for move to/from %tr. Use MaskE for kand*,
533 kandn*, knot*, kor*, kxnor*, kxor*, kadd*, kunpck*, kortest*,
534 ktest*, and kshift*. Use Edq / MaskE for kmov*.
535 * i386-dis-evex.h: Reference mod_table[] for opcode 0F387C.
536 * i386-dis-evex-mod.h: New entries for opcodes 0F3828, 0F382A,
537 0F3838, 0F383A, 0F387A, 0F387B, and 0F387C.
538 * i386-dis-evex-prefix.h: Reference mod_table[] for opcodes
539 0F3828_P_1 and 0F3838_P_1.
540 * i386-dis-evex-w.h: Reference mod_table[] for opcodes
541 0F382A_P_1, 0F383A_P_1, 0F387A, and 0F387B.
543 2020-07-14 Jan Beulich <jbeulich@suse.com>
545 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_3,
546 PREFIX_0FAE_REG_5_MOD_0, PREFIX_0FC3_MOD_0, PREFIX_0F38C8,
547 PREFIX_0F38C9, PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC,
548 PREFIX_0F38CD, PREFIX_0F38F9, PREFIX_0F3ACC, PREFIX_VEX_0F77,
549 PREFIX_VEX_0F38F2, PREFIX_VEX_0F38F3_REG_1,
550 PREFIX_VEX_0F38F3_REG_2, PREFIX_VEX_0F38F3_REG_3): Delete.
551 (MOD_0F38F9_PREFIX_0, VEX_LEN_0F77_P_0, VEX_LEN_0F38F2_P_0,
552 VEX_LEN_0F38F3_R_1_P_0, VEX_LEN_0F38F3_R_2_P_0,
553 VEX_LEN_0F38F3_R_3_P_0): Rename to ...
554 (MOD_0F38F9, VEX_LEN_0F77, VEX_LEN_0F38F2, VEX_LEN_0F38F3_R_1,
555 VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3): ... these respectively.
556 (reg_table, prefix_table, three_byte_table, vex_table,
557 vex_len_table, mod_table, rm_table): Replace / remove respective
559 (intel_operand_size, OP_E_register, OP_G): Avoid undue setting
560 of PREFIX_DATA in used_prefixes.
562 2020-07-14 Jan Beulich <jbeulich@suse.com>
564 * i386-dis.c (MOD_VEX_0F3A30_L_0_W_0, MOD_VEX_0F3A30_L_0_W_1,
565 MOD_VEX_0F3A31_L_0_W_0, MOD_VEX_0F3A31_L_0_W_1,
566 MOD_VEX_0F3A32_L_0_W_0, MOD_VEX_0F3A32_L_0_W_1,
567 MOD_VEX_0F3A33_L_0_W_0, MOD_VEX_0F3A33_L_0_W_1): Replace by ...
568 (MOD_VEX_0F3A30_L_0, MOD_VEX_0F3A31_L_0,
569 MOD_VEX_0F3A32_L_0, MOD_VEX_0F3A33_L_0): ... these.
570 (VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
571 VEX_W_0F3A33_L_0): Delete.
572 (dis386): Adjust "BW" description.
573 (vex_len_table): Refer to mod_table[] for opcodes 0F3A30,
574 0F3A31, 0F3A32, and 0F3A33.
575 (vex_w_table): Delete opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
577 (mod_table): Replace opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
580 2020-07-14 Jan Beulich <jbeulich@suse.com>
582 * i386-dis.c (PREFIX_0F6C, PREFIX_0F6D, PREFIX_0F73_REG_3,
583 PREFIX_0F73_REG_7, PREFIX_0F3810, PREFIX_0F3814, PREFIX_0F3815,
584 PREFIX_0F3817, PREFIX_0F3820, PREFIX_0F3821, PREFIX_0F3822,
585 PREFIX_0F3823, PREFIX_0F3824, PREFIX_0F3825, PREFIX_0F3828,
586 PREFIX_0F3829, PREFIX_0F382A, PREFIX_0F382B, PREFIX_0F3830,
587 PREFIX_0F3831, PREFIX_0F3832, PREFIX_0F3833, PREFIX_0F3834,
588 PREFIX_0F3835, PREFIX_0F3837, PREFIX_0F3838, PREFIX_0F3839,
589 PREFIX_0F383A, PREFIX_0F383B, PREFIX_0F383C, PREFIX_0F383D,
590 PREFIX_0F383E, PREFIX_0F383F, PREFIX_0F3840, PREFIX_0F3841,
591 PREFIX_0F3880, PREFIX_0F3881, PREFIX_0F3882, PREFIX_0F38CF,
592 PREFIX_0F38DB, PREFIX_0F38DC, PREFIX_0F38DD, PREFIX_0F38DE,
593 PREFIX_0F38DF, PREFIX_0F38F5, PREFIX_0F3A08, PREFIX_0F3A09,
594 PREFIX_0F3A0A, PREFIX_0F3A0B, PREFIX_0F3A0C, PREFIX_0F3A0D,
595 PREFIX_0F3A0E, PREFIX_0F3A14, PREFIX_0F3A15, PREFIX_0F3A16,
596 PREFIX_0F3A17, PREFIX_0F3A20, PREFIX_0F3A21, PREFIX_0F3A22,
597 PREFIX_0F3A40, PREFIX_0F3A41, PREFIX_0F3A42, PREFIX_0F3A44,
598 PREFIX_0F3A60, PREFIX_0F3A61, PREFIX_0F3A62, PREFIX_0F3A63,
599 PREFIX_0F3ACE, PREFIX_0F3ACF, PREFIX_0F3ADF, PREFIX_VEX_0F60,
600 PREFIX_VEX_0F61, PREFIX_VEX_0F62, PREFIX_VEX_0F63,
601 PREFIX_VEX_0F64, PREFIX_VEX_0F65, PREFIX_VEX_0F66,
602 PREFIX_VEX_0F67, PREFIX_VEX_0F68, PREFIX_VEX_0F69,
603 PREFIX_VEX_0F6A, PREFIX_VEX_0F6B, PREFIX_VEX_0F6C,
604 PREFIX_VEX_0F6D, PREFIX_VEX_0F6E, PREFIX_VEX_0F71_REG_2,
605 PREFIX_VEX_0F71_REG_4, PREFIX_VEX_0F71_REG_6,
606 PREFIX_VEX_0F72_REG_2, PREFIX_VEX_0F72_REG_4,
607 PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
608 PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
609 PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74,
610 PREFIX_VEX_0F75, PREFIX_VEX_0F76, PREFIX_VEX_0FC4,
611 PREFIX_VEX_0FC5, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
612 PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
613 PREFIX_VEX_0FD6, PREFIX_VEX_0FD7, PREFIX_VEX_0FD8,
614 PREFIX_VEX_0FD9, PREFIX_VEX_0FDA, PREFIX_VEX_0FDB,
615 PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
616 PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
617 PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
618 PREFIX_VEX_0FE5, PREFIX_VEX_0FE7, PREFIX_VEX_0FE8,
619 PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
620 PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
621 PREFIX_VEX_0FEF, PREFIX_VEX_0FF1, PREFIX_VEX_0FF2,
622 PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
623 PREFIX_VEX_0FF6, PREFIX_VEX_0FF7, PREFIX_VEX_0FF8,
624 PREFIX_VEX_0FF9, PREFIX_VEX_0FFA, PREFIX_VEX_0FFB,
625 PREFIX_VEX_0FFC, PREFIX_VEX_0FFD, PREFIX_VEX_0FFE,
626 PREFIX_VEX_0F3800, PREFIX_VEX_0F3801, PREFIX_VEX_0F3802,
627 PREFIX_VEX_0F3803, PREFIX_VEX_0F3804, PREFIX_VEX_0F3805,
628 PREFIX_VEX_0F3806, PREFIX_VEX_0F3807, PREFIX_VEX_0F3808,
629 PREFIX_VEX_0F3809, PREFIX_VEX_0F380A, PREFIX_VEX_0F380B,
630 PREFIX_VEX_0F380C, PREFIX_VEX_0F380D, PREFIX_VEX_0F380E,
631 PREFIX_VEX_0F380F, PREFIX_VEX_0F3813, PREFIX_VEX_0F3816,
632 PREFIX_VEX_0F3817, PREFIX_VEX_0F3818, PREFIX_VEX_0F3819,
633 PREFIX_VEX_0F381A, PREFIX_VEX_0F381C, PREFIX_VEX_0F381D,
634 PREFIX_VEX_0F381E, PREFIX_VEX_0F3820, PREFIX_VEX_0F3821,
635 PREFIX_VEX_0F3822, PREFIX_VEX_0F3823, PREFIX_VEX_0F3824,
636 PREFIX_VEX_0F3825, PREFIX_VEX_0F3828, PREFIX_VEX_0F3829,
637 PREFIX_VEX_0F382A, PREFIX_VEX_0F382B, PREFIX_VEX_0F382C,
638 PREFIX_VEX_0F382D, PREFIX_VEX_0F382E, PREFIX_VEX_0F382F,
639 PREFIX_VEX_0F3830, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
640 PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
641 PREFIX_VEX_0F3836, PREFIX_VEX_0F3837, PREFIX_VEX_0F3838,
642 PREFIX_VEX_0F3839, PREFIX_VEX_0F383A, PREFIX_VEX_0F383B,
643 PREFIX_VEX_0F383C, PREFIX_VEX_0F383D, PREFIX_VEX_0F383E,
644 PREFIX_VEX_0F383F, PREFIX_VEX_0F3840, PREFIX_VEX_0F3841,
645 PREFIX_VEX_0F3845, PREFIX_VEX_0F3846, PREFIX_VEX_0F3847,
646 PREFIX_VEX_0F3858, PREFIX_VEX_0F3859, PREFIX_VEX_0F385A,
647 PREFIX_VEX_0F3878, PREFIX_VEX_0F3879, PREFIX_VEX_0F388C,
648 PREFIX_VEX_0F388E, PREFIX_VEX_0F3890, PREFIX_VEX_0F3891,
649 PREFIX_VEX_0F3892, PREFIX_VEX_0F3893, PREFIX_VEX_0F3896,
650 PREFIX_VEX_0F3897, PREFIX_VEX_0F3898, PREFIX_VEX_0F3899,
651 PREFIX_VEX_0F389A, PREFIX_VEX_0F389B, PREFIX_VEX_0F389C,
652 PREFIX_VEX_0F389D, PREFIX_VEX_0F389E, PREFIX_VEX_0F389F,
653 PREFIX_VEX_0F38A6, PREFIX_VEX_0F38A7, PREFIX_VEX_0F38A8,
654 PREFIX_VEX_0F38A9, PREFIX_VEX_0F38AA, PREFIX_VEX_0F38AB,
655 PREFIX_VEX_0F38AC, PREFIX_VEX_0F38AD, PREFIX_VEX_0F38AE,
656 PREFIX_VEX_0F38AF, PREFIX_VEX_0F38B6, PREFIX_VEX_0F38B7,
657 PREFIX_VEX_0F38B8, PREFIX_VEX_0F38B9, PREFIX_VEX_0F38BA,
658 PREFIX_VEX_0F38BB, PREFIX_VEX_0F38BC, PREFIX_VEX_0F38BD,
659 PREFIX_VEX_0F38BE, PREFIX_VEX_0F38BF, PREFIX_VEX_0F38CF,
660 PREFIX_VEX_0F38DB, PREFIX_VEX_0F38DC, PREFIX_VEX_0F38DD,
661 PREFIX_VEX_0F38DE, PREFIX_VEX_0F38DF, PREFIX_VEX_0F3A00,
662 PREFIX_VEX_0F3A01, PREFIX_VEX_0F3A02, PREFIX_VEX_0F3A04,
663 PREFIX_VEX_0F3A05, PREFIX_VEX_0F3A06, PREFIX_VEX_0F3A08,
664 PREFIX_VEX_0F3A09, PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B,
665 PREFIX_VEX_0F3A0C, PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E,
666 PREFIX_VEX_0F3A0F, PREFIX_VEX_0F3A14, PREFIX_VEX_0F3A15,
667 PREFIX_VEX_0F3A16, PREFIX_VEX_0F3A17, PREFIX_VEX_0F3A18,
668 PREFIX_VEX_0F3A19, PREFIX_VEX_0F3A1D, PREFIX_VEX_0F3A20,
669 PREFIX_VEX_0F3A21, PREFIX_VEX_0F3A22, PREFIX_VEX_0F3A30,
670 PREFIX_VEX_0F3A31, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3A33,
671 PREFIX_VEX_0F3A38, PREFIX_VEX_0F3A39, PREFIX_VEX_0F3A40,
672 PREFIX_VEX_0F3A41, PREFIX_VEX_0F3A42, PREFIX_VEX_0F3A44,
673 PREFIX_VEX_0F3A46, PREFIX_VEX_0F3A48, PREFIX_VEX_0F3A49,
674 PREFIX_VEX_0F3A4A, PREFIX_VEX_0F3A4B, PREFIX_VEX_0F3A4C,
675 PREFIX_VEX_0F3A5C, PREFIX_VEX_0F3A5D, PREFIX_VEX_0F3A5E,
676 PREFIX_VEX_0F3A5F, PREFIX_VEX_0F3A60, PREFIX_VEX_0F3A61,
677 PREFIX_VEX_0F3A62, PREFIX_VEX_0F3A63, PREFIX_VEX_0F3A68,
678 PREFIX_VEX_0F3A69, PREFIX_VEX_0F3A6A, PREFIX_VEX_0F3A6B,
679 PREFIX_VEX_0F3A6C, PREFIX_VEX_0F3A6D, PREFIX_VEX_0F3A6E,
680 PREFIX_VEX_0F3A6F, PREFIX_VEX_0F3A78, PREFIX_VEX_0F3A79,
681 PREFIX_VEX_0F3A7A, PREFIX_VEX_0F3A7B, PREFIX_VEX_0F3A7C,
682 PREFIX_VEX_0F3A7D, PREFIX_VEX_0F3A7E, PREFIX_VEX_0F3A7F,
683 PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF, PREFIX_VEX_0F3ADF,
684 PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F66,
685 PREFIX_EVEX_0F6E, PREFIX_EVEX_0F71_REG_2,
686 PREFIX_EVEX_0F71_REG_4, PREFIX_EVEX_0F71_REG_6,
687 PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
688 PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
689 PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
690 PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_6,
691 PREFIX_EVEX_0F73_REG_7, PREFIX_EVEX_0F74, PREFIX_EVEX_0F75,
692 PREFIX_EVEX_0F76, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5,
693 PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF,
694 PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB,
695 PREFIX_EVEX_0FEF, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3816,
696 PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B,
697 PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F382C,
698 PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
699 PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F,
700 PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843,
701 PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846,
702 PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D,
703 PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3850,
704 PREFIX_EVEX_0F3851, PREFIX_EVEX_0F3854, PREFIX_EVEX_0F3855,
705 PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B,
706 PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863, PREFIX_EVEX_0F3864,
707 PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3866, PREFIX_EVEX_0F3870,
708 PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3875,
709 PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387A,
710 PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387D,
711 PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3883,
712 PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
713 PREFIX_EVEX_0F388B, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F388F,
714 PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892,
715 PREFIX_EVEX_0F3893, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1,
716 PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38B4,
717 PREFIX_EVEX_0F38B5, PREFIX_EVEX_0F38C4,
718 PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2,
719 PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6,
720 PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2,
721 PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6,
722 PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB,
723 PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00,
724 PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A05,
725 PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A,
726 PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15,
727 PREFIX_EVEX_0F3A16, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18,
728 PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B,
729 PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A20,
730 PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A22, PREFIX_EVEX_0F3A23,
731 PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27,
732 PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A,
733 PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F,
734 PREFIX_EVEX_0F3A42, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A50,
735 PREFIX_EVEX_0F3A51, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55,
736 PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66,
737 PREFIX_EVEX_0F3A67, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
738 PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73): Delete.
739 (MOD_0F382A_PREFIX_2, MOD_0F38F5_PREFIX_2,
740 MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
741 MOD_VEX_0F381A_PREFIX_2, MOD_VEX_0F382A_PREFIX_2,
742 MOD_VEX_0F382C_PREFIX_2, MOD_VEX_0F382D_PREFIX_2,
743 MOD_VEX_0F382E_PREFIX_2, MOD_VEX_0F382F_PREFIX_2,
744 MOD_VEX_0F385A_PREFIX_2, MOD_VEX_0F388C_PREFIX_2,
745 MOD_VEX_0F388E_PREFIX_2, MOD_VEX_W_0_0F3A30_P_2_LEN_0,
746 MOD_VEX_W_1_0F3A30_P_2_LEN_0, MOD_VEX_W_0_0F3A31_P_2_LEN_0,
747 MOD_VEX_W_1_0F3A31_P_2_LEN_0, MOD_VEX_W_0_0F3A32_P_2_LEN_0,
748 MOD_VEX_W_1_0F3A32_P_2_LEN_0, MOD_VEX_W_0_0F3A33_P_2_LEN_0,
749 MOD_VEX_W_1_0F3A33_P_2_LEN_0, MOD_EVEX_0F381A_P_2_W_0,
750 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
751 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
752 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0,
753 MOD_EVEX_0F385B_P_2_W_1, VEX_LEN_0F6E_P_2,
754 VEX_LEN_0FC4_P_2, VEX_LEN_0FC5_P_2, VEX_LEN_0FD6_P_2,
755 VEX_LEN_0FF7_P_2, VEX_LEN_0F3816_P_2, VEX_LEN_0F3819_P_2,
756 VEX_LEN_0F381A_P_2_M_0, VEX_LEN_0F3836_P_2,
757 VEX_LEN_0F3841_P_2, VEX_LEN_0F385A_P_2_M_0,
758 VEX_LEN_0F38DB_P_2, VEX_LEN_0F3A00_P_2, VEX_LEN_0F3A01_P_2,
759 VEX_LEN_0F3A06_P_2, VEX_LEN_0F3A14_P_2, VEX_LEN_0F3A15_P_2,
760 VEX_LEN_0F3A16_P_2, VEX_LEN_0F3A17_P_2, VEX_LEN_0F3A18_P_2,
761 VEX_LEN_0F3A19_P_2, VEX_LEN_0F3A20_P_2, VEX_LEN_0F3A21_P_2,
762 VEX_LEN_0F3A22_P_2, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A31_P_2,
763 VEX_LEN_0F3A32_P_2, VEX_LEN_0F3A33_P_2, VEX_LEN_0F3A38_P_2,
764 VEX_LEN_0F3A39_P_2, VEX_LEN_0F3A41_P_2, VEX_LEN_0F3A46_P_2,
765 VEX_LEN_0F3A60_P_2, VEX_LEN_0F3A61_P_2, VEX_LEN_0F3A62_P_2,
766 VEX_LEN_0F3A63_P_2, VEX_LEN_0F3ADF_P_2, EVEX_LEN_0F6E_P_2,
767 EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2, EVEX_LEN_0FD6_P_2,
768 EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3819_P_2_W_0,
769 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0_M_0,
770 EVEX_LEN_0F381A_P_2_W_1_M_0, EVEX_LEN_0F381B_P_2_W_0_M_0,
771 EVEX_LEN_0F381B_P_2_W_1_M_0, EVEX_LEN_0F3836_P_2,
772 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
773 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0,
774 EVEX_LEN_0F38C6_REG_1_PREFIX_2, EVEX_LEN_0F38C6_REG_2_PREFIX_2,
775 EVEX_LEN_0F38C6_REG_5_PREFIX_2, EVEX_LEN_0F38C6_REG_6_PREFIX_2,
776 EVEX_LEN_0F38C7_R_1_P_2_W_0, EVEX_LEN_0F38C7_R_1_P_2_W_1,
777 EVEX_LEN_0F38C7_R_2_P_2_W_0, EVEX_LEN_0F38C7_R_2_P_2_W_1,
778 EVEX_LEN_0F38C7_R_5_P_2_W_0, EVEX_LEN_0F38C7_R_5_P_2_W_1,
779 EVEX_LEN_0F38C7_R_6_P_2_W_0, EVEX_LEN_0F38C7_R_6_P_2_W_1,
780 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1,
781 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
782 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A18_P_2_W_0,
783 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
784 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
785 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
786 EVEX_LEN_0F3A1B_P_2_W_1, EVEX_LEN_0F3A20_P_2,
787 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2,
788 EVEX_LEN_0F3A23_P_2_W_0, EVEX_LEN_0F3A23_P_2_W_1,
789 EVEX_LEN_0F3A38_P_2_W_0, EVEX_LEN_0F3A38_P_2_W_1,
790 EVEX_LEN_0F3A39_P_2_W_0, EVEX_LEN_0F3A39_P_2_W_1,
791 EVEX_LEN_0F3A3A_P_2_W_0, EVEX_LEN_0F3A3A_P_2_W_1,
792 EVEX_LEN_0F3A3B_P_2_W_0, EVEX_LEN_0F3A3B_P_2_W_1,
793 EVEX_LEN_0F3A43_P_2_W_0, EVEX_LEN_0F3A43_P_2_W_1
794 VEX_W_0F380C_P_2, VEX_W_0F380D_P_2, VEX_W_0F380E_P_2,
795 VEX_W_0F380F_P_2, VEX_W_0F3813_P_2, VEX_W_0F3816_P_2,
796 VEX_W_0F3818_P_2, VEX_W_0F3819_P_2,
797 VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F382C_P_2_M_0,
798 VEX_W_0F382D_P_2_M_0, VEX_W_0F382E_P_2_M_0,
799 VEX_W_0F382F_P_2_M_0, VEX_W_0F3836_P_2,
800 VEX_W_0F3846_P_2, VEX_W_0F3858_P_2, VEX_W_0F3859_P_2,
801 VEX_W_0F385A_P_2_M_0_L_0, VEX_W_0F3878_P_2,
802 VEX_W_0F3879_P_2, VEX_W_0F38CF_P_2, VEX_W_0F3A00_P_2,
803 VEX_W_0F3A01_P_2, VEX_W_0F3A02_P_2, VEX_W_0F3A04_P_2,
804 VEX_W_0F3A05_P_2, VEX_W_0F3A06_P_2_L_0,
805 VEX_W_0F3A18_P_2_L_0, VEX_W_0F3A19_P_2_L_0,
806 VEX_W_0F3A1D_P_2, VEX_W_0F3A30_P_2_LEN_0,
807 VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0,
808 VEX_W_0F3A33_P_2_LEN_0, VEX_W_0F3A38_P_2_L_0,
809 VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0,
810 VEX_W_0F3A4A_P_2, VEX_W_0F3A4B_P_2, VEX_W_0F3A4C_P_2,
811 VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2, EVEX_W_0F66_P_2,
812 EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2,
813 EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2,
814 EVEX_W_0F76_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE7_P_2,
815 EVEX_W_0F380D_P_2, EVEX_W_0F3819_P_2,
816 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2,
817 EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
818 EVEX_W_0F3837_P_2, EVEX_W_0F3859_P_2,
819 EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2,
820 EVEX_W_0F3870_P_2, EVEX_W_0F387A_P_2,
821 EVEX_W_0F387B_P_2, EVEX_W_0F3883_P_2,
822 EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2,
823 EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
824 EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2,
825 EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2,
826 EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
827 EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
828 EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2,
829 EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2,
830 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
831 EVEX_W_0F3A1B_P_2, EVEX_W_0F3A21_P_2,
832 EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2,
833 EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
834 EVEX_W_0F3A3B_P_2, EVEX_W_0F3A42_P_2,
835 EVEX_W_0F3A43_P_2, EVEX_W_0F3A70_P_2,
836 EVEX_W_0F3A72_P_2): Rename to ...
837 (MOD_0F382A, MOD_0F38F5, MOD_VEX_0FD7, MOD_VEX_0FE7,
838 MOD_VEX_0F381A, MOD_VEX_0F382A, MOD_VEX_0F382C, MOD_VEX_0F382D,
839 MOD_VEX_0F382E, MOD_VEX_0F382F, MOD_VEX_0F385A, MOD_VEX_0F388C,
840 MOD_VEX_0F388E, MOD_VEX_0F3A30_L_0_W_0,
841 MOD_VEX_0F3A30_L_0_W_1, MOD_VEX_0F3A31_L_0_W_0,
842 MOD_VEX_0F3A31_L_0_W_1, MOD_VEX_0F3A32_L_0_W_0,
843 MOD_VEX_0F3A32_L_0_W_1, MOD_VEX_0F3A33_L_0_W_0,
844 MOD_VEX_0F3A33_L_0_W_1, MOD_EVEX_0F381A_W_0,
845 MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0, MOD_EVEX_0F381B_W_1,
846 MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1, MOD_EVEX_0F385B_W_0,
847 MOD_EVEX_0F385B_W_1, VEX_LEN_0F6E, VEX_LEN_0FC4, VEX_LEN_0FC5,
848 VEX_LEN_0FD6, VEX_LEN_0FF7, VEX_LEN_0F3816, VEX_LEN_0F3819,
849 VEX_LEN_0F381A_M_0, VEX_LEN_0F3836, VEX_LEN_0F3841,
850 VEX_LEN_0F385A_M_0, VEX_LEN_0F38DB, VEX_LEN_0F3A00,
851 VEX_LEN_0F3A01, VEX_LEN_0F3A06, VEX_LEN_0F3A14, VEX_LEN_0F3A15,
852 VEX_LEN_0F3A16, VEX_LEN_0F3A17, VEX_LEN_0F3A18, VEX_LEN_0F3A19,
853 VEX_LEN_0F3A20, VEX_LEN_0F3A21, VEX_LEN_0F3A22, VEX_LEN_0F3A30,
854 VEX_LEN_0F3A31, VEX_LEN_0F3A32, VEX_LEN_0F3A33, VEX_LEN_0F3A38,
855 VEX_LEN_0F3A39, VEX_LEN_0F3A41, VEX_LEN_0F3A46, VEX_LEN_0F3A60,
856 VEX_LEN_0F3A61, VEX_LEN_0F3A62, VEX_LEN_0F3A63, VEX_LEN_0F3ADF,
857 EVEX_LEN_0F6E, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
858 EVEX_LEN_0F3816, EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
859 EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
860 EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
861 EVEX_LEN_0F3836, EVEX_LEN_0F385A_W_0_M_0,
862 EVEX_LEN_0F385A_W_1_M_0, EVEX_LEN_0F385B_W_0_M_0,
863 EVEX_LEN_0F385B_W_1_M_0, EVEX_LEN_0F38C6_R_1_M_0,
864 EVEX_LEN_0F38C6_R_2_M_0, EVEX_LEN_0F38C6_R_5_M_0,
865 EVEX_LEN_0F38C6_R_6_M_0, EVEX_LEN_0F38C7_R_1_M_0_W_0,
866 EVEX_LEN_0F38C7_R_1_M_0_W_1, EVEX_LEN_0F38C7_R_2_M_0_W_0,
867 EVEX_LEN_0F38C7_R_2_M_0_W_1, EVEX_LEN_0F38C7_R_5_M_0_W_0,
868 EVEX_LEN_0F38C7_R_5_M_0_W_1, EVEX_LEN_0F38C7_R_6_M_0_W_0,
869 EVEX_LEN_0F38C7_R_6_M_0_W_1, EVEX_LEN_0F3A00_W_1,
870 EVEX_LEN_0F3A01_W_1, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
871 EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A18_W_0,
872 EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
873 EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0,
874 EVEX_LEN_0F3A1A_W_1, EVEX_LEN_0F3A1B_W_0,
875 EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A20, EVEX_LEN_0F3A21_W_0,
876 EVEX_LEN_0F3A22, EVEX_LEN_0F3A23_W_0, EVEX_LEN_0F3A23_W_1,
877 EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
878 EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1,
879 EVEX_LEN_0F3A3A_W_0, EVEX_LEN_0F3A3A_W_1,
880 EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
881 EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1
882 VEX_W_0F380C, VEX_W_0F380D, VEX_W_0F380E, VEX_W_0F380F,
883 VEX_W_0F3813, VEX_W_0F3816_L_1, VEX_W_0F3818,
884 VEX_W_0F3819_L_1, VEX_W_0F381A_M_0_L_1, VEX_W_0F382C_M_0,
885 VEX_W_0F382D_M_0, VEX_W_0F382E_M_0, VEX_W_0F382F_M_0,
886 VEX_W_0F3836, VEX_W_0F3846, VEX_W_0F3858, VEX_W_0F3859,
887 VEX_W_0F385A_M_0_L_0, VEX_W_0F3878, VEX_W_0F3879,
888 VEX_W_0F38CF, VEX_W_0F3A00_L_1, VEX_W_0F3A01_L_1,
889 VEX_W_0F3A02, VEX_W_0F3A04, VEX_W_0F3A05, VEX_W_0F3A06_L_1,
890 VEX_W_0F3A18_L_1, VEX_W_0F3A19_L_1, VEX_W_0F3A1D,
891 VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
892 VEX_W_0F3A33_L_0, VEX_W_0F3A38_L_1, VEX_W_0F3A39_L_1,
893 VEX_W_0F3A46_L_1, VEX_W_0F3A4A, VEX_W_0F3A4B, VEX_W_0F3A4C,
894 VEX_W_0F3ACE, VEX_W_0F3ACF, EVEX_W_0F66, EVEX_W_0F72_R_2,
895 EVEX_W_0F72_R_6, EVEX_W_0F73_R_2, EVEX_W_0F73_R_6,
896 EVEX_W_0F76, EVEX_W_0FD6_L_0, EVEX_W_0FE7, EVEX_W_0F380D,
897 EVEX_W_0F3819, EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F381E,
898 EVEX_W_0F381F, EVEX_W_0F3837, EVEX_W_0F3859, EVEX_W_0F385A,
899 EVEX_W_0F385B, EVEX_W_0F3870, EVEX_W_0F387A, EVEX_W_0F387B,
900 EVEX_W_0F3883, EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1,
901 EVEX_W_0F38A3, EVEX_W_0F38C7_R_1_M_0,
902 EVEX_W_0F38C7_R_2_M_0, EVEX_W_0F38C7_R_5_M_0,
903 EVEX_W_0F38C7_R_6_M_0, EVEX_W_0F3A00, EVEX_W_0F3A01,
904 EVEX_W_0F3A05, EVEX_W_0F3A08, EVEX_W_0F3A09, EVEX_W_0F3A0A,
905 EVEX_W_0F3A0B, EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A,
906 EVEX_W_0F3A1B, EVEX_W_0F3A21, EVEX_W_0F3A23, EVEX_W_0F3A38,
907 EVEX_W_0F3A39, EVEX_W_0F3A3A, EVEX_W_0F3A3B, EVEX_W_0F3A42,
908 EVEX_W_0F3A43, EVEX_W_0F3A70, EVEX_W_0F3A72): ... these
910 (dis386_twobyte, three_byte_table, vex_table, vex_len_table,
911 vex_w_table, mod_table): Replace / remove respective entries.
912 (print_insn): Move up dp->prefix_requirement handling. Handle
914 * i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-mod.h,
915 i386-dis-evex-prefix.h, i386-dis-evex-reg.h, i386-dis-evex-w.h:
916 Replace / remove respective entries.
918 2020-07-14 Jan Beulich <jbeulich@suse.com>
920 * i386-dis.c (PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
921 PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F): Delete.
922 (prefix_table): Add EXxEVexS operand to vcvttss2si, vcvttsd2si,
923 vcvtss2si, vcvtsd2si, vucomiss, and vucomisd table entries.
924 Retain X macro and PREFIX_OPCODE use from tjhe EVEX table for
926 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
927 0F2C, 0F2D, 0F2E, and 0F2F.
928 * i386-dis-evex-prefix.h: Delete opcode 0F2C, 0F2D, 0F2E, and
931 2020-07-14 Jan Beulich <jbeulich@suse.com>
933 * i386-dis.c (OP_VexR, VexScalarR): New.
934 (OP_EX_Vex, OP_XMM_Vex, EXdVexScalarS, EXqVexScalarS,
935 XMVexScalar, d_scalar_swap_mode, q_scalar_swap_mode,
936 need_vex_reg): Delete.
937 (prefix_table): Replace VexScalar by VexScalarR and
938 XMVexScalar by XMScalar for vmovss and vmovsd. Replace
939 EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
940 (vex_len_table): Replace EXqVexScalarS by EXqS.
941 (get_valid_dis386): Don't set need_vex_reg.
942 (print_insn): Don't initialize need_vex_reg.
943 (intel_operand_size, OP_E_memory): Drop d_scalar_swap_mode and
944 q_scalar_swap_mode cases.
945 (OP_EX): Don't check for d_scalar_swap_mode and
947 (OP_VEX): Done check need_vex_reg.
948 * i386-dis-evex-w.h: Replace VexScalar by VexScalarR and
949 XMVexScalar by XMScalar for vmovss and vmovsd. Replace
950 EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
952 2020-07-14 Jan Beulich <jbeulich@suse.com>
954 * i386-dis.c (Vex128, Vex256, vex128_mode, vex256_mode): Delete.
955 (VEX_W_0F381A_P_2_M_0, VEX_W_0F385A_P_2_M_0, VEX_W_0F3A06_P_2,
956 VEX_W_0F3A18_P_2, VEX_W_0F3A19_P_2, VEX_W_0F3A38_P_2,
957 VEX_W_0F3A39_P_2, VEX_W_0F3A46_P_2): Rename to ...
958 (VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F385A_P_2_M_0_L_0,
959 VEX_W_0F3A06_P_2_L_0, VEX_W_0F3A18_P_2_L_0,
960 VEX_W_0F3A19_P_2_L_0, VEX_W_0F3A38_P_2_L_0,
961 VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0): ... respectively.
962 (vex_table): Replace Vex128 by Vex.
963 (vex_len_table): Likewise. Adjust referenced enum names.
964 (vex_w_table): Replace Vex128 and Vex256 by Vex. Adjust
965 referenced enum names.
966 (OP_VEX): Drop vex128_mode and vex256_mode cases.
967 * i386-dis-evex-len.h (evex_len_table): Replace Vex128 by Vex.
969 2020-07-14 Jan Beulich <jbeulich@suse.com>
971 * i386-dis.c (dis386): "LW" description now applies to "DQ".
972 (putop): Handle "DQ". Don't handle "LW" anymore.
973 (prefix_table, mod_table): Replace %LW by %DQ.
974 * i386-dis-evex-len.h, i386-dis-evex-prefix.h: Likewise.
976 2020-07-14 Jan Beulich <jbeulich@suse.com>
978 * i386-dis.c (OP_E_memory): Move xmm_mw_mode, xmm_mb_mode,
979 dqd_mode, xmm_md_mode, d_mode, d_swap_mode, and
980 d_scalar_swap_mode case handling. Move shift adjsutment into
981 the case its applicable to.
983 2020-07-14 Jan Beulich <jbeulich@suse.com>
985 * i386-dis.c (EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2): Delete.
986 (EXbScalar, EXwScalar): Fold to ...
987 (EXbwUnit): ... this.
988 (b_scalar_mode, w_scalar_mode): Fold to ...
989 (bw_unit_mode): ... this.
990 (intel_operand_size, OP_E_memory): Replace b_scalar_mode /
991 w_scalar_mode handling by bw_unit_mode one.
992 * i386-dis-evex-w.h: Move entries for opcodes 0F3862 and 0F3863
994 * i386-dis-evex-prefix.h: ... here.
996 2020-07-14 Jan Beulich <jbeulich@suse.com>
998 * i386-dis.c (PCMPESTR_Fixup): Delete.
999 (dis386): Adjust "LQ" description.
1000 (prefix_table): Make %LQ apply to AT&T case only for cvtsi2ss,
1001 cvtsi2sd, ptwrite, vcvtsi2ss, and vcvtsi2sd. Replace use of
1002 PCMPESTR_Fixup by !%LQ and EXx for pcmpestrm, pcmpestri,
1003 vpcmpestrm, and vpcmpestri.
1004 (putop): Honor "cond" when handling LQ.
1005 * i386-dis-evex-prefix.h: Make %LQ apply to AT&T case only for
1006 vcvtsi2ss and vcvtusi2ss.
1007 * i386-dis-evex-w.h: Make %LQ apply to AT&T case only for
1008 vcvtsi2sd and vcvtusi2sd.
1010 2020-07-14 Jan Beulich <jbeulich@suse.com>
1012 * i386-dis.c (VCMP_Fixup, VCMP): Delete.
1013 (simd_cmp_op): Add const.
1014 (vex_cmp_op): Move up and drop initial 8 entries. Add const.
1015 (CMP_Fixup): Handle VEX case.
1016 (prefix_table): Replace VCMP by CMP.
1017 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Likewise.
1019 2020-07-14 Jan Beulich <jbeulich@suse.com>
1021 * i386-dis.c (MOVBE_Fixup): Delete.
1023 (prefix_table): Use Mv for movbe entries.
1025 2020-07-14 Jan Beulich <jbeulich@suse.com>
1027 * i386-dis.c (CRC32_Fixup): Delete.
1028 (prefix_table): Use Eb/Ev for crc32 entries.
1030 2020-07-14 Jan Beulich <jbeulich@suse.com>
1032 * i386-dis.c (OP_E_register, OP_G, OP_REG, CRC32_Fixup):
1033 Conditionalize invocations of "USED_REX (0)".
1035 2020-07-14 Jan Beulich <jbeulich@suse.com>
1037 * i386-dis.c (eBX, eCX, eDX, eSP, eBP, eSI, eDI, DL, BL, AH,
1038 CH, DH, BH, AX, DX): Delete.
1039 (OP_IMREG): Drop handling of eBX_reg, eCX_reg, eDX_reg, eSP_reg,
1040 eBP_reg, eSI_reg, eDI_reg, dl_reg, bl_reg, ah_reg, ch_reg,
1041 dh_reg, bh_reg, ax_reg, and dx_reg. Simplify what's left.
1043 2020-07-10 Lili Cui <lili.cui@intel.com>
1045 * i386-dis.c (TMM): New.
1048 (MVexSIBMEM): Likewise.
1049 (tmm_mode): Likewise.
1050 (vex_sibmem_mode): Likewise.
1051 (REG_VEX_0F3849_X86_64_P_0_W_0_M_1): Likewise.
1052 (MOD_VEX_0F3849_X86_64_P_0_W_0): Likewise.
1053 (MOD_VEX_0F3849_X86_64_P_2_W_0): Likewise.
1054 (MOD_VEX_0F3849_X86_64_P_3_W_0): Likewise.
1055 (MOD_VEX_0F384B_X86_64_P_1_W_0): Likewise.
1056 (MOD_VEX_0F384B_X86_64_P_2_W_0): Likewise.
1057 (MOD_VEX_0F384B_X86_64_P_3_W_0): Likewise.
1058 (MOD_VEX_0F385C_X86_64_P_1_W_0): Likewise.
1059 (MOD_VEX_0F385E_X86_64_P_0_W_0): Likewise.
1060 (MOD_VEX_0F385E_X86_64_P_1_W_0): Likewise.
1061 (MOD_VEX_0F385E_X86_64_P_2_W_0): Likewise.
1062 (MOD_VEX_0F385E_X86_64_P_3_W_0): Likewise.
1063 (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0): Likewise.
1064 (PREFIX_VEX_0F3849_X86_64): Likewise.
1065 (PREFIX_VEX_0F384B_X86_64): Likewise.
1066 (PREFIX_VEX_0F385C_X86_64): Likewise.
1067 (PREFIX_VEX_0F385E_X86_64): Likewise.
1068 (X86_64_VEX_0F3849): Likewise.
1069 (X86_64_VEX_0F384B): Likewise.
1070 (X86_64_VEX_0F385C): Likewise.
1071 (X86_64_VEX_0F385E): Likewise.
1072 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0): Likewise.
1073 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0): Likewise.
1074 (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0): Likewise.
1075 (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0): Likewise.
1076 (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0): Likewise.
1077 (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0): Likewise.
1078 (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0): Likewise.
1079 (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0): Likewise.
1080 (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0): Likewise.
1081 (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0): Likewise.
1082 (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0): Likewise.
1083 (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0): Likewise.
1084 (VEX_W_0F3849_X86_64_P_0): Likewise.
1085 (VEX_W_0F3849_X86_64_P_2): Likewise.
1086 (VEX_W_0F3849_X86_64_P_3): Likewise.
1087 (VEX_W_0F384B_X86_64_P_1): Likewise.
1088 (VEX_W_0F384B_X86_64_P_2): Likewise.
1089 (VEX_W_0F384B_X86_64_P_3): Likewise.
1090 (VEX_W_0F385C_X86_64_P_1): Likewise.
1091 (VEX_W_0F385E_X86_64_P_0): Likewise.
1092 (VEX_W_0F385E_X86_64_P_1): Likewise.
1093 (VEX_W_0F385E_X86_64_P_2): Likewise.
1094 (VEX_W_0F385E_X86_64_P_3): Likewise.
1095 (names_tmm): Likewise.
1096 (att_names_tmm): Likewise.
1097 (intel_operand_size): Handle void_mode.
1098 (OP_XMM): Handle tmm_mode.
1101 * i386-gen.c (cpu_flag_init): Add entries for CpuAMX_INT8,
1102 CpuAMX_BF16 and CpuAMX_TILE.
1103 (operand_type_shorthands): Add RegTMM.
1104 (operand_type_init): Likewise.
1105 (operand_types): Add Tmmword.
1106 (cpu_flag_init): Add CPU_AMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
1107 (cpu_flags): Add CpuAMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
1108 * i386-opc.h (CpuAMX_INT8): New.
1109 (CpuAMX_BF16): Likewise.
1110 (CpuAMX_TILE): Likewise.
1112 (Tmmword): Likewise.
1113 (i386_cpu_flags): Add cpuamx_int8, cpuamx_bf16 and cpuamx_tile.
1114 (i386_opcode_modifier): Extend width of fields vexvvvv and sib.
1115 (i386_operand_type): Add tmmword.
1116 * i386-opc.tbl: Add AMX instructions.
1117 * i386-reg.tbl: Add AMX registers.
1118 * i386-init.h: Regenerated.
1119 * i386-tbl.h: Likewise.
1121 2020-07-08 Jan Beulich <jbeulich@suse.com>
1123 * i386-dis.c (OP_LWPCB_E, OP_LWP_E): Delete.
1124 (REG_XOP_LWPCB, REG_XOP_LWP, REG_XOP_TBM_01, REG_XOP_TBM_02):
1126 (REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
1127 REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0): ... these
1129 (MOD_VEX_0FXOP_09_12, VEX_LEN_0FXOP_08_85, VEX_LEN_0FXOP_08_86,
1130 VEX_LEN_0FXOP_08_87, VEX_LEN_0FXOP_08_8E, VEX_LEN_0FXOP_08_8F,
1131 VEX_LEN_0FXOP_08_95, VEX_LEN_0FXOP_08_96, VEX_LEN_0FXOP_08_97,
1132 VEX_LEN_0FXOP_08_9E, VEX_LEN_0FXOP_08_9F, VEX_LEN_0FXOP_08_A3,
1133 VEX_LEN_0FXOP_08_A6, VEX_LEN_0FXOP_08_B6, VEX_LEN_0FXOP_08_C0,
1134 VEX_LEN_0FXOP_08_C1, VEX_LEN_0FXOP_08_C2, VEX_LEN_0FXOP_08_C3,
1135 VEX_LEN_0FXOP_09_01, VEX_LEN_0FXOP_09_02, VEX_LEN_0FXOP_09_12_M_1,
1136 VEX_LEN_0FXOP_09_90, VEX_LEN_0FXOP_09_91, VEX_LEN_0FXOP_09_92,
1137 VEX_LEN_0FXOP_09_93, VEX_LEN_0FXOP_09_94, VEX_LEN_0FXOP_09_95,
1138 VEX_LEN_0FXOP_09_96, VEX_LEN_0FXOP_09_97, VEX_LEN_0FXOP_09_98,
1139 VEX_LEN_0FXOP_09_99, VEX_LEN_0FXOP_09_9A, VEX_LEN_0FXOP_09_9B,
1140 VEX_LEN_0FXOP_09_C1, VEX_LEN_0FXOP_09_C2, VEX_LEN_0FXOP_09_C3,
1141 VEX_LEN_0FXOP_09_C6, VEX_LEN_0FXOP_09_C7, VEX_LEN_0FXOP_09_CB,
1142 VEX_LEN_0FXOP_09_D1, VEX_LEN_0FXOP_09_D2, VEX_LEN_0FXOP_09_D3,
1143 VEX_LEN_0FXOP_09_D6, VEX_LEN_0FXOP_09_D7, VEX_LEN_0FXOP_09_DB,
1144 VEX_LEN_0FXOP_09_E1, VEX_LEN_0FXOP_09_E2, VEX_LEN_0FXOP_09_E3,
1145 VEX_LEN_0FXOP_0A_12, VEX_W_0FXOP_08_85_L_0,
1146 VEX_W_0FXOP_08_86_L_0, VEX_W_0FXOP_08_87_L_0,
1147 VEX_W_0FXOP_08_8E_L_0, VEX_W_0FXOP_08_8F_L_0,
1148 VEX_W_0FXOP_08_95_L_0, VEX_W_0FXOP_08_96_L_0,
1149 VEX_W_0FXOP_08_97_L_0, VEX_W_0FXOP_08_9E_L_0,
1150 VEX_W_0FXOP_08_9F_L_0, VEX_W_0FXOP_08_A6_L_0,
1151 VEX_W_0FXOP_08_B6_L_0, VEX_W_0FXOP_08_C0_L_0,
1152 VEX_W_0FXOP_08_C1_L_0, VEX_W_0FXOP_08_C2_L_0,
1153 VEX_W_0FXOP_08_C3_L_0, VEX_W_0FXOP_08_CC_L_0,
1154 VEX_W_0FXOP_08_CD_L_0, VEX_W_0FXOP_08_CE_L_0,
1155 VEX_W_0FXOP_08_CF_L_0, VEX_W_0FXOP_08_EC_L_0,
1156 VEX_W_0FXOP_08_ED_L_0, VEX_W_0FXOP_08_EE_L_0,
1157 VEX_W_0FXOP_08_EF_L_0, VEX_W_0FXOP_09_C1_L_0,
1158 VEX_W_0FXOP_09_C2_L_0, VEX_W_0FXOP_09_C3_L_0,
1159 VEX_W_0FXOP_09_C6_L_0, VEX_W_0FXOP_09_C7_L_0,
1160 VEX_W_0FXOP_09_CB_L_0, VEX_W_0FXOP_09_D1_L_0,
1161 VEX_W_0FXOP_09_D2_L_0, VEX_W_0FXOP_09_D3_L_0,
1162 VEX_W_0FXOP_09_D6_L_0, VEX_W_0FXOP_09_D7_L_0,
1163 VEX_W_0FXOP_09_DB_L_0, VEX_W_0FXOP_09_E1_L_0,
1164 VEX_W_0FXOP_09_E2_L_0, VEX_W_0FXOP_09_E3_L_0): New enumerators.
1165 (reg_table): Re-order XOP entries. Adjust their operands.
1166 (xop_table): Replace 08_85, 08_86, 08_87, 08_8E, 08_8F, 08_95,
1167 08_96, 08_97, 08_9E, 08_9F, 08_A3, 08_A6, 08_B6, 08_C0, 08_C1,
1168 08_C2, 08_C3, 09_01, 09_02, 09_12, 09_90, 09_91, 09_92, 09_93,
1169 09_94, 09_95, 09_96, 09_97, 09_98, 09_99, 09_9A, 09_9B, 09_C1,
1170 09_C2, 09_C3, 09_C6, 09_C7, 09_CB, 09_D1, 09_D2, 09_D3, 09_D6,
1171 09_D7, 09_DB, 09_E1, 09_E2, 09_E3, and VEX_LEN_0FXOP_0A_12
1172 entries by references ...
1173 (vex_len_table): ... to resepctive new entries here. For several
1174 new and existing entries reference ...
1175 (vex_w_table): ... new entries here.
1176 (mod_table): New MOD_VEX_0FXOP_09_12 entry.
1178 2020-07-08 Jan Beulich <jbeulich@suse.com>
1180 * i386-dis.c (XMVexScalarI4): Define.
1181 (VEX_LEN_0F3A6A_P_2, VEX_LEN_0F3A6B_P_2, VEX_LEN_0F3A6E_P_2,
1182 VEX_LEN_0F3A6F_P_2, VEX_LEN_0F3A7A_P_2, VEX_LEN_0F3A7B_P_2,
1183 VEX_LEN_0F3A7E_P_2, VEX_LEN_0F3A7F_P_2): Delete.
1184 (vex_len_table): Move scalar FMA4 entries ...
1185 (prefix_table): ... here.
1186 (OP_REG_VexI4): Handle scalar_mode.
1187 * i386-opc.tbl: Use VexLIG for scalar FMA4 insns.
1188 * i386-tbl.h: Re-generate.
1190 2020-07-08 Jan Beulich <jbeulich@suse.com>
1192 * i386-dis.c (OP_Vex_2src_1, OP_Vex_2src_2, Vex_2src_1,
1193 Vex_2src_2): Delete.
1194 (OP_VexW, VexW): New.
1195 (xop_table): Use EXx for rotates by immediate. Use EXx and VexW
1196 for shifts and rotates by register.
1198 2020-07-08 Jan Beulich <jbeulich@suse.com>
1200 * i386-dis.c (OP_EX_VexImmW, OP_XMM_VexW, EXVexImmW, XMVexW,
1201 VEX_W_0F3A48_P_2, VEX_W_0F3A49_P_2, vex_w_done, get_vex_imm8,
1202 OP_EX_VexReg): Delete.
1203 (OP_VexI4, VexI4): New.
1204 (vex_w_table): Move vpermil2ps and vpermil2pd entries ...
1205 (prefix_table): ... here.
1206 (print_insn): Drop setting of vex_w_done.
1208 2020-07-08 Jan Beulich <jbeulich@suse.com>
1210 * i386-dis.c (OP_EX_VexW, EXVexW, EXdVexW, EXqVexW): Delete.
1211 (prefix_table, vex_len_table): Replace operands for FMA4 insns.
1212 (xop_table): Replace operands of 4-operand insns.
1213 (OP_REG_VexI4): Move VEX.W based operand swaping here.
1215 2020-07-07 Claudiu Zissulescu <claziss@synopsys.com>
1217 * arc-opc.c (insert_rbd): New function.
1220 * arc-tbl.h (vadd2, vadd4h, vmac2h, vmpy2h, vsub4h): Update
1223 2020-07-07 Jan Beulich <jbeulich@suse.com>
1225 * i386-dis.c (EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2,
1226 EVEX_W_0F3828_P_1, EVEX_W_0F3829_P_1, EVEX_W_0F3854_P_2,
1227 EVEX_W_0F3866_P_2, EVEX_W_0F3875_P_2, EVEX_W_0F387D_P_2,
1228 EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2, EVEX_W_0F3A3F_P_2):
1230 (putop): Handle "BW".
1231 * i386-dis-evex-w.h: Move entries for opcodes 0F3826, 0F3826,
1232 0F3828, 0F3829, 0F3854, 0F3866, 0F3875, 0F387D, 0F388D, 0F3A3E,
1234 * i386-dis-evex-prefix.h: ... here.
1236 2020-07-06 Jan Beulich <jbeulich@suse.com>
1238 * i386-dis.c (VEX_LEN_0FXOP_09_80, VEX_LEN_0FXOP_09_81): Delete.
1239 (VEX_LEN_0FXOP_09_82_W_0, VEX_LEN_0FXOP_09_83_W_0,
1240 VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81, VEX_W_0FXOP_09_82,
1241 VEX_W_0FXOP_09_83): New enumerators.
1242 (xop_table): Reference the above.
1243 (vex_len_table): Replace vfrczp* entries by vfrczs* ones.
1244 (vex_w_table): New VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81,
1245 VEX_W_0FXOP_09_82, and VEX_W_0FXOP_09_83 entries.
1246 (get_valid_dis386): Return bad_opcode for XOP.PP != 0.
1248 2020-07-06 Jan Beulich <jbeulich@suse.com>
1250 * i386-dis.c (EVEX_W_0F3838_P_1,
1251 EVEX_W_0F3839_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3855_P_2,
1252 EVEX_W_0F3868_P_3, EVEX_W_0F3871_P_2, EVEX_W_0F3873_P_2,
1253 EVEX_W_0F3A50_P_2, EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2,
1254 EVEX_W_0F3A57_P_2, EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2,
1255 EVEX_W_0F3A71_P_2, EVEX_W_0F3A73_P_2): Delete.
1256 (putop): Centralize management of last[]. Delete SAVE_LAST.
1257 * i386-dis-evex-w.h: Move entries for opcodes 0F3838, 0F3839,
1258 0F3840, 0F3855, 0F3868, 0F3871, 0F3873, 0F3A50, 0F3A51, 0F3A56,
1259 0F3A57, 0F3A66, 0F3A67, 0F3A71, and 0F3A73 ...
1260 * i386-dis-evex-prefix.h: here.
1262 2020-07-06 Jan Beulich <jbeulich@suse.com>
1264 * i386-dis.c (MOD_EVEX_0F381A_P_2_W_0, MOD_EVEX_0F381A_P_2_W_1,
1265 MOD_EVEX_0F381B_P_2_W_0, MOD_EVEX_0F381B_P_2_W_1,
1266 MOD_EVEX_0F385A_P_2_W_0, MOD_EVEX_0F385A_P_2_W_1,
1267 MOD_EVEX_0F385B_P_2_W_0, MOD_EVEX_0F385B_P_2_W_1): New
1269 (EVEX_LEN_0F381A_P_2_W_0, EVEX_LEN_0F381A_P_2_W_1,
1270 EVEX_LEN_0F381B_P_2_W_0, EVEX_LEN_0F381B_P_2_W_1,
1271 EVEX_LEN_0F385A_P_2_W_0, EVEX_LEN_0F385A_P_2_W_1,
1272 EVEX_LEN_0F385B_P_2_W_0, EVEX_LEN_0F385B_P_2_W_1): Rename to ...
1273 (EVEX_LEN_0F381A_P_2_W_0_M_0, EVEX_LEN_0F381A_P_2_W_1_M_0,
1274 EVEX_LEN_0F381B_P_2_W_0_M_0, EVEX_LEN_0F381B_P_2_W_1_M_0,
1275 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
1276 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0): ...
1277 these, respectively.
1278 * i386-dis-evex-len.h: Adjust comments.
1279 * i386-dis-evex-mod.h: New MOD_EVEX_0F381A_P_2_W_0,
1280 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
1281 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
1282 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0, and
1283 MOD_EVEX_0F385B_P_2_W_1 table entries.
1284 * i386-dis-evex-w.h: Reference mod_table[] for
1285 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2, and
1288 2020-07-06 Jan Beulich <jbeulich@suse.com>
1290 * i386-dis-evex-len.h (vbroadcastf32x8, vbroadcasti32x8,
1291 vinsertf32x8, vinsertf64x4, vextractf32x8, vextractf64x4): Use
1293 (vinserti32x8, vinserti64x4, vextracti32x8, vextracti64x4):
1294 Likewise. Mark 256-bit entries invalid.
1296 2020-07-06 Jan Beulich <jbeulich@suse.com>
1298 * i386-dis.c (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
1299 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
1300 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
1301 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
1302 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
1303 PREFIX_EVEX_0F382B): Delete.
1304 (EVEX_W_0F62_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6B_P_2,
1305 EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0FD2_P_2,
1306 EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FF2_P_2,
1307 EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2,
1308 EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F382B_P_2): Rename
1310 (EVEX_W_0F62, EVEX_W_0F6A, EVEX_W_0F6B, EVEX_W_0F6C,
1311 EVEX_W_0F6D, EVEX_W_0FD2, EVEX_W_0FD3, EVEX_W_0FD4,
1312 EVEX_W_0FF2, EVEX_W_0FF3, EVEX_W_0FF4, EVEX_W_0FFA,
1313 EVEX_W_0FFB, EVEX_W_0FFE, EVEX_W_0F382B): ... these
1315 * i386-dis-evex.h (evex_table): Reference VEX_W table entries
1316 for opcodes 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4,
1317 0FF2, 0FF3, 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
1318 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
1319 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
1320 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
1321 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
1322 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
1323 PREFIX_EVEX_0F382B): Remove table entries.
1324 * i386-dis-evex-w.h: Reference VEX table entries for opcodes
1325 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4, 0FF2, 0FF3,
1326 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
1328 2020-07-06 Jan Beulich <jbeulich@suse.com>
1330 * i386-dis.c (EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3836_P_2,
1331 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1): New
1333 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0F3816_P_2,
1334 EVEX_LEN_0F3836_P_2, EVEX_LEN_0F3A00_P_2_W_1, and
1335 EVEX_LEN_0F3A01_P_2_W_1 table entries.
1336 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
1339 2020-07-06 Jan Beulich <jbeulich@suse.com>
1341 * i386-dis.c (EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2,
1342 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
1343 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
1344 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2): New enumerators.
1345 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0FC4_P_2,
1346 EVEX_LEN_0FC5_P_2, EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2,
1347 EVEX_LEN_0F3A16_P_2, EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
1348 EVEX_LEN_0F3A21_P_2_W_0, and EVEX_LEN_0F3A22_P_2 table entries.
1349 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
1352 2020-07-06 Jan Beulich <jbeulich@suse.com>
1354 * i386-dis.c (PREFIX_EVEX_0F3A1D, EVEX_W_0F3A1D_P_2): Delete.
1355 (VEX_W_0F3813_P_2, VEX_W_0F3A1D_P_2): New enumerators.
1356 (prefix_table): Reference VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2
1358 (vex_w_table): New VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2 table
1360 * i386-dis-evex.h (evex_table): Reference VEX table entry for
1362 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F3A1D): Delete table
1364 * i386-dis-evex-w.h (EVEX_W_0F3A1D_P_2): Likewise.
1366 2020-07-06 Jan Beulich <jbeulich@suse.com>
1368 * i386-dis.c (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
1369 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
1370 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
1371 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
1372 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
1373 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
1374 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
1375 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
1376 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
1377 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
1378 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
1379 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
1380 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
1381 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
1382 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
1383 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
1384 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
1385 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
1386 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
1387 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
1388 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
1389 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
1390 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
1391 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
1392 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
1393 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
1394 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF,
1395 EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2, EVEX_W_0F3858_P_2,
1396 EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F3A04_P_2,
1397 EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2): Delete.
1398 (prefix_table): Add EXxEVexR to FMA table entries.
1399 (OP_Rounding): Move abort() invocation.
1400 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
1401 0F60, 0F61, 0F63, 0F67, 0F68, 0F69, 0FD1, 0FD5, 0FD8, 0FD9,
1402 0FDA, 0FDC, 0FDD, 0FDE, 0FE0, 0FE1, 0FE3, 0FE4, 0FE5, 0FE8,
1403 0FE9, 0FEA, 0FEC, 0FED, 0FEE, 0FF1, 0FF5, 0FF6, 0FF8, 0FF9,
1404 0FFC, 0FFD, 0F3800, 0F3804, 0F380B, 0F380C, 0F3818, 0F381C,
1405 0F381D, 0F383C, 0F383E, 0F3858, 0F3878, 0F3879, 0F3896, 0F3897,
1406 0F3898, 0F3899, 0F389C, 0F389D, 0F389E, 0F389F, 0F38A6, 0F38A7,
1407 0F38A8, 0F38A9, 0F38AC, 0F38AD, 0F38AE, 0F38AF, 0F38B6, 0F38B7,
1408 0F38B8, 0F38B9, 0F38BA, 0F38BB, 0F38BC, 0F38BD, 0F38BE, 0F38BF,
1409 0F38CF, 0F38DC, 0F38DD, 0F38DE, 0F38DF, 0F3A04, 0F3A0F, 0F3A44,
1411 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
1412 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
1413 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
1414 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
1415 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
1416 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
1417 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
1418 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
1419 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
1420 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
1421 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
1422 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
1423 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
1424 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
1425 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
1426 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
1427 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
1428 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
1429 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
1430 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
1431 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
1432 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
1433 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
1434 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
1435 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
1436 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
1437 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF):
1438 Delete table entries.
1439 * i386-dis-evex-w.h (EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2,
1440 EVEX_W_0F3858_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2,
1441 EVEX_W_0F3A04_P_2, EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2):
1444 2020-07-06 Jan Beulich <jbeulich@suse.com>
1446 * i386-dis.c (EXqScalarS): Delete.
1447 (vex_len_table): Replace EXqScalarS by EXqVexScalarS.
1448 * i386-dis-evex-w.h (vmovq): Use EXqVexScalarS.
1450 2020-07-06 Jan Beulich <jbeulich@suse.com>
1452 * i386-dis.c (safe-ctype.h): Include.
1453 (EXdScalar, EXqScalar): Delete.
1454 (d_scalar_mode, q_scalar_mode): Delete.
1455 (prefix_table, vex_len_table): Use EXxmm_md in place of
1456 EXdScalar and EXxmm_mq in place of EXqScalar.
1457 (intel_operand_size, OP_E_memory, OP_EX): Remove uses of
1458 d_scalar_mode and q_scalar_mode.
1459 * i386-dis-evex-w.h (vmovss): Use EXxmm_md.
1460 (vmovsd): Use EXxmm_mq.
1462 2020-07-06 Yuri Chornoivan <yurchor@ukr.net>
1465 * arc-dis.c: Fix spelling mistake.
1466 * po/opcodes.pot: Regenerate.
1468 2020-07-06 Nick Clifton <nickc@redhat.com>
1470 * po/pt_BR.po: Updated Brazilian Portugugese translation.
1471 * po/uk.po: Updated Ukranian translation.
1473 2020-07-04 Nick Clifton <nickc@redhat.com>
1475 * configure: Regenerate.
1476 * po/opcodes.pot: Regenerate.
1478 2020-07-04 Nick Clifton <nickc@redhat.com>
1480 Binutils 2.35 branch created.
1482 2020-07-02 H.J. Lu <hongjiu.lu@intel.com>
1484 * i386-gen.c (opcode_modifiers): Add VexSwapSources.
1485 * i386-opc.h (VexSwapSources): New.
1486 (i386_opcode_modifier): Add vexswapsources.
1487 * i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions
1488 with two source operands swapped.
1489 * i386-tbl.h: Regenerated.
1491 2020-06-30 Nelson Chu <nelson.chu@sifive.com>
1493 * riscv-dis.c (print_insn_args, case 'E'): Updated. Let the
1494 unprivileged CSR can also be initialized.
1496 2020-06-29 Alan Modra <amodra@gmail.com>
1498 * arm-dis.c: Use C style comments.
1499 * cr16-opc.c: Likewise.
1500 * ft32-dis.c: Likewise.
1501 * moxie-opc.c: Likewise.
1502 * tic54x-dis.c: Likewise.
1503 * s12z-opc.c: Remove useless comment.
1504 * xgate-dis.c: Likewise.
1506 2020-06-26 H.J. Lu <hongjiu.lu@intel.com>
1508 * i386-opc.tbl: Add a blank line.
1510 2020-06-26 H.J. Lu <hongjiu.lu@intel.com>
1512 * i386-gen.c (opcode_modifiers): Replace VecSIB with SIB.
1513 (VecSIB128): Renamed to ...
1515 (VecSIB256): Renamed to ...
1517 (VecSIB512): Renamed to ...
1519 (VecSIB): Renamed to ...
1521 (i386_opcode_modifier): Replace vecsib with sib.
1522 * i386-opc.tbl (VecSIB128): New.
1523 (VecSIB256): Likewise.
1524 (VecSIB512): Likewise.
1525 Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VecSIB128, VecSIB256
1526 and VecSIB512, respectively.
1528 2020-06-26 Jan Beulich <jbeulich@suse.com>
1530 * i386-dis.c: Adjust description of I macro.
1531 (x86_64_table): Drop use of I.
1532 (float_mem): Replace use of I.
1533 (putop): Remove handling of I. Adjust setting/clearing of "alt".
1535 2020-06-26 Jan Beulich <jbeulich@suse.com>
1537 * i386-dis.c: (print_insn): Avoid straight assignment to
1538 priv.orig_sizeflag when processing -M sub-options.
1540 2020-06-25 Jan Beulich <jbeulich@suse.com>
1542 * i386-dis.c: Adjust description of J macro.
1543 (dis386, x86_64_table, mod_table): Replace J.
1544 (putop): Remove handling of J.
1546 2020-06-25 Jan Beulich <jbeulich@suse.com>
1548 * i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt.
1550 2020-06-25 Jan Beulich <jbeulich@suse.com>
1552 * i386-dis.c: Adjust description of "LQ" macro.
1553 (dis386_twobyte): Use LQ for sysret.
1554 (putop): Adjust handling of LQ.
1556 2020-06-22 Nelson Chu <nelson.chu@sifive.com>
1558 * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
1559 * riscv-dis.c: Include elfxx-riscv.h.
1561 2020-06-18 H.J. Lu <hongjiu.lu@intel.com>
1563 * i386-dis.c (prefix_table): Revert the last vmgexit change.
1565 2020-06-17 Lili Cui <lili.cui@intel.com>
1567 * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
1569 2020-06-14 H.J. Lu <hongjiu.lu@intel.com>
1572 * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
1573 * i386-opc.tbl: Likewise.
1574 * i386-tbl.h: Regenerated.
1576 2020-06-12 Nelson Chu <nelson.chu@sifive.com>
1578 * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
1580 2020-06-11 Alex Coplan <alex.coplan@arm.com>
1582 * aarch64-opc.c (SYSREG): New macro for describing system registers.
1583 (SR_CORE): Likewise.
1584 (SR_FEAT): Likewise.
1586 (SR_V8_1): Likewise.
1587 (SR_V8_2): Likewise.
1588 (SR_V8_3): Likewise.
1589 (SR_V8_4): Likewise.
1592 (SR_SSBS): Likewise.
1594 (SR_ID_PFR2): Likewise.
1595 (SR_PROFILE): Likewise.
1596 (SR_MEMTAG): Likewise.
1597 (SR_SCXTNUM): Likewise.
1598 (aarch64_sys_regs): Refactor to store feature information in the table.
1599 (aarch64_sys_reg_supported_p): Collapse logic for system registers
1600 that now describe their own features.
1601 (aarch64_pstatefield_supported_p): Likewise.
1603 2020-06-09 H.J. Lu <hongjiu.lu@intel.com>
1605 * i386-dis.c (prefix_table): Fix a typo in comments.
1607 2020-06-09 Jan Beulich <jbeulich@suse.com>
1609 * i386-dis.c (rex_ignored): Delete.
1610 (ckprefix): Drop rex_ignored initialization.
1611 (get_valid_dis386): Drop setting of rex_ignored.
1612 (print_insn): Drop checking of rex_ignored. Don't record data
1613 size prefix as used with VEX-and-alike encodings.
1615 2020-06-09 Jan Beulich <jbeulich@suse.com>
1617 * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
1618 MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
1619 (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
1620 (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
1621 (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
1622 VEX_0F12, and VEX_0F16.
1623 (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
1624 VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
1625 (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
1626 from movlps and movhlps. New MOD_0F12_PREFIX_2,
1627 MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
1628 MOD_VEX_0F16_PREFIX_2 entries.
1630 2020-06-09 Jan Beulich <jbeulich@suse.com>
1632 * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
1633 MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
1634 (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1635 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
1636 PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
1637 PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
1638 EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
1639 EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
1640 EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
1641 EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
1642 EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
1643 EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
1644 EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
1645 EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
1646 EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
1647 EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
1648 EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
1649 EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
1650 EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
1651 EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
1652 EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
1653 EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
1654 EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
1655 EVEX_W_0FC6_P_2): Delete.
1656 (print_insn): Add EVEX.W vs embedded prefix consistency check
1657 to prefix validation.
1658 * i386-dis-evex.h (evex_table): Don't further descend for
1659 vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
1660 and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
1662 * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
1663 * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
1664 vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
1665 vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
1666 2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
1667 Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1668 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
1669 PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
1670 PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
1671 * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
1672 EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
1673 EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
1674 EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
1675 EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
1676 EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
1677 EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
1678 EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
1679 EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
1680 EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
1681 EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
1682 EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
1683 EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
1684 EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
1685 EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
1686 EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
1687 EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
1688 EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
1690 2020-06-09 Jan Beulich <jbeulich@suse.com>
1692 * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
1693 vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
1694 (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
1696 (print_insn): Drop pointless check against bad_opcode. Split
1697 prefix validation into legacy and VEX-and-alike parts.
1698 (putop): Re-work 'X' macro handling.
1700 2020-06-09 Jan Beulich <jbeulich@suse.com>
1702 * i386-dis.c (MOD_0F51): Rename to ...
1703 (MOD_0F50): ... this.
1705 2020-06-08 Alex Coplan <alex.coplan@arm.com>
1707 * arm-dis.c (arm_opcodes): Add dfb.
1708 (thumb32_opcodes): Add dfb.
1710 2020-06-08 Jan Beulich <jbeulich@suse.com>
1712 * i386-opc.h (reg_entry): Const-qualify reg_name field.
1714 2020-06-06 Alan Modra <amodra@gmail.com>
1716 * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
1718 2020-06-05 Alan Modra <amodra@gmail.com>
1720 * cgen-dis.c (hash_insn_array): Increase size of buf. Assert
1721 size is large enough.
1723 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
1725 * disassemble.c (disassemble_init_for_target): Set endian_code for
1727 * bpf-desc.c: Regenerate.
1728 * bpf-opc.c: Likewise.
1729 * bpf-dis.c: Likewise.
1731 2020-06-03 Jose E. Marchesi <jose.marchesi@oracle.com>
1733 * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
1734 (cgen_put_insn_value): Likewise.
1735 (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
1736 * cgen-dis.in (print_insn): Likewise.
1737 * cgen-ibld.in (insert_1): Likewise.
1738 (insert_1): Likewise.
1739 (insert_insn_normal): Likewise.
1740 (extract_1): Likewise.
1741 * bpf-dis.c: Regenerate.
1742 * bpf-ibld.c: Likewise.
1743 * bpf-ibld.c: Likewise.
1744 * cgen-dis.in: Likewise.
1745 * cgen-ibld.in: Likewise.
1746 * cgen-opc.c: Likewise.
1747 * epiphany-dis.c: Likewise.
1748 * epiphany-ibld.c: Likewise.
1749 * fr30-dis.c: Likewise.
1750 * fr30-ibld.c: Likewise.
1751 * frv-dis.c: Likewise.
1752 * frv-ibld.c: Likewise.
1753 * ip2k-dis.c: Likewise.
1754 * ip2k-ibld.c: Likewise.
1755 * iq2000-dis.c: Likewise.
1756 * iq2000-ibld.c: Likewise.
1757 * lm32-dis.c: Likewise.
1758 * lm32-ibld.c: Likewise.
1759 * m32c-dis.c: Likewise.
1760 * m32c-ibld.c: Likewise.
1761 * m32r-dis.c: Likewise.
1762 * m32r-ibld.c: Likewise.
1763 * mep-dis.c: Likewise.
1764 * mep-ibld.c: Likewise.
1765 * mt-dis.c: Likewise.
1766 * mt-ibld.c: Likewise.
1767 * or1k-dis.c: Likewise.
1768 * or1k-ibld.c: Likewise.
1769 * xc16x-dis.c: Likewise.
1770 * xc16x-ibld.c: Likewise.
1771 * xstormy16-dis.c: Likewise.
1772 * xstormy16-ibld.c: Likewise.
1774 2020-06-04 Jose E. Marchesi <jemarch@gnu.org>
1776 * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
1777 (print_insn_): Handle instruction endian.
1778 * bpf-dis.c: Regenerate.
1779 * bpf-desc.c: Regenerate.
1780 * epiphany-dis.c: Likewise.
1781 * epiphany-desc.c: Likewise.
1782 * fr30-dis.c: Likewise.
1783 * fr30-desc.c: Likewise.
1784 * frv-dis.c: Likewise.
1785 * frv-desc.c: Likewise.
1786 * ip2k-dis.c: Likewise.
1787 * ip2k-desc.c: Likewise.
1788 * iq2000-dis.c: Likewise.
1789 * iq2000-desc.c: Likewise.
1790 * lm32-dis.c: Likewise.
1791 * lm32-desc.c: Likewise.
1792 * m32c-dis.c: Likewise.
1793 * m32c-desc.c: Likewise.
1794 * m32r-dis.c: Likewise.
1795 * m32r-desc.c: Likewise.
1796 * mep-dis.c: Likewise.
1797 * mep-desc.c: Likewise.
1798 * mt-dis.c: Likewise.
1799 * mt-desc.c: Likewise.
1800 * or1k-dis.c: Likewise.
1801 * or1k-desc.c: Likewise.
1802 * xc16x-dis.c: Likewise.
1803 * xc16x-desc.c: Likewise.
1804 * xstormy16-dis.c: Likewise.
1805 * xstormy16-desc.c: Likewise.
1807 2020-06-03 Nick Clifton <nickc@redhat.com>
1809 * po/sr.po: Updated Serbian translation.
1811 2020-06-03 Nelson Chu <nelson.chu@sifive.com>
1813 * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
1814 (riscv_get_priv_spec_class): Likewise.
1816 2020-06-01 Alan Modra <amodra@gmail.com>
1818 * bpf-desc.c: Regenerate.
1820 2020-05-28 Jose E. Marchesi <jose.marchesi@oracle.com>
1821 David Faust <david.faust@oracle.com>
1823 * bpf-desc.c: Regenerate.
1824 * bpf-opc.h: Likewise.
1825 * bpf-opc.c: Likewise.
1826 * bpf-dis.c: Likewise.
1828 2020-05-28 Alan Modra <amodra@gmail.com>
1830 * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
1833 2020-05-28 Alan Modra <amodra@gmail.com>
1835 * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
1837 (print_insn_ns32k): Revert last change.
1839 2020-05-28 Nick Clifton <nickc@redhat.com>
1841 * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
1844 2020-05-26 Sandra Loosemore <sandra@codesourcery.com>
1846 Fix extraction of signed constants in nios2 disassembler (again).
1848 * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
1849 extractions of signed fields.
1851 2020-05-26 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
1853 * s390-opc.txt: Relocate vector load/store instructions with
1854 additional alignment parameter and change architecture level
1855 constraint from z14 to z13.
1857 2020-05-21 Alan Modra <amodra@gmail.com>
1859 * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
1860 * sparc-dis.c: Likewise.
1861 * tic4x-dis.c: Likewise.
1862 * xtensa-dis.c: Likewise.
1863 * bpf-desc.c: Regenerate.
1864 * epiphany-desc.c: Regenerate.
1865 * fr30-desc.c: Regenerate.
1866 * frv-desc.c: Regenerate.
1867 * ip2k-desc.c: Regenerate.
1868 * iq2000-desc.c: Regenerate.
1869 * lm32-desc.c: Regenerate.
1870 * m32c-desc.c: Regenerate.
1871 * m32r-desc.c: Regenerate.
1872 * mep-asm.c: Regenerate.
1873 * mep-desc.c: Regenerate.
1874 * mt-desc.c: Regenerate.
1875 * or1k-desc.c: Regenerate.
1876 * xc16x-desc.c: Regenerate.
1877 * xstormy16-desc.c: Regenerate.
1879 2020-05-20 Nelson Chu <nelson.chu@sifive.com>
1881 * riscv-opc.c (riscv_ext_version_table): The table used to store
1882 all information about the supported spec and the corresponding ISA
1883 versions. Currently, only Zicsr is supported to verify the
1884 correctness of Z sub extension settings. Others will be supported
1885 in the future patches.
1886 (struct isa_spec_t, isa_specs): List for all supported ISA spec
1887 classes and the corresponding strings.
1888 (riscv_get_isa_spec_class): New function. Get the corresponding ISA
1889 spec class by giving a ISA spec string.
1890 * riscv-opc.c (struct priv_spec_t): New structure.
1891 (struct priv_spec_t priv_specs): List for all supported privilege spec
1892 classes and the corresponding strings.
1893 (riscv_get_priv_spec_class): New function. Get the corresponding
1894 privilege spec class by giving a spec string.
1895 (riscv_get_priv_spec_name): New function. Get the corresponding
1896 privilege spec string by giving a CSR version class.
1897 * riscv-dis.c: Updated since DECLARE_CSR is changed.
1898 * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
1899 according to the chosen version. Build a hash table riscv_csr_hash to
1900 store the valid CSR for the chosen pirv verison. Dump the direct
1901 CSR address rather than it's name if it is invalid.
1902 (parse_riscv_dis_option_without_args): New function. Parse the options
1904 (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
1905 parse the options without arguments first, and then handle the options
1906 with arguments. Add the new option -Mpriv-spec, which has argument.
1907 * riscv-dis.c (print_riscv_disassembler_options): Add description
1908 about the new OBJDUMP option.
1910 2020-05-19 Peter Bergner <bergner@linux.ibm.com>
1912 * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
1913 WC values on POWER10 sync, dcbf and wait instructions.
1914 (insert_pl, extract_pl): New functions.
1915 (L2OPT, LS, WC): Use insert_ls and extract_ls.
1916 (LS3): New , 3-bit L for sync.
1917 (LS3, L3OPT): New, 3-bit L for sync and dcbf.
1918 (SC2, PL): New, 2-bit SC and PL for sync and wait.
1919 (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
1920 (XOPL3, XWCPL, XSYNCLS): New opcode macros.
1921 (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
1922 plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
1923 <wait>: Enable PL operand on POWER10.
1924 <dcbf>: Enable L3OPT operand on POWER10.
1925 <sync>: Enable SC2 operand on POWER10.
1927 2020-05-19 Stafford Horne <shorne@gmail.com>
1930 * or1k-asm.c: Regenerate.
1931 * or1k-desc.c: Regenerate.
1932 * or1k-desc.h: Regenerate.
1933 * or1k-dis.c: Regenerate.
1934 * or1k-ibld.c: Regenerate.
1935 * or1k-opc.c: Regenerate.
1936 * or1k-opc.h: Regenerate.
1937 * or1k-opinst.c: Regenerate.
1939 2020-05-11 Alan Modra <amodra@gmail.com>
1941 * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
1944 2020-05-11 Alan Modra <amodra@gmail.com>
1946 * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
1947 stxvrbx, stxvrhx, stxvrwx, stxvrdx.
1949 2020-05-11 Alan Modra <amodra@gmail.com>
1951 * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
1953 2020-05-11 Alan Modra <amodra@gmail.com>
1955 * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
1956 vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
1958 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
1960 * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
1963 2020-05-11 Alan Modra <amodra@gmail.com>
1965 * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
1966 (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
1967 vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
1968 (prefix_opcodes): Add xxeval.
1970 2020-05-11 Alan Modra <amodra@gmail.com>
1972 * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
1973 xxgenpcvwm, xxgenpcvdm.
1975 2020-05-11 Alan Modra <amodra@gmail.com>
1977 * ppc-opc.c (MP, VXVAM_MASK): Define.
1978 (VXVAPS_MASK): Use VXVA_MASK.
1979 (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
1980 vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
1981 vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
1982 vcntmbb, vcntmbh, vcntmbw, vcntmbd.
1984 2020-05-11 Alan Modra <amodra@gmail.com>
1985 Peter Bergner <bergner@linux.ibm.com>
1987 * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
1989 (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
1990 YMSK2, XA6a, XA6ap, XB6a entries.
1991 (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
1992 (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
1994 (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
1995 xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
1996 xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
1997 xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
1998 xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
1999 xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
2000 xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
2001 (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
2002 pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
2003 pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
2004 pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
2005 pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
2006 pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
2007 pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
2009 2020-05-11 Alan Modra <amodra@gmail.com>
2011 * ppc-opc.c (insert_imm32, extract_imm32): New functions.
2012 (insert_xts, extract_xts): New functions.
2013 (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
2014 (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
2015 (VXRC_MASK, VXSH_MASK): Define.
2016 (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
2017 vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
2018 vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
2019 vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
2020 vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
2021 (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
2022 xxblendvh, xxblendvw, xxblendvd, xxpermx.
2024 2020-05-11 Alan Modra <amodra@gmail.com>
2026 * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
2027 vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
2028 vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
2029 vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
2030 xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
2032 2020-05-11 Alan Modra <amodra@gmail.com>
2034 * ppc-opc.c (insert_xtp, extract_xtp): New functions.
2035 (XTP, DQXP, DQXP_MASK): Define.
2036 (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
2037 (prefix_opcodes): Add plxvp and pstxvp.
2039 2020-05-11 Alan Modra <amodra@gmail.com>
2041 * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
2042 vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
2043 vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
2045 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
2047 * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
2049 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
2051 * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
2053 (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
2055 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
2057 * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
2059 2020-05-11 Alan Modra <amodra@gmail.com>
2061 * ppc-dis.c (powerpc_init_dialect): Default to "power10".
2063 2020-05-11 Alan Modra <amodra@gmail.com>
2065 * ppc-dis.c (ppc_opts): Add "power10" entry.
2066 (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
2067 * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
2069 2020-05-11 Nick Clifton <nickc@redhat.com>
2071 * po/fr.po: Updated French translation.
2073 2020-04-30 Alex Coplan <alex.coplan@arm.com>
2075 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
2076 * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
2077 (operand_general_constraint_met_p): validate
2078 AARCH64_OPND_UNDEFINED.
2079 * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
2081 * aarch64-asm-2.c: Regenerated.
2082 * aarch64-dis-2.c: Regenerated.
2083 * aarch64-opc-2.c: Regenerated.
2085 2020-04-29 Nick Clifton <nickc@redhat.com>
2088 * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
2091 2020-04-29 Nick Clifton <nickc@redhat.com>
2093 * po/sv.po: Updated Swedish translation.
2095 2020-04-29 Nick Clifton <nickc@redhat.com>
2098 * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
2099 IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
2100 * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
2103 2020-04-21 Andreas Schwab <schwab@linux-m68k.org>
2106 * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
2107 cmpi only on m68020up and cpu32.
2109 2020-04-20 Sudakshina Das <sudi.das@arm.com>
2111 * aarch64-asm.c (aarch64_ins_none): New.
2112 * aarch64-asm.h (ins_none): New declaration.
2113 * aarch64-dis.c (aarch64_ext_none): New.
2114 * aarch64-dis.h (ext_none): New declaration.
2115 * aarch64-opc.c (aarch64_print_operand): Update case for
2116 AARCH64_OPND_BARRIER_PSB.
2117 * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
2118 (AARCH64_OPERANDS): Update inserter/extracter for
2119 AARCH64_OPND_BARRIER_PSB to use new dummy functions.
2120 * aarch64-asm-2.c: Regenerated.
2121 * aarch64-dis-2.c: Regenerated.
2122 * aarch64-opc-2.c: Regenerated.
2124 2020-04-20 Sudakshina Das <sudi.das@arm.com>
2126 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
2127 (aarch64_feature_ras, RAS): Likewise.
2128 (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
2129 (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
2130 autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
2131 autiaz, autiasp, autibz, autibsp to be CORE_INSN.
2132 * aarch64-asm-2.c: Regenerated.
2133 * aarch64-dis-2.c: Regenerated.
2134 * aarch64-opc-2.c: Regenerated.
2136 2020-04-17 Fredrik Strupe <fredrik@strupe.net>
2138 * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
2139 (print_insn_neon): Support disassembly of conditional
2142 2020-02-16 David Faust <david.faust@oracle.com>
2144 * bpf-desc.c: Regenerate.
2145 * bpf-desc.h: Likewise.
2146 * bpf-opc.c: Regenerate.
2147 * bpf-opc.h: Likewise.
2149 2020-04-07 Lili Cui <lili.cui@intel.com>
2151 * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
2152 (prefix_table): New instructions (see prefixes above).
2153 (rm_table): Likewise
2154 * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
2155 CPU_ANY_TSXLDTRK_FLAGS.
2156 (cpu_flags): Add CpuTSXLDTRK.
2157 * i386-opc.h (enum): Add CpuTSXLDTRK.
2158 (i386_cpu_flags): Add cputsxldtrk.
2159 * i386-opc.tbl: Add XSUSPLDTRK insns.
2160 * i386-init.h: Regenerate.
2161 * i386-tbl.h: Likewise.
2163 2020-04-02 Lili Cui <lili.cui@intel.com>
2165 * i386-dis.c (prefix_table): New instructions serialize.
2166 * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
2167 CPU_ANY_SERIALIZE_FLAGS.
2168 (cpu_flags): Add CpuSERIALIZE.
2169 * i386-opc.h (enum): Add CpuSERIALIZE.
2170 (i386_cpu_flags): Add cpuserialize.
2171 * i386-opc.tbl: Add SERIALIZE insns.
2172 * i386-init.h: Regenerate.
2173 * i386-tbl.h: Likewise.
2175 2020-03-26 Alan Modra <amodra@gmail.com>
2177 * disassemble.h (opcodes_assert): Declare.
2178 (OPCODES_ASSERT): Define.
2179 * disassemble.c: Don't include assert.h. Include opintl.h.
2180 (opcodes_assert): New function.
2181 * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
2182 (bfd_h8_disassemble): Reduce size of data array. Correctly
2183 calculate maxlen. Omit insn decoding when insn length exceeds
2184 maxlen. Exit from nibble loop when looking for E, before
2185 accessing next data byte. Move processing of E outside loop.
2186 Replace tests of maxlen in loop with assertions.
2188 2020-03-26 Alan Modra <amodra@gmail.com>
2190 * arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
2192 2020-03-25 Alan Modra <amodra@gmail.com>
2194 * z80-dis.c (suffix): Init mybuf.
2196 2020-03-22 Alan Modra <amodra@gmail.com>
2198 * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
2199 successflly read from section.
2201 2020-03-22 Alan Modra <amodra@gmail.com>
2203 * arc-dis.c (find_format): Use ISO C string concatenation rather
2204 than line continuation within a string. Don't access needs_limm
2205 before testing opcode != NULL.
2207 2020-03-22 Alan Modra <amodra@gmail.com>
2209 * ns32k-dis.c (print_insn_arg): Update comment.
2210 (print_insn_ns32k): Reduce size of index_offset array, and
2211 initialize, passing -1 to print_insn_arg for args that are not
2212 an index. Don't exit arg loop early. Abort on bad arg number.
2214 2020-03-22 Alan Modra <amodra@gmail.com>
2216 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
2217 * s12z-opc.c: Formatting.
2218 (operands_f): Return an int.
2219 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
2220 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
2221 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
2222 (exg_sex_discrim): Likewise.
2223 (create_immediate_operand, create_bitfield_operand),
2224 (create_register_operand_with_size, create_register_all_operand),
2225 (create_register_all16_operand, create_simple_memory_operand),
2226 (create_memory_operand, create_memory_auto_operand): Don't
2227 segfault on malloc failure.
2228 (z_ext24_decode): Return an int status, negative on fail, zero
2230 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
2231 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
2232 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
2233 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
2234 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
2235 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
2236 (loop_primitive_decode, shift_decode, psh_pul_decode),
2237 (bit_field_decode): Similarly.
2238 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
2239 to return value, update callers.
2240 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
2241 Don't segfault on NULL operand.
2242 (decode_operation): Return OP_INVALID on first fail.
2243 (decode_s12z): Check all reads, returning -1 on fail.
2245 2020-03-20 Alan Modra <amodra@gmail.com>
2247 * metag-dis.c (print_insn_metag): Don't ignore status from
2250 2020-03-20 Alan Modra <amodra@gmail.com>
2252 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
2253 Initialize parts of buffer not written when handling a possible
2254 2-byte insn at end of section. Don't attempt decoding of such
2255 an insn by the 4-byte machinery.
2257 2020-03-20 Alan Modra <amodra@gmail.com>
2259 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
2260 partially filled buffer. Prevent lookup of 4-byte insns when
2261 only VLE 2-byte insns are possible due to section size. Print
2262 ".word" rather than ".long" for 2-byte leftovers.
2264 2020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
2267 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
2269 2020-03-13 Jan Beulich <jbeulich@suse.com>
2271 * i386-dis.c (X86_64_0D): Rename to ...
2272 (X86_64_0E): ... this.
2274 2020-03-09 H.J. Lu <hongjiu.lu@intel.com>
2276 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
2277 * Makefile.in: Regenerated.
2279 2020-03-09 Jan Beulich <jbeulich@suse.com>
2281 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
2283 * i386-tbl.h: Re-generate.
2285 2020-03-09 Jan Beulich <jbeulich@suse.com>
2287 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
2288 vprot*, vpsha*, and vpshl*.
2289 * i386-tbl.h: Re-generate.
2291 2020-03-09 Jan Beulich <jbeulich@suse.com>
2293 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
2294 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
2295 * i386-tbl.h: Re-generate.
2297 2020-03-09 Jan Beulich <jbeulich@suse.com>
2299 * i386-gen.c (set_bitfield): Ignore zero-length field names.
2300 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
2301 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
2302 * i386-tbl.h: Re-generate.
2304 2020-03-09 Jan Beulich <jbeulich@suse.com>
2306 * i386-gen.c (struct template_arg, struct template_instance,
2307 struct template_param, struct template, templates,
2308 parse_template, expand_templates): New.
2309 (process_i386_opcodes): Various local variables moved to
2310 expand_templates. Call parse_template and expand_templates.
2311 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
2312 * i386-tbl.h: Re-generate.
2314 2020-03-06 Jan Beulich <jbeulich@suse.com>
2316 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
2317 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
2318 register and memory source templates. Replace VexW= by VexW*
2320 * i386-tbl.h: Re-generate.
2322 2020-03-06 Jan Beulich <jbeulich@suse.com>
2324 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
2325 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
2326 * i386-tbl.h: Re-generate.
2328 2020-03-06 Jan Beulich <jbeulich@suse.com>
2330 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
2331 * i386-tbl.h: Re-generate.
2333 2020-03-06 Jan Beulich <jbeulich@suse.com>
2335 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
2336 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
2337 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
2338 VexW0 on SSE2AVX variants.
2339 (vmovq): Drop NoRex64 from XMM/XMM variants.
2340 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
2341 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
2342 applicable use VexW0.
2343 * i386-tbl.h: Re-generate.
2345 2020-03-06 Jan Beulich <jbeulich@suse.com>
2347 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
2348 * i386-opc.h (Rex64): Delete.
2349 (struct i386_opcode_modifier): Remove rex64 field.
2350 * i386-opc.tbl (crc32): Drop Rex64.
2351 Replace Rex64 with Size64 everywhere else.
2352 * i386-tbl.h: Re-generate.
2354 2020-03-06 Jan Beulich <jbeulich@suse.com>
2356 * i386-dis.c (OP_E_memory): Exclude recording of used address
2357 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
2358 addressed memory operands for MPX insns.
2360 2020-03-06 Jan Beulich <jbeulich@suse.com>
2362 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
2363 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
2364 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
2365 (ptwrite): Split into non-64-bit and 64-bit forms.
2366 * i386-tbl.h: Re-generate.
2368 2020-03-06 Jan Beulich <jbeulich@suse.com>
2370 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
2372 * i386-tbl.h: Re-generate.
2374 2020-03-04 Jan Beulich <jbeulich@suse.com>
2376 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
2377 (prefix_table): Move vmmcall here. Add vmgexit.
2378 (rm_table): Replace vmmcall entry by prefix_table[] escape.
2379 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
2380 (cpu_flags): Add CpuSEV_ES entry.
2381 * i386-opc.h (CpuSEV_ES): New.
2382 (union i386_cpu_flags): Add cpusev_es field.
2383 * i386-opc.tbl (vmgexit): New.
2384 * i386-init.h, i386-tbl.h: Re-generate.
2386 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
2388 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
2390 * i386-opc.h (IGNORESIZE): New.
2391 (DEFAULTSIZE): Likewise.
2392 (IgnoreSize): Removed.
2393 (DefaultSize): Likewise.
2394 (MnemonicSize): New.
2395 (i386_opcode_modifier): Replace ignoresize/defaultsize with
2397 * i386-opc.tbl (IgnoreSize): New.
2398 (DefaultSize): Likewise.
2399 * i386-tbl.h: Regenerated.
2401 2020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
2404 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
2407 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
2410 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
2411 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
2412 * i386-tbl.h: Regenerated.
2414 2020-02-26 Alan Modra <amodra@gmail.com>
2416 * aarch64-asm.c: Indent labels correctly.
2417 * aarch64-dis.c: Likewise.
2418 * aarch64-gen.c: Likewise.
2419 * aarch64-opc.c: Likewise.
2420 * alpha-dis.c: Likewise.
2421 * i386-dis.c: Likewise.
2422 * nds32-asm.c: Likewise.
2423 * nfp-dis.c: Likewise.
2424 * visium-dis.c: Likewise.
2426 2020-02-25 Claudiu Zissulescu <claziss@gmail.com>
2428 * arc-regs.h (int_vector_base): Make it available for all ARC
2431 2020-02-20 Nelson Chu <nelson.chu@sifive.com>
2433 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
2436 2020-02-19 Nelson Chu <nelson.chu@sifive.com>
2438 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
2439 c.mv/c.li if rs1 is zero.
2441 2020-02-17 H.J. Lu <hongjiu.lu@intel.com>
2443 * i386-gen.c (cpu_flag_init): Replace CpuABM with
2444 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
2446 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
2447 * i386-opc.h (CpuABM): Removed.
2449 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
2450 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
2451 popcnt. Remove CpuABM from lzcnt.
2452 * i386-init.h: Regenerated.
2453 * i386-tbl.h: Likewise.
2455 2020-02-17 Jan Beulich <jbeulich@suse.com>
2457 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
2458 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
2459 VexW1 instead of open-coding them.
2460 * i386-tbl.h: Re-generate.
2462 2020-02-17 Jan Beulich <jbeulich@suse.com>
2464 * i386-opc.tbl (AddrPrefixOpReg): Define.
2465 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
2466 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
2467 templates. Drop NoRex64.
2468 * i386-tbl.h: Re-generate.
2470 2020-02-17 Jan Beulich <jbeulich@suse.com>
2473 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
2474 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
2475 into Intel syntax instance (with Unpsecified) and AT&T one
2477 (vcvtneps2bf16): Likewise, along with folding the two so far
2479 * i386-tbl.h: Re-generate.
2481 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
2483 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
2484 CPU_ANY_SSE4A_FLAGS.
2486 2020-02-17 Alan Modra <amodra@gmail.com>
2488 * i386-gen.c (cpu_flag_init): Correct last change.
2490 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
2492 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
2495 2020-02-14 H.J. Lu <hongjiu.lu@intel.com>
2497 * i386-opc.tbl (movsx): Remove Intel syntax comments.
2500 2020-02-14 Jan Beulich <jbeulich@suse.com>
2503 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
2504 destination for Cpu64-only variant.
2505 (movzx): Fold patterns.
2506 * i386-tbl.h: Re-generate.
2508 2020-02-13 Jan Beulich <jbeulich@suse.com>
2510 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
2511 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
2512 CPU_ANY_SSE4_FLAGS entry.
2513 * i386-init.h: Re-generate.
2515 2020-02-12 Jan Beulich <jbeulich@suse.com>
2517 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
2518 with Unspecified, making the present one AT&T syntax only.
2519 * i386-tbl.h: Re-generate.
2521 2020-02-12 Jan Beulich <jbeulich@suse.com>
2523 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
2524 * i386-tbl.h: Re-generate.
2526 2020-02-12 Jan Beulich <jbeulich@suse.com>
2529 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
2530 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
2531 Amd64 and Intel64 templates.
2532 (call, jmp): Likewise for far indirect variants. Dro
2534 * i386-tbl.h: Re-generate.
2536 2020-02-11 Jan Beulich <jbeulich@suse.com>
2538 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
2539 * i386-opc.h (ShortForm): Delete.
2540 (struct i386_opcode_modifier): Remove shortform field.
2541 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
2542 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
2543 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
2544 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
2546 * i386-tbl.h: Re-generate.
2548 2020-02-11 Jan Beulich <jbeulich@suse.com>
2550 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
2551 fucompi): Drop ShortForm from operand-less templates.
2552 * i386-tbl.h: Re-generate.
2554 2020-02-11 Alan Modra <amodra@gmail.com>
2556 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
2557 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
2558 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
2559 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
2560 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
2562 2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
2564 * arm-dis.c (print_insn_cde): Define 'V' parse character.
2565 (cde_opcodes): Add VCX* instructions.
2567 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
2568 Matthew Malcomson <matthew.malcomson@arm.com>
2570 * arm-dis.c (struct cdeopcode32): New.
2571 (CDE_OPCODE): New macro.
2572 (cde_opcodes): New disassembly table.
2573 (regnames): New option to table.
2574 (cde_coprocs): New global variable.
2575 (print_insn_cde): New
2576 (print_insn_thumb32): Use print_insn_cde.
2577 (parse_arm_disassembler_options): Parse coprocN args.
2579 2020-02-10 H.J. Lu <hongjiu.lu@intel.com>
2582 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
2584 * i386-opc.h (AMD64): Removed.
2585 (Intel64): Likewose.
2587 (INTEL64): Likewise.
2588 (INTEL64ONLY): Likewise.
2589 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
2590 * i386-opc.tbl (Amd64): New.
2591 (Intel64): Likewise.
2592 (Intel64Only): Likewise.
2593 Replace AMD64 with Amd64. Update sysenter/sysenter with
2594 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
2595 * i386-tbl.h: Regenerated.
2597 2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
2600 * z80-dis.c: Add support for GBZ80 opcodes.
2602 2020-02-04 Alan Modra <amodra@gmail.com>
2604 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
2606 2020-02-03 Alan Modra <amodra@gmail.com>
2608 * m32c-ibld.c: Regenerate.
2610 2020-02-01 Alan Modra <amodra@gmail.com>
2612 * frv-ibld.c: Regenerate.
2614 2020-01-31 Jan Beulich <jbeulich@suse.com>
2616 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
2617 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
2618 (OP_E_memory): Replace xmm_mdq_mode case label by
2619 vex_scalar_w_dq_mode one.
2620 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
2622 2020-01-31 Jan Beulich <jbeulich@suse.com>
2624 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
2625 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
2626 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
2627 (intel_operand_size): Drop vex_w_dq_mode case label.
2629 2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
2631 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
2632 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
2634 2020-01-30 Alan Modra <amodra@gmail.com>
2636 * m32c-ibld.c: Regenerate.
2638 2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
2640 * bpf-opc.c: Regenerate.
2642 2020-01-30 Jan Beulich <jbeulich@suse.com>
2644 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
2645 (dis386): Use them to replace C2/C3 table entries.
2646 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
2647 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
2648 ones. Use Size64 instead of DefaultSize on Intel64 ones.
2649 * i386-tbl.h: Re-generate.
2651 2020-01-30 Jan Beulich <jbeulich@suse.com>
2653 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
2655 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
2657 * i386-tbl.h: Re-generate.
2659 2020-01-30 Alan Modra <amodra@gmail.com>
2661 * tic4x-dis.c (tic4x_dp): Make unsigned.
2663 2020-01-27 H.J. Lu <hongjiu.lu@intel.com>
2664 Jan Beulich <jbeulich@suse.com>
2667 * i386-dis.c (MOVSXD_Fixup): New function.
2668 (movsxd_mode): New enum.
2669 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
2670 (intel_operand_size): Handle movsxd_mode.
2671 (OP_E_register): Likewise.
2673 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
2674 register on movsxd. Add movsxd with 16-bit destination register
2675 for AMD64 and Intel64 ISAs.
2676 * i386-tbl.h: Regenerated.
2678 2020-01-27 Tamar Christina <tamar.christina@arm.com>
2681 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
2682 * aarch64-asm-2.c: Regenerate
2683 * aarch64-dis-2.c: Likewise.
2684 * aarch64-opc-2.c: Likewise.
2686 2020-01-21 Jan Beulich <jbeulich@suse.com>
2688 * i386-opc.tbl (sysret): Drop DefaultSize.
2689 * i386-tbl.h: Re-generate.
2691 2020-01-21 Jan Beulich <jbeulich@suse.com>
2693 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
2695 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
2696 * i386-tbl.h: Re-generate.
2698 2020-01-20 Nick Clifton <nickc@redhat.com>
2700 * po/de.po: Updated German translation.
2701 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2702 * po/uk.po: Updated Ukranian translation.
2704 2020-01-20 Alan Modra <amodra@gmail.com>
2706 * hppa-dis.c (fput_const): Remove useless cast.
2708 2020-01-20 Alan Modra <amodra@gmail.com>
2710 * arm-dis.c (print_insn_arm): Wrap 'T' value.
2712 2020-01-18 Nick Clifton <nickc@redhat.com>
2714 * configure: Regenerate.
2715 * po/opcodes.pot: Regenerate.
2717 2020-01-18 Nick Clifton <nickc@redhat.com>
2719 Binutils 2.34 branch created.
2721 2020-01-17 Christian Biesinger <cbiesinger@google.com>
2723 * opintl.h: Fix spelling error (seperate).
2725 2020-01-17 H.J. Lu <hongjiu.lu@intel.com>
2727 * i386-opc.tbl: Add {vex} pseudo prefix.
2728 * i386-tbl.h: Regenerated.
2730 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
2733 * arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
2734 (neon_opcodes): Likewise.
2735 (select_arm_features): Make sure we enable MVE bits when selecting
2736 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
2739 2020-01-16 Jan Beulich <jbeulich@suse.com>
2741 * i386-opc.tbl: Drop stale comment from XOP section.
2743 2020-01-16 Jan Beulich <jbeulich@suse.com>
2745 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
2746 (extractps): Add VexWIG to SSE2AVX forms.
2747 * i386-tbl.h: Re-generate.
2749 2020-01-16 Jan Beulich <jbeulich@suse.com>
2751 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
2752 Size64 from and use VexW1 on SSE2AVX forms.
2753 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
2754 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
2755 * i386-tbl.h: Re-generate.
2757 2020-01-15 Alan Modra <amodra@gmail.com>
2759 * tic4x-dis.c (tic4x_version): Make unsigned long.
2760 (optab, optab_special, registernames): New file scope vars.
2761 (tic4x_print_register): Set up registernames rather than
2762 malloc'd registertable.
2763 (tic4x_disassemble): Delete optable and optable_special. Use
2764 optab and optab_special instead. Throw away old optab,
2765 optab_special and registernames when info->mach changes.
2767 2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
2770 * z80-dis.c (suffix): Use .db instruction to generate double
2773 2020-01-14 Alan Modra <amodra@gmail.com>
2775 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
2776 values to unsigned before shifting.
2778 2020-01-13 Thomas Troeger <tstroege@gmx.de>
2780 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
2782 (print_insn_thumb16, print_insn_thumb32): Likewise.
2783 (print_insn): Initialize the insn info.
2784 * i386-dis.c (print_insn): Initialize the insn info fields, and
2787 2020-01-13 Claudiu Zissulescu <claziss@gmail.com>
2789 * arc-opc.c (C_NE): Make it required.
2791 2020-01-13 Claudiu Zissulescu <claziss@gmail.com>
2793 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
2794 reserved register name.
2796 2020-01-13 Alan Modra <amodra@gmail.com>
2798 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
2799 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
2801 2020-01-13 Alan Modra <amodra@gmail.com>
2803 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
2804 result of wasm_read_leb128 in a uint64_t and check that bits
2805 are not lost when copying to other locals. Use uint32_t for
2806 most locals. Use PRId64 when printing int64_t.
2808 2020-01-13 Alan Modra <amodra@gmail.com>
2810 * score-dis.c: Formatting.
2811 * score7-dis.c: Formatting.
2813 2020-01-13 Alan Modra <amodra@gmail.com>
2815 * score-dis.c (print_insn_score48): Use unsigned variables for
2816 unsigned values. Don't left shift negative values.
2817 (print_insn_score32): Likewise.
2818 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
2820 2020-01-13 Alan Modra <amodra@gmail.com>
2822 * tic4x-dis.c (tic4x_print_register): Remove dead code.
2824 2020-01-13 Alan Modra <amodra@gmail.com>
2826 * fr30-ibld.c: Regenerate.
2828 2020-01-13 Alan Modra <amodra@gmail.com>
2830 * xgate-dis.c (print_insn): Don't left shift signed value.
2831 (ripBits): Formatting, use 1u.
2833 2020-01-10 Alan Modra <amodra@gmail.com>
2835 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
2836 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
2838 2020-01-10 Alan Modra <amodra@gmail.com>
2840 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
2841 and XRREG value earlier to avoid a shift with negative exponent.
2842 * m10200-dis.c (disassemble): Similarly.
2844 2020-01-09 Nick Clifton <nickc@redhat.com>
2847 * z80-dis.c (ld_ii_ii): Use correct cast.
2849 2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
2852 * z80-dis.c (ld_ii_ii): Use character constant when checking
2855 2020-01-09 Jan Beulich <jbeulich@suse.com>
2857 * i386-dis.c (SEP_Fixup): New.
2859 (dis386_twobyte): Use it for sysenter/sysexit.
2860 (enum x86_64_isa): Change amd64 enumerator to value 1.
2861 (OP_J): Compare isa64 against intel64 instead of amd64.
2862 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
2864 * i386-tbl.h: Re-generate.
2866 2020-01-08 Alan Modra <amodra@gmail.com>
2868 * z8k-dis.c: Include libiberty.h
2869 (instr_data_s): Make max_fetched unsigned.
2870 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
2871 Don't exceed byte_info bounds.
2872 (output_instr): Make num_bytes unsigned.
2873 (unpack_instr): Likewise for nibl_count and loop.
2874 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
2876 * z8k-opc.h: Regenerate.
2878 2020-01-07 Shahab Vahedi <shahab@synopsys.com>
2880 * arc-tbl.h (llock): Use 'LLOCK' as class.
2882 (scond): Use 'SCOND' as class.
2884 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
2887 2020-01-06 Alan Modra <amodra@gmail.com>
2889 * m32c-ibld.c: Regenerate.
2891 2020-01-06 Alan Modra <amodra@gmail.com>
2894 * z80-dis.c (suffix): Don't use a local struct buffer copy.
2895 Peek at next byte to prevent recursion on repeated prefix bytes.
2896 Ensure uninitialised "mybuf" is not accessed.
2897 (print_insn_z80): Don't zero n_fetch and n_used here,..
2898 (print_insn_z80_buf): ..do it here instead.
2900 2020-01-04 Alan Modra <amodra@gmail.com>
2902 * m32r-ibld.c: Regenerate.
2904 2020-01-04 Alan Modra <amodra@gmail.com>
2906 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
2908 2020-01-04 Alan Modra <amodra@gmail.com>
2910 * crx-dis.c (match_opcode): Avoid shift left of signed value.
2912 2020-01-04 Alan Modra <amodra@gmail.com>
2914 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
2916 2020-01-03 Jan Beulich <jbeulich@suse.com>
2918 * aarch64-tbl.h (aarch64_opcode_table): Use
2919 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
2921 2020-01-03 Jan Beulich <jbeulich@suse.com>
2923 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
2924 forms of SUDOT and USDOT.
2926 2020-01-03 Jan Beulich <jbeulich@suse.com>
2928 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
2930 * aarch64-dis-2.c: Re-generate.
2932 2020-01-03 Jan Beulich <jbeulich@suse.com>
2934 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
2936 * aarch64-dis-2.c: Re-generate.
2938 2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
2940 * z80-dis.c: Add support for eZ80 and Z80 instructions.
2942 2020-01-01 Alan Modra <amodra@gmail.com>
2944 Update year range in copyright notice of all files.
2946 For older changes see ChangeLog-2019
2948 Copyright (C) 2020 Free Software Foundation, Inc.
2950 Copying and distribution of this file, with or without modification,
2951 are permitted in any medium without royalty provided the copyright
2952 notice and this notice are preserved.
2958 version-control: never
projects / binutils-gdb.git / blob